File: /usr/src/linux/drivers/isdn/hisax/hfc_pci.h
1 /* $Id: hfc_pci.h,v 1.8.6.1 2001/04/08 19:32:26 kai Exp $
2 *
3 * specific defines for CCD's HFC 2BDS0 PCI chips
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 *
7 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 /*********************************************/
26 /* thresholds for transparent B-channel mode */
27 /* change mask and threshold simultaneously */
28 /*********************************************/
29 #define HFCPCI_BTRANS_THRESHOLD 128
30 #define HFCPCI_BTRANS_THRESMASK 0x00
31
32
33
34 /* defines for PCI config */
35
36 #define PCI_ENA_MEMIO 0x02
37 #define PCI_ENA_MASTER 0x04
38
39
40 /* GCI/IOM bus monitor registers */
41
42 #define HCFPCI_C_I 0x08
43 #define HFCPCI_TRxR 0x0C
44 #define HFCPCI_MON1_D 0x28
45 #define HFCPCI_MON2_D 0x2C
46
47
48 /* GCI/IOM bus timeslot registers */
49
50 #define HFCPCI_B1_SSL 0x80
51 #define HFCPCI_B2_SSL 0x84
52 #define HFCPCI_AUX1_SSL 0x88
53 #define HFCPCI_AUX2_SSL 0x8C
54 #define HFCPCI_B1_RSL 0x90
55 #define HFCPCI_B2_RSL 0x94
56 #define HFCPCI_AUX1_RSL 0x98
57 #define HFCPCI_AUX2_RSL 0x9C
58
59 /* GCI/IOM bus data registers */
60
61 #define HFCPCI_B1_D 0xA0
62 #define HFCPCI_B2_D 0xA4
63 #define HFCPCI_AUX1_D 0xA8
64 #define HFCPCI_AUX2_D 0xAC
65
66 /* GCI/IOM bus configuration registers */
67
68 #define HFCPCI_MST_EMOD 0xB4
69 #define HFCPCI_MST_MODE 0xB8
70 #define HFCPCI_CONNECT 0xBC
71
72
73 /* Interrupt and status registers */
74
75 #define HFCPCI_FIFO_EN 0x44
76 #define HFCPCI_TRM 0x48
77 #define HFCPCI_B_MODE 0x4C
78 #define HFCPCI_CHIP_ID 0x58
79 #define HFCPCI_CIRM 0x60
80 #define HFCPCI_CTMT 0x64
81 #define HFCPCI_INT_M1 0x68
82 #define HFCPCI_INT_M2 0x6C
83 #define HFCPCI_INT_S1 0x78
84 #define HFCPCI_INT_S2 0x7C
85 #define HFCPCI_STATUS 0x70
86
87 /* S/T section registers */
88
89 #define HFCPCI_STATES 0xC0
90 #define HFCPCI_SCTRL 0xC4
91 #define HFCPCI_SCTRL_E 0xC8
92 #define HFCPCI_SCTRL_R 0xCC
93 #define HFCPCI_SQ 0xD0
94 #define HFCPCI_CLKDEL 0xDC
95 #define HFCPCI_B1_REC 0xF0
96 #define HFCPCI_B1_SEND 0xF0
97 #define HFCPCI_B2_REC 0xF4
98 #define HFCPCI_B2_SEND 0xF4
99 #define HFCPCI_D_REC 0xF8
100 #define HFCPCI_D_SEND 0xF8
101 #define HFCPCI_E_REC 0xFC
102
103
104 /* bits in status register (READ) */
105 #define HFCPCI_PCI_PROC 0x02
106 #define HFCPCI_NBUSY 0x04
107 #define HFCPCI_TIMER_ELAP 0x10
108 #define HFCPCI_STATINT 0x20
109 #define HFCPCI_FRAMEINT 0x40
110 #define HFCPCI_ANYINT 0x80
111
112 /* bits in CTMT (Write) */
113 #define HFCPCI_CLTIMER 0x80
114 #define HFCPCI_TIM3_125 0x04
115 #define HFCPCI_TIM25 0x10
116 #define HFCPCI_TIM50 0x14
117 #define HFCPCI_TIM400 0x18
118 #define HFCPCI_TIM800 0x1C
119 #define HFCPCI_AUTO_TIMER 0x20
120 #define HFCPCI_TRANSB2 0x02
121 #define HFCPCI_TRANSB1 0x01
122
123 /* bits in CIRM (Write) */
124 #define HFCPCI_AUX_MSK 0x07
125 #define HFCPCI_RESET 0x08
126 #define HFCPCI_B1_REV 0x40
127 #define HFCPCI_B2_REV 0x80
128
129 /* bits in INT_M1 and INT_S1 */
130 #define HFCPCI_INTS_B1TRANS 0x01
131 #define HFCPCI_INTS_B2TRANS 0x02
132 #define HFCPCI_INTS_DTRANS 0x04
133 #define HFCPCI_INTS_B1REC 0x08
134 #define HFCPCI_INTS_B2REC 0x10
135 #define HFCPCI_INTS_DREC 0x20
136 #define HFCPCI_INTS_L1STATE 0x40
137 #define HFCPCI_INTS_TIMER 0x80
138
139 /* bits in INT_M2 */
140 #define HFCPCI_PROC_TRANS 0x01
141 #define HFCPCI_GCI_I_CHG 0x02
142 #define HFCPCI_GCI_MON_REC 0x04
143 #define HFCPCI_IRQ_ENABLE 0x08
144 #define HFCPCI_PMESEL 0x80
145
146 /* bits in STATES */
147 #define HFCPCI_STATE_MSK 0x0F
148 #define HFCPCI_LOAD_STATE 0x10
149 #define HFCPCI_ACTIVATE 0x20
150 #define HFCPCI_DO_ACTION 0x40
151 #define HFCPCI_NT_G2_G3 0x80
152
153 /* bits in HFCD_MST_MODE */
154 #define HFCPCI_MASTER 0x01
155 #define HFCPCI_SLAVE 0x00
156 /* remaining bits are for codecs control */
157
158 /* bits in HFCD_SCTRL */
159 #define SCTRL_B1_ENA 0x01
160 #define SCTRL_B2_ENA 0x02
161 #define SCTRL_MODE_TE 0x00
162 #define SCTRL_MODE_NT 0x04
163 #define SCTRL_LOW_PRIO 0x08
164 #define SCTRL_SQ_ENA 0x10
165 #define SCTRL_TEST 0x20
166 #define SCTRL_NONE_CAP 0x40
167 #define SCTRL_PWR_DOWN 0x80
168
169 /* bits in SCTRL_E */
170 #define HFCPCI_AUTO_AWAKE 0x01
171 #define HFCPCI_DBIT_1 0x04
172 #define HFCPCI_IGNORE_COL 0x08
173 #define HFCPCI_CHG_B1_B2 0x80
174
175 /****************************/
176 /* bits in FIFO_EN register */
177 /****************************/
178 #define HFCPCI_FIFOEN_B1 0x03
179 #define HFCPCI_FIFOEN_B2 0x0C
180 #define HFCPCI_FIFOEN_DTX 0x10
181 #define HFCPCI_FIFOEN_B1TX 0x01
182 #define HFCPCI_FIFOEN_B1RX 0x02
183 #define HFCPCI_FIFOEN_B2TX 0x04
184 #define HFCPCI_FIFOEN_B2RX 0x08
185
186
187 /***********************************/
188 /* definitions of fifo memory area */
189 /***********************************/
190 #define MAX_D_FRAMES 15
191 #define MAX_B_FRAMES 31
192 #define B_SUB_VAL 0x200
193 #define B_FIFO_SIZE (0x2000 - B_SUB_VAL)
194 #define D_FIFO_SIZE 512
195 #define D_FREG_MASK 0xF
196
197 typedef struct {
198 unsigned short z1; /* Z1 pointer 16 Bit */
199 unsigned short z2; /* Z2 pointer 16 Bit */
200 } z_type;
201
202 typedef struct {
203 u_char data[D_FIFO_SIZE]; /* FIFO data space */
204 u_char fill1[0x20A0-D_FIFO_SIZE]; /* reserved, do not use */
205 u_char f1,f2; /* f pointers */
206 u_char fill2[0x20C0-0x20A2]; /* reserved, do not use */
207 z_type za[MAX_D_FRAMES+1]; /* mask index with D_FREG_MASK for access */
208 u_char fill3[0x4000-0x2100]; /* align 16K */
209 } dfifo_type;
210
211 typedef struct {
212 z_type za[MAX_B_FRAMES+1]; /* only range 0x0..0x1F allowed */
213 u_char f1,f2; /* f pointers */
214 u_char fill[0x2100-0x2082]; /* alignment */
215 } bzfifo_type;
216
217
218 typedef union {
219 struct {
220 dfifo_type d_tx; /* D-send channel */
221 dfifo_type d_rx; /* D-receive channel */
222 } d_chan;
223 struct {
224 u_char fill1[0x200];
225 u_char txdat_b1[B_FIFO_SIZE];
226 bzfifo_type txbz_b1;
227
228 bzfifo_type txbz_b2;
229 u_char txdat_b2[B_FIFO_SIZE];
230
231 u_char fill2[D_FIFO_SIZE];
232
233 u_char rxdat_b1[B_FIFO_SIZE];
234 bzfifo_type rxbz_b1;
235
236 bzfifo_type rxbz_b2;
237 u_char rxdat_b2[B_FIFO_SIZE];
238 } b_chans;
239 u_char fill[32768];
240 } fifo_area;
241
242
243 #define Write_hfc(a,b,c) (*(((u_char *)a->hw.hfcpci.pci_io)+b) = c)
244 #define Read_hfc(a,b) (*(((u_char *)a->hw.hfcpci.pci_io)+b))
245
246 extern void main_irq_hcpci(struct BCState *bcs);
247 extern void inithfcpci(struct IsdnCardState *cs);
248 extern void releasehfcpci(struct IsdnCardState *cs);
249