File: /usr/src/linux/drivers/isdn/hisax/hfc_pci.c
1 /* $Id: hfc_pci.c,v 1.34.6.7 2001/07/27 09:08:27 kai Exp $
2
3 * hfc_pci.c low level driver for CCD´s hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
8 *
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 1999 by Karsten Keil (keil@isdn4linux.de)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28 #include <linux/init.h>
29 #include <linux/config.h>
30 #define __NO_VERSION__
31 #include "hisax.h"
32 #include "hfc_pci.h"
33 #include "isdnl1.h"
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36
37 extern const char *CardType[];
38
39 static const char *hfcpci_revision = "$Revision: 1.34.6.7 $";
40
41 /* table entry in the PCI devices list */
42 typedef struct {
43 int vendor_id;
44 int device_id;
45 char *vendor_name;
46 char *card_name;
47 } PCI_ENTRY;
48
49 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
50 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
51 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
52
53 static const PCI_ENTRY id_list[] =
54 {
55 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0, "CCD/Billion/Asuscom", "2BD0"},
56 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000, "Billion", "B000"},
57 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006, "Billion", "B006"},
58 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007, "Billion", "B007"},
59 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008, "Billion", "B008"},
60 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009, "Billion", "B009"},
61 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A, "Billion", "B00A"},
62 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B, "Billion", "B00B"},
63 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C, "Billion", "B00C"},
64 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100, "Seyeon", "B100"},
65 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1, "Abocom/Magitek", "2BD1"},
66 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675, "Asuscom/Askey", "675"},
67 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
68 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
69 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
70 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
71 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
72 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
73 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
74 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
75 {0, 0, NULL, NULL},
76 };
77
78
79 #if CONFIG_PCI
80
81 /******************************************/
82 /* free hardware resources used by driver */
83 /******************************************/
84 void
85 release_io_hfcpci(struct IsdnCardState *cs)
86 {
87 long flags;
88
89 save_flags(flags);
90 cli();
91 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
92 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
93 restore_flags(flags);
94 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
95 sti();
96 set_current_state(TASK_UNINTERRUPTIBLE);
97 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
98 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
99 #if CONFIG_PCI
100 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
101 #endif /* CONFIG_PCI */
102 del_timer(&cs->hw.hfcpci.timer);
103 kfree(cs->hw.hfcpci.share_start);
104 cs->hw.hfcpci.share_start = NULL;
105 vfree(cs->hw.hfcpci.pci_io);
106 }
107
108 /********************************************************************************/
109 /* function called to reset the HFC PCI chip. A complete software reset of chip */
110 /* and fifos is done. */
111 /********************************************************************************/
112 static void
113 reset_hfcpci(struct IsdnCardState *cs)
114 {
115 long flags;
116
117 save_flags(flags);
118 cli();
119 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
120 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
121 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
122
123 printk(KERN_INFO "HFC_PCI: resetting card\n");
124 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
125 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
126 sti();
127 set_current_state(TASK_UNINTERRUPTIBLE);
128 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
129 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
130 set_current_state(TASK_UNINTERRUPTIBLE);
131 schedule_timeout((20 * HZ) / 1000); /* Timeout 20ms */
132 if (Read_hfc(cs, HFCPCI_STATUS) & 2)
133 printk(KERN_WARNING "HFC-PCI init bit busy\n");
134
135 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
136 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
137
138 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
139 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
140
141 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */
142 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
143 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
144 cs->hw.hfcpci.bswapped = 0; /* no exchange */
145 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
146 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
147 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
148
149 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
150 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
151 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
152
153 /* Clear already pending ints */
154 if (Read_hfc(cs, HFCPCI_INT_S1));
155
156 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */
157 udelay(10);
158 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */
159 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
160
161 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
162 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
163 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
164 cs->hw.hfcpci.sctrl_r = 0;
165 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
166
167 /* Init GCI/IOM2 in master mode */
168 /* Slots 0 and 1 are set for B-chan 1 and 2 */
169 /* D- and monitor/CI channel are not enabled */
170 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
171 /* STIO2 is used as data input, B1+B2 from IOM->ST */
172 /* ST B-channel send disabled -> continous 1s */
173 /* The IOM slots are always enabled */
174 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
175 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
176 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
177 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
178 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
179 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
180
181 /* Finally enable IRQ output */
182 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
183 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
184 if (Read_hfc(cs, HFCPCI_INT_S2));
185 restore_flags(flags);
186 }
187
188 /***************************************************/
189 /* Timer function called when kernel timer expires */
190 /***************************************************/
191 static void
192 hfcpci_Timer(struct IsdnCardState *cs)
193 {
194 cs->hw.hfcpci.timer.expires = jiffies + 75;
195 /* WD RESET */
196 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
197 add_timer(&cs->hw.hfcpci.timer);
198 */
199 }
200
201
202 /*********************************/
203 /* schedule a new D-channel task */
204 /*********************************/
205 static void
206 sched_event_D_pci(struct IsdnCardState *cs, int event)
207 {
208 test_and_set_bit(event, &cs->event);
209 queue_task(&cs->tqueue, &tq_immediate);
210 mark_bh(IMMEDIATE_BH);
211 }
212
213 /*********************************/
214 /* schedule a new b_channel task */
215 /*********************************/
216 static void
217 hfcpci_sched_event(struct BCState *bcs, int event)
218 {
219 bcs->event |= 1 << event;
220 queue_task(&bcs->tqueue, &tq_immediate);
221 mark_bh(IMMEDIATE_BH);
222 }
223
224 /************************************************/
225 /* select a b-channel entry matching and active */
226 /************************************************/
227 static
228 struct BCState *
229 Sel_BCS(struct IsdnCardState *cs, int channel)
230 {
231 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
232 return (&cs->bcs[0]);
233 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
234 return (&cs->bcs[1]);
235 else
236 return (NULL);
237 }
238
239 /***************************************/
240 /* clear the desired B-channel rx fifo */
241 /***************************************/
242 static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo)
243 { u_char fifo_state;
244 bzfifo_type *bzr;
245
246 if (fifo) {
247 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
248 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
249 } else {
250 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
251 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
252 }
253 if (fifo_state)
254 cs->hw.hfcpci.fifo_en ^= fifo_state;
255 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
256 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
257 bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
258 bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
259 bzr->f1 = MAX_B_FRAMES;
260 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
261 if (fifo_state)
262 cs->hw.hfcpci.fifo_en |= fifo_state;
263 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
264 }
265
266 /***************************************/
267 /* clear the desired B-channel tx fifo */
268 /***************************************/
269 static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo)
270 { u_char fifo_state;
271 bzfifo_type *bzt;
272
273 if (fifo) {
274 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
275 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
276 } else {
277 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
278 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
279 }
280 if (fifo_state)
281 cs->hw.hfcpci.fifo_en ^= fifo_state;
282 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
283 bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
284 bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
285 bzt->f1 = MAX_B_FRAMES;
286 bzt->f2 = bzt->f1; /* init F pointers to remain constant */
287 if (fifo_state)
288 cs->hw.hfcpci.fifo_en |= fifo_state;
289 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
290 }
291
292 /*********************************************/
293 /* read a complete B-frame out of the buffer */
294 /*********************************************/
295 static struct sk_buff
296 *
297 hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
298 {
299 u_char *ptr, *ptr1, new_f2;
300 struct sk_buff *skb;
301 struct IsdnCardState *cs = bcs->cs;
302 long flags;
303 int total, maxlen, new_z2;
304 z_type *zp;
305
306 save_flags(flags);
307 sti();
308 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
309 debugl1(cs, "hfcpci_empty_fifo");
310 zp = &bz->za[bz->f2]; /* point to Z-Regs */
311 new_z2 = zp->z2 + count; /* new position in fifo */
312 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
313 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
314 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
315 if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
316 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
317 if (cs->debug & L1_DEB_WARN)
318 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
319 #ifdef ERROR_STATISTIC
320 bcs->err_inv++;
321 #endif
322 bz->za[new_f2].z2 = new_z2;
323 bz->f2 = new_f2; /* next buffer */
324 skb = NULL;
325 } else if (!(skb = dev_alloc_skb(count - 3)))
326 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
327 else {
328 total = count;
329 count -= 3;
330 ptr = skb_put(skb, count);
331
332 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
333 maxlen = count; /* complete transfer */
334 else
335 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
336
337 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
338 memcpy(ptr, ptr1, maxlen); /* copy data */
339 count -= maxlen;
340
341 if (count) { /* rest remaining */
342 ptr += maxlen;
343 ptr1 = bdata; /* start of buffer */
344 memcpy(ptr, ptr1, count); /* rest */
345 }
346 bz->za[new_f2].z2 = new_z2;
347 bz->f2 = new_f2; /* next buffer */
348
349 }
350 restore_flags(flags);
351 return (skb);
352 }
353
354 /*******************************/
355 /* D-channel receive procedure */
356 /*******************************/
357 static
358 int
359 receive_dmsg(struct IsdnCardState *cs)
360 {
361 struct sk_buff *skb;
362 int maxlen;
363 int rcnt, total;
364 int count = 5;
365 u_char *ptr, *ptr1;
366 dfifo_type *df;
367 z_type *zp;
368
369 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
370 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
371 debugl1(cs, "rec_dmsg blocked");
372 return (1);
373 }
374 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
375 zp = &df->za[df->f2 & D_FREG_MASK];
376 rcnt = zp->z1 - zp->z2;
377 if (rcnt < 0)
378 rcnt += D_FIFO_SIZE;
379 rcnt++;
380 if (cs->debug & L1_DEB_ISAC)
381 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
382 df->f1, df->f2, zp->z1, zp->z2, rcnt);
383
384 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
385 (df->data[zp->z1])) {
386 if (cs->debug & L1_DEB_WARN)
387 debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
388 #ifdef ERROR_STATISTIC
389 cs->err_rx++;
390 #endif
391 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
392 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
393 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
394 total = rcnt;
395 rcnt -= 3;
396 ptr = skb_put(skb, rcnt);
397
398 if (zp->z2 + rcnt <= D_FIFO_SIZE)
399 maxlen = rcnt; /* complete transfer */
400 else
401 maxlen = D_FIFO_SIZE - zp->z2; /* maximum */
402
403 ptr1 = df->data + zp->z2; /* start of data */
404 memcpy(ptr, ptr1, maxlen); /* copy data */
405 rcnt -= maxlen;
406
407 if (rcnt) { /* rest remaining */
408 ptr += maxlen;
409 ptr1 = df->data; /* start of buffer */
410 memcpy(ptr, ptr1, rcnt); /* rest */
411 }
412 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
413 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
414
415 skb_queue_tail(&cs->rq, skb);
416 sched_event_D_pci(cs, D_RCVBUFREADY);
417 } else
418 printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
419 }
420 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
421 return (1);
422 }
423
424 /*******************************************************************************/
425 /* check for transparent receive data and read max one threshold size if avail */
426 /*******************************************************************************/
427 int
428 hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
429 {
430 unsigned short *z1r, *z2r;
431 int new_z2, fcnt, maxlen;
432 struct sk_buff *skb;
433 u_char *ptr, *ptr1;
434
435 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
436 z2r = z1r + 1;
437
438 if (!(fcnt = *z1r - *z2r))
439 return (0); /* no data avail */
440
441 if (fcnt <= 0)
442 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
443 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
444 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
445
446 new_z2 = *z2r + fcnt; /* new position in fifo */
447 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
448 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
449
450 if (!(skb = dev_alloc_skb(fcnt)))
451 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
452 else {
453 ptr = skb_put(skb, fcnt);
454 if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
455 maxlen = fcnt; /* complete transfer */
456 else
457 maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */
458
459 ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */
460 memcpy(ptr, ptr1, maxlen); /* copy data */
461 fcnt -= maxlen;
462
463 if (fcnt) { /* rest remaining */
464 ptr += maxlen;
465 ptr1 = bdata; /* start of buffer */
466 memcpy(ptr, ptr1, fcnt); /* rest */
467 }
468 cli();
469 skb_queue_tail(&bcs->rqueue, skb);
470 sti();
471 hfcpci_sched_event(bcs, B_RCVBUFREADY);
472 }
473
474 *z2r = new_z2; /* new position */
475 return (1);
476 } /* hfcpci_empty_fifo_trans */
477
478 /**********************************/
479 /* B-channel main receive routine */
480 /**********************************/
481 void
482 main_rec_hfcpci(struct BCState *bcs)
483 {
484 long flags;
485 struct IsdnCardState *cs = bcs->cs;
486 int rcnt, real_fifo;
487 int receive, count = 5;
488 struct sk_buff *skb;
489 bzfifo_type *bz;
490 u_char *bdata;
491 z_type *zp;
492
493
494 save_flags(flags);
495 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
496 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
497 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
498 real_fifo = 1;
499 } else {
500 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
501 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
502 real_fifo = 0;
503 }
504 Begin:
505 count--;
506 cli();
507 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
508 debugl1(cs, "rec_data %d blocked", bcs->channel);
509 restore_flags(flags);
510 return;
511 }
512 sti();
513 if (bz->f1 != bz->f2) {
514 if (cs->debug & L1_DEB_HSCX)
515 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
516 bcs->channel, bz->f1, bz->f2);
517 zp = &bz->za[bz->f2];
518
519 rcnt = zp->z1 - zp->z2;
520 if (rcnt < 0)
521 rcnt += B_FIFO_SIZE;
522 rcnt++;
523 if (cs->debug & L1_DEB_HSCX)
524 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
525 bcs->channel, zp->z1, zp->z2, rcnt);
526 if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
527 cli();
528 skb_queue_tail(&bcs->rqueue, skb);
529 sti();
530 hfcpci_sched_event(bcs, B_RCVBUFREADY);
531 }
532 rcnt = bz->f1 - bz->f2;
533 if (rcnt < 0)
534 rcnt += MAX_B_FRAMES + 1;
535 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
536 rcnt = 0;
537 hfcpci_clear_fifo_rx(cs, real_fifo);
538 }
539 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
540 if (rcnt > 1)
541 receive = 1;
542 else
543 receive = 0;
544 } else if (bcs->mode == L1_MODE_TRANS)
545 receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
546 else
547 receive = 0;
548 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
549 if (count && receive)
550 goto Begin;
551 restore_flags(flags);
552 return;
553 }
554
555 /**************************/
556 /* D-channel send routine */
557 /**************************/
558 static void
559 hfcpci_fill_dfifo(struct IsdnCardState *cs)
560 {
561 long flags;
562 int fcnt;
563 int count, new_z1, maxlen;
564 dfifo_type *df;
565 u_char *src, *dst, new_f1;
566
567 if (!cs->tx_skb)
568 return;
569 if (cs->tx_skb->len <= 0)
570 return;
571
572 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
573
574 if (cs->debug & L1_DEB_ISAC)
575 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
576 df->f1, df->f2,
577 df->za[df->f1 & D_FREG_MASK].z1);
578 fcnt = df->f1 - df->f2; /* frame count actually buffered */
579 if (fcnt < 0)
580 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
581 if (fcnt > (MAX_D_FRAMES - 1)) {
582 if (cs->debug & L1_DEB_ISAC)
583 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
584 #ifdef ERROR_STATISTIC
585 cs->err_tx++;
586 #endif
587 return;
588 }
589 /* now determine free bytes in FIFO buffer */
590 count = df->za[df->f1 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1;
591 if (count <= 0)
592 count += D_FIFO_SIZE; /* count now contains available bytes */
593
594 if (cs->debug & L1_DEB_ISAC)
595 debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
596 cs->tx_skb->len, count);
597 if (count < cs->tx_skb->len) {
598 if (cs->debug & L1_DEB_ISAC)
599 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
600 return;
601 }
602 count = cs->tx_skb->len; /* get frame len */
603 new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
604 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
605 src = cs->tx_skb->data; /* source pointer */
606 dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
607 maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */
608 if (maxlen > count)
609 maxlen = count; /* limit size */
610 memcpy(dst, src, maxlen); /* first copy */
611
612 count -= maxlen; /* remaining bytes */
613 if (count) {
614 dst = df->data; /* start of buffer */
615 src += maxlen; /* new position */
616 memcpy(dst, src, count);
617 }
618 save_flags(flags);
619 cli();
620 df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */
621 df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */
622 df->f1 = new_f1; /* next frame */
623 restore_flags(flags);
624
625 dev_kfree_skb_any(cs->tx_skb);
626 cs->tx_skb = NULL;
627 return;
628 }
629
630 /**************************/
631 /* B-channel send routine */
632 /**************************/
633 static void
634 hfcpci_fill_fifo(struct BCState *bcs)
635 {
636 struct IsdnCardState *cs = bcs->cs;
637 long flags;
638 int maxlen, fcnt;
639 int count, new_z1;
640 bzfifo_type *bz;
641 u_char *bdata;
642 u_char new_f1, *src, *dst;
643 unsigned short *z1t, *z2t;
644
645 if (!bcs->tx_skb)
646 return;
647 if (bcs->tx_skb->len <= 0)
648 return;
649
650 save_flags(flags);
651 sti();
652
653 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
654 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
655 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
656 } else {
657 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
658 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
659 }
660
661 if (bcs->mode == L1_MODE_TRANS) {
662 z1t = &bz->za[MAX_B_FRAMES].z1;
663 z2t = z1t + 1;
664 if (cs->debug & L1_DEB_HSCX)
665 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
666 bcs->channel, *z1t, *z2t);
667 fcnt = *z2t - *z1t;
668 if (fcnt <= 0)
669 fcnt += B_FIFO_SIZE; /* fcnt contains available bytes in fifo */
670 fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */
671
672 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
673 if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
674 /* data is suitable for fifo */
675 count = bcs->tx_skb->len;
676
677 new_z1 = *z1t + count; /* new buffer Position */
678 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
679 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
680 src = bcs->tx_skb->data; /* source pointer */
681 dst = bdata + (*z1t - B_SUB_VAL);
682 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */
683 if (maxlen > count)
684 maxlen = count; /* limit size */
685 memcpy(dst, src, maxlen); /* first copy */
686
687 count -= maxlen; /* remaining bytes */
688 if (count) {
689 dst = bdata; /* start of buffer */
690 src += maxlen; /* new position */
691 memcpy(dst, src, count);
692 }
693 bcs->tx_cnt -= bcs->tx_skb->len;
694 fcnt += bcs->tx_skb->len;
695 *z1t = new_z1; /* now send data */
696 } else if (cs->debug & L1_DEB_HSCX)
697 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
698 bcs->channel, bcs->tx_skb->len);
699
700 dev_kfree_skb_any(bcs->tx_skb);
701 cli();
702 bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */
703 sti();
704 }
705 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
706 restore_flags(flags);
707 return;
708 }
709 if (cs->debug & L1_DEB_HSCX)
710 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
711 bcs->channel, bz->f1, bz->f2,
712 bz->za[bz->f1].z1);
713
714 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
715 if (fcnt < 0)
716 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
717 if (fcnt > (MAX_B_FRAMES - 1)) {
718 if (cs->debug & L1_DEB_HSCX)
719 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
720 restore_flags(flags);
721 return;
722 }
723 /* now determine free bytes in FIFO buffer */
724 count = bz->za[bz->f1].z2 - bz->za[bz->f1].z1;
725 if (count <= 0)
726 count += B_FIFO_SIZE; /* count now contains available bytes */
727
728 if (cs->debug & L1_DEB_HSCX)
729 debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
730 bcs->channel, bcs->tx_skb->len,
731 count, current->state);
732
733 if (count < bcs->tx_skb->len) {
734 if (cs->debug & L1_DEB_HSCX)
735 debugl1(cs, "hfcpci_fill_fifo no fifo mem");
736 restore_flags(flags);
737 return;
738 }
739 count = bcs->tx_skb->len; /* get frame len */
740 new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */
741 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
742 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
743
744 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
745 src = bcs->tx_skb->data; /* source pointer */
746 dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
747 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */
748 if (maxlen > count)
749 maxlen = count; /* limit size */
750 memcpy(dst, src, maxlen); /* first copy */
751
752 count -= maxlen; /* remaining bytes */
753 if (count) {
754 dst = bdata; /* start of buffer */
755 src += maxlen; /* new position */
756 memcpy(dst, src, count);
757 }
758 bcs->tx_cnt -= bcs->tx_skb->len;
759 if (bcs->st->lli.l1writewakeup &&
760 (PACKET_NOACK != bcs->tx_skb->pkt_type))
761 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
762
763 cli();
764 bz->za[new_f1].z1 = new_z1; /* for next buffer */
765 bz->f1 = new_f1; /* next frame */
766 restore_flags(flags);
767
768 dev_kfree_skb_any(bcs->tx_skb);
769 bcs->tx_skb = NULL;
770 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
771 return;
772 }
773
774 /**********************************************/
775 /* D-channel l1 state call for leased NT-mode */
776 /**********************************************/
777 static void
778 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
779 {
780 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
781
782 switch (pr) {
783 case (PH_DATA | REQUEST):
784 case (PH_PULL | REQUEST):
785 case (PH_PULL | INDICATION):
786 st->l1.l1hw(st, pr, arg);
787 break;
788 case (PH_ACTIVATE | REQUEST):
789 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
790 break;
791 case (PH_TESTLOOP | REQUEST):
792 if (1 & (long) arg)
793 debugl1(cs, "PH_TEST_LOOP B1");
794 if (2 & (long) arg)
795 debugl1(cs, "PH_TEST_LOOP B2");
796 if (!(3 & (long) arg))
797 debugl1(cs, "PH_TEST_LOOP DISABLED");
798 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
799 break;
800 default:
801 if (cs->debug)
802 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
803 break;
804 }
805 }
806
807
808
809 /***********************/
810 /* set/reset echo mode */
811 /***********************/
812 static int
813 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
814 {
815 long flags;
816 int i = *(unsigned int *) ic->parm.num;
817
818 if ((ic->arg == 98) &&
819 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
820 save_flags(flags);
821 cli();
822 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
823 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */
824 udelay(10);
825 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
826 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
827 udelay(10);
828 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */
829 udelay(10);
830 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
831 cs->dc.hfcpci.ph_state = 1;
832 cs->hw.hfcpci.nt_mode = 1;
833 cs->hw.hfcpci.nt_timer = 0;
834 cs->stlist->l2.l2l1 = dch_nt_l2l1;
835 restore_flags(flags);
836 debugl1(cs, "NT mode activated");
837 return (0);
838 }
839 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
840 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
841 return (-EINVAL);
842
843 save_flags(flags);
844 cli();
845 if (i) {
846 cs->logecho = 1;
847 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
848 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
849 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
850 } else {
851 cs->logecho = 0;
852 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
853 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
854 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
855 }
856 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
857 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
858 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
859 cs->hw.hfcpci.ctmt &= ~2;
860 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
861 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
862 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
863 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
864 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
865 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
866 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
867 restore_flags(flags);
868 return (0);
869 } /* hfcpci_auxcmd */
870
871 /*****************************/
872 /* E-channel receive routine */
873 /*****************************/
874 static void
875 receive_emsg(struct IsdnCardState *cs)
876 {
877 long flags;
878 int rcnt;
879 int receive, count = 5;
880 bzfifo_type *bz;
881 u_char *bdata;
882 z_type *zp;
883 u_char *ptr, *ptr1, new_f2;
884 int total, maxlen, new_z2;
885 u_char e_buffer[256];
886
887 save_flags(flags);
888 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
889 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
890 Begin:
891 count--;
892 cli();
893 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
894 debugl1(cs, "echo_rec_data blocked");
895 restore_flags(flags);
896 return;
897 }
898 sti();
899 if (bz->f1 != bz->f2) {
900 if (cs->debug & L1_DEB_ISAC)
901 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
902 bz->f1, bz->f2);
903 zp = &bz->za[bz->f2];
904
905 rcnt = zp->z1 - zp->z2;
906 if (rcnt < 0)
907 rcnt += B_FIFO_SIZE;
908 rcnt++;
909 if (cs->debug & L1_DEB_ISAC)
910 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
911 zp->z1, zp->z2, rcnt);
912 new_z2 = zp->z2 + rcnt; /* new position in fifo */
913 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
914 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
915 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
916 if ((rcnt > 256 + 3) || (count < 4) ||
917 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
918 if (cs->debug & L1_DEB_WARN)
919 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
920 bz->za[new_f2].z2 = new_z2;
921 bz->f2 = new_f2; /* next buffer */
922 } else {
923 total = rcnt;
924 rcnt -= 3;
925 ptr = e_buffer;
926
927 if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
928 maxlen = rcnt; /* complete transfer */
929 else
930 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
931
932 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
933 memcpy(ptr, ptr1, maxlen); /* copy data */
934 rcnt -= maxlen;
935
936 if (rcnt) { /* rest remaining */
937 ptr += maxlen;
938 ptr1 = bdata; /* start of buffer */
939 memcpy(ptr, ptr1, rcnt); /* rest */
940 }
941 bz->za[new_f2].z2 = new_z2;
942 bz->f2 = new_f2; /* next buffer */
943 if (cs->debug & DEB_DLOG_HEX) {
944 ptr = cs->dlog;
945 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
946 *ptr++ = 'E';
947 *ptr++ = 'C';
948 *ptr++ = 'H';
949 *ptr++ = 'O';
950 *ptr++ = ':';
951 ptr += QuickHex(ptr, e_buffer, total - 3);
952 ptr--;
953 *ptr++ = '\n';
954 *ptr = 0;
955 HiSax_putstatus(cs, NULL, cs->dlog);
956 } else
957 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
958 }
959 }
960
961 rcnt = bz->f1 - bz->f2;
962 if (rcnt < 0)
963 rcnt += MAX_B_FRAMES + 1;
964 if (rcnt > 1)
965 receive = 1;
966 else
967 receive = 0;
968 } else
969 receive = 0;
970 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
971 if (count && receive)
972 goto Begin;
973 restore_flags(flags);
974 return;
975 } /* receive_emsg */
976
977 /*********************/
978 /* Interrupt handler */
979 /*********************/
980 static void
981 hfcpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
982 {
983 struct IsdnCardState *cs = dev_id;
984 u_char exval;
985 struct BCState *bcs;
986 int count = 15;
987 long flags;
988 u_char val, stat;
989
990 if (!cs) {
991 printk(KERN_WARNING "HFC-PCI: Spurious interrupt!\n");
992 return;
993 }
994 if (!(cs->hw.hfcpci.int_m2 & 0x08))
995 return; /* not initialised */
996
997 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
998 val = Read_hfc(cs, HFCPCI_INT_S1);
999 if (cs->debug & L1_DEB_ISAC)
1000 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
1001 } else
1002 return;
1003
1004 if (cs->debug & L1_DEB_ISAC)
1005 debugl1(cs, "HFC-PCI irq %x %s", val,
1006 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
1007 "locked" : "unlocked");
1008 val &= cs->hw.hfcpci.int_m1;
1009 if (val & 0x40) { /* state machine irq */
1010 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
1011 if (cs->debug & L1_DEB_ISAC)
1012 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
1013 exval);
1014 cs->dc.hfcpci.ph_state = exval;
1015 sched_event_D_pci(cs, D_L1STATECHANGE);
1016 val &= ~0x40;
1017 }
1018 if (val & 0x80) { /* timer irq */
1019 if (cs->hw.hfcpci.nt_mode) {
1020 if ((--cs->hw.hfcpci.nt_timer) < 0)
1021 sched_event_D_pci(cs, D_L1STATECHANGE);
1022 }
1023 val &= ~0x80;
1024 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1025 }
1026 while (val) {
1027 save_flags(flags);
1028 cli();
1029 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1030 cs->hw.hfcpci.int_s1 |= val;
1031 restore_flags(flags);
1032 return;
1033 }
1034 if (cs->hw.hfcpci.int_s1 & 0x18) {
1035 exval = val;
1036 val = cs->hw.hfcpci.int_s1;
1037 cs->hw.hfcpci.int_s1 = exval;
1038 }
1039 if (val & 0x08) {
1040 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1041 if (cs->debug)
1042 debugl1(cs, "hfcpci spurious 0x08 IRQ");
1043 } else
1044 main_rec_hfcpci(bcs);
1045 }
1046 if (val & 0x10) {
1047 if (cs->logecho)
1048 receive_emsg(cs);
1049 else if (!(bcs = Sel_BCS(cs, 1))) {
1050 if (cs->debug)
1051 debugl1(cs, "hfcpci spurious 0x10 IRQ");
1052 } else
1053 main_rec_hfcpci(bcs);
1054 }
1055 if (val & 0x01) {
1056 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1057 if (cs->debug)
1058 debugl1(cs, "hfcpci spurious 0x01 IRQ");
1059 } else {
1060 if (bcs->tx_skb) {
1061 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1062 hfcpci_fill_fifo(bcs);
1063 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1064 } else
1065 debugl1(cs, "fill_data %d blocked", bcs->channel);
1066 } else {
1067 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1068 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1069 hfcpci_fill_fifo(bcs);
1070 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1071 } else
1072 debugl1(cs, "fill_data %d blocked", bcs->channel);
1073 } else {
1074 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1075 }
1076 }
1077 }
1078 }
1079 if (val & 0x02) {
1080 if (!(bcs = Sel_BCS(cs, 1))) {
1081 if (cs->debug)
1082 debugl1(cs, "hfcpci spurious 0x02 IRQ");
1083 } else {
1084 if (bcs->tx_skb) {
1085 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1086 hfcpci_fill_fifo(bcs);
1087 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1088 } else
1089 debugl1(cs, "fill_data %d blocked", bcs->channel);
1090 } else {
1091 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1092 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1093 hfcpci_fill_fifo(bcs);
1094 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1095 } else
1096 debugl1(cs, "fill_data %d blocked", bcs->channel);
1097 } else {
1098 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1099 }
1100 }
1101 }
1102 }
1103 if (val & 0x20) { /* receive dframe */
1104 receive_dmsg(cs);
1105 }
1106 if (val & 0x04) { /* dframe transmitted */
1107 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
1108 del_timer(&cs->dbusytimer);
1109 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
1110 sched_event_D_pci(cs, D_CLEARBUSY);
1111 if (cs->tx_skb) {
1112 if (cs->tx_skb->len) {
1113 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1114 hfcpci_fill_dfifo(cs);
1115 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1116 } else {
1117 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1118 }
1119 goto afterXPR;
1120 } else {
1121 dev_kfree_skb_irq(cs->tx_skb);
1122 cs->tx_cnt = 0;
1123 cs->tx_skb = NULL;
1124 }
1125 }
1126 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
1127 cs->tx_cnt = 0;
1128 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1129 hfcpci_fill_dfifo(cs);
1130 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1131 } else {
1132 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1133 }
1134 } else
1135 sched_event_D_pci(cs, D_XMTBUFREADY);
1136 }
1137 afterXPR:
1138 if (cs->hw.hfcpci.int_s1 && count--) {
1139 val = cs->hw.hfcpci.int_s1;
1140 cs->hw.hfcpci.int_s1 = 0;
1141 if (cs->debug & L1_DEB_ISAC)
1142 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
1143 } else
1144 val = 0;
1145 restore_flags(flags);
1146 }
1147 }
1148
1149 /********************************************************************/
1150 /* timer callback for D-chan busy resolution. Currently no function */
1151 /********************************************************************/
1152 static void
1153 hfcpci_dbusy_timer(struct IsdnCardState *cs)
1154 {
1155 }
1156
1157 /*************************************/
1158 /* Layer 1 D-channel hardware access */
1159 /*************************************/
1160 static void
1161 HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
1162 {
1163 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1164 struct sk_buff *skb = arg;
1165 long flags;
1166
1167 switch (pr) {
1168 case (PH_DATA | REQUEST):
1169 if (cs->debug & DEB_DLOG_HEX)
1170 LogFrame(cs, skb->data, skb->len);
1171 if (cs->debug & DEB_DLOG_VERBOSE)
1172 dlogframe(cs, skb, 0);
1173 if (cs->tx_skb) {
1174 skb_queue_tail(&cs->sq, skb);
1175 #ifdef L2FRAME_DEBUG /* psa */
1176 if (cs->debug & L1_DEB_LAPD)
1177 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1178 #endif
1179 } else {
1180 cs->tx_skb = skb;
1181 cs->tx_cnt = 0;
1182 #ifdef L2FRAME_DEBUG /* psa */
1183 if (cs->debug & L1_DEB_LAPD)
1184 Logl2Frame(cs, skb, "PH_DATA", 0);
1185 #endif
1186 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1187 hfcpci_fill_dfifo(cs);
1188 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1189 } else
1190 debugl1(cs, "hfcpci_fill_dfifo blocked");
1191
1192 }
1193 break;
1194 case (PH_PULL | INDICATION):
1195 if (cs->tx_skb) {
1196 if (cs->debug & L1_DEB_WARN)
1197 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1198 skb_queue_tail(&cs->sq, skb);
1199 break;
1200 }
1201 if (cs->debug & DEB_DLOG_HEX)
1202 LogFrame(cs, skb->data, skb->len);
1203 if (cs->debug & DEB_DLOG_VERBOSE)
1204 dlogframe(cs, skb, 0);
1205 cs->tx_skb = skb;
1206 cs->tx_cnt = 0;
1207 #ifdef L2FRAME_DEBUG /* psa */
1208 if (cs->debug & L1_DEB_LAPD)
1209 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1210 #endif
1211 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1212 hfcpci_fill_dfifo(cs);
1213 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1214 } else
1215 debugl1(cs, "hfcpci_fill_dfifo blocked");
1216 break;
1217 case (PH_PULL | REQUEST):
1218 #ifdef L2FRAME_DEBUG /* psa */
1219 if (cs->debug & L1_DEB_LAPD)
1220 debugl1(cs, "-> PH_REQUEST_PULL");
1221 #endif
1222 if (!cs->tx_skb) {
1223 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1224 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1225 } else
1226 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1227 break;
1228 case (HW_RESET | REQUEST):
1229 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */
1230 udelay(6);
1231 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */
1232 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1233 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1234 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1235 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1236 break;
1237 case (HW_ENABLE | REQUEST):
1238 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
1239 break;
1240 case (HW_DEACTIVATE | REQUEST):
1241 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1242 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1243 break;
1244 case (HW_INFO3 | REQUEST):
1245 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1246 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1247 break;
1248 case (HW_TESTLOOP | REQUEST):
1249 switch ((int) arg) {
1250 case (1):
1251 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */
1252 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */
1253 save_flags(flags);
1254 cli();
1255 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1256 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1257 restore_flags(flags);
1258 break;
1259
1260 case (2):
1261 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */
1262 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */
1263 save_flags(flags);
1264 cli();
1265 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1266 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1267 restore_flags(flags);
1268 break;
1269
1270 default:
1271 if (cs->debug & L1_DEB_WARN)
1272 debugl1(cs, "hfcpci_l1hw loop invalid %4x", (int) arg);
1273 return;
1274 }
1275 save_flags(flags);
1276 cli();
1277 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
1278 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1279 restore_flags(flags);
1280 break;
1281 default:
1282 if (cs->debug & L1_DEB_WARN)
1283 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1284 break;
1285 }
1286 }
1287
1288 /***********************************************/
1289 /* called during init setting l1 stack pointer */
1290 /***********************************************/
1291 void
1292 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
1293 {
1294 st->l1.l1hw = HFCPCI_l1hw;
1295 }
1296
1297 /**************************************/
1298 /* send B-channel data if not blocked */
1299 /**************************************/
1300 static void
1301 hfcpci_send_data(struct BCState *bcs)
1302 {
1303 struct IsdnCardState *cs = bcs->cs;
1304
1305 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1306 hfcpci_fill_fifo(bcs);
1307 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1308 } else
1309 debugl1(cs, "send_data %d blocked", bcs->channel);
1310 }
1311
1312 /***************************************************************/
1313 /* activate/deactivate hardware for selected channels and mode */
1314 /***************************************************************/
1315 void
1316 mode_hfcpci(struct BCState *bcs, int mode, int bc)
1317 {
1318 struct IsdnCardState *cs = bcs->cs;
1319 long flags;
1320 int fifo2;
1321
1322 if (cs->debug & L1_DEB_HSCX)
1323 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
1324 mode, bc, bcs->channel);
1325 bcs->mode = mode;
1326 bcs->channel = bc;
1327 fifo2 = bc;
1328 save_flags(flags);
1329 cli();
1330 if (cs->chanlimit > 1) {
1331 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1332 cs->hw.hfcpci.sctrl_e &= ~0x80;
1333 } else {
1334 if (bc) {
1335 if (mode != L1_MODE_NULL) {
1336 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
1337 cs->hw.hfcpci.sctrl_e |= 0x80;
1338 } else {
1339 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1340 cs->hw.hfcpci.sctrl_e &= ~0x80;
1341 }
1342 fifo2 = 0;
1343 } else {
1344 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1345 cs->hw.hfcpci.sctrl_e &= ~0x80;
1346 }
1347 }
1348 switch (mode) {
1349 case (L1_MODE_NULL):
1350 if (bc) {
1351 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1352 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1353 } else {
1354 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1355 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1356 }
1357 if (fifo2) {
1358 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1359 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1360 } else {
1361 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1362 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1363 }
1364 break;
1365 case (L1_MODE_TRANS):
1366 hfcpci_clear_fifo_rx(cs, fifo2);
1367 hfcpci_clear_fifo_tx(cs, fifo2);
1368 if (bc) {
1369 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1370 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1371 } else {
1372 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1373 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1374 }
1375 if (fifo2) {
1376 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1377 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1378 cs->hw.hfcpci.ctmt |= 2;
1379 cs->hw.hfcpci.conn &= ~0x18;
1380 } else {
1381 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1382 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1383 cs->hw.hfcpci.ctmt |= 1;
1384 cs->hw.hfcpci.conn &= ~0x03;
1385 }
1386 break;
1387 case (L1_MODE_HDLC):
1388 hfcpci_clear_fifo_rx(cs, fifo2);
1389 hfcpci_clear_fifo_tx(cs, fifo2);
1390 if (bc) {
1391 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1392 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1393 } else {
1394 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1395 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1396 }
1397 if (fifo2) {
1398 cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
1399 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1400 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1401 cs->hw.hfcpci.ctmt &= ~2;
1402 cs->hw.hfcpci.conn &= ~0x18;
1403 } else {
1404 cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
1405 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1406 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1407 cs->hw.hfcpci.ctmt &= ~1;
1408 cs->hw.hfcpci.conn &= ~0x03;
1409 }
1410 break;
1411 case (L1_MODE_EXTRN):
1412 if (bc) {
1413 cs->hw.hfcpci.conn |= 0x10;
1414 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1415 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1416 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1417 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1418 } else {
1419 cs->hw.hfcpci.conn |= 0x02;
1420 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1421 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1422 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1423 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1424 }
1425 break;
1426 }
1427 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1428 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1429 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1430 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1431 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1432 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1433 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1434 restore_flags(flags);
1435 }
1436
1437 /******************************/
1438 /* Layer2 -> Layer 1 Transfer */
1439 /******************************/
1440 static void
1441 hfcpci_l2l1(struct PStack *st, int pr, void *arg)
1442 {
1443 struct sk_buff *skb = arg;
1444 long flags;
1445
1446 switch (pr) {
1447 case (PH_DATA | REQUEST):
1448 save_flags(flags);
1449 cli();
1450 if (st->l1.bcs->tx_skb) {
1451 skb_queue_tail(&st->l1.bcs->squeue, skb);
1452 restore_flags(flags);
1453 } else {
1454 st->l1.bcs->tx_skb = skb;
1455 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1456 */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1457 restore_flags(flags);
1458 }
1459 break;
1460 case (PH_PULL | INDICATION):
1461 if (st->l1.bcs->tx_skb) {
1462 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1463 break;
1464 }
1465 save_flags(flags);
1466 cli();
1467 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1468 */ st->l1.bcs->tx_skb = skb;
1469 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1470 restore_flags(flags);
1471 break;
1472 case (PH_PULL | REQUEST):
1473 if (!st->l1.bcs->tx_skb) {
1474 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1475 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1476 } else
1477 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1478 break;
1479 case (PH_ACTIVATE | REQUEST):
1480 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1481 mode_hfcpci(st->l1.bcs, st->l1.mode, st->l1.bc);
1482 l1_msg_b(st, pr, arg);
1483 break;
1484 case (PH_DEACTIVATE | REQUEST):
1485 l1_msg_b(st, pr, arg);
1486 break;
1487 case (PH_DEACTIVATE | CONFIRM):
1488 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1489 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1490 mode_hfcpci(st->l1.bcs, 0, st->l1.bc);
1491 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1492 break;
1493 }
1494 }
1495
1496 /******************************************/
1497 /* deactivate B-channel access and queues */
1498 /******************************************/
1499 static void
1500 close_hfcpci(struct BCState *bcs)
1501 {
1502 mode_hfcpci(bcs, 0, bcs->channel);
1503 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1504 skb_queue_purge(&bcs->rqueue);
1505 skb_queue_purge(&bcs->squeue);
1506 if (bcs->tx_skb) {
1507 dev_kfree_skb_any(bcs->tx_skb);
1508 bcs->tx_skb = NULL;
1509 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1510 }
1511 }
1512 }
1513
1514 /*************************************/
1515 /* init B-channel queues and control */
1516 /*************************************/
1517 static int
1518 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
1519 {
1520 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1521 skb_queue_head_init(&bcs->rqueue);
1522 skb_queue_head_init(&bcs->squeue);
1523 }
1524 bcs->tx_skb = NULL;
1525 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1526 bcs->event = 0;
1527 bcs->tx_cnt = 0;
1528 return (0);
1529 }
1530
1531 /*********************************/
1532 /* inits the stack for B-channel */
1533 /*********************************/
1534 static int
1535 setstack_2b(struct PStack *st, struct BCState *bcs)
1536 {
1537 bcs->channel = st->l1.bc;
1538 if (open_hfcpcistate(st->l1.hardware, bcs))
1539 return (-1);
1540 st->l1.bcs = bcs;
1541 st->l2.l2l1 = hfcpci_l2l1;
1542 setstack_manager(st);
1543 bcs->st = st;
1544 setstack_l1_B(st);
1545 return (0);
1546 }
1547
1548 /***************************/
1549 /* handle L1 state changes */
1550 /***************************/
1551 static void
1552 hfcpci_bh(struct IsdnCardState *cs)
1553 {
1554 long flags;
1555 /* struct PStack *stptr;
1556 */
1557 if (!cs)
1558 return;
1559 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1560 if (!cs->hw.hfcpci.nt_mode)
1561 switch (cs->dc.hfcpci.ph_state) {
1562 case (0):
1563 l1_msg(cs, HW_RESET | INDICATION, NULL);
1564 break;
1565 case (3):
1566 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1567 break;
1568 case (8):
1569 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1570 break;
1571 case (6):
1572 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1573 break;
1574 case (7):
1575 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1576 break;
1577 default:
1578 break;
1579 } else {
1580 switch (cs->dc.hfcpci.ph_state) {
1581 case (2):
1582 save_flags(flags);
1583 cli();
1584 if (cs->hw.hfcpci.nt_timer < 0) {
1585 cs->hw.hfcpci.nt_timer = 0;
1586 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1587 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1588 /* Clear already pending ints */
1589 if (Read_hfc(cs, HFCPCI_INT_S1));
1590
1591 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1592 udelay(10);
1593 Write_hfc(cs, HFCPCI_STATES, 4);
1594 cs->dc.hfcpci.ph_state = 4;
1595 } else {
1596 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1597 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1598 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1599 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1600 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1601 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1602 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1603 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */
1604 }
1605 restore_flags(flags);
1606 break;
1607 case (1):
1608 case (3):
1609 case (4):
1610 save_flags(flags);
1611 cli();
1612 cs->hw.hfcpci.nt_timer = 0;
1613 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1614 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1615 restore_flags(flags);
1616 break;
1617 default:
1618 break;
1619 }
1620 }
1621 }
1622 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1623 DChannel_proc_rcv(cs);
1624 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1625 DChannel_proc_xmt(cs);
1626 }
1627
1628
1629 /********************************/
1630 /* called for card init message */
1631 /********************************/
1632 void __init
1633 inithfcpci(struct IsdnCardState *cs)
1634 {
1635 cs->setstack_d = setstack_hfcpci;
1636 cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
1637 cs->dbusytimer.data = (long) cs;
1638 init_timer(&cs->dbusytimer);
1639 cs->tqueue.routine = (void *) (void *) hfcpci_bh;
1640 cs->BC_Send_Data = &hfcpci_send_data;
1641 cs->bcs[0].BC_SetStack = setstack_2b;
1642 cs->bcs[1].BC_SetStack = setstack_2b;
1643 cs->bcs[0].BC_Close = close_hfcpci;
1644 cs->bcs[1].BC_Close = close_hfcpci;
1645 mode_hfcpci(cs->bcs, 0, 0);
1646 mode_hfcpci(cs->bcs + 1, 0, 1);
1647 }
1648
1649
1650
1651 /*******************************************/
1652 /* handle card messages from control layer */
1653 /*******************************************/
1654 static int
1655 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1656 {
1657 long flags;
1658
1659 if (cs->debug & L1_DEB_ISAC)
1660 debugl1(cs, "HFCPCI: card_msg %x", mt);
1661 switch (mt) {
1662 case CARD_RESET:
1663 reset_hfcpci(cs);
1664 return (0);
1665 case CARD_RELEASE:
1666 release_io_hfcpci(cs);
1667 return (0);
1668 case CARD_INIT:
1669 inithfcpci(cs);
1670 save_flags(flags);
1671 sti();
1672 set_current_state(TASK_UNINTERRUPTIBLE);
1673 schedule_timeout((80 * HZ) / 1000); /* Timeout 80ms */
1674 /* now switch timer interrupt off */
1675 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1676 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1677 /* reinit mode reg */
1678 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1679 restore_flags(flags);
1680 return (0);
1681 case CARD_TEST:
1682 return (0);
1683 }
1684 return (0);
1685 }
1686
1687
1688 /* this variable is used as card index when more than one cards are present */
1689 static struct pci_dev *dev_hfcpci __initdata = NULL;
1690
1691 #endif /* CONFIG_PCI */
1692
1693 int __init
1694 setup_hfcpci(struct IsdnCard *card)
1695 {
1696 struct IsdnCardState *cs = card->cs;
1697 char tmp[64];
1698 int i;
1699 struct pci_dev *tmp_hfcpci = NULL;
1700
1701 #ifdef __BIG_ENDIAN
1702 #error "not running on big endian machines now"
1703 #endif
1704 strcpy(tmp, hfcpci_revision);
1705 printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
1706 #if CONFIG_PCI
1707 cs->hw.hfcpci.int_s1 = 0;
1708 cs->dc.hfcpci.ph_state = 0;
1709 cs->hw.hfcpci.fifo = 255;
1710 if (cs->typ == ISDN_CTYPE_HFC_PCI) {
1711 i = 0;
1712 while (id_list[i].vendor_id) {
1713 tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
1714 id_list[i].device_id,
1715 dev_hfcpci);
1716 i++;
1717 if (tmp_hfcpci) {
1718 if (pci_enable_device(tmp_hfcpci))
1719 continue;
1720 pci_set_master(tmp_hfcpci);
1721 if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
1722 continue;
1723 else
1724 break;
1725 }
1726 }
1727
1728 if (tmp_hfcpci) {
1729 i--;
1730 dev_hfcpci = tmp_hfcpci; /* old device */
1731 cs->hw.hfcpci.pci_bus = dev_hfcpci->bus->number;
1732 cs->hw.hfcpci.pci_device_fn = dev_hfcpci->devfn;
1733 cs->irq = dev_hfcpci->irq;
1734 if (!cs->irq) {
1735 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1736 return (0);
1737 }
1738 cs->hw.hfcpci.pci_io = (char *) dev_hfcpci->resource[ 1].start;
1739 printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
1740 } else {
1741 printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
1742 return (0);
1743 }
1744 if (!cs->hw.hfcpci.pci_io) {
1745 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1746 return (0);
1747 }
1748 /* Allocate memory for FIFOS */
1749 /* Because the HFC-PCI needs a 32K physical alignment, we */
1750 /* need to allocate the double mem and align the address */
1751 if (!((void *) cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) {
1752 printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n");
1753 return 0;
1754 }
1755 (ulong) cs->hw.hfcpci.fifos =
1756 (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000;
1757 pcibios_write_config_dword(cs->hw.hfcpci.pci_bus,
1758 cs->hw.hfcpci.pci_device_fn, 0x80,
1759 (u_int) virt_to_bus(cs->hw.hfcpci.fifos));
1760 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1761 printk(KERN_INFO
1762 "HFC-PCI: defined at mem %#x fifo %#x(%#x) IRQ %d HZ %d\n",
1763 (u_int) cs->hw.hfcpci.pci_io,
1764 (u_int) cs->hw.hfcpci.fifos,
1765 (u_int) virt_to_bus(cs->hw.hfcpci.fifos),
1766 cs->irq, HZ);
1767 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
1768 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
1769 cs->hw.hfcpci.int_m1 = 0;
1770 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1771 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1772 /* At this point the needed PCI config is done */
1773 /* fifos are still not enabled */
1774 } else
1775 return (0); /* no valid card type */
1776
1777
1778 cs->readisac = NULL;
1779 cs->writeisac = NULL;
1780 cs->readisacfifo = NULL;
1781 cs->writeisacfifo = NULL;
1782 cs->BC_Read_Reg = NULL;
1783 cs->BC_Write_Reg = NULL;
1784 cs->irq_func = &hfcpci_interrupt;
1785 cs->irq_flags |= SA_SHIRQ;
1786
1787 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1788 cs->hw.hfcpci.timer.data = (long) cs;
1789 init_timer(&cs->hw.hfcpci.timer);
1790
1791 reset_hfcpci(cs);
1792 cs->cardmsg = &hfcpci_card_msg;
1793 cs->auxcmd = &hfcpci_auxcmd;
1794 return (1);
1795 #else
1796 printk(KERN_WARNING "HFC-PCI: NO_PCI_BIOS\n");
1797 return (0);
1798 #endif /* CONFIG_PCI */
1799 }
1800