File: /usr/src/linux/drivers/isdn/hisax/hfc_sx.h
1 /* $Id: hfc_sx.h,v 1.2 2000/06/26 08:59:13 keil Exp $
2 *
3 * specific defines for CCD's HFC 2BDS0 S+,SP chips
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 *
7 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 /*********************************************/
26 /* thresholds for transparent B-channel mode */
27 /* change mask and threshold simultaneously */
28 /*********************************************/
29 #define HFCSX_BTRANS_THRESHOLD 128
30 #define HFCSX_BTRANS_THRESMASK 0x00
31
32 /* GCI/IOM bus monitor registers */
33
34 #define HFCSX_C_I 0x02
35 #define HFCSX_TRxR 0x03
36 #define HFCSX_MON1_D 0x0A
37 #define HFCSX_MON2_D 0x0B
38
39
40 /* GCI/IOM bus timeslot registers */
41
42 #define HFCSX_B1_SSL 0x20
43 #define HFCSX_B2_SSL 0x21
44 #define HFCSX_AUX1_SSL 0x22
45 #define HFCSX_AUX2_SSL 0x23
46 #define HFCSX_B1_RSL 0x24
47 #define HFCSX_B2_RSL 0x25
48 #define HFCSX_AUX1_RSL 0x26
49 #define HFCSX_AUX2_RSL 0x27
50
51 /* GCI/IOM bus data registers */
52
53 #define HFCSX_B1_D 0x28
54 #define HFCSX_B2_D 0x29
55 #define HFCSX_AUX1_D 0x2A
56 #define HFCSX_AUX2_D 0x2B
57
58 /* GCI/IOM bus configuration registers */
59
60 #define HFCSX_MST_EMOD 0x2D
61 #define HFCSX_MST_MODE 0x2E
62 #define HFCSX_CONNECT 0x2F
63
64
65 /* Interrupt and status registers */
66
67 #define HFCSX_TRM 0x12
68 #define HFCSX_B_MODE 0x13
69 #define HFCSX_CHIP_ID 0x16
70 #define HFCSX_CIRM 0x18
71 #define HFCSX_CTMT 0x19
72 #define HFCSX_INT_M1 0x1A
73 #define HFCSX_INT_M2 0x1B
74 #define HFCSX_INT_S1 0x1E
75 #define HFCSX_INT_S2 0x1F
76 #define HFCSX_STATUS 0x1C
77
78 /* S/T section registers */
79
80 #define HFCSX_STATES 0x30
81 #define HFCSX_SCTRL 0x31
82 #define HFCSX_SCTRL_E 0x32
83 #define HFCSX_SCTRL_R 0x33
84 #define HFCSX_SQ 0x34
85 #define HFCSX_CLKDEL 0x37
86 #define HFCSX_B1_REC 0x3C
87 #define HFCSX_B1_SEND 0x3C
88 #define HFCSX_B2_REC 0x3D
89 #define HFCSX_B2_SEND 0x3D
90 #define HFCSX_D_REC 0x3E
91 #define HFCSX_D_SEND 0x3E
92 #define HFCSX_E_REC 0x3F
93
94 /****************/
95 /* FIFO section */
96 /****************/
97 #define HFCSX_FIF_SEL 0x10
98 #define HFCSX_FIF_Z1L 0x80
99 #define HFCSX_FIF_Z1H 0x84
100 #define HFCSX_FIF_Z2L 0x88
101 #define HFCSX_FIF_Z2H 0x8C
102 #define HFCSX_FIF_INCF1 0xA8
103 #define HFCSX_FIF_DWR 0xAC
104 #define HFCSX_FIF_F1 0xB0
105 #define HFCSX_FIF_F2 0xB4
106 #define HFCSX_FIF_INCF2 0xB8
107 #define HFCSX_FIF_DRD 0xBC
108
109 /* bits in status register (READ) */
110 #define HFCSX_SX_PROC 0x02
111 #define HFCSX_NBUSY 0x04
112 #define HFCSX_TIMER_ELAP 0x10
113 #define HFCSX_STATINT 0x20
114 #define HFCSX_FRAMEINT 0x40
115 #define HFCSX_ANYINT 0x80
116
117 /* bits in CTMT (Write) */
118 #define HFCSX_CLTIMER 0x80
119 #define HFCSX_TIM3_125 0x04
120 #define HFCSX_TIM25 0x10
121 #define HFCSX_TIM50 0x14
122 #define HFCSX_TIM400 0x18
123 #define HFCSX_TIM800 0x1C
124 #define HFCSX_AUTO_TIMER 0x20
125 #define HFCSX_TRANSB2 0x02
126 #define HFCSX_TRANSB1 0x01
127
128 /* bits in CIRM (Write) */
129 #define HFCSX_IRQ_SELMSK 0x07
130 #define HFCSX_IRQ_SELDIS 0x00
131 #define HFCSX_RESET 0x08
132 #define HFCSX_FIFO_RESET 0x80
133
134
135 /* bits in INT_M1 and INT_S1 */
136 #define HFCSX_INTS_B1TRANS 0x01
137 #define HFCSX_INTS_B2TRANS 0x02
138 #define HFCSX_INTS_DTRANS 0x04
139 #define HFCSX_INTS_B1REC 0x08
140 #define HFCSX_INTS_B2REC 0x10
141 #define HFCSX_INTS_DREC 0x20
142 #define HFCSX_INTS_L1STATE 0x40
143 #define HFCSX_INTS_TIMER 0x80
144
145 /* bits in INT_M2 */
146 #define HFCSX_PROC_TRANS 0x01
147 #define HFCSX_GCI_I_CHG 0x02
148 #define HFCSX_GCI_MON_REC 0x04
149 #define HFCSX_IRQ_ENABLE 0x08
150
151 /* bits in STATES */
152 #define HFCSX_STATE_MSK 0x0F
153 #define HFCSX_LOAD_STATE 0x10
154 #define HFCSX_ACTIVATE 0x20
155 #define HFCSX_DO_ACTION 0x40
156 #define HFCSX_NT_G2_G3 0x80
157
158 /* bits in HFCD_MST_MODE */
159 #define HFCSX_MASTER 0x01
160 #define HFCSX_SLAVE 0x00
161 /* remaining bits are for codecs control */
162
163 /* bits in HFCD_SCTRL */
164 #define SCTRL_B1_ENA 0x01
165 #define SCTRL_B2_ENA 0x02
166 #define SCTRL_MODE_TE 0x00
167 #define SCTRL_MODE_NT 0x04
168 #define SCTRL_LOW_PRIO 0x08
169 #define SCTRL_SQ_ENA 0x10
170 #define SCTRL_TEST 0x20
171 #define SCTRL_NONE_CAP 0x40
172 #define SCTRL_PWR_DOWN 0x80
173
174 /* bits in SCTRL_E */
175 #define HFCSX_AUTO_AWAKE 0x01
176 #define HFCSX_DBIT_1 0x04
177 #define HFCSX_IGNORE_COL 0x08
178 #define HFCSX_CHG_B1_B2 0x80
179
180 /**********************************/
181 /* definitions for FIFO selection */
182 /**********************************/
183 #define HFCSX_SEL_D_RX 5
184 #define HFCSX_SEL_D_TX 4
185 #define HFCSX_SEL_B1_RX 1
186 #define HFCSX_SEL_B1_TX 0
187 #define HFCSX_SEL_B2_RX 3
188 #define HFCSX_SEL_B2_TX 2
189
190 #define MAX_D_FRAMES 15
191 #define MAX_B_FRAMES 31
192 #define B_SUB_VAL_32K 0x0200
193 #define B_FIFO_SIZE_32K (0x2000 - B_SUB_VAL_32K)
194 #define B_SUB_VAL_8K 0x1A00
195 #define B_FIFO_SIZE_8K (0x2000 - B_SUB_VAL_8K)
196 #define D_FIFO_SIZE 512
197 #define D_FREG_MASK 0xF
198
199 /************************************************************/
200 /* structure holding additional dynamic data -> send marker */
201 /************************************************************/
202 struct hfcsx_extra {
203 unsigned short marker[2*(MAX_B_FRAMES+1) + (MAX_D_FRAMES+1)];
204 };
205
206 extern void main_irq_hfcsx(struct BCState *bcs);
207 extern void inithfcsx(struct IsdnCardState *cs);
208 extern void releasehfcsx(struct IsdnCardState *cs);
209