File: /usr/src/linux/drivers/isdn/hisax/hfc_sx.c
1 /* $Id: hfc_sx.c,v 1.9.6.2 2001/07/18 16:25:12 kai Exp $
2
3 * hfc_sx.c low level driver for CCD´s hfc-s+/sp based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD HFC PCI cards
7 *
8 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26 #define __NO_VERSION__
27 #include <linux/init.h>
28 #include "hisax.h"
29 #include "hfc_sx.h"
30 #include "isdnl1.h"
31 #include <linux/interrupt.h>
32
33 extern const char *CardType[];
34
35 static const char *hfcsx_revision = "$Revision: 1.9.6.2 $";
36
37 /***************************************/
38 /* IRQ-table for CCDs demo board */
39 /* IRQs 6,5,10,11,12,15 are supported */
40 /***************************************/
41
42 /* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1
43 *
44 * Thanks to Uwe Wisniewski
45 *
46 * ISA-SLOT Signal PIN
47 * B25 IRQ3 92 IRQ_G
48 * B23 IRQ5 94 IRQ_A
49 * B4 IRQ2/9 95 IRQ_B
50 * D3 IRQ10 96 IRQ_C
51 * D4 IRQ11 97 IRQ_D
52 * D5 IRQ12 98 IRQ_E
53 * D6 IRQ15 99 IRQ_F
54 */
55
56 #undef CCD_DEMO_BOARD
57 #ifdef CCD_DEMO_BOARD
58 static u_char ccd_sp_irqtab[16] = {
59 0,0,0,0,0,2,1,0,0,0,3,4,5,0,0,6
60 };
61 #else /* Teles 16.3c */
62 static u_char ccd_sp_irqtab[16] = {
63 0,0,0,7,0,1,0,0,0,2,3,4,5,0,0,6
64 };
65 #endif
66 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
67
68 #define byteout(addr,val) outb(val,addr)
69 #define bytein(addr) inb(addr)
70
71 /******************************/
72 /* In/Out access to registers */
73 /******************************/
74 static inline void
75 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
76 { long flags;
77
78 save_flags(flags);
79 cli();
80 byteout(cs->hw.hfcsx.base+1, regnum);
81 byteout(cs->hw.hfcsx.base, val);
82 restore_flags(flags);
83 }
84
85 static inline u_char
86 Read_hfc(struct IsdnCardState *cs, u_char regnum)
87 { long flags;
88 u_char ret;
89
90 save_flags(flags);
91 cli();
92 byteout(cs->hw.hfcsx.base+1, regnum);
93 ret = bytein(cs->hw.hfcsx.base);
94 restore_flags(flags);
95 return(ret);
96 }
97
98
99 /**************************************************/
100 /* select a fifo and remember which one for reuse */
101 /**************************************************/
102 static void
103 fifo_select(struct IsdnCardState *cs, u_char fifo)
104 { long flags;
105
106 if (fifo == cs->hw.hfcsx.last_fifo)
107 return; /* still valid */
108
109 save_flags(flags);
110 cli();
111 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL);
112 byteout(cs->hw.hfcsx.base, fifo);
113 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
114 udelay(4);
115 byteout(cs->hw.hfcsx.base, fifo);
116 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
117 restore_flags(flags);
118 }
119
120 /******************************************/
121 /* reset the specified fifo to defaults. */
122 /* If its a send fifo init needed markers */
123 /******************************************/
124 static void
125 reset_fifo(struct IsdnCardState *cs, u_char fifo)
126 { long flags;
127
128 save_flags(flags);
129 cli();
130 fifo_select(cs, fifo); /* first select the fifo */
131 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM);
132 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
133 udelay(1);
134 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
135 restore_flags(flags);
136 }
137
138
139 /*************************************************************/
140 /* write_fifo writes the skb contents to the desired fifo */
141 /* if no space is available or an error occurs 0 is returned */
142 /* the skb is not released in any way. */
143 /*************************************************************/
144 static int
145 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
146 { unsigned short *msp;
147 int fifo_size, count, z1, z2;
148 u_char f_msk, f1, f2, *src;
149
150 if (skb->len <= 0) return(0);
151 if (fifo & 1) return(0); /* no write fifo */
152
153 fifo_select(cs, fifo);
154 if (fifo & 4) {
155 fifo_size = D_FIFO_SIZE; /* D-channel */
156 f_msk = MAX_D_FRAMES;
157 if (trans_max) return(0); /* only HDLC */
158 }
159 else {
160 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
161 f_msk = MAX_B_FRAMES;
162 }
163
164 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
165 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
166
167 /* Check for transparent mode */
168 if (trans_max) {
169 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
170 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
171 count = z2 - z1;
172 if (count <= 0)
173 count += fifo_size; /* free bytes */
174 if (count < skb->len+1) return(0); /* no room */
175 count = fifo_size - count; /* bytes still not send */
176 if (count > 2 * trans_max) return(0); /* delay to long */
177 count = skb->len;
178 src = skb->data;
179 while (count--)
180 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
181 return(1); /* success */
182 }
183
184 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
185 msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES+1));
186 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
187 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
188
189 count = f1 - f2; /* frame count actually buffered */
190 if (count < 0)
191 count += (f_msk + 1); /* if wrap around */
192 if (count > f_msk-1) {
193 if (cs->debug & L1_DEB_ISAC_FIFO)
194 debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1);
195 return(0);
196 }
197
198 *(msp + f1) = z1; /* remember marker */
199
200 if (cs->debug & L1_DEB_ISAC_FIFO)
201 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)",
202 fifo, f1, f2, z1);
203 /* now determine free bytes in FIFO buffer */
204 count = *(msp + f2) - z1;
205 if (count <= 0)
206 count += fifo_size; /* count now contains available bytes */
207
208 if (cs->debug & L1_DEB_ISAC_FIFO)
209 debugl1(cs, "hfcsx_write_fifo %d count(%ld/%d)",
210 fifo, skb->len, count);
211 if (count < skb->len) {
212 if (cs->debug & L1_DEB_ISAC_FIFO)
213 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
214 return(0);
215 }
216
217 count = skb->len; /* get frame len */
218 src = skb->data; /* source pointer */
219 while (count--)
220 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
221
222 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
223 udelay(1);
224 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
225 return(1);
226 }
227
228 /***************************************************************/
229 /* read_fifo reads data to an skb from the desired fifo */
230 /* if no data is available or an error occurs NULL is returned */
231 /* the skb is not released in any way. */
232 /***************************************************************/
233 static struct sk_buff *
234 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
235 { int fifo_size, count, z1, z2;
236 u_char f_msk, f1, f2, *dst;
237 struct sk_buff *skb;
238
239 if (!(fifo & 1)) return(NULL); /* no read fifo */
240 fifo_select(cs, fifo);
241 if (fifo & 4) {
242 fifo_size = D_FIFO_SIZE; /* D-channel */
243 f_msk = MAX_D_FRAMES;
244 if (trans_max) return(NULL); /* only hdlc */
245 }
246 else {
247 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
248 f_msk = MAX_B_FRAMES;
249 }
250
251 /* transparent mode */
252 if (trans_max) {
253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
257 /* now determine bytes in actual FIFO buffer */
258 count = z1 - z2;
259 if (count <= 0)
260 count += fifo_size; /* count now contains buffered bytes */
261 count++;
262 if (count > trans_max)
263 count = trans_max; /* limit length */
264 if ((skb = dev_alloc_skb(count))) {
265 dst = skb_put(skb, count);
266 while (count--)
267 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
268 return(skb);
269 }
270 else return(NULL); /* no memory */
271 }
272
273 do {
274 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
275 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
276
277 if (f1 == f2) return(NULL); /* no frame available */
278
279 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
280 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
281 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
282 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
283
284 if (cs->debug & L1_DEB_ISAC_FIFO)
285 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
286 fifo, f1, f2, z1, z2);
287 /* now determine bytes in actual FIFO buffer */
288 count = z1 - z2;
289 if (count <= 0)
290 count += fifo_size; /* count now contains buffered bytes */
291 count++;
292
293 if (cs->debug & L1_DEB_ISAC_FIFO)
294 debugl1(cs, "hfcsx_read_fifo %d count %ld)",
295 fifo, count);
296
297 if ((count > fifo_size) || (count < 4)) {
298 if (cs->debug & L1_DEB_WARN)
299 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count);
300 while (count) {
301 count--; /* empty fifo */
302 Read_hfc(cs, HFCSX_FIF_DRD);
303 }
304 skb = NULL;
305 } else
306 if ((skb = dev_alloc_skb(count - 3))) {
307 count -= 3;
308 dst = skb_put(skb, count);
309
310 while (count--)
311 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
312
313 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
314 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
315 if (Read_hfc(cs, HFCSX_FIF_DRD)) {
316 dev_kfree_skb_irq(skb);
317 if (cs->debug & L1_DEB_ISAC_FIFO)
318 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
319 skb = NULL;
320 }
321 } else {
322 printk(KERN_WARNING "HFC-SX: receive out of memory\n");
323 return(NULL);
324 }
325
326 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
327 udelay(1);
328 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
329 udelay(1);
330 } while (!skb); /* retry in case of crc error */
331 return(skb);
332 }
333
334 /******************************************/
335 /* free hardware resources used by driver */
336 /******************************************/
337 void
338 release_io_hfcsx(struct IsdnCardState *cs)
339 {
340 long flags;
341
342 save_flags(flags);
343 cli();
344 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */
345 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
346 restore_flags(flags);
347 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */
348 sti();
349 set_current_state(TASK_UNINTERRUPTIBLE);
350 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
351 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */
352 del_timer(&cs->hw.hfcsx.timer);
353 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */
354 kfree(cs->hw.hfcsx.extra);
355 cs->hw.hfcsx.extra = NULL;
356 }
357
358 /**********************************************************/
359 /* set_fifo_size determines the size of the RAM and FIFOs */
360 /* returning 0 -> need to reset the chip again. */
361 /**********************************************************/
362 static int set_fifo_size(struct IsdnCardState *cs)
363 {
364
365 if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */
366
367 if ((cs->hw.hfcsx.chip >> 4) == 9) {
368 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
369 return(1);
370 }
371
372 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
373 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
374 return(0);
375
376 }
377
378 /********************************************************************************/
379 /* function called to reset the HFC SX chip. A complete software reset of chip */
380 /* and fifos is done. */
381 /********************************************************************************/
382 static void
383 reset_hfcsx(struct IsdnCardState *cs)
384 {
385 long flags;
386
387 save_flags(flags);
388 cli();
389 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */
390 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
391
392 printk(KERN_INFO "HFC_SX: resetting card\n");
393 while (1) {
394 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */
395 sti();
396 set_current_state(TASK_UNINTERRUPTIBLE);
397 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
398 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
399 set_current_state(TASK_UNINTERRUPTIBLE);
400 schedule_timeout((20 * HZ) / 1000); /* Timeout 20ms */
401 if (Read_hfc(cs, HFCSX_STATUS) & 2)
402 printk(KERN_WARNING "HFC-SX init bit busy\n");
403 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
404 if (!set_fifo_size(cs)) continue;
405 break;
406 }
407
408 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */
409 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
410
411 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */
412 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE;
413 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */
414 cs->hw.hfcsx.bswapped = 0; /* no exchange */
415 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */
416 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
417 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
418
419 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
420 HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
421 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
422
423 /* Clear already pending ints */
424 if (Read_hfc(cs, HFCSX_INT_S1));
425
426 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */
427 udelay(10);
428 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */
429 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */
430
431 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
432 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
433 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
434 cs->hw.hfcsx.sctrl_r = 0;
435 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
436
437 /* Init GCI/IOM2 in master mode */
438 /* Slots 0 and 1 are set for B-chan 1 and 2 */
439 /* D- and monitor/CI channel are not enabled */
440 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
441 /* STIO2 is used as data input, B1+B2 from IOM->ST */
442 /* ST B-channel send disabled -> continous 1s */
443 /* The IOM slots are always enabled */
444 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */
445 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
446 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
447 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
448 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
449 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
450
451 /* Finally enable IRQ output */
452 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE;
453 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
454 if (Read_hfc(cs, HFCSX_INT_S2));
455 restore_flags(flags);
456 }
457
458 /***************************************************/
459 /* Timer function called when kernel timer expires */
460 /***************************************************/
461 static void
462 hfcsx_Timer(struct IsdnCardState *cs)
463 {
464 cs->hw.hfcsx.timer.expires = jiffies + 75;
465 /* WD RESET */
466 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
467 add_timer(&cs->hw.hfcsx.timer);
468 */
469 }
470
471
472 /*********************************/
473 /* schedule a new D-channel task */
474 /*********************************/
475 static void
476 sched_event_D_sx(struct IsdnCardState *cs, int event)
477 {
478 test_and_set_bit(event, &cs->event);
479 queue_task(&cs->tqueue, &tq_immediate);
480 mark_bh(IMMEDIATE_BH);
481 }
482
483 /*********************************/
484 /* schedule a new b_channel task */
485 /*********************************/
486 static void
487 hfcsx_sched_event(struct BCState *bcs, int event)
488 {
489 bcs->event |= 1 << event;
490 queue_task(&bcs->tqueue, &tq_immediate);
491 mark_bh(IMMEDIATE_BH);
492 }
493
494 /************************************************/
495 /* select a b-channel entry matching and active */
496 /************************************************/
497 static
498 struct BCState *
499 Sel_BCS(struct IsdnCardState *cs, int channel)
500 {
501 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
502 return (&cs->bcs[0]);
503 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
504 return (&cs->bcs[1]);
505 else
506 return (NULL);
507 }
508
509 /*******************************/
510 /* D-channel receive procedure */
511 /*******************************/
512 static
513 int
514 receive_dmsg(struct IsdnCardState *cs)
515 {
516 struct sk_buff *skb;
517 int count = 5;
518
519 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
520 debugl1(cs, "rec_dmsg blocked");
521 return (1);
522 }
523
524 do {
525 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
526 if (skb) {
527 skb_queue_tail(&cs->rq, skb);
528 sched_event_D_sx(cs, D_RCVBUFREADY);
529 }
530 } while (--count && skb);
531
532 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
533 return (1);
534 }
535
536 /**********************************/
537 /* B-channel main receive routine */
538 /**********************************/
539 void
540 main_rec_hfcsx(struct BCState *bcs)
541 {
542 long flags;
543 struct IsdnCardState *cs = bcs->cs;
544 int count = 5;
545 struct sk_buff *skb;
546
547 save_flags(flags);
548
549 Begin:
550 count--;
551 cli();
552 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
553 debugl1(cs, "rec_data %d blocked", bcs->channel);
554 restore_flags(flags);
555 return;
556 }
557 sti();
558 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
559 HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
560 (bcs->mode == L1_MODE_TRANS) ?
561 HFCSX_BTRANS_THRESHOLD : 0);
562
563 if (skb) {
564 cli();
565 skb_queue_tail(&bcs->rqueue, skb);
566 sti();
567 hfcsx_sched_event(bcs, B_RCVBUFREADY);
568 }
569
570 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
571 if (count && skb)
572 goto Begin;
573 restore_flags(flags);
574 return;
575 }
576
577 /**************************/
578 /* D-channel send routine */
579 /**************************/
580 static void
581 hfcsx_fill_dfifo(struct IsdnCardState *cs)
582 {
583 if (!cs->tx_skb)
584 return;
585 if (cs->tx_skb->len <= 0)
586 return;
587
588 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
589 dev_kfree_skb_any(cs->tx_skb);
590 cs->tx_skb = NULL;
591 }
592 return;
593 }
594
595 /**************************/
596 /* B-channel send routine */
597 /**************************/
598 static void
599 hfcsx_fill_fifo(struct BCState *bcs)
600 {
601 struct IsdnCardState *cs = bcs->cs;
602 long flags;
603
604 if (!bcs->tx_skb)
605 return;
606 if (bcs->tx_skb->len <= 0)
607 return;
608
609 save_flags(flags);
610 sti();
611
612 if (write_fifo(cs, bcs->tx_skb,
613 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
614 HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
615 (bcs->mode == L1_MODE_TRANS) ?
616 HFCSX_BTRANS_THRESHOLD : 0)) {
617
618 bcs->tx_cnt -= bcs->tx_skb->len;
619 if (bcs->st->lli.l1writewakeup &&
620 (PACKET_NOACK != bcs->tx_skb->pkt_type))
621 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
622 dev_kfree_skb_any(bcs->tx_skb);
623 bcs->tx_skb = NULL;
624 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
625 }
626
627 cli();
628 restore_flags(flags);
629 return;
630 }
631
632 /**********************************************/
633 /* D-channel l1 state call for leased NT-mode */
634 /**********************************************/
635 static void
636 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
637 {
638 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
639
640 switch (pr) {
641 case (PH_DATA | REQUEST):
642 case (PH_PULL | REQUEST):
643 case (PH_PULL | INDICATION):
644 st->l1.l1hw(st, pr, arg);
645 break;
646 case (PH_ACTIVATE | REQUEST):
647 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
648 break;
649 case (PH_TESTLOOP | REQUEST):
650 if (1 & (long) arg)
651 debugl1(cs, "PH_TEST_LOOP B1");
652 if (2 & (long) arg)
653 debugl1(cs, "PH_TEST_LOOP B2");
654 if (!(3 & (long) arg))
655 debugl1(cs, "PH_TEST_LOOP DISABLED");
656 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
657 break;
658 default:
659 if (cs->debug)
660 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
661 break;
662 }
663 }
664
665
666
667 /***********************/
668 /* set/reset echo mode */
669 /***********************/
670 static int
671 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
672 {
673 long flags;
674 int i = *(unsigned int *) ic->parm.num;
675
676 if ((ic->arg == 98) &&
677 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
678 save_flags(flags);
679 cli();
680 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */
681 udelay(10);
682 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
683 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */
684 udelay(10);
685 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */
686 udelay(10);
687 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
688 cs->dc.hfcsx.ph_state = 1;
689 cs->hw.hfcsx.nt_mode = 1;
690 cs->hw.hfcsx.nt_timer = 0;
691 cs->stlist->l2.l2l1 = dch_nt_l2l1;
692 restore_flags(flags);
693 debugl1(cs, "NT mode activated");
694 return (0);
695 }
696 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) ||
697 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12))
698 return (-EINVAL);
699
700 save_flags(flags);
701 cli();
702 if (i) {
703 cs->logecho = 1;
704 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */
705 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC;
706 /* reset Channel !!!!! */
707 } else {
708 cs->logecho = 0;
709 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */
710 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC;
711 }
712 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
713 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
714 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */
715 cs->hw.hfcsx.ctmt &= ~2;
716 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
717 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
718 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
719 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
720 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
721 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
722 restore_flags(flags);
723 return (0);
724 } /* hfcsx_auxcmd */
725
726 /*****************************/
727 /* E-channel receive routine */
728 /*****************************/
729 static void
730 receive_emsg(struct IsdnCardState *cs)
731 {
732 long flags;
733 int count = 5;
734 u_char *ptr;
735 struct sk_buff *skb;
736
737
738 save_flags(flags);
739 cli();
740 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
741 debugl1(cs, "echo_rec_data blocked");
742 restore_flags(flags);
743 return;
744 }
745 sti();
746
747 do {
748 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
749 if (skb) {
750 if (cs->debug & DEB_DLOG_HEX) {
751 ptr = cs->dlog;
752 if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
753 *ptr++ = 'E';
754 *ptr++ = 'C';
755 *ptr++ = 'H';
756 *ptr++ = 'O';
757 *ptr++ = ':';
758 ptr += QuickHex(ptr, skb->data, skb->len);
759 ptr--;
760 *ptr++ = '\n';
761 *ptr = 0;
762 HiSax_putstatus(cs, NULL, cs->dlog);
763 } else
764 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
765 }
766 dev_kfree_skb_any(skb);
767 }
768 } while (--count && skb);
769
770 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
771 restore_flags(flags);
772 return;
773 } /* receive_emsg */
774
775
776 /*********************/
777 /* Interrupt handler */
778 /*********************/
779 static void
780 hfcsx_interrupt(int intno, void *dev_id, struct pt_regs *regs)
781 {
782 struct IsdnCardState *cs = dev_id;
783 u_char exval;
784 struct BCState *bcs;
785 int count = 15;
786 long flags;
787 u_char val, stat;
788
789 if (!cs) {
790 printk(KERN_WARNING "HFC-SX: Spurious interrupt!\n");
791 return;
792 }
793 if (!(cs->hw.hfcsx.int_m2 & 0x08))
794 return; /* not initialised */
795
796 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) {
797 val = Read_hfc(cs, HFCSX_INT_S1);
798 if (cs->debug & L1_DEB_ISAC)
799 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val);
800 } else
801 return;
802
803 if (cs->debug & L1_DEB_ISAC)
804 debugl1(cs, "HFC-SX irq %x %s", val,
805 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
806 "locked" : "unlocked");
807 val &= cs->hw.hfcsx.int_m1;
808 if (val & 0x40) { /* state machine irq */
809 exval = Read_hfc(cs, HFCSX_STATES) & 0xf;
810 if (cs->debug & L1_DEB_ISAC)
811 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state,
812 exval);
813 cs->dc.hfcsx.ph_state = exval;
814 sched_event_D_sx(cs, D_L1STATECHANGE);
815 val &= ~0x40;
816 }
817 if (val & 0x80) { /* timer irq */
818 if (cs->hw.hfcsx.nt_mode) {
819 if ((--cs->hw.hfcsx.nt_timer) < 0)
820 sched_event_D_sx(cs, D_L1STATECHANGE);
821 }
822 val &= ~0x80;
823 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
824 }
825 while (val) {
826 save_flags(flags);
827 cli();
828 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
829 cs->hw.hfcsx.int_s1 |= val;
830 restore_flags(flags);
831 return;
832 }
833 if (cs->hw.hfcsx.int_s1 & 0x18) {
834 exval = val;
835 val = cs->hw.hfcsx.int_s1;
836 cs->hw.hfcsx.int_s1 = exval;
837 }
838 if (val & 0x08) {
839 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
840 if (cs->debug)
841 debugl1(cs, "hfcsx spurious 0x08 IRQ");
842 } else
843 main_rec_hfcsx(bcs);
844 }
845 if (val & 0x10) {
846 if (cs->logecho)
847 receive_emsg(cs);
848 else if (!(bcs = Sel_BCS(cs, 1))) {
849 if (cs->debug)
850 debugl1(cs, "hfcsx spurious 0x10 IRQ");
851 } else
852 main_rec_hfcsx(bcs);
853 }
854 if (val & 0x01) {
855 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
856 if (cs->debug)
857 debugl1(cs, "hfcsx spurious 0x01 IRQ");
858 } else {
859 if (bcs->tx_skb) {
860 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
861 hfcsx_fill_fifo(bcs);
862 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
863 } else
864 debugl1(cs, "fill_data %d blocked", bcs->channel);
865 } else {
866 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
867 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
868 hfcsx_fill_fifo(bcs);
869 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
870 } else
871 debugl1(cs, "fill_data %d blocked", bcs->channel);
872 } else {
873 hfcsx_sched_event(bcs, B_XMTBUFREADY);
874 }
875 }
876 }
877 }
878 if (val & 0x02) {
879 if (!(bcs = Sel_BCS(cs, 1))) {
880 if (cs->debug)
881 debugl1(cs, "hfcsx spurious 0x02 IRQ");
882 } else {
883 if (bcs->tx_skb) {
884 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
885 hfcsx_fill_fifo(bcs);
886 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
887 } else
888 debugl1(cs, "fill_data %d blocked", bcs->channel);
889 } else {
890 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
891 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
892 hfcsx_fill_fifo(bcs);
893 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
894 } else
895 debugl1(cs, "fill_data %d blocked", bcs->channel);
896 } else {
897 hfcsx_sched_event(bcs, B_XMTBUFREADY);
898 }
899 }
900 }
901 }
902 if (val & 0x20) { /* receive dframe */
903 receive_dmsg(cs);
904 }
905 if (val & 0x04) { /* dframe transmitted */
906 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
907 del_timer(&cs->dbusytimer);
908 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
909 sched_event_D_sx(cs, D_CLEARBUSY);
910 if (cs->tx_skb) {
911 if (cs->tx_skb->len) {
912 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
913 hfcsx_fill_dfifo(cs);
914 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
915 } else {
916 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
917 }
918 goto afterXPR;
919 } else {
920 dev_kfree_skb_irq(cs->tx_skb);
921 cs->tx_cnt = 0;
922 cs->tx_skb = NULL;
923 }
924 }
925 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
926 cs->tx_cnt = 0;
927 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
928 hfcsx_fill_dfifo(cs);
929 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
930 } else {
931 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
932 }
933 } else
934 sched_event_D_sx(cs, D_XMTBUFREADY);
935 }
936 afterXPR:
937 if (cs->hw.hfcsx.int_s1 && count--) {
938 val = cs->hw.hfcsx.int_s1;
939 cs->hw.hfcsx.int_s1 = 0;
940 if (cs->debug & L1_DEB_ISAC)
941 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count);
942 } else
943 val = 0;
944 restore_flags(flags);
945 }
946 }
947
948 /********************************************************************/
949 /* timer callback for D-chan busy resolution. Currently no function */
950 /********************************************************************/
951 static void
952 hfcsx_dbusy_timer(struct IsdnCardState *cs)
953 {
954 }
955
956 /*************************************/
957 /* Layer 1 D-channel hardware access */
958 /*************************************/
959 static void
960 HFCSX_l1hw(struct PStack *st, int pr, void *arg)
961 {
962 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
963 struct sk_buff *skb = arg;
964 long flags;
965
966 switch (pr) {
967 case (PH_DATA | REQUEST):
968 if (cs->debug & DEB_DLOG_HEX)
969 LogFrame(cs, skb->data, skb->len);
970 if (cs->debug & DEB_DLOG_VERBOSE)
971 dlogframe(cs, skb, 0);
972 if (cs->tx_skb) {
973 skb_queue_tail(&cs->sq, skb);
974 #ifdef L2FRAME_DEBUG /* psa */
975 if (cs->debug & L1_DEB_LAPD)
976 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
977 #endif
978 } else {
979 cs->tx_skb = skb;
980 cs->tx_cnt = 0;
981 #ifdef L2FRAME_DEBUG /* psa */
982 if (cs->debug & L1_DEB_LAPD)
983 Logl2Frame(cs, skb, "PH_DATA", 0);
984 #endif
985 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
986 hfcsx_fill_dfifo(cs);
987 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
988 } else
989 debugl1(cs, "hfcsx_fill_dfifo blocked");
990
991 }
992 break;
993 case (PH_PULL | INDICATION):
994 if (cs->tx_skb) {
995 if (cs->debug & L1_DEB_WARN)
996 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
997 skb_queue_tail(&cs->sq, skb);
998 break;
999 }
1000 if (cs->debug & DEB_DLOG_HEX)
1001 LogFrame(cs, skb->data, skb->len);
1002 if (cs->debug & DEB_DLOG_VERBOSE)
1003 dlogframe(cs, skb, 0);
1004 cs->tx_skb = skb;
1005 cs->tx_cnt = 0;
1006 #ifdef L2FRAME_DEBUG /* psa */
1007 if (cs->debug & L1_DEB_LAPD)
1008 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1009 #endif
1010 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1011 hfcsx_fill_dfifo(cs);
1012 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1013 } else
1014 debugl1(cs, "hfcsx_fill_dfifo blocked");
1015 break;
1016 case (PH_PULL | REQUEST):
1017 #ifdef L2FRAME_DEBUG /* psa */
1018 if (cs->debug & L1_DEB_LAPD)
1019 debugl1(cs, "-> PH_REQUEST_PULL");
1020 #endif
1021 if (!cs->tx_skb) {
1022 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1023 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1024 } else
1025 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1026 break;
1027 case (HW_RESET | REQUEST):
1028 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */
1029 udelay(6);
1030 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
1031 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
1032 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1033 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
1034 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1035 break;
1036 case (HW_ENABLE | REQUEST):
1037 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
1038 break;
1039 case (HW_DEACTIVATE | REQUEST):
1040 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
1041 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1042 break;
1043 case (HW_INFO3 | REQUEST):
1044 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
1045 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1046 break;
1047 case (HW_TESTLOOP | REQUEST):
1048 switch ((int) arg) {
1049 case (1):
1050 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */
1051 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */
1052 save_flags(flags);
1053 cli();
1054 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
1055 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1056 restore_flags(flags);
1057 break;
1058
1059 case (2):
1060 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */
1061 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */
1062 save_flags(flags);
1063 cli();
1064 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
1065 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1066 restore_flags(flags);
1067 break;
1068
1069 default:
1070 if (cs->debug & L1_DEB_WARN)
1071 debugl1(cs, "hfcsx_l1hw loop invalid %4x", (int) arg);
1072 return;
1073 }
1074 save_flags(flags);
1075 cli();
1076 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */
1077 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
1078 restore_flags(flags);
1079 break;
1080 default:
1081 if (cs->debug & L1_DEB_WARN)
1082 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
1083 break;
1084 }
1085 }
1086
1087 /***********************************************/
1088 /* called during init setting l1 stack pointer */
1089 /***********************************************/
1090 void
1091 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs)
1092 {
1093 st->l1.l1hw = HFCSX_l1hw;
1094 }
1095
1096 /**************************************/
1097 /* send B-channel data if not blocked */
1098 /**************************************/
1099 static void
1100 hfcsx_send_data(struct BCState *bcs)
1101 {
1102 struct IsdnCardState *cs = bcs->cs;
1103
1104 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1105 hfcsx_fill_fifo(bcs);
1106 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1107 } else
1108 debugl1(cs, "send_data %d blocked", bcs->channel);
1109 }
1110
1111 /***************************************************************/
1112 /* activate/deactivate hardware for selected channels and mode */
1113 /***************************************************************/
1114 void
1115 mode_hfcsx(struct BCState *bcs, int mode, int bc)
1116 {
1117 struct IsdnCardState *cs = bcs->cs;
1118 long flags;
1119 int fifo2;
1120
1121 if (cs->debug & L1_DEB_HSCX)
1122 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d",
1123 mode, bc, bcs->channel);
1124 bcs->mode = mode;
1125 bcs->channel = bc;
1126 fifo2 = bc;
1127 save_flags(flags);
1128 cli();
1129 if (cs->chanlimit > 1) {
1130 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1131 cs->hw.hfcsx.sctrl_e &= ~0x80;
1132 } else {
1133 if (bc) {
1134 if (mode != L1_MODE_NULL) {
1135 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */
1136 cs->hw.hfcsx.sctrl_e |= 0x80;
1137 } else {
1138 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1139 cs->hw.hfcsx.sctrl_e &= ~0x80;
1140 }
1141 fifo2 = 0;
1142 } else {
1143 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1144 cs->hw.hfcsx.sctrl_e &= ~0x80;
1145 }
1146 }
1147 switch (mode) {
1148 case (L1_MODE_NULL):
1149 if (bc) {
1150 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1151 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1152 } else {
1153 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1154 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1155 }
1156 if (fifo2) {
1157 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1158 } else {
1159 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1160 }
1161 break;
1162 case (L1_MODE_TRANS):
1163 if (bc) {
1164 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1165 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1166 } else {
1167 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1168 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1169 }
1170 if (fifo2) {
1171 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1172 cs->hw.hfcsx.ctmt |= 2;
1173 cs->hw.hfcsx.conn &= ~0x18;
1174 } else {
1175 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1176 cs->hw.hfcsx.ctmt |= 1;
1177 cs->hw.hfcsx.conn &= ~0x03;
1178 }
1179 break;
1180 case (L1_MODE_HDLC):
1181 if (bc) {
1182 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1183 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1184 } else {
1185 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1186 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1187 }
1188 if (fifo2) {
1189 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1190 cs->hw.hfcsx.ctmt &= ~2;
1191 cs->hw.hfcsx.conn &= ~0x18;
1192 } else {
1193 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1194 cs->hw.hfcsx.ctmt &= ~1;
1195 cs->hw.hfcsx.conn &= ~0x03;
1196 }
1197 break;
1198 case (L1_MODE_EXTRN):
1199 if (bc) {
1200 cs->hw.hfcsx.conn |= 0x10;
1201 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1202 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1203 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1204 } else {
1205 cs->hw.hfcsx.conn |= 0x02;
1206 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1207 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1208 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1209 }
1210 break;
1211 }
1212 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1213 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1214 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1215 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1216 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1217 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1218 if (mode != L1_MODE_EXTRN) {
1219 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1220 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1221 }
1222 restore_flags(flags);
1223 }
1224
1225 /******************************/
1226 /* Layer2 -> Layer 1 Transfer */
1227 /******************************/
1228 static void
1229 hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1230 {
1231 struct sk_buff *skb = arg;
1232 long flags;
1233
1234 switch (pr) {
1235 case (PH_DATA | REQUEST):
1236 save_flags(flags);
1237 cli();
1238 if (st->l1.bcs->tx_skb) {
1239 skb_queue_tail(&st->l1.bcs->squeue, skb);
1240 restore_flags(flags);
1241 } else {
1242 st->l1.bcs->tx_skb = skb;
1243 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1244 */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1245 restore_flags(flags);
1246 }
1247 break;
1248 case (PH_PULL | INDICATION):
1249 if (st->l1.bcs->tx_skb) {
1250 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1251 break;
1252 }
1253 save_flags(flags);
1254 cli();
1255 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1256 */ st->l1.bcs->tx_skb = skb;
1257 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1258 restore_flags(flags);
1259 break;
1260 case (PH_PULL | REQUEST):
1261 if (!st->l1.bcs->tx_skb) {
1262 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1263 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1264 } else
1265 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1266 break;
1267 case (PH_ACTIVATE | REQUEST):
1268 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1269 mode_hfcsx(st->l1.bcs, st->l1.mode, st->l1.bc);
1270 l1_msg_b(st, pr, arg);
1271 break;
1272 case (PH_DEACTIVATE | REQUEST):
1273 l1_msg_b(st, pr, arg);
1274 break;
1275 case (PH_DEACTIVATE | CONFIRM):
1276 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1277 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1278 mode_hfcsx(st->l1.bcs, 0, st->l1.bc);
1279 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1280 break;
1281 }
1282 }
1283
1284 /******************************************/
1285 /* deactivate B-channel access and queues */
1286 /******************************************/
1287 static void
1288 close_hfcsx(struct BCState *bcs)
1289 {
1290 mode_hfcsx(bcs, 0, bcs->channel);
1291 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1292 skb_queue_purge(&bcs->rqueue);
1293 skb_queue_purge(&bcs->squeue);
1294 if (bcs->tx_skb) {
1295 dev_kfree_skb_any(bcs->tx_skb);
1296 bcs->tx_skb = NULL;
1297 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1298 }
1299 }
1300 }
1301
1302 /*************************************/
1303 /* init B-channel queues and control */
1304 /*************************************/
1305 static int
1306 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs)
1307 {
1308 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1309 skb_queue_head_init(&bcs->rqueue);
1310 skb_queue_head_init(&bcs->squeue);
1311 }
1312 bcs->tx_skb = NULL;
1313 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1314 bcs->event = 0;
1315 bcs->tx_cnt = 0;
1316 return (0);
1317 }
1318
1319 /*********************************/
1320 /* inits the stack for B-channel */
1321 /*********************************/
1322 static int
1323 setstack_2b(struct PStack *st, struct BCState *bcs)
1324 {
1325 bcs->channel = st->l1.bc;
1326 if (open_hfcsxstate(st->l1.hardware, bcs))
1327 return (-1);
1328 st->l1.bcs = bcs;
1329 st->l2.l2l1 = hfcsx_l2l1;
1330 setstack_manager(st);
1331 bcs->st = st;
1332 setstack_l1_B(st);
1333 return (0);
1334 }
1335
1336 /***************************/
1337 /* handle L1 state changes */
1338 /***************************/
1339 static void
1340 hfcsx_bh(struct IsdnCardState *cs)
1341 {
1342 long flags;
1343 /* struct PStack *stptr;
1344 */
1345 if (!cs)
1346 return;
1347 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1348 if (!cs->hw.hfcsx.nt_mode)
1349 switch (cs->dc.hfcsx.ph_state) {
1350 case (0):
1351 l1_msg(cs, HW_RESET | INDICATION, NULL);
1352 break;
1353 case (3):
1354 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1355 break;
1356 case (8):
1357 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1358 break;
1359 case (6):
1360 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1361 break;
1362 case (7):
1363 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1364 break;
1365 default:
1366 break;
1367 } else {
1368 switch (cs->dc.hfcsx.ph_state) {
1369 case (2):
1370 save_flags(flags);
1371 cli();
1372 if (cs->hw.hfcsx.nt_timer < 0) {
1373 cs->hw.hfcsx.nt_timer = 0;
1374 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1375 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1376 /* Clear already pending ints */
1377 if (Read_hfc(cs, HFCSX_INT_S1));
1378
1379 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1380 udelay(10);
1381 Write_hfc(cs, HFCSX_STATES, 4);
1382 cs->dc.hfcsx.ph_state = 4;
1383 } else {
1384 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1385 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1386 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1387 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1388 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1389 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1390 cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1391 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */
1392 }
1393 restore_flags(flags);
1394 break;
1395 case (1):
1396 case (3):
1397 case (4):
1398 save_flags(flags);
1399 cli();
1400 cs->hw.hfcsx.nt_timer = 0;
1401 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1402 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1403 restore_flags(flags);
1404 break;
1405 default:
1406 break;
1407 }
1408 }
1409 }
1410 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1411 DChannel_proc_rcv(cs);
1412 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1413 DChannel_proc_xmt(cs);
1414 }
1415
1416
1417 /********************************/
1418 /* called for card init message */
1419 /********************************/
1420 void __devinit
1421 inithfcsx(struct IsdnCardState *cs)
1422 {
1423 cs->setstack_d = setstack_hfcsx;
1424 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer;
1425 cs->dbusytimer.data = (long) cs;
1426 init_timer(&cs->dbusytimer);
1427 cs->tqueue.routine = (void *) (void *) hfcsx_bh;
1428 cs->BC_Send_Data = &hfcsx_send_data;
1429 cs->bcs[0].BC_SetStack = setstack_2b;
1430 cs->bcs[1].BC_SetStack = setstack_2b;
1431 cs->bcs[0].BC_Close = close_hfcsx;
1432 cs->bcs[1].BC_Close = close_hfcsx;
1433 mode_hfcsx(cs->bcs, 0, 0);
1434 mode_hfcsx(cs->bcs + 1, 0, 1);
1435 }
1436
1437
1438
1439 /*******************************************/
1440 /* handle card messages from control layer */
1441 /*******************************************/
1442 static int
1443 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1444 {
1445 long flags;
1446
1447 if (cs->debug & L1_DEB_ISAC)
1448 debugl1(cs, "HFCSX: card_msg %x", mt);
1449 switch (mt) {
1450 case CARD_RESET:
1451 reset_hfcsx(cs);
1452 return (0);
1453 case CARD_RELEASE:
1454 release_io_hfcsx(cs);
1455 return (0);
1456 case CARD_INIT:
1457 inithfcsx(cs);
1458 save_flags(flags);
1459 sti();
1460 set_current_state(TASK_UNINTERRUPTIBLE);
1461 schedule_timeout((80 * HZ) / 1000); /* Timeout 80ms */
1462 /* now switch timer interrupt off */
1463 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1464 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1465 /* reinit mode reg */
1466 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1467 restore_flags(flags);
1468 return (0);
1469 case CARD_TEST:
1470 return (0);
1471 }
1472 return (0);
1473 }
1474
1475
1476
1477 int __devinit
1478 setup_hfcsx(struct IsdnCard *card)
1479 {
1480 struct IsdnCardState *cs = card->cs;
1481 char tmp[64];
1482 long flags;
1483
1484 strcpy(tmp, hfcsx_revision);
1485 printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp));
1486 cs->hw.hfcsx.base = card->para[1] & 0xfffe;
1487 cs->irq = card->para[0];
1488 cs->hw.hfcsx.int_s1 = 0;
1489 cs->dc.hfcsx.ph_state = 0;
1490 cs->hw.hfcsx.fifo = 255;
1491 if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1492 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1493 if ((!cs->hw.hfcsx.base) ||
1494 check_region((cs->hw.hfcsx.base), 2)) {
1495 printk(KERN_WARNING
1496 "HiSax: HFC-SX io-base %#lx already in use\n",
1497 cs->hw.hfcsx.base);
1498 return(0);
1499 } else {
1500 request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn");
1501 }
1502 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1503 byteout(cs->hw.hfcsx.base + 1,
1504 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1505 udelay(10);
1506 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID);
1507 switch (cs->hw.hfcsx.chip >> 4) {
1508 case 1:
1509 tmp[0] ='+';
1510 break;
1511 case 9:
1512 tmp[0] ='P';
1513 break;
1514 default:
1515 printk(KERN_WARNING
1516 "HFC-SX: invalid chip id 0x%x\n",
1517 cs->hw.hfcsx.chip >> 4);
1518 release_region(cs->hw.hfcsx.base, 2);
1519 return(0);
1520 }
1521 if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1522 printk(KERN_WARNING
1523 "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF);
1524 release_region(cs->hw.hfcsx.base, 2);
1525 return(0);
1526 }
1527 save_flags(flags);
1528 cli();
1529 if (!(cs->hw.hfcsx.extra = (void *)
1530 kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1531 restore_flags(flags);
1532 release_region(cs->hw.hfcsx.base, 2);
1533 printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1534 return(0);
1535 }
1536 restore_flags(flags);
1537
1538 printk(KERN_INFO
1539 "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1540 tmp[0], (u_int) cs->hw.hfcsx.base,
1541 cs->irq, HZ);
1542 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */
1543 cs->hw.hfcsx.int_m1 = 0;
1544 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1545 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
1546 } else
1547 return (0); /* no valid card type */
1548
1549 cs->readisac = NULL;
1550 cs->writeisac = NULL;
1551 cs->readisacfifo = NULL;
1552 cs->writeisacfifo = NULL;
1553 cs->BC_Read_Reg = NULL;
1554 cs->BC_Write_Reg = NULL;
1555 cs->irq_func = &hfcsx_interrupt;
1556
1557 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer;
1558 cs->hw.hfcsx.timer.data = (long) cs;
1559 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */
1560 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */
1561 init_timer(&cs->hw.hfcsx.timer);
1562
1563 reset_hfcsx(cs);
1564 cs->cardmsg = &hfcsx_card_msg;
1565 cs->auxcmd = &hfcsx_auxcmd;
1566 return (1);
1567 }
1568
1569
1570
1571
1572