File: /usr/include/asm/processor.h
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <linux/config.h>
18 #include <linux/threads.h>
19
20 /*
21 * Default implementation of macro that returns current
22 * instruction pointer ("program counter").
23 */
24 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
25
26 /*
27 * CPU type and hardware bug flags. Kept separately for each CPU.
28 * Members of this structure are referenced in head.S, so think twice
29 * before touching them. [mj]
30 */
31
32 struct cpuinfo_x86 {
33 __u8 x86; /* CPU family */
34 __u8 x86_vendor; /* CPU vendor */
35 __u8 x86_model;
36 __u8 x86_mask;
37 char wp_works_ok; /* It doesn't on 386's */
38 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
39 char hard_math;
40 char rfu;
41 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
42 __u32 x86_capability[NCAPINTS];
43 char x86_vendor_id[16];
44 char x86_model_id[64];
45 int x86_cache_size; /* in KB - valid for CPUS which support this
46 call */
47 int fdiv_bug;
48 int f00f_bug;
49 int coma_bug;
50 unsigned long loops_per_jiffy;
51 unsigned long *pgd_quick;
52 unsigned long *pmd_quick;
53 unsigned long *pte_quick;
54 unsigned long pgtable_cache_sz;
55 };
56
57 #define X86_VENDOR_INTEL 0
58 #define X86_VENDOR_CYRIX 1
59 #define X86_VENDOR_AMD 2
60 #define X86_VENDOR_UMC 3
61 #define X86_VENDOR_NEXGEN 4
62 #define X86_VENDOR_CENTAUR 5
63 #define X86_VENDOR_RISE 6
64 #define X86_VENDOR_TRANSMETA 7
65 #define X86_VENDOR_UNKNOWN 0xff
66
67 /*
68 * capabilities of CPUs
69 */
70
71 extern struct cpuinfo_x86 boot_cpu_data;
72 extern struct tss_struct init_tss[NR_CPUS];
73
74 #ifdef CONFIG_SMP
75 extern struct cpuinfo_x86 cpu_data[];
76 #define current_cpu_data cpu_data[smp_processor_id()]
77 #else
78 #define cpu_data &boot_cpu_data
79 #define current_cpu_data boot_cpu_data
80 #endif
81
82 #define cpu_has_pge (test_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability))
83 #define cpu_has_pse (test_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability))
84 #define cpu_has_pae (test_bit(X86_FEATURE_PAE, boot_cpu_data.x86_capability))
85 #define cpu_has_tsc (test_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability))
86 #define cpu_has_de (test_bit(X86_FEATURE_DE, boot_cpu_data.x86_capability))
87 #define cpu_has_vme (test_bit(X86_FEATURE_VME, boot_cpu_data.x86_capability))
88 #define cpu_has_fxsr (test_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability))
89 #define cpu_has_xmm (test_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability))
90 #define cpu_has_fpu (test_bit(X86_FEATURE_FPU, boot_cpu_data.x86_capability))
91 #define cpu_has_apic (test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability))
92
93 extern char ignore_irq13;
94
95 extern void identify_cpu(struct cpuinfo_x86 *);
96 extern void print_cpu_info(struct cpuinfo_x86 *);
97 extern void dodgy_tsc(void);
98
99 /*
100 * EFLAGS bits
101 */
102 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
103 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
104 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
105 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
106 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
107 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
108 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
109 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
110 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
111 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
112 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
113 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
114 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
115 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
116 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
117 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
118 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
119
120 /*
121 * Generic CPUID function
122 */
123 extern inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
124 {
125 __asm__("cpuid"
126 : "=a" (*eax),
127 "=b" (*ebx),
128 "=c" (*ecx),
129 "=d" (*edx)
130 : "a" (op));
131 }
132
133 /*
134 * CPUID functions returning a single datum
135 */
136 extern inline unsigned int cpuid_eax(unsigned int op)
137 {
138 unsigned int eax, ebx, ecx, edx;
139
140 __asm__("cpuid"
141 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
142 : "a" (op));
143 return eax;
144 }
145 extern inline unsigned int cpuid_ebx(unsigned int op)
146 {
147 unsigned int eax, ebx, ecx, edx;
148
149 __asm__("cpuid"
150 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
151 : "a" (op));
152 return ebx;
153 }
154 extern inline unsigned int cpuid_ecx(unsigned int op)
155 {
156 unsigned int eax, ebx, ecx, edx;
157
158 __asm__("cpuid"
159 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
160 : "a" (op));
161 return ecx;
162 }
163 extern inline unsigned int cpuid_edx(unsigned int op)
164 {
165 unsigned int eax, ebx, ecx, edx;
166
167 __asm__("cpuid"
168 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
169 : "a" (op));
170 return edx;
171 }
172
173 /*
174 * Intel CPU features in CR4
175 */
176 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
177 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
178 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
179 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
180 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
181 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
182 #define X86_CR4_MCE 0x0040 /* Machine check enable */
183 #define X86_CR4_PGE 0x0080 /* enable global pages */
184 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
185 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
186 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
187
188 /*
189 * Save the cr4 feature set we're using (ie
190 * Pentium 4MB enable and PPro Global page
191 * enable), so that any CPU's that boot up
192 * after us can get the correct flags.
193 */
194 extern unsigned long mmu_cr4_features;
195
196 static inline void set_in_cr4 (unsigned long mask)
197 {
198 mmu_cr4_features |= mask;
199 __asm__("movl %%cr4,%%eax\n\t"
200 "orl %0,%%eax\n\t"
201 "movl %%eax,%%cr4\n"
202 : : "irg" (mask)
203 :"ax");
204 }
205
206 static inline void clear_in_cr4 (unsigned long mask)
207 {
208 mmu_cr4_features &= ~mask;
209 __asm__("movl %%cr4,%%eax\n\t"
210 "andl %0,%%eax\n\t"
211 "movl %%eax,%%cr4\n"
212 : : "irg" (~mask)
213 :"ax");
214 }
215
216 /*
217 * Cyrix CPU configuration register indexes
218 */
219 #define CX86_CCR0 0xc0
220 #define CX86_CCR1 0xc1
221 #define CX86_CCR2 0xc2
222 #define CX86_CCR3 0xc3
223 #define CX86_CCR4 0xe8
224 #define CX86_CCR5 0xe9
225 #define CX86_CCR6 0xea
226 #define CX86_DIR0 0xfe
227 #define CX86_DIR1 0xff
228 #define CX86_ARR_BASE 0xc4
229 #define CX86_RCR_BASE 0xdc
230
231 /*
232 * Cyrix CPU indexed register access macros
233 */
234
235 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
236
237 #define setCx86(reg, data) do { \
238 outb((reg), 0x22); \
239 outb((data), 0x23); \
240 } while (0)
241
242 /*
243 * Bus types (default is ISA, but people can check others with these..)
244 */
245 #ifdef CONFIG_EISA
246 extern int EISA_bus;
247 #else
248 #define EISA_bus (0)
249 #endif
250 extern int MCA_bus;
251
252 /* from system description table in BIOS. Mostly for MCA use, but
253 others may find it useful. */
254 extern unsigned int machine_id;
255 extern unsigned int machine_submodel_id;
256 extern unsigned int BIOS_revision;
257 extern unsigned int mca_pentium_flag;
258
259 /*
260 * User space process size: 3GB (default).
261 */
262 #define TASK_SIZE (PAGE_OFFSET)
263
264 /* This decides where the kernel will search for a free chunk of vm
265 * space during mmap's.
266 */
267 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
268
269 /*
270 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
271 */
272 #define IO_BITMAP_SIZE 32
273 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
274 #define INVALID_IO_BITMAP_OFFSET 0x8000
275
276 struct i387_fsave_struct {
277 long cwd;
278 long swd;
279 long twd;
280 long fip;
281 long fcs;
282 long foo;
283 long fos;
284 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
285 long status; /* software status information */
286 };
287
288 struct i387_fxsave_struct {
289 unsigned short cwd;
290 unsigned short swd;
291 unsigned short twd;
292 unsigned short fop;
293 long fip;
294 long fcs;
295 long foo;
296 long fos;
297 long mxcsr;
298 long reserved;
299 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
300 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
301 long padding[56];
302 } __attribute__ ((aligned (16)));
303
304 struct i387_soft_struct {
305 long cwd;
306 long swd;
307 long twd;
308 long fip;
309 long fcs;
310 long foo;
311 long fos;
312 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
313 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
314 struct info *info;
315 unsigned long entry_eip;
316 };
317
318 union i387_union {
319 struct i387_fsave_struct fsave;
320 struct i387_fxsave_struct fxsave;
321 struct i387_soft_struct soft;
322 };
323
324 typedef struct {
325 unsigned long seg;
326 } mm_segment_t;
327
328 struct tss_struct {
329 unsigned short back_link,__blh;
330 unsigned long esp0;
331 unsigned short ss0,__ss0h;
332 unsigned long esp1;
333 unsigned short ss1,__ss1h;
334 unsigned long esp2;
335 unsigned short ss2,__ss2h;
336 unsigned long __cr3;
337 unsigned long eip;
338 unsigned long eflags;
339 unsigned long eax,ecx,edx,ebx;
340 unsigned long esp;
341 unsigned long ebp;
342 unsigned long esi;
343 unsigned long edi;
344 unsigned short es, __esh;
345 unsigned short cs, __csh;
346 unsigned short ss, __ssh;
347 unsigned short ds, __dsh;
348 unsigned short fs, __fsh;
349 unsigned short gs, __gsh;
350 unsigned short ldt, __ldth;
351 unsigned short trace, bitmap;
352 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
353 /*
354 * pads the TSS to be cacheline-aligned (size is 0x100)
355 */
356 unsigned long __cacheline_filler[5];
357 };
358
359 struct thread_struct {
360 unsigned long esp0;
361 unsigned long eip;
362 unsigned long esp;
363 unsigned long fs;
364 unsigned long gs;
365 /* Hardware debugging registers */
366 unsigned long debugreg[8]; /* %%db0-7 debug registers */
367 /* fault info */
368 unsigned long cr2, trap_no, error_code;
369 /* floating point info */
370 union i387_union i387;
371 /* virtual 86 mode info */
372 struct vm86_struct * vm86_info;
373 unsigned long screen_bitmap;
374 unsigned long v86flags, v86mask, v86mode, saved_esp0;
375 /* IO permissions */
376 int ioperm;
377 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
378 };
379
380 #define INIT_THREAD { \
381 0, \
382 0, 0, 0, 0, \
383 { [0 ... 7] = 0 }, /* debugging registers */ \
384 0, 0, 0, \
385 { { 0, }, }, /* 387 state */ \
386 0,0,0,0,0,0, \
387 0,{~0,} /* io permissions */ \
388 }
389
390 #define INIT_MMAP \
391 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
392
393 #define INIT_TSS { \
394 0,0, /* back_link, __blh */ \
395 sizeof(init_stack) + (long) &init_stack, /* esp0 */ \
396 __KERNEL_DS, 0, /* ss0 */ \
397 0,0,0,0,0,0, /* stack1, stack2 */ \
398 0, /* cr3 */ \
399 0,0, /* eip,eflags */ \
400 0,0,0,0, /* eax,ecx,edx,ebx */ \
401 0,0,0,0, /* esp,ebp,esi,edi */ \
402 0,0,0,0,0,0, /* es,cs,ss */ \
403 0,0,0,0,0,0, /* ds,fs,gs */ \
404 __LDT(0),0, /* ldt */ \
405 0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */ \
406 {~0, } /* ioperm */ \
407 }
408
409 #define start_thread(regs, new_eip, new_esp) do { \
410 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
411 set_fs(USER_DS); \
412 regs->xds = __USER_DS; \
413 regs->xes = __USER_DS; \
414 regs->xss = __USER_DS; \
415 regs->xcs = __USER_CS; \
416 regs->eip = new_eip; \
417 regs->esp = new_esp; \
418 } while (0)
419
420 /* Forward declaration, a strange C thing */
421 struct task_struct;
422 struct mm_struct;
423
424 /* Free all resources held by a thread. */
425 extern void release_thread(struct task_struct *);
426 /*
427 * create a kernel thread without removing it from tasklists
428 */
429 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
430
431 /* Copy and release all segment info associated with a VM */
432 extern void copy_segments(struct task_struct *p, struct mm_struct * mm);
433 extern void release_segments(struct mm_struct * mm);
434
435 /*
436 * Return saved PC of a blocked thread.
437 */
438 extern inline unsigned long thread_saved_pc(struct thread_struct *t)
439 {
440 return ((unsigned long *)t->esp)[3];
441 }
442
443 unsigned long get_wchan(struct task_struct *p);
444 #define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
445 #define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
446
447 #define THREAD_SIZE (2*PAGE_SIZE)
448 #define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
449 #define free_task_struct(p) free_pages((unsigned long) (p), 1)
450 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
451
452 #define init_task (init_task_union.task)
453 #define init_stack (init_task_union.stack)
454
455 struct microcode {
456 unsigned int hdrver;
457 unsigned int rev;
458 unsigned int date;
459 unsigned int sig;
460 unsigned int cksum;
461 unsigned int ldrver;
462 unsigned int pf;
463 unsigned int reserved[5];
464 unsigned int bits[500];
465 };
466
467 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
468 #define MICROCODE_IOCFREE _IO('6',0)
469
470 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
471 extern inline void rep_nop(void)
472 {
473 __asm__ __volatile__("rep;nop");
474 }
475
476 #endif /* __ASM_I386_PROCESSOR_H */
477