File: /usr/src/linux/arch/arm/mach-sa1100/dma-sa1100.c
1 /*
2 * arch/arm/kernel/dma-sa1100.c
3 *
4 * Support functions for the SA11x0 internal DMA channels.
5 * (see also Documentation/arm/SA1100/DMA)
6 *
7 * Copyright (C) 2000 Nicolas Pitre
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/sched.h>
18 #include <linux/spinlock.h>
19 #include <linux/slab.h>
20 #include <linux/errno.h>
21
22 #include <asm/system.h>
23 #include <asm/irq.h>
24 #include <asm/hardware.h>
25 #include <asm/io.h>
26 #include <asm/dma.h>
27 #include <asm/mach/dma.h>
28
29
30 #undef DEBUG
31 #ifdef DEBUG
32 #define DPRINTK( s, arg... ) printk( "dma<%s>: " s, dma->device_id , ##arg )
33 #else
34 #define DPRINTK( x... )
35 #endif
36
37
38 /*
39 * DMA control register structure
40 */
41 typedef struct {
42 volatile u_long DDAR;
43 volatile u_long SetDCSR;
44 volatile u_long ClrDCSR;
45 volatile u_long RdDCSR;
46 volatile dma_addr_t DBSA;
47 volatile u_long DBTA;
48 volatile dma_addr_t DBSB;
49 volatile u_long DBTB;
50 } dma_regs_t;
51
52 #include "dma.h"
53
54 sa1100_dma_t dma_chan[MAX_SA1100_DMA_CHANNELS];
55
56 /*
57 * Maximum physical DMA buffer size
58 */
59 #define MAX_DMA_SIZE 0x1fff
60 #define MAX_DMA_ORDER 12
61
62
63 /*
64 * DMA processing...
65 */
66
67 static inline int start_sa1100_dma(sa1100_dma_t * dma, dma_addr_t dma_ptr, int size)
68 {
69 dma_regs_t *regs = dma->regs;
70 int status;
71 int use_bufa;
72
73 status = regs->RdDCSR;
74
75 /* If both DMA buffers are started, there's nothing else we can do. */
76 if ((status & DCSR_STRTA) && (status & DCSR_STRTB)) {
77 DPRINTK("start: st %#x busy\n", status);
78 return -EBUSY;
79 }
80
81 use_bufa = (((status & DCSR_BIU) && (status & DCSR_STRTB)) ||
82 (!(status & DCSR_BIU) && !(status & DCSR_STRTA)));
83 if (use_bufa) {
84 regs->ClrDCSR = DCSR_DONEA | DCSR_STRTA;
85 regs->DBSA = dma_ptr;
86 regs->DBTA = size;
87 regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN;
88 DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size);
89 } else {
90 regs->ClrDCSR = DCSR_DONEB | DCSR_STRTB;
91 regs->DBSB = dma_ptr;
92 regs->DBTB = size;
93 regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN;
94 DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size);
95 }
96
97 return 0;
98 }
99
100
101 static int start_dma(sa1100_dma_t *dma, dma_addr_t dma_ptr, int size)
102 {
103 if (channel_is_sa1111_sac(dma - dma_chan))
104 return start_sa1111_sac_dma(dma, dma_ptr, size);
105 return start_sa1100_dma(dma, dma_ptr, size);
106 }
107
108
109 /* This must be called with IRQ disabled */
110 static void process_dma(sa1100_dma_t * dma)
111 {
112 dma_buf_t *buf;
113 int chunksize;
114
115 for (;;) {
116 buf = dma->tail;
117
118 if (!buf || dma->stopped) {
119 /* no more data available */
120 DPRINTK("process: no more buf (dma %s)\n",
121 dma->curr ? "active" : "inactive");
122 /*
123 * Some devices may require DMA still sending data
124 * at any time for clock reference, etc.
125 * Note: if there is still a data buffer being
126 * processed then the ref count is negative. This
127 * allows for the DMA termination to be accounted in
128 * the proper order.
129 */
130 if (dma->spin_size && dma->spin_ref >= 0) {
131 chunksize = dma->spin_size;
132 if (chunksize > MAX_DMA_SIZE)
133 chunksize = (1 << MAX_DMA_ORDER);
134 while (start_dma(dma, dma->spin_addr, chunksize) == 0)
135 dma->spin_ref++;
136 if (dma->curr != NULL)
137 dma->spin_ref = -dma->spin_ref;
138 }
139 break;
140 }
141
142 /*
143 * Let's try to start DMA on the current buffer.
144 * If DMA is busy then we break here.
145 */
146 chunksize = buf->size;
147 if (chunksize > MAX_DMA_SIZE)
148 chunksize = (1 << MAX_DMA_ORDER);
149 DPRINTK("process: b=%#x s=%d\n", (int) buf->id, buf->size);
150 if (start_dma(dma, buf->dma_ptr, chunksize) != 0)
151 break;
152 if (!dma->curr)
153 dma->curr = buf;
154 buf->ref++;
155 buf->dma_ptr += chunksize;
156 buf->size -= chunksize;
157 if (buf->size == 0) {
158 /* current buffer is done: move tail to the next one */
159 dma->tail = buf->next;
160 DPRINTK("process: next b=%#x\n", (int) dma->tail);
161 }
162 }
163 }
164
165
166 /* This must be called with IRQ disabled */
167 void sa1100_dma_done (sa1100_dma_t *dma)
168 {
169 dma_buf_t *buf = dma->curr;
170
171 if (dma->spin_ref > 0) {
172 dma->spin_ref--;
173 } else if (buf) {
174 buf->ref--;
175 if (buf->ref == 0 && buf->size == 0) {
176 /*
177 * Current buffer is done.
178 * Move current reference to the next one and send
179 * the processed buffer to the callback function,
180 * then discard it.
181 */
182 DPRINTK("IRQ: buf done\n");
183 dma->curr = buf->next;
184 if (dma->curr == NULL)
185 dma->spin_ref = -dma->spin_ref;
186 if (dma->head == buf)
187 dma->head = NULL;
188 if (dma->callback) {
189 int size = buf->dma_ptr - buf->dma_start;
190 dma->callback(buf->id, size);
191 }
192 kfree(buf);
193 }
194 }
195
196 process_dma(dma);
197 }
198
199
200 static void dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
201 {
202 sa1100_dma_t *dma = (sa1100_dma_t *) dev_id;
203 int status = dma->regs->RdDCSR;
204
205 DPRINTK("IRQ: b=%#x st=%#x\n", (int) dma->curr->id, status);
206
207 dma->regs->ClrDCSR = DCSR_ERROR | DCSR_DONEA | DCSR_DONEB;
208 if (!(status & (DCSR_DONEA | DCSR_DONEB)))
209 return;
210
211 sa1100_dma_done (dma);
212 }
213
214
215 /*
216 * DMA interface functions
217 */
218
219 static spinlock_t dma_list_lock;
220
221 int sa1100_request_dma (dmach_t * channel, const char *device_id,
222 dma_device_t device)
223 {
224 sa1100_dma_t *dma = NULL;
225 dma_regs_t *regs;
226 int i, err;
227
228 *channel = -1; /* to be sure we catch the freeing of a misregistered channel */
229
230 err = 0;
231 spin_lock(&dma_list_lock);
232 for (i = 0; i < SA1100_DMA_CHANNELS; i++) {
233 if (dma_chan[i].in_use) {
234 if (dma_chan[i].device == device) {
235 err = -EBUSY;
236 break;
237 }
238 } else if (!dma) {
239 dma = &dma_chan[i];
240 }
241 }
242 if (!err) {
243 if (dma)
244 dma->in_use = 1;
245 else
246 err = -ENOSR;
247 }
248 spin_unlock(&dma_list_lock);
249 if (err)
250 return err;
251
252 err = request_irq(dma->irq, dma_irq_handler, SA_INTERRUPT,
253 device_id, (void *) dma);
254 if (err) {
255 printk(KERN_ERR
256 "%s: unable to request IRQ %d for DMA channel\n",
257 device_id, dma->irq);
258 return err;
259 }
260
261 *channel = dma - dma_chan;
262 dma->device_id = device_id;
263 dma->device = device;
264 dma->callback = NULL;
265 dma->spin_size = 0;
266
267 regs = dma->regs;
268 regs->ClrDCSR =
269 (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
270 DCSR_IE | DCSR_ERROR | DCSR_RUN);
271 regs->DDAR = device;
272 DPRINTK("requested\n");
273 return 0;
274 }
275
276
277 int sa1100_dma_set_callback(dmach_t channel, dma_callback_t cb)
278 {
279 sa1100_dma_t *dma = &dma_chan[channel];
280
281 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
282 return -EINVAL;
283
284 dma->callback = cb;
285 DPRINTK("cb = %p\n", cb);
286 return 0;
287 }
288
289
290 int sa1100_dma_set_spin(dmach_t channel, dma_addr_t addr, int size)
291 {
292 sa1100_dma_t *dma = &dma_chan[channel];
293 int flags;
294
295 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
296 return -EINVAL;
297
298 DPRINTK("set spin %d at %#x\n", size, addr);
299 local_irq_save(flags);
300 dma->spin_addr = addr;
301 dma->spin_size = size;
302 if (size)
303 process_dma(dma);
304 local_irq_restore(flags);
305 return 0;
306 }
307
308
309 int sa1100_dma_queue_buffer(dmach_t channel, void *buf_id,
310 dma_addr_t data, int size)
311 {
312 sa1100_dma_t *dma;
313 dma_buf_t *buf;
314 int flags;
315
316 dma = &dma_chan[channel];
317 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
318 return -EINVAL;
319
320 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
321 if (!buf)
322 return -ENOMEM;
323
324 buf->next = NULL;
325 buf->ref = 0;
326 buf->dma_ptr = buf->dma_start = data;
327 buf->size = size;
328 buf->id = buf_id;
329 DPRINTK("queueing b=%#x a=%#x s=%d\n", (int) buf_id, data, size);
330
331 local_irq_save(flags);
332 if (dma->head)
333 dma->head->next = buf;
334 dma->head = buf;
335 if (!dma->tail)
336 dma->tail = buf;
337 process_dma(dma);
338 local_irq_restore(flags);
339
340 return 0;
341 }
342
343
344 int sa1100_dma_get_current(dmach_t channel, void **buf_id, dma_addr_t *addr)
345 {
346 sa1100_dma_t *dma = &dma_chan[channel];
347 dma_regs_t *regs;
348 int flags, ret;
349
350 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
351 return -EINVAL;
352
353 if (channel_is_sa1111_sac(channel))
354 return sa1111_dma_get_current(channel, buf_id, addr);
355
356 regs = dma->regs;
357 local_irq_save(flags);
358 if (dma->curr && dma->spin_ref <= 0) {
359 dma_buf_t *buf = dma->curr;
360 int status, using_bufa;
361
362 status = regs->RdDCSR;
363 /*
364 * If we got here, that's because there is, or recently was, a
365 * buffer being processed. We must determine whether buffer
366 * A or B is active. Two possibilities: either we are
367 * in the middle of a buffer, or the DMA controller just
368 * switched to the next toggle but the interrupt hasn't been
369 * serviced yet. The former case is straight forward. In
370 * the later case, we'll do like if DMA is just at the end
371 * of the previous toggle since all registers haven't been
372 * reset yet. This goes around the edge case and since we're
373 * always a little behind anyways it shouldn't make a big
374 * difference. If DMA has been stopped prior calling this
375 * then the position is always exact.
376 */
377 using_bufa = ((!(status & DCSR_BIU) && (status & DCSR_STRTA)) ||
378 ( (status & DCSR_BIU) && !(status & DCSR_STRTB)));
379 if (buf_id)
380 *buf_id = buf->id;
381 *addr = (using_bufa) ? regs->DBSA : regs->DBSB;
382 /*
383 * Clamp funky pointers sometimes returned by the hardware
384 * on completed DMA transfers
385 */
386 if (*addr < buf->dma_start ||
387 *addr > buf->dma_ptr)
388 *addr = buf->dma_ptr;
389 DPRINTK("curr_pos: b=%#x a=%#x\n", (int)dma->curr->id, *addr);
390 ret = 0;
391 } else if (dma->tail && dma->stopped) {
392 dma_buf_t *buf = dma->tail;
393 if (buf_id)
394 *buf_id = buf->id;
395 *addr = buf->dma_ptr;
396 ret = 0;
397 } else {
398 if (buf_id)
399 *buf_id = NULL;
400 *addr = 0;
401 ret = -ENXIO;
402 }
403 local_irq_restore(flags);
404 return ret;
405 }
406
407
408 int sa1100_dma_stop(dmach_t channel)
409 {
410 sa1100_dma_t *dma = &dma_chan[channel];
411 int flags;
412
413 if (channel_is_sa1111_sac(channel))
414 return sa1111_dma_stop(channel);
415
416 if (dma->stopped)
417 return 0;
418 local_irq_save(flags);
419 dma->stopped = 1;
420 /*
421 * Stop DMA and tweak state variables so everything could restart
422 * from there when resume/wakeup occurs.
423 */
424 dma->regs->ClrDCSR = DCSR_RUN | DCSR_IE;
425 if (dma->curr) {
426 dma_buf_t *buf = dma->curr;
427 if (dma->spin_ref <= 0) {
428 dma_addr_t curpos;
429 sa1100_dma_get_current(channel, NULL, &curpos);
430 buf->size += buf->dma_ptr - curpos;
431 buf->dma_ptr = curpos;
432 }
433 buf->ref = 0;
434 dma->tail = buf;
435 dma->curr = NULL;
436 }
437 dma->spin_ref = 0;
438 dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB;
439 process_dma(dma);
440 local_irq_restore(flags);
441 return 0;
442 }
443
444
445 int sa1100_dma_resume(dmach_t channel)
446 {
447 sa1100_dma_t *dma = &dma_chan[channel];
448
449 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
450 return -EINVAL;
451
452 if (channel_is_sa1111_sac(channel))
453 return sa1111_dma_resume(channel);
454
455 if (dma->stopped) {
456 int flags;
457 save_flags_cli(flags);
458 dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB|DCSR_RUN|DCSR_IE;
459 dma->stopped = 0;
460 dma->spin_ref = 0;
461 process_dma(dma);
462 restore_flags(flags);
463 }
464 return 0;
465 }
466
467
468 int sa1100_dma_flush_all(dmach_t channel)
469 {
470 sa1100_dma_t *dma = &dma_chan[channel];
471 dma_buf_t *buf, *next_buf;
472 int flags;
473
474 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
475 return -EINVAL;
476
477 local_irq_save(flags);
478 if (channel_is_sa1111_sac(channel))
479 sa1111_reset_sac_dma(channel);
480 else
481 dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB|DCSR_RUN|DCSR_IE;
482 buf = dma->curr;
483 if (!buf)
484 buf = dma->tail;
485 dma->head = dma->tail = dma->curr = NULL;
486 dma->stopped = 0;
487 dma->spin_ref = 0;
488 process_dma(dma);
489 local_irq_restore(flags);
490 while (buf) {
491 next_buf = buf->next;
492 kfree(buf);
493 buf = next_buf;
494 }
495 DPRINTK("flushed\n");
496 return 0;
497 }
498
499
500 void sa1100_free_dma(dmach_t channel)
501 {
502 sa1100_dma_t *dma;
503
504 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS)
505 return;
506
507 dma = &dma_chan[channel];
508 if (!dma->in_use) {
509 printk(KERN_ERR "Trying to free free DMA%d\n", channel);
510 return;
511 }
512
513 sa1100_dma_set_spin(channel, 0, 0);
514 sa1100_dma_flush_all(channel);
515
516 if (channel_is_sa1111_sac(channel)) {
517 sa1111_cleanup_sac_dma(channel);
518 } else {
519 free_irq(IRQ_DMA0 + channel, (void *) dma);
520 }
521 dma->in_use = 0;
522
523 DPRINTK("freed\n");
524 }
525
526
527 EXPORT_SYMBOL(sa1100_request_dma);
528 EXPORT_SYMBOL(sa1100_dma_set_callback);
529 EXPORT_SYMBOL(sa1100_dma_set_spin);
530 EXPORT_SYMBOL(sa1100_dma_queue_buffer);
531 EXPORT_SYMBOL(sa1100_dma_get_current);
532 EXPORT_SYMBOL(sa1100_dma_stop);
533 EXPORT_SYMBOL(sa1100_dma_resume);
534 EXPORT_SYMBOL(sa1100_dma_flush_all);
535 EXPORT_SYMBOL(sa1100_free_dma);
536
537
538 #ifdef CONFIG_PM
539 /* Drivers should call this from their PM callback function */
540
541 int sa1100_dma_sleep(dmach_t channel)
542 {
543 sa1100_dma_t *dma = &dma_chan[channel];
544 int orig_state;
545
546 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
547 return -EINVAL;
548
549 if (channel_is_sa1111_sac(channel)) {
550 /* We'll cheat a little until someone actually
551 * write the real thing.
552 */
553 sa1111_reset_sac_dma(channel);
554 return 0;
555 }
556
557 orig_state = dma->stopped;
558 sa1100_dma_stop(channel);
559 dma->regs->ClrDCSR = DCSR_RUN | DCSR_IE | DCSR_STRTA | DCSR_STRTB;
560 dma->stopped = orig_state;
561 dma->spin_ref = 0;
562 return 0;
563 }
564
565 int sa1100_dma_wakeup(dmach_t channel)
566 {
567 sa1100_dma_t *dma = &dma_chan[channel];
568 dma_regs_t *regs;
569 int flags;
570
571 if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use)
572 return -EINVAL;
573
574 if (channel_is_sa1111_sac(channel)) {
575 /* We'll cheat a little until someone actually
576 * write the real thing.
577 */
578 return 0;
579 }
580
581 regs = dma->regs;
582 regs->ClrDCSR =
583 (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
584 DCSR_IE | DCSR_ERROR | DCSR_RUN);
585 regs->DDAR = dma->device;
586 local_irq_save(flags);
587 process_dma(dma);
588 local_irq_restore(flags);
589 return 0;
590 }
591
592 EXPORT_SYMBOL(sa1100_dma_sleep);
593 EXPORT_SYMBOL(sa1100_dma_wakeup);
594
595 #endif
596
597
598 static int __init sa1100_init_dma(void)
599 {
600 int channel;
601 for (channel = 0; channel < SA1100_DMA_CHANNELS; channel++) {
602 dma_chan[channel].regs =
603 (dma_regs_t *) io_p2v(_DDAR(channel));
604 dma_chan[channel].irq = IRQ_DMA0 + channel;
605 }
606 return 0;
607 }
608
609 __initcall(sa1100_init_dma);
610