File: /usr/src/linux/drivers/mtd/chips/amd_flash.c
1 /*
2 * MTD map driver for AMD compatible flash chips (non-CFI)
3 *
4 * Author: Jonas Holmberg <jonas.holmberg@axis.com>
5 *
6 * $Id: amd_flash.c,v 1.8 2001/06/02 14:47:16 dwmw2 Exp $
7 *
8 * Copyright (c) 2001 Axis Communications AB
9 *
10 * This file is under GPL.
11 *
12 */
13
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/errno.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mtd/map.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25
26 /* There's no limit. It exists only to avoid realloc. */
27 #define MAX_AMD_CHIPS 8
28
29 #define DEVICE_TYPE_X8 (8 / 8)
30 #define DEVICE_TYPE_X16 (16 / 8)
31 #define DEVICE_TYPE_X32 (32 / 8)
32
33 /* Addresses */
34 #define ADDR_MANUFACTURER 0x0000
35 #define ADDR_DEVICE_ID 0x0001
36 #define ADDR_UNLOCK_1 0x0555
37 #define ADDR_UNLOCK_2 0x02AA
38
39 /* Commands */
40 #define CMD_UNLOCK_DATA_1 0x00AA
41 #define CMD_UNLOCK_DATA_2 0x0055
42 #define CMD_MANUFACTURER_UNLOCK_DATA 0x0090
43 #define CMD_UNLOCK_BYPASS_MODE 0x0020
44 #define CMD_PROGRAM_UNLOCK_DATA 0x00A0
45 #define CMD_RESET_DATA 0x00F0
46 #define CMD_SECTOR_ERASE_UNLOCK_DATA 0x0080
47 #define CMD_SECTOR_ERASE_UNLOCK_DATA_2 0x0030
48
49 /* Manufacturers */
50 #define MANUFACTURER_AMD 0x0001
51 #define MANUFACTURER_FUJITSU 0x0004
52 #define MANUFACTURER_ST 0x0020
53 #define MANUFACTURER_SST 0x00BF
54 #define MANUFACTURER_TOSHIBA 0x0098
55
56 /* AMD */
57 #define AM29F800BB 0x2258
58 #define AM29F800BT 0x22D6
59 #define AM29LV800BB 0x225B
60 #define AM29LV800BT 0x22DA
61 #define AM29LV160DT 0x22C4
62 #define AM29LV160DB 0x2249
63
64 /* Fujitsu */
65 #define MBM29LV160TE 0x22C4
66 #define MBM29LV160BE 0x2249
67
68 /* ST - www.st.com */
69 #define M29W800T 0x00D7
70 #define M29W160DT 0x22C4
71 #define M29W160DB 0x2249
72
73 /* SST */
74 #define SST39LF800 0x2781
75 #define SST39LF160 0x2782
76
77 /* Toshiba */
78 #define TC58FVT160 0x00C2
79 #define TC58FVB160 0x0043
80
81 #define D6_MASK 0x40
82
83 struct amd_flash_private {
84 int device_type;
85 int interleave;
86 int numchips;
87 unsigned long chipshift;
88 // const char *im_name;
89 struct flchip chips[0];
90 };
91
92 struct amd_flash_info {
93 const __u16 mfr_id;
94 const __u16 dev_id;
95 const char *name;
96 const u_long size;
97 const int numeraseregions;
98 const struct mtd_erase_region_info regions[4];
99 };
100
101
102
103 static int amd_flash_read(struct mtd_info *, loff_t, size_t, size_t *,
104 u_char *);
105 static int amd_flash_write(struct mtd_info *, loff_t, size_t, size_t *,
106 const u_char *);
107 static int amd_flash_erase(struct mtd_info *, struct erase_info *);
108 static void amd_flash_sync(struct mtd_info *);
109 static int amd_flash_suspend(struct mtd_info *);
110 static void amd_flash_resume(struct mtd_info *);
111 static void amd_flash_destroy(struct mtd_info *);
112 static struct mtd_info *amd_flash_probe(struct map_info *map);
113
114
115 static struct mtd_chip_driver amd_flash_chipdrv = {
116 probe: amd_flash_probe,
117 destroy: amd_flash_destroy,
118 name: "amd_flash",
119 module: THIS_MODULE
120 };
121
122
123
124 static const char im_name[] = "amd_flash";
125
126
127
128 static inline __u32 wide_read(struct map_info *map, __u32 addr)
129 {
130 if (map->buswidth == 1) {
131 return map->read8(map, addr);
132 } else if (map->buswidth == 2) {
133 return map->read16(map, addr);
134 } else if (map->buswidth == 4) {
135 return map->read32(map, addr);
136 }
137
138 return 0;
139 }
140
141 static inline void wide_write(struct map_info *map, __u32 val, __u32 addr)
142 {
143 if (map->buswidth == 1) {
144 map->write8(map, val, addr);
145 } else if (map->buswidth == 2) {
146 map->write16(map, val, addr);
147 } else if (map->buswidth == 4) {
148 map->write32(map, val, addr);
149 }
150 }
151
152 static inline __u32 make_cmd(struct map_info *map, __u32 cmd)
153 {
154 const struct amd_flash_private *private = map->fldrv_priv;
155 if ((private->interleave == 2) &&
156 (private->device_type == DEVICE_TYPE_X16)) {
157 cmd |= (cmd << 16);
158 }
159
160 return cmd;
161 }
162
163 static inline void send_unlock(struct map_info *map, unsigned long base)
164 {
165 wide_write(map, (CMD_UNLOCK_DATA_1 << 16) | CMD_UNLOCK_DATA_1,
166 base + (map->buswidth * ADDR_UNLOCK_1));
167 wide_write(map, (CMD_UNLOCK_DATA_2 << 16) | CMD_UNLOCK_DATA_2,
168 base + (map->buswidth * ADDR_UNLOCK_2));
169 }
170
171 static inline void send_cmd(struct map_info *map, unsigned long base, __u32 cmd)
172 {
173 send_unlock(map, base);
174 wide_write(map, make_cmd(map, cmd),
175 base + (map->buswidth * ADDR_UNLOCK_1));
176 }
177
178 static inline void send_cmd_to_addr(struct map_info *map, unsigned long base,
179 __u32 cmd, unsigned long addr)
180 {
181 send_unlock(map, base);
182 wide_write(map, make_cmd(map, cmd), addr);
183 }
184
185 static inline int flash_is_busy(struct map_info *map, unsigned long addr,
186 int interleave)
187 {
188
189 if ((interleave == 2) && (map->buswidth == 4)) {
190 __u32 read1, read2;
191
192 read1 = wide_read(map, addr);
193 read2 = wide_read(map, addr);
194
195 return (((read1 >> 16) & D6_MASK) !=
196 ((read2 >> 16) & D6_MASK)) ||
197 (((read1 & 0xffff) & D6_MASK) !=
198 ((read2 & 0xffff) & D6_MASK));
199 }
200
201 return ((wide_read(map, addr) & D6_MASK) !=
202 (wide_read(map, addr) & D6_MASK));
203 }
204
205
206
207 /*
208 * Reads JEDEC manufacturer ID and device ID and returns the index of the first
209 * matching table entry (-1 if not found or alias for already found chip).
210 */
211 static int probe_new_chip(struct mtd_info *mtd, __u32 base,
212 struct flchip *chips,
213 struct amd_flash_private *private,
214 const struct amd_flash_info *table, int table_size)
215 {
216 __u32 mfr_id, dev_id;
217 struct map_info *map = mtd->priv;
218 struct amd_flash_private temp;
219 int i;
220
221 temp.device_type = DEVICE_TYPE_X16; // Assume X16 (FIXME)
222 temp.interleave = 2;
223 map->fldrv_priv = &temp;
224
225 /* Enter autoselect mode. */
226 send_cmd(map, base, CMD_RESET_DATA);
227 send_cmd(map, base, CMD_MANUFACTURER_UNLOCK_DATA);
228
229 mfr_id = wide_read(map, base + (map->buswidth * ADDR_MANUFACTURER));
230 dev_id = wide_read(map, base + (map->buswidth * ADDR_DEVICE_ID));
231
232 if ((map->buswidth == 4) && ((mfr_id >> 16) == (mfr_id & 0xffff)) &&
233 ((dev_id >> 16) == (dev_id & 0xffff))) {
234 mfr_id = mfr_id & 0xffff;
235 dev_id = dev_id & 0xffff;
236 } else {
237 temp.interleave = 1;
238 }
239
240 for (i = 0; i < table_size; i++) {
241 if ((mfr_id == table[i].mfr_id) &&
242 (dev_id == table[i].dev_id)) {
243 if (chips) {
244 int j;
245
246 /* Is this an alias for an already found chip?
247 * In that case that chip should be in
248 * autoselect mode now.
249 */
250 for (j = 0; j < private->numchips; j++) {
251 if ((wide_read(map, chips[j].start +
252 (map->buswidth *
253 ADDR_MANUFACTURER))
254 == mfr_id)
255 &&
256 (wide_read(map, chips[j].start +
257 (map->buswidth *
258 ADDR_DEVICE_ID))
259 == dev_id)) {
260
261 /* Exit autoselect mode. */
262 send_cmd(map, base,
263 CMD_RESET_DATA);
264
265 return -1;
266 }
267 }
268
269 if (private->numchips == MAX_AMD_CHIPS) {
270 printk(KERN_WARNING
271 "%s: Too many flash chips "
272 "detected. Increase "
273 "MAX_AMD_CHIPS from %d.\n",
274 map->name, MAX_AMD_CHIPS);
275
276 return -1;
277 }
278
279 chips[private->numchips].start = base;
280 chips[private->numchips].state = FL_READY;
281 chips[private->numchips].mutex =
282 &chips[private->numchips]._spinlock;
283 private->numchips++;
284 }
285
286 printk("%s: Found %d x %ldMiB %s at 0x%x\n", map->name,
287 temp.interleave, (table[i].size)/(1024*1024),
288 table[i].name, base);
289
290 mtd->size += table[i].size * temp.interleave;
291 mtd->numeraseregions += table[i].numeraseregions;
292
293 break;
294 }
295 }
296
297 /* Exit autoselect mode. */
298 send_cmd(map, base, CMD_RESET_DATA);
299
300 if (i == table_size) {
301 printk(KERN_DEBUG "%s: unknown flash device at 0x%x, "
302 "mfr id 0x%x, dev id 0x%x\n", map->name,
303 base, mfr_id, dev_id);
304 map->fldrv_priv = NULL;
305
306 return -1;
307 }
308
309 private->device_type = temp.device_type;
310 private->interleave = temp.interleave;
311
312 return i;
313 }
314
315
316
317 static struct mtd_info *amd_flash_probe(struct map_info *map)
318 {
319 /* Keep this table on the stack so that it gets deallocated after the
320 * probe is done.
321 */
322 const struct amd_flash_info table[] = {
323 {
324 mfr_id: MANUFACTURER_AMD,
325 dev_id: AM29LV160DT,
326 name: "AMD AM29LV160DT",
327 size: 0x00200000,
328 numeraseregions: 4,
329 regions: {
330 { offset: 0x000000, erasesize: 0x10000, numblocks: 31 },
331 { offset: 0x1F0000, erasesize: 0x08000, numblocks: 1 },
332 { offset: 0x1F8000, erasesize: 0x02000, numblocks: 2 },
333 { offset: 0x1FC000, erasesize: 0x04000, numblocks: 1 }
334 }
335 }, {
336 mfr_id: MANUFACTURER_AMD,
337 dev_id: AM29LV160DB,
338 name: "AMD AM29LV160DB",
339 size: 0x00200000,
340 numeraseregions: 4,
341 regions: {
342 { offset: 0x000000, erasesize: 0x04000, numblocks: 1 },
343 { offset: 0x004000, erasesize: 0x02000, numblocks: 2 },
344 { offset: 0x008000, erasesize: 0x08000, numblocks: 1 },
345 { offset: 0x010000, erasesize: 0x10000, numblocks: 31 }
346 }
347 }, {
348 mfr_id: MANUFACTURER_TOSHIBA,
349 dev_id: TC58FVT160,
350 name: "Toshiba TC58FVT160",
351 size: 0x00200000,
352 numeraseregions: 4,
353 regions: {
354 { offset: 0x000000, erasesize: 0x10000, numblocks: 31 },
355 { offset: 0x1F0000, erasesize: 0x08000, numblocks: 1 },
356 { offset: 0x1F8000, erasesize: 0x02000, numblocks: 2 },
357 { offset: 0x1FC000, erasesize: 0x04000, numblocks: 1 }
358 }
359 }, {
360 mfr_id: MANUFACTURER_FUJITSU,
361 dev_id: MBM29LV160TE,
362 name: "Fujitsu MBM29LV160TE",
363 size: 0x00200000,
364 numeraseregions: 4,
365 regions: {
366 { offset: 0x000000, erasesize: 0x10000, numblocks: 31 },
367 { offset: 0x1F0000, erasesize: 0x08000, numblocks: 1 },
368 { offset: 0x1F8000, erasesize: 0x02000, numblocks: 2 },
369 { offset: 0x1FC000, erasesize: 0x04000, numblocks: 1 }
370 }
371 }, {
372 mfr_id: MANUFACTURER_TOSHIBA,
373 dev_id: TC58FVB160,
374 name: "Toshiba TC58FVB160",
375 size: 0x00200000,
376 numeraseregions: 4,
377 regions: {
378 { offset: 0x000000, erasesize: 0x04000, numblocks: 1 },
379 { offset: 0x004000, erasesize: 0x02000, numblocks: 2 },
380 { offset: 0x008000, erasesize: 0x08000, numblocks: 1 },
381 { offset: 0x010000, erasesize: 0x10000, numblocks: 31 }
382 }
383 }, {
384 mfr_id: MANUFACTURER_FUJITSU,
385 dev_id: MBM29LV160BE,
386 name: "Fujitsu MBM29LV160BE",
387 size: 0x00200000,
388 numeraseregions: 4,
389 regions: {
390 { offset: 0x000000, erasesize: 0x04000, numblocks: 1 },
391 { offset: 0x004000, erasesize: 0x02000, numblocks: 2 },
392 { offset: 0x008000, erasesize: 0x08000, numblocks: 1 },
393 { offset: 0x010000, erasesize: 0x10000, numblocks: 31 }
394 }
395 }, {
396 mfr_id: MANUFACTURER_AMD,
397 dev_id: AM29LV800BB,
398 name: "AMD AM29LV800BB",
399 size: 0x00100000,
400 numeraseregions: 4,
401 regions: {
402 { offset: 0x000000, erasesize: 0x04000, numblocks: 1 },
403 { offset: 0x004000, erasesize: 0x02000, numblocks: 2 },
404 { offset: 0x008000, erasesize: 0x08000, numblocks: 1 },
405 { offset: 0x010000, erasesize: 0x10000, numblocks: 15 }
406 }
407 }, {
408 mfr_id: MANUFACTURER_AMD,
409 dev_id: AM29F800BB,
410 name: "AMD AM29F800BB",
411 size: 0x00100000,
412 numeraseregions: 4,
413 regions: {
414 { offset: 0x000000, erasesize: 0x04000, numblocks: 1 },
415 { offset: 0x004000, erasesize: 0x02000, numblocks: 2 },
416 { offset: 0x008000, erasesize: 0x08000, numblocks: 1 },
417 { offset: 0x010000, erasesize: 0x10000, numblocks: 15 }
418 }
419 }, {
420 mfr_id: MANUFACTURER_AMD,
421 dev_id: AM29LV800BT,
422 name: "AMD AM29LV800BT",
423 size: 0x00100000,
424 numeraseregions: 4,
425 regions: {
426 { offset: 0x000000, erasesize: 0x10000, numblocks: 15 },
427 { offset: 0x0F0000, erasesize: 0x08000, numblocks: 1 },
428 { offset: 0x0F8000, erasesize: 0x02000, numblocks: 2 },
429 { offset: 0x0FC000, erasesize: 0x04000, numblocks: 1 }
430 }
431 }, {
432 mfr_id: MANUFACTURER_AMD,
433 dev_id: AM29F800BT,
434 name: "AMD AM29F800BT",
435 size: 0x00100000,
436 numeraseregions: 4,
437 regions: {
438 { offset: 0x000000, erasesize: 0x10000, numblocks: 15 },
439 { offset: 0x0F0000, erasesize: 0x08000, numblocks: 1 },
440 { offset: 0x0F8000, erasesize: 0x02000, numblocks: 2 },
441 { offset: 0x0FC000, erasesize: 0x04000, numblocks: 1 }
442 }
443 }, {
444 mfr_id: MANUFACTURER_AMD,
445 dev_id: AM29LV800BB,
446 name: "AMD AM29LV800BB",
447 size: 0x00100000,
448 numeraseregions: 4,
449 regions: {
450 { offset: 0x000000, erasesize: 0x10000, numblocks: 15 },
451 { offset: 0x0F0000, erasesize: 0x08000, numblocks: 1 },
452 { offset: 0x0F8000, erasesize: 0x02000, numblocks: 2 },
453 { offset: 0x0FC000, erasesize: 0x04000, numblocks: 1 }
454 }
455 }, {
456 mfr_id: MANUFACTURER_ST,
457 dev_id: M29W800T,
458 name: "ST M29W800T",
459 size: 0x00100000,
460 numeraseregions: 4,
461 regions: {
462 { offset: 0x000000, erasesize: 0x10000, numblocks: 15 },
463 { offset: 0x0F0000, erasesize: 0x08000, numblocks: 1 },
464 { offset: 0x0F8000, erasesize: 0x02000, numblocks: 2 },
465 { offset: 0x0FC000, erasesize: 0x04000, numblocks: 1 }
466 }
467 }, {
468 mfr_id: MANUFACTURER_ST,
469 dev_id: M29W160DT,
470 name: "ST M29W160DT",
471 size: 0x00200000,
472 numeraseregions: 4,
473 regions: {
474 { offset: 0x000000, erasesize: 0x10000, numblocks: 31 },
475 { offset: 0x1F0000, erasesize: 0x08000, numblocks: 1 },
476 { offset: 0x1F8000, erasesize: 0x02000, numblocks: 2 },
477 { offset: 0x1FC000, erasesize: 0x04000, numblocks: 1 }
478 }
479 }, {
480 mfr_id: MANUFACTURER_ST,
481 dev_id: M29W160DB,
482 name: "ST M29W160DB",
483 size: 0x00200000,
484 numeraseregions: 4,
485 regions: {
486 { offset: 0x000000, erasesize: 0x04000, numblocks: 1 },
487 { offset: 0x004000, erasesize: 0x02000, numblocks: 2 },
488 { offset: 0x008000, erasesize: 0x08000, numblocks: 1 },
489 { offset: 0x010000, erasesize: 0x10000, numblocks: 31 }
490 }
491 }
492 };
493
494 struct mtd_info *mtd;
495 struct flchip chips[MAX_AMD_CHIPS];
496 int table_pos[MAX_AMD_CHIPS];
497 struct amd_flash_private temp;
498 struct amd_flash_private *private;
499 u_long size;
500 unsigned long base;
501 int i;
502 int reg_idx;
503 int offset;
504
505 mtd = (struct mtd_info*)kmalloc(sizeof(*mtd), GFP_KERNEL);
506 if (!mtd) {
507 printk(KERN_WARNING
508 "%s: kmalloc failed for info structure\n", map->name);
509 return NULL;
510 }
511 memset(mtd, 0, sizeof(*mtd));
512 mtd->priv = map;
513
514 memset(&temp, 0, sizeof(temp));
515
516 printk("%s: Probing for AMD compatible flash...\n", map->name);
517
518 if ((table_pos[0] = probe_new_chip(mtd, 0, NULL, &temp, table,
519 sizeof(table)/sizeof(table[0])))
520 == -1) {
521 printk(KERN_WARNING
522 "%s: Found no AMD compatible device at location zero\n",
523 map->name);
524 kfree(mtd);
525
526 return NULL;
527 }
528
529 chips[0].start = 0;
530 chips[0].state = FL_READY;
531 chips[0].mutex = &chips[0]._spinlock;
532 temp.numchips = 1;
533 for (size = mtd->size; size > 1; size >>= 1) {
534 temp.chipshift++;
535 }
536 switch (temp.interleave) {
537 case 2:
538 temp.chipshift += 1;
539 break;
540 case 4:
541 temp.chipshift += 2;
542 break;
543 }
544
545 /* Find out if there are any more chips in the map. */
546 for (base = (1 << temp.chipshift);
547 base < map->size;
548 base += (1 << temp.chipshift)) {
549 int numchips = temp.numchips;
550 table_pos[numchips] = probe_new_chip(mtd, base, chips,
551 &temp, table, sizeof(table)/sizeof(table[0]));
552 }
553
554 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info) *
555 mtd->numeraseregions, GFP_KERNEL);
556 if (!mtd->eraseregions) {
557 printk(KERN_WARNING "%s: Failed to allocate "
558 "memory for MTD erase region info\n", map->name);
559 kfree(mtd);
560 map->fldrv_priv = NULL;
561 return 0;
562 }
563
564 reg_idx = 0;
565 offset = 0;
566 for (i = 0; i < temp.numchips; i++) {
567 int dev_size;
568 int j;
569
570 dev_size = 0;
571 for (j = 0; j < table[table_pos[i]].numeraseregions; j++) {
572 mtd->eraseregions[reg_idx].offset = offset +
573 (table[table_pos[i]].regions[j].offset *
574 temp.interleave);
575 mtd->eraseregions[reg_idx].erasesize =
576 table[table_pos[i]].regions[j].erasesize *
577 temp.interleave;
578 mtd->eraseregions[reg_idx].numblocks =
579 table[table_pos[i]].regions[j].numblocks;
580 if (mtd->erasesize <
581 mtd->eraseregions[reg_idx].erasesize) {
582 mtd->erasesize =
583 mtd->eraseregions[reg_idx].erasesize;
584 }
585 dev_size += mtd->eraseregions[reg_idx].erasesize *
586 mtd->eraseregions[reg_idx].numblocks;
587 reg_idx++;
588 }
589 offset += dev_size;
590 }
591 mtd->type = MTD_NORFLASH;
592 mtd->flags = MTD_CAP_NORFLASH;
593 mtd->name = map->name;
594 mtd->erase = amd_flash_erase;
595 mtd->read = amd_flash_read;
596 mtd->write = amd_flash_write;
597 mtd->sync = amd_flash_sync;
598 mtd->suspend = amd_flash_suspend;
599 mtd->resume = amd_flash_resume;
600
601 private = kmalloc(sizeof(*private) + (sizeof(struct flchip) *
602 temp.numchips), GFP_KERNEL);
603 if (!private) {
604 printk(KERN_WARNING
605 "%s: kmalloc failed for private structure\n", map->name);
606 kfree(mtd);
607 map->fldrv_priv = NULL;
608 return NULL;
609 }
610 memcpy(private, &temp, sizeof(temp));
611 memcpy(private->chips, chips,
612 sizeof(struct flchip) * private->numchips);
613 for (i = 0; i < private->numchips; i++) {
614 init_waitqueue_head(&private->chips[i].wq);
615 spin_lock_init(&private->chips[i]._spinlock);
616 }
617
618 map->fldrv_priv = private;
619
620 map->fldrv = &amd_flash_chipdrv;
621 MOD_INC_USE_COUNT;
622
623 return mtd;
624 }
625
626
627
628 static inline int read_one_chip(struct map_info *map, struct flchip *chip,
629 loff_t adr, size_t len, u_char *buf)
630 {
631 DECLARE_WAITQUEUE(wait, current);
632 unsigned long timeo = jiffies + HZ;
633
634 retry:
635 spin_lock_bh(chip->mutex);
636
637 if (chip->state != FL_READY){
638 printk(KERN_INFO "%s: waiting for chip to read, state = %d\n",
639 map->name, chip->state);
640 set_current_state(TASK_UNINTERRUPTIBLE);
641 add_wait_queue(&chip->wq, &wait);
642
643 spin_unlock_bh(chip->mutex);
644
645 schedule();
646 remove_wait_queue(&chip->wq, &wait);
647
648 if(signal_pending(current)) {
649 return -EINTR;
650 }
651
652 timeo = jiffies + HZ;
653
654 goto retry;
655 }
656
657 adr += chip->start;
658
659 chip->state = FL_READY;
660
661 map->copy_from(map, buf, adr, len);
662
663 wake_up(&chip->wq);
664 spin_unlock_bh(chip->mutex);
665
666 return 0;
667 }
668
669
670
671 static int amd_flash_read(struct mtd_info *mtd, loff_t from, size_t len,
672 size_t *retlen, u_char *buf)
673 {
674 struct map_info *map = mtd->priv;
675 struct amd_flash_private *private = map->fldrv_priv;
676 unsigned long ofs;
677 int chipnum;
678 int ret = 0;
679
680 if ((from + len) > mtd->size) {
681 printk(KERN_WARNING "%s: read request past end of device "
682 "(0x%lx)\n", map->name, (unsigned long)from + len);
683
684 return -EINVAL;
685 }
686
687 /* Offset within the first chip that the first read should start. */
688 chipnum = (from >> private->chipshift);
689 ofs = from - (chipnum << private->chipshift);
690
691 *retlen = 0;
692
693 while (len) {
694 unsigned long this_len;
695
696 if (chipnum >= private->numchips) {
697 break;
698 }
699
700 if ((len + ofs - 1) >> private->chipshift) {
701 this_len = (1 << private->chipshift) - ofs;
702 } else {
703 this_len = len;
704 }
705
706 ret = read_one_chip(map, &private->chips[chipnum], ofs,
707 this_len, buf);
708 if (ret) {
709 break;
710 }
711
712 *retlen += this_len;
713 len -= this_len;
714 buf += this_len;
715
716 ofs = 0;
717 chipnum++;
718 }
719
720 return ret;
721 }
722
723
724
725 static int write_one_word(struct map_info *map, struct flchip *chip,
726 unsigned long adr, __u32 datum)
727 {
728 unsigned long timeo = jiffies + HZ;
729 struct amd_flash_private *private = map->fldrv_priv;
730 DECLARE_WAITQUEUE(wait, current);
731 int ret = 0;
732 int times_left;
733
734 retry:
735 spin_lock_bh(chip->mutex);
736
737 if (chip->state != FL_READY){
738 printk("%s: waiting for chip to write, state = %d\n",
739 map->name, chip->state);
740 set_current_state(TASK_UNINTERRUPTIBLE);
741 add_wait_queue(&chip->wq, &wait);
742
743 spin_unlock_bh(chip->mutex);
744
745 schedule();
746 remove_wait_queue(&chip->wq, &wait);
747 printk(KERN_INFO "%s: woke up to write\n", map->name);
748 if(signal_pending(current))
749 return -EINTR;
750
751 timeo = jiffies + HZ;
752
753 goto retry;
754 }
755
756 chip->state = FL_WRITING;
757
758 adr += chip->start;
759 ENABLE_VPP(map);
760 send_cmd(map, chip->start, CMD_PROGRAM_UNLOCK_DATA);
761 wide_write(map, datum, adr);
762
763 times_left = 500000;
764 while (times_left-- && flash_is_busy(map, chip->start,
765 private->interleave)) {
766 if (current->need_resched) {
767 spin_unlock_bh(chip->mutex);
768 schedule();
769 spin_lock_bh(chip->mutex);
770 }
771 }
772
773 if (!times_left) {
774 printk(KERN_WARNING "%s: write to 0x%lx timed out!\n",
775 map->name, adr);
776 ret = -EIO;
777 } else {
778 __u32 verify;
779 if ((verify = wide_read(map, adr)) != datum) {
780 printk(KERN_WARNING "%s: write to 0x%lx failed. "
781 "datum = %x, verify = %x\n",
782 map->name, adr, datum, verify);
783 ret = -EIO;
784 }
785 }
786
787 DISABLE_VPP(map);
788 chip->state = FL_READY;
789 wake_up(&chip->wq);
790 spin_unlock_bh(chip->mutex);
791
792 return ret;
793 }
794
795
796
797 static int amd_flash_write(struct mtd_info *mtd, loff_t to , size_t len,
798 size_t *retlen, const u_char *buf)
799 {
800 struct map_info *map = mtd->priv;
801 struct amd_flash_private *private = map->fldrv_priv;
802 int ret = 0;
803 int chipnum;
804 unsigned long ofs;
805 unsigned long chipstart;
806
807 *retlen = 0;
808 if (!len) {
809 return 0;
810 }
811
812 chipnum = to >> private->chipshift;
813 ofs = to - (chipnum << private->chipshift);
814 chipstart = private->chips[chipnum].start;
815
816 /* If it's not bus-aligned, do the first byte write. */
817 if (ofs & (map->buswidth - 1)) {
818 unsigned long bus_ofs = ofs & ~(map->buswidth - 1);
819 int i = ofs - bus_ofs;
820 int n = 0;
821 u_char tmp_buf[4];
822 __u32 datum;
823
824 map->copy_from(map, tmp_buf,
825 bus_ofs + private->chips[chipnum].start,
826 map->buswidth);
827 while (len && i < map->buswidth)
828 tmp_buf[i++] = buf[n++], len--;
829
830 if (map->buswidth == 2) {
831 datum = *(__u16*)tmp_buf;
832 } else if (map->buswidth == 4) {
833 datum = *(__u32*)tmp_buf;
834 } else {
835 return -EINVAL; /* should never happen, but be safe */
836 }
837
838 ret = write_one_word(map, &private->chips[chipnum], bus_ofs,
839 datum);
840 if (ret) {
841 return ret;
842 }
843
844 ofs += n;
845 buf += n;
846 (*retlen) += n;
847
848 if (ofs >> private->chipshift) {
849 chipnum++;
850 ofs = 0;
851 if (chipnum == private->numchips) {
852 return 0;
853 }
854 }
855 }
856
857 /* We are now aligned, write as much as possible. */
858 while(len >= map->buswidth) {
859 __u32 datum;
860
861 if (map->buswidth == 1) {
862 datum = *(__u8*)buf;
863 } else if (map->buswidth == 2) {
864 datum = *(__u16*)buf;
865 } else if (map->buswidth == 4) {
866 datum = *(__u32*)buf;
867 } else {
868 return -EINVAL;
869 }
870
871 ret = write_one_word(map, &private->chips[chipnum], ofs, datum);
872
873 if (ret) {
874 return ret;
875 }
876
877 ofs += map->buswidth;
878 buf += map->buswidth;
879 (*retlen) += map->buswidth;
880 len -= map->buswidth;
881
882 if (ofs >> private->chipshift) {
883 chipnum++;
884 ofs = 0;
885 if (chipnum == private->numchips) {
886 return 0;
887 }
888 chipstart = private->chips[chipnum].start;
889 }
890 }
891
892 if (len & (map->buswidth - 1)) {
893 int i = 0, n = 0;
894 u_char tmp_buf[2];
895 __u32 datum;
896
897 map->copy_from(map, tmp_buf,
898 ofs + private->chips[chipnum].start,
899 map->buswidth);
900 while (len--) {
901 tmp_buf[i++] = buf[n++];
902 }
903
904 if (map->buswidth == 2) {
905 datum = *(__u16*)tmp_buf;
906 } else if (map->buswidth == 4) {
907 datum = *(__u32*)tmp_buf;
908 } else {
909 return -EINVAL; /* should never happen, but be safe */
910 }
911
912 ret = write_one_word(map, &private->chips[chipnum], ofs, datum);
913
914 if (ret) {
915 return ret;
916 }
917
918 (*retlen) += n;
919 }
920
921 return 0;
922 }
923
924
925
926 static inline int erase_one_block(struct map_info *map, struct flchip *chip,
927 unsigned long adr, u_long size)
928 {
929 unsigned long timeo = jiffies + HZ;
930 struct amd_flash_private *private = map->fldrv_priv;
931 DECLARE_WAITQUEUE(wait, current);
932
933 retry:
934 spin_lock_bh(chip->mutex);
935
936 if (chip->state != FL_READY){
937 set_current_state(TASK_UNINTERRUPTIBLE);
938 add_wait_queue(&chip->wq, &wait);
939
940 spin_unlock_bh(chip->mutex);
941
942 schedule();
943 remove_wait_queue(&chip->wq, &wait);
944
945 if (signal_pending(current)) {
946 return -EINTR;
947 }
948
949 timeo = jiffies + HZ;
950
951 goto retry;
952 }
953
954 chip->state = FL_ERASING;
955
956 adr += chip->start;
957 ENABLE_VPP(map);
958 send_cmd(map, chip->start, CMD_SECTOR_ERASE_UNLOCK_DATA);
959 send_cmd_to_addr(map, chip->start, CMD_SECTOR_ERASE_UNLOCK_DATA_2, adr);
960
961 timeo = jiffies + (HZ * 20);
962
963 spin_unlock_bh(chip->mutex);
964 schedule_timeout(HZ);
965 spin_lock_bh(chip->mutex);
966
967 while (flash_is_busy(map, chip->start, private->interleave)) {
968
969 if (chip->state != FL_ERASING) {
970 /* Someone's suspended the erase. Sleep */
971 set_current_state(TASK_UNINTERRUPTIBLE);
972 add_wait_queue(&chip->wq, &wait);
973
974 spin_unlock_bh(chip->mutex);
975 printk(KERN_INFO "%s: erase suspended. Sleeping\n",
976 map->name);
977 schedule();
978 remove_wait_queue(&chip->wq, &wait);
979
980 if (signal_pending(current)) {
981 return -EINTR;
982 }
983
984 timeo = jiffies + (HZ*2); /* FIXME */
985 spin_lock_bh(chip->mutex);
986 continue;
987 }
988
989 /* OK Still waiting */
990 if (time_after(jiffies, timeo)) {
991 chip->state = FL_READY;
992 spin_unlock_bh(chip->mutex);
993 printk(KERN_WARNING "%s: waiting for erase to complete "
994 "timed out.\n", map->name);
995 DISABLE_VPP(map);
996
997 return -EIO;
998 }
999
1000 /* Latency issues. Drop the lock, wait a while and retry */
1001 spin_unlock_bh(chip->mutex);
1002
1003 if (current->need_resched)
1004 schedule();
1005 else
1006 udelay(1);
1007
1008 spin_lock_bh(chip->mutex);
1009 }
1010
1011 /* Verify every single word */
1012 {
1013 int address;
1014 int error = 0;
1015 __u8 verify;
1016
1017 for (address = adr; address < (adr + size); address++) {
1018 if ((verify = map->read8(map, address)) != 0xFF) {
1019 error = 1;
1020 break;
1021 }
1022 }
1023 if (error) {
1024 chip->state = FL_READY;
1025 spin_unlock_bh(chip->mutex);
1026 printk(KERN_WARNING
1027 "%s: verify error at 0x%x, size %ld.\n",
1028 map->name, address, size);
1029 DISABLE_VPP(map);
1030
1031 return -EIO;
1032 }
1033 }
1034
1035 DISABLE_VPP(map);
1036 chip->state = FL_READY;
1037 wake_up(&chip->wq);
1038 spin_unlock_bh(chip->mutex);
1039
1040 return 0;
1041 }
1042
1043
1044
1045 static int amd_flash_erase(struct mtd_info *mtd, struct erase_info *instr)
1046 {
1047 struct map_info *map = mtd->priv;
1048 struct amd_flash_private *private = map->fldrv_priv;
1049 unsigned long adr, len;
1050 int chipnum;
1051 int ret = 0;
1052 int i;
1053 int first;
1054 struct mtd_erase_region_info *regions = mtd->eraseregions;
1055
1056 if (instr->addr > mtd->size) {
1057 return -EINVAL;
1058 }
1059
1060 if ((instr->len + instr->addr) > mtd->size) {
1061 return -EINVAL;
1062 }
1063
1064 /* Check that both start and end of the requested erase are
1065 * aligned with the erasesize at the appropriate addresses.
1066 */
1067
1068 i = 0;
1069
1070 /* Skip all erase regions which are ended before the start of
1071 the requested erase. Actually, to save on the calculations,
1072 we skip to the first erase region which starts after the
1073 start of the requested erase, and then go back one.
1074 */
1075
1076 while ((i < mtd->numeraseregions) &&
1077 (instr->addr >= regions[i].offset)) {
1078 i++;
1079 }
1080 i--;
1081
1082 /* OK, now i is pointing at the erase region in which this
1083 * erase request starts. Check the start of the requested
1084 * erase range is aligned with the erase size which is in
1085 * effect here.
1086 */
1087
1088 if (instr->addr & (regions[i].erasesize-1)) {
1089 return -EINVAL;
1090 }
1091
1092 /* Remember the erase region we start on. */
1093
1094 first = i;
1095
1096 /* Next, check that the end of the requested erase is aligned
1097 * with the erase region at that address.
1098 */
1099
1100 while ((i < mtd->numeraseregions) &&
1101 ((instr->addr + instr->len) >= regions[i].offset)) {
1102 i++;
1103 }
1104
1105 /* As before, drop back one to point at the region in which
1106 * the address actually falls.
1107 */
1108
1109 i--;
1110
1111 if ((instr->addr + instr->len) & (regions[i].erasesize-1)) {
1112 return -EINVAL;
1113 }
1114
1115 chipnum = instr->addr >> private->chipshift;
1116 adr = instr->addr - (chipnum << private->chipshift);
1117 len = instr->len;
1118
1119 i = first;
1120
1121 while (len) {
1122 ret = erase_one_block(map, &private->chips[chipnum], adr,
1123 regions[i].erasesize);
1124
1125 if (ret) {
1126 return ret;
1127 }
1128
1129 adr += regions[i].erasesize;
1130 len -= regions[i].erasesize;
1131
1132 if ((adr % (1 << private->chipshift)) ==
1133 ((regions[i].offset + (regions[i].erasesize *
1134 regions[i].numblocks))
1135 % (1 << private->chipshift))) {
1136 i++;
1137 }
1138
1139 if (adr >> private->chipshift) {
1140 adr = 0;
1141 chipnum++;
1142 if (chipnum >= private->numchips) {
1143 break;
1144 }
1145 }
1146 }
1147
1148 instr->state = MTD_ERASE_DONE;
1149 if (instr->callback) {
1150 instr->callback(instr);
1151 }
1152
1153 return 0;
1154 }
1155
1156
1157
1158 static void amd_flash_sync(struct mtd_info *mtd)
1159 {
1160 struct map_info *map = mtd->priv;
1161 struct amd_flash_private *private = map->fldrv_priv;
1162 int i;
1163 struct flchip *chip;
1164 int ret = 0;
1165 DECLARE_WAITQUEUE(wait, current);
1166
1167 for (i = 0; !ret && (i < private->numchips); i++) {
1168 chip = &private->chips[i];
1169
1170 retry:
1171 spin_lock_bh(chip->mutex);
1172
1173 switch(chip->state) {
1174 case FL_READY:
1175 case FL_STATUS:
1176 case FL_CFI_QUERY:
1177 case FL_JEDEC_QUERY:
1178 chip->oldstate = chip->state;
1179 chip->state = FL_SYNCING;
1180 /* No need to wake_up() on this state change -
1181 * as the whole point is that nobody can do anything
1182 * with the chip now anyway.
1183 */
1184 case FL_SYNCING:
1185 spin_unlock_bh(chip->mutex);
1186 break;
1187
1188 default:
1189 /* Not an idle state */
1190 add_wait_queue(&chip->wq, &wait);
1191
1192 spin_unlock_bh(chip->mutex);
1193
1194 schedule();
1195
1196 remove_wait_queue(&chip->wq, &wait);
1197
1198 goto retry;
1199 }
1200 }
1201
1202 /* Unlock the chips again */
1203 for (i--; i >= 0; i--) {
1204 chip = &private->chips[i];
1205
1206 spin_lock_bh(chip->mutex);
1207
1208 if (chip->state == FL_SYNCING) {
1209 chip->state = chip->oldstate;
1210 wake_up(&chip->wq);
1211 }
1212 spin_unlock_bh(chip->mutex);
1213 }
1214 }
1215
1216
1217
1218 static int amd_flash_suspend(struct mtd_info *mtd)
1219 {
1220 printk("amd_flash_suspend(): not implemented!\n");
1221 return -EINVAL;
1222 }
1223
1224
1225
1226 static void amd_flash_resume(struct mtd_info *mtd)
1227 {
1228 printk("amd_flash_resume(): not implemented!\n");
1229 }
1230
1231
1232
1233 static void amd_flash_destroy(struct mtd_info *mtd)
1234 {
1235 struct map_info *map = mtd->priv;
1236 struct amd_flash_private *private = map->fldrv_priv;
1237 kfree(private);
1238 }
1239
1240 int __init amd_flash_init(void)
1241 {
1242 register_mtd_chip_driver(&amd_flash_chipdrv);
1243 return 0;
1244 }
1245
1246 void __exit amd_flash_exit(void)
1247 {
1248 unregister_mtd_chip_driver(&amd_flash_chipdrv);
1249 }
1250
1251 module_init(amd_flash_init);
1252 module_exit(amd_flash_exit);
1253