File: /usr/src/linux/drivers/mtd/maps/cstm_mips_ixx.c
1 /*
2 * $Id: cstm_mips_ixx.c,v 1.3 2001/06/02 14:52:23 dwmw2 Exp $
3 *
4 * Mapping of a custom board with both AMD CFI and JEDEC flash in partitions.
5 * Config with both CFI and JEDEC device support.
6 *
7 * Basically physmap.c with the addition of partitions and
8 * an array of mapping info to accomodate more than one flash type per board.
9 *
10 * Copyright 2000 MontaVista Software Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33 #include <linux/module.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <asm/io.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/map.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/config.h>
41
42 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
43 #include <linux/delay.h>
44 #endif
45
46 __u8 cstm_mips_ixx_read8(struct map_info *map, unsigned long ofs)
47 {
48 return *(__u8 *)(map->map_priv_1 + ofs);
49 }
50
51 __u16 cstm_mips_ixx_read16(struct map_info *map, unsigned long ofs)
52 {
53 return *(__u16 *)(map->map_priv_1 + ofs);
54 }
55
56 __u32 cstm_mips_ixx_read32(struct map_info *map, unsigned long ofs)
57 {
58 return *(__u32 *)(map->map_priv_1 + ofs);
59 }
60
61 void cstm_mips_ixx_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
62 {
63 memcpy_fromio(to, map->map_priv_1 + from, len);
64 }
65
66 void cstm_mips_ixx_write8(struct map_info *map, __u8 d, unsigned long adr)
67 {
68 *(__u8 *)(map->map_priv_1 + adr) = d;
69 }
70
71 void cstm_mips_ixx_write16(struct map_info *map, __u16 d, unsigned long adr)
72 {
73 *(__u16 *)(map->map_priv_1 + adr) = d;
74 }
75
76 void cstm_mips_ixx_write32(struct map_info *map, __u32 d, unsigned long adr)
77 {
78 *(__u32 *)(map->map_priv_1 + adr) = d;
79 }
80
81 void cstm_mips_ixx_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
82 {
83 memcpy_toio(map->map_priv_1 + to, from, len);
84 }
85
86 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
87 #define CC_GCR 0xB4013818
88 #define CC_GPBCR 0xB401380A
89 #define CC_GPBDR 0xB4013808
90 #define CC_M68K_DEVICE 1
91 #define CC_M68K_FUNCTION 6
92 #define CC_CONFADDR 0xB8004000
93 #define CC_CONFDATA 0xB8004004
94 #define CC_FC_FCR 0xB8002004
95 #define CC_FC_DCR 0xB8002008
96 #define CC_GPACR 0xB4013802
97 #define CC_GPAICR 0xB4013804
98 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
99
100 void cstm_mips_ixx_set_vpp(struct map_info *map,int vpp)
101 {
102 if (vpp) {
103 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
104 __u16 data;
105 __u8 data1;
106 static u8 first = 1;
107
108 // Set GPIO port B pin3 to high
109 data = *(__u16 *)(CC_GPBCR);
110 data = (data & 0xff0f) | 0x0040;
111 *(__u16 *)CC_GPBCR = data;
112 *(__u8 *)CC_GPBDR = (*(__u8*)CC_GPBDR) | 0x08;
113 if (first) {
114 first = 0;
115 /* need to have this delay for first
116 enabling vpp after powerup */
117 udelay(40);
118 }
119 #endif /* CONFIG_MIPS_ITE8172 */
120 }
121 else {
122 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
123 __u16 data;
124
125 // Set GPIO port B pin3 to high
126 data = *(__u16 *)(CC_GPBCR);
127 data = (data & 0xff3f) | 0x0040;
128 *(__u16 *)CC_GPBCR = data;
129 *(__u8 *)CC_GPBDR = (*(__u8*)CC_GPBDR) & 0xf7;
130 #endif /* CONFIG_MIPS_ITE8172 */
131 }
132 }
133
134 const struct map_info basic_cstm_mips_ixx_map = {
135 NULL,
136 0,
137 0,
138 cstm_mips_ixx_read8,
139 cstm_mips_ixx_read16,
140 cstm_mips_ixx_read32,
141 cstm_mips_ixx_copy_from,
142 cstm_mips_ixx_write8,
143 cstm_mips_ixx_write16,
144 cstm_mips_ixx_write32,
145 cstm_mips_ixx_copy_to,
146 cstm_mips_ixx_set_vpp,
147 0,
148 0
149 };
150
151 /* board and partition description */
152
153 #define MAX_PHYSMAP_PARTITIONS 8
154 struct cstm_mips_ixx_info {
155 char *name;
156 unsigned long window_addr;
157 unsigned long window_size;
158 int buswidth;
159 int num_partitions;
160 };
161
162 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
163 #define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
164 const struct cstm_mips_ixx_info cstm_mips_ixx_board_desc[PHYSMAP_NUMBER] =
165 {
166 { // 28F128J3A in 2x16 configuration
167 "big flash", // name
168 0x08000000, // window_addr
169 0x02000000, // window_size
170 4, // buswidth
171 1, // num_partitions
172 }
173
174 };
175 static struct mtd_partition cstm_mips_ixx_partitions[PHYSMAP_NUMBER][MAX_PHYSMAP_PARTITIONS] = {
176 { // 28F128J3A in 2x16 configuration
177 {
178 name: "main partition ",
179 size: 0x02000000, // 128 x 2 x 128k byte sectors
180 offset: 0,
181 },
182 },
183 };
184 #else /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
185 #define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
186 const struct cstm_mips_ixx_info cstm_mips_ixx_board_desc[PHYSMAP_NUMBER] =
187 {
188 {
189 "MTD flash", // name
190 CONFIG_MTD_CSTM_MIPS_IXX_START, // window_addr
191 CONFIG_MTD_CSTM_MIPS_IXX_LEN, // window_size
192 CONFIG_MTD_CSTM_MIPS_IXX_BUSWIDTH, // buswidth
193 1, // num_partitions
194 },
195
196 };
197 static struct mtd_partition cstm_mips_ixx_partitions[PHYSMAP_NUMBER][MAX_PHYSMAP_PARTITIONS] = {
198 {
199 {
200 name: "main partition",
201 size: CONFIG_MTD_CSTM_MIPS_IXX_LEN,
202 offset: 0,
203 },
204 },
205 };
206 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
207
208 struct map_info cstm_mips_ixx_map[PHYSMAP_NUMBER];
209
210 #if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
211 #define init_cstm_mips_ixx init_module
212 #define cleanup_cstm_mips_ixx cleanup_module
213 #endif
214
215 int __init init_cstm_mips_ixx(void)
216 {
217 int i;
218 int jedec;
219 struct mtd_info *mymtd;
220 struct mtd_partition *parts;
221
222 /* Initialize mapping */
223 for (i=0;i<PHYSMAP_NUMBER;i++) {
224 printk(KERN_NOTICE "cstm_mips_ixx flash device: %lx at %lx\n", cstm_mips_ixx_board_desc[i].window_size, cstm_mips_ixx_board_desc[i].window_addr);
225 memcpy((char *)&cstm_mips_ixx_map[i],(char *)&basic_cstm_mips_ixx_map,sizeof(struct map_info));
226 cstm_mips_ixx_map[i].map_priv_1 = (unsigned long)ioremap(cstm_mips_ixx_board_desc[i].window_addr, cstm_mips_ixx_board_desc[i].window_size);
227 if (!cstm_mips_ixx_map[i].map_priv_1) {
228 printk(KERN_WARNING "Failed to ioremap\n");
229 return -EIO;
230 }
231 cstm_mips_ixx_map[i].name = cstm_mips_ixx_board_desc[i].name;
232 cstm_mips_ixx_map[i].size = cstm_mips_ixx_board_desc[i].window_size;
233 cstm_mips_ixx_map[i].buswidth = cstm_mips_ixx_board_desc[i].buswidth;
234 //printk(KERN_NOTICE "cstm_mips_ixx: ioremap is %x\n",(unsigned int)(cstm_mips_ixx_map[i].map_priv_1));
235 }
236
237 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
238 setup_ITE_IVR_flash();
239 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
240
241 for (i=0;i<PHYSMAP_NUMBER;i++) {
242 parts = &cstm_mips_ixx_partitions[i][0];
243 jedec = 0;
244 mymtd = (struct mtd_info *)do_map_probe("cfi", &cstm_mips_ixx_map[i]);
245 //printk(KERN_NOTICE "phymap %d cfi_probe: mymtd is %x\n",i,(unsigned int)mymtd);
246 if (!mymtd) {
247 jedec = 1;
248 mymtd = (struct mtd_info *)do_map_probe("jedec", &cstm_mips_ixx_map[i]);
249 printk(KERN_NOTICE "cstm_mips_ixx %d jedec: mymtd is %x\n",i,(unsigned int)mymtd);
250 }
251 if (mymtd) {
252 mymtd->module = THIS_MODULE;
253
254 cstm_mips_ixx_map[i].map_priv_2 = (unsigned long)mymtd;
255 add_mtd_partitions(mymtd, parts, cstm_mips_ixx_board_desc[i].num_partitions);
256 }
257 else
258 return -ENXIO;
259 }
260 return 0;
261 }
262
263 static void __exit cleanup_cstm_mips_ixx(void)
264 {
265 int i;
266 struct mtd_info *mymtd;
267
268 for (i=0;i<PHYSMAP_NUMBER;i++) {
269 mymtd = (struct mtd_info *)cstm_mips_ixx_map[i].map_priv_2;
270 if (mymtd) {
271 del_mtd_partitions(mymtd);
272 map_destroy(mymtd);
273 }
274 if (cstm_mips_ixx_map[i].map_priv_1) {
275 iounmap((void *)cstm_mips_ixx_map[i].map_priv_1);
276 cstm_mips_ixx_map[i].map_priv_1 = 0;
277 }
278 }
279 }
280 #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
281 void PCISetULongByOffset(__u32 DevNumber, __u32 FuncNumber, __u32 Offset, __u32 data)
282 {
283 __u32 offset;
284
285 offset = ( unsigned long )( 0x80000000 | ( DevNumber << 11 ) + ( FuncNumber << 8 ) + Offset) ;
286
287 *(__u32 *)CC_CONFADDR = offset;
288 *(__u32 *)CC_CONFDATA = data;
289 }
290 void setup_ITE_IVR_flash()
291 {
292 __u32 size, base;
293
294 size = 0x0e000000; // 32MiB
295 base = (0x08000000) >> 8 >>1; // Bug: we must shift one more bit
296
297 /* need to set ITE flash to 32 bits instead of default 8 */
298 #ifdef CONFIG_MIPS_IVR
299 *(__u32 *)CC_FC_FCR = 0x55;
300 *(__u32 *)CC_GPACR = 0xfffc;
301 #else
302 *(__u32 *)CC_FC_FCR = 0x77;
303 #endif
304 /* turn bursting off */
305 *(__u32 *)CC_FC_DCR = 0x0;
306
307 /* setup for one chip 4 byte PCI access */
308 PCISetULongByOffset(CC_M68K_DEVICE, CC_M68K_FUNCTION, 0x60, size | base);
309 PCISetULongByOffset(CC_M68K_DEVICE, CC_M68K_FUNCTION, 0x64, 0x02);
310 }
311 #endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
312
313 module_init(init_cstm_mips_ixx);
314 module_exit(cleanup_cstm_mips_ixx);
315