File: /usr/src/linux/drivers/net/8139too.c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@mandrakesoft.com>
6 Copyright 2000,2001 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Submitting bug reports:
82
83 "rtl8139-diag -mmmaaavvveefN" output
84 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
85
86 See 8139too.txt for more details.
87
88 -----------------------------------------------------------------------------
89
90 Theory of Operation
91
92 I. Board Compatibility
93
94 This device driver is designed for the RealTek RTL8139 series, the RealTek
95 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
96 low-end boards, sometimes with its markings changed.
97
98
99 II. Board-specific settings
100
101 PCI bus devices are configured by the system at boot time, so no jumpers
102 need to be set on the board. The system BIOS will assign the
103 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
104
105 III. Driver operation
106
107 IIIa. Rx Ring buffers
108
109 The receive unit uses a single linear ring buffer rather than the more
110 common (and more efficient) descriptor-based architecture. Incoming frames
111 are sequentially stored into the Rx region, and the host copies them into
112 skbuffs.
113
114 Comment: While it is theoretically possible to process many frames in place,
115 any delay in Rx processing would cause us to drop frames. More importantly,
116 the Linux protocol stack is not designed to operate in this manner.
117
118 IIIb. Tx operation
119
120 The RTL8139 uses a fixed set of four Tx descriptors in register space.
121 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
122 aligns the IP header on word boundaries, and 14 byte ethernet header means
123 that almost all frames will need to be copied to an alignment buffer.
124
125 IVb. References
126
127 http://www.realtek.com.tw/cn/cn.html
128 http://www.scyld.com/expert/NWay.html
129
130 IVc. Errata
131
132 1) The RTL-8139 has a serious problem with motherboards which do
133 posted MMIO writes to PCI space. This driver works around the
134 problem by having an MMIO register write be immediately followed by
135 an MMIO register read.
136
137 */
138
139 #define DRV_NAME "8139too"
140 #define DRV_VERSION "0.9.18a"
141
142
143 #include <linux/config.h>
144 #include <linux/module.h>
145 #include <linux/kernel.h>
146 #include <linux/pci.h>
147 #include <linux/init.h>
148 #include <linux/ioport.h>
149 #include <linux/netdevice.h>
150 #include <linux/etherdevice.h>
151 #include <linux/rtnetlink.h>
152 #include <linux/delay.h>
153 #include <linux/ethtool.h>
154 #include <linux/mii.h>
155 #include <linux/completion.h>
156 #include <asm/io.h>
157 #include <asm/uaccess.h>
158
159 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
160 #define PFX DRV_NAME ": "
161
162
163 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
164 #ifdef CONFIG_8139TOO_PIO
165 #define USE_IO_OPS 1
166 #endif
167
168 /* define to 1 to enable copious debugging info */
169 #undef RTL8139_DEBUG
170
171 /* define to 1 to disable lightweight runtime debugging checks */
172 #undef RTL8139_NDEBUG
173
174
175 #ifdef RTL8139_DEBUG
176 /* note: prints function name for you */
177 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
178 #else
179 # define DPRINTK(fmt, args...)
180 #endif
181
182 #ifdef RTL8139_NDEBUG
183 # define assert(expr) do {} while (0)
184 #else
185 # define assert(expr) \
186 if(!(expr)) { \
187 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
188 #expr,__FILE__,__FUNCTION__,__LINE__); \
189 }
190 #endif
191
192
193 /* A few user-configurable values. */
194 /* media options */
195 #define MAX_UNITS 8
196 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
197 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
198
199 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
200 static int max_interrupt_work = 20;
201
202 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
203 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
204 static int multicast_filter_limit = 32;
205
206 /* Size of the in-memory receive ring. */
207 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
208 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
209 #define RX_BUF_PAD 16
210 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
211 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
212 #define RX_EARLY_THRESH 14
213
214 /* Number of Tx descriptor registers. */
215 #define NUM_TX_DESC 4
216
217 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
218 #define MAX_ETH_FRAME_SIZE 1536
219
220 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
221 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
222 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
223
224 /* PCI Tuning Parameters
225 Threshold is bytes transferred to chip before transmission starts. */
226 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
227
228 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
229 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
230 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
231 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
232
233
234 /* Operational parameters that usually are not changed. */
235 /* Time in jiffies before concluding the transmitter is hung. */
236 #define TX_TIMEOUT (6*HZ)
237
238
239 enum {
240 HAS_MII_XCVR = 0x010000,
241 HAS_CHIP_XCVR = 0x020000,
242 HAS_LNK_CHNG = 0x040000,
243 };
244
245 #define RTL_MIN_IO_SIZE 0x80
246 #define RTL8139B_IO_SIZE 256
247
248 #define RTL8129_CAPS HAS_MII_XCVR
249 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
250
251 typedef enum {
252 RTL8139 = 0,
253 RTL8139_CB,
254 SMC1211TX,
255 /*MPX5030,*/
256 DELTA8139,
257 ADDTRON8139,
258 DFE538TX,
259 RTL8129,
260 } board_t;
261
262
263 /* indexed by board_t, above */
264 static struct {
265 const char *name;
266 u32 hw_flags;
267 } board_info[] __devinitdata = {
268 { "RealTek RTL8139 Fast Ethernet", RTL8139_CAPS },
269 { "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },
270 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },
271 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/
272 { "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },
273 { "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },
274 { "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
275 { "RealTek RTL8129", RTL8129_CAPS },
276 };
277
278
279 static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {
280 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
281 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB },
282 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
283 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
284 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
285 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
286 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },
287
288 #ifdef CONFIG_8139TOO_8129
289 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
290 #endif
291
292 /* some crazy cards report invalid vendor ids like
293 * 0x0001 here. The other ids are valid and constant,
294 * so we simply don't match on the main vendor id.
295 */
296 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
297 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, DFE538TX },
298
299 {0,}
300 };
301 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
302
303
304 /* The rest of these values should never change. */
305
306 /* Symbolic offsets to registers. */
307 enum RTL8139_registers {
308 MAC0 = 0, /* Ethernet hardware address. */
309 MAR0 = 8, /* Multicast filter. */
310 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
311 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
312 RxBuf = 0x30,
313 RxEarlyCnt = 0x34,
314 RxEarlyStatus = 0x36,
315 ChipCmd = 0x37,
316 RxBufPtr = 0x38,
317 RxBufAddr = 0x3A,
318 IntrMask = 0x3C,
319 IntrStatus = 0x3E,
320 TxConfig = 0x40,
321 ChipVersion = 0x43,
322 RxConfig = 0x44,
323 Timer = 0x48, /* A general-purpose counter. */
324 RxMissed = 0x4C, /* 24 bits valid, write clears. */
325 Cfg9346 = 0x50,
326 Config0 = 0x51,
327 Config1 = 0x52,
328 FlashReg = 0x54,
329 MediaStatus = 0x58,
330 Config3 = 0x59,
331 Config4 = 0x5A, /* absent on RTL-8139A */
332 HltClk = 0x5B,
333 MultiIntr = 0x5C,
334 TxSummary = 0x60,
335 BasicModeCtrl = 0x62,
336 BasicModeStatus = 0x64,
337 NWayAdvert = 0x66,
338 NWayLPAR = 0x68,
339 NWayExpansion = 0x6A,
340 /* Undocumented registers, but required for proper operation. */
341 FIFOTMS = 0x70, /* FIFO Control and test. */
342 CSCR = 0x74, /* Chip Status and Configuration Register. */
343 PARA78 = 0x78,
344 PARA7c = 0x7c, /* Magic transceiver parameter register. */
345 Config5 = 0xD8, /* absent on RTL-8139A */
346 };
347
348 enum ClearBitMasks {
349 MultiIntrClear = 0xF000,
350 ChipCmdClear = 0xE2,
351 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
352 };
353
354 enum ChipCmdBits {
355 CmdReset = 0x10,
356 CmdRxEnb = 0x08,
357 CmdTxEnb = 0x04,
358 RxBufEmpty = 0x01,
359 };
360
361 /* Interrupt register bits, using my own meaningful names. */
362 enum IntrStatusBits {
363 PCIErr = 0x8000,
364 PCSTimeout = 0x4000,
365 RxFIFOOver = 0x40,
366 RxUnderrun = 0x20,
367 RxOverflow = 0x10,
368 TxErr = 0x08,
369 TxOK = 0x04,
370 RxErr = 0x02,
371 RxOK = 0x01,
372
373 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
374 };
375
376 enum TxStatusBits {
377 TxHostOwns = 0x2000,
378 TxUnderrun = 0x4000,
379 TxStatOK = 0x8000,
380 TxOutOfWindow = 0x20000000,
381 TxAborted = 0x40000000,
382 TxCarrierLost = 0x80000000,
383 };
384 enum RxStatusBits {
385 RxMulticast = 0x8000,
386 RxPhysical = 0x4000,
387 RxBroadcast = 0x2000,
388 RxBadSymbol = 0x0020,
389 RxRunt = 0x0010,
390 RxTooLong = 0x0008,
391 RxCRCErr = 0x0004,
392 RxBadAlign = 0x0002,
393 RxStatusOK = 0x0001,
394 };
395
396 /* Bits in RxConfig. */
397 enum rx_mode_bits {
398 AcceptErr = 0x20,
399 AcceptRunt = 0x10,
400 AcceptBroadcast = 0x08,
401 AcceptMulticast = 0x04,
402 AcceptMyPhys = 0x02,
403 AcceptAllPhys = 0x01,
404 };
405
406 /* Bits in TxConfig. */
407 enum tx_config_bits {
408 TxIFG1 = (1 << 25), /* Interframe Gap Time */
409 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
410 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
411 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
412 TxClearAbt = (1 << 0), /* Clear abort (WO) */
413 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
414
415 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
416 };
417
418 /* Bits in Config1 */
419 enum Config1Bits {
420 Cfg1_PM_Enable = 0x01,
421 Cfg1_VPD_Enable = 0x02,
422 Cfg1_PIO = 0x04,
423 Cfg1_MMIO = 0x08,
424 LWAKE = 0x10, /* not on 8139, 8139A */
425 Cfg1_Driver_Load = 0x20,
426 Cfg1_LED0 = 0x40,
427 Cfg1_LED1 = 0x80,
428 SLEEP = (1 << 1), /* only on 8139, 8139A */
429 PWRDN = (1 << 0), /* only on 8139, 8139A */
430 };
431
432 /* Bits in Config4 */
433 enum Config4Bits {
434 LWPTN = (1 << 2), /* not on 8139, 8139A */
435 };
436
437 enum RxConfigBits {
438 /* Early Rx threshold, none or X/16 */
439 RxCfgEarlyRxNone = 0,
440 RxCfgEarlyRxShift = 24,
441
442 /* rx fifo threshold */
443 RxCfgFIFOShift = 13,
444 RxCfgFIFONone = (7 << RxCfgFIFOShift),
445
446 /* Max DMA burst */
447 RxCfgDMAShift = 8,
448 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
449
450 /* rx ring buffer length */
451 RxCfgRcv8K = 0,
452 RxCfgRcv16K = (1 << 11),
453 RxCfgRcv32K = (1 << 12),
454 RxCfgRcv64K = (1 << 11) | (1 << 12),
455
456 /* Disable packet wrap at end of Rx buffer */
457 RxNoWrap = (1 << 7),
458 };
459
460
461 /* Twister tuning parameters from RealTek.
462 Completely undocumented, but required to tune bad links. */
463 enum CSCRBits {
464 CSCR_LinkOKBit = 0x0400,
465 CSCR_LinkChangeBit = 0x0800,
466 CSCR_LinkStatusBits = 0x0f000,
467 CSCR_LinkDownOffCmd = 0x003c0,
468 CSCR_LinkDownCmd = 0x0f3c0,
469 };
470
471
472 enum Cfg9346Bits {
473 Cfg9346_Lock = 0x00,
474 Cfg9346_Unlock = 0xC0,
475 };
476
477
478 #define PARA78_default 0x78fa8388
479 #define PARA7c_default 0xcb38de43 /* param[0][3] */
480 #define PARA7c_xxx 0xcb38de43
481 static const unsigned long param[4][4] = {
482 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
483 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
484 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
485 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
486 };
487
488 struct ring_info {
489 struct sk_buff *skb;
490 dma_addr_t mapping;
491 };
492
493
494 typedef enum {
495 CH_8139 = 0,
496 CH_8139_K,
497 CH_8139A,
498 CH_8139B,
499 CH_8130,
500 CH_8139C,
501 } chip_t;
502
503 enum chip_flags {
504 HasHltClk = (1 << 0),
505 HasLWake = (1 << 1),
506 };
507
508
509 /* directly indexed by chip_t, above */
510 const static struct {
511 const char *name;
512 u8 version; /* from RTL8139C docs */
513 u32 RxConfigMask; /* should clear the bits supported by this chip */
514 u32 flags;
515 } rtl_chip_info[] = {
516 { "RTL-8139",
517 0x40,
518 0xf0fe0040, /* XXX copied from RTL8139A, verify */
519 HasHltClk,
520 },
521
522 { "RTL-8139 rev K",
523 0x60,
524 0xf0fe0040,
525 HasHltClk,
526 },
527
528 { "RTL-8139A",
529 0x70,
530 0xf0fe0040,
531 HasHltClk, /* XXX undocumented? */
532 },
533
534 { "RTL-8139B",
535 0x78,
536 0xf0fc0040,
537 HasLWake,
538 },
539
540 { "RTL-8130",
541 0x7C,
542 0xf0fe0040, /* XXX copied from RTL8139A, verify */
543 HasLWake,
544 },
545
546 { "RTL-8139C",
547 0x74,
548 0xf0fc0040, /* XXX copied from RTL8139B, verify */
549 HasLWake,
550 },
551
552 };
553
554 struct rtl_extra_stats {
555 unsigned long early_rx;
556 unsigned long tx_buf_mapped;
557 unsigned long tx_timeouts;
558 };
559
560 struct rtl8139_private {
561 void *mmio_addr;
562 int drv_flags;
563 struct pci_dev *pci_dev;
564 struct net_device_stats stats;
565 unsigned char *rx_ring;
566 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
567 unsigned int tx_flag;
568 unsigned long cur_tx;
569 unsigned long dirty_tx;
570 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
571 struct ring_info tx_info[NUM_TX_DESC];
572 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
573 unsigned char *tx_bufs; /* Tx bounce buffer region. */
574 dma_addr_t rx_ring_dma;
575 dma_addr_t tx_bufs_dma;
576 signed char phys[4]; /* MII device addresses. */
577 char twistie, twist_row, twist_col; /* Twister tune state. */
578 unsigned int full_duplex:1; /* Full-duplex operation requested. */
579 unsigned int duplex_lock:1;
580 unsigned int default_port:4; /* Last dev->if_port value. */
581 unsigned int media2:4; /* Secondary monitored media port. */
582 unsigned int medialock:1; /* Don't sense media type. */
583 unsigned int mediasense:1; /* Media sensing in progress. */
584 spinlock_t lock;
585 chip_t chipset;
586 pid_t thr_pid;
587 wait_queue_head_t thr_wait;
588 struct completion thr_exited;
589 u32 rx_config;
590 struct rtl_extra_stats xstats;
591 };
592
593 MODULE_AUTHOR ("Jeff Garzik <jgarzik@mandrakesoft.com>");
594 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
595 MODULE_PARM (multicast_filter_limit, "i");
596 MODULE_PARM (max_interrupt_work, "i");
597 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
598 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
599 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
600 MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");
601 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
602 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
603
604 static int read_eeprom (void *ioaddr, int location, int addr_len);
605 static int rtl8139_open (struct net_device *dev);
606 static int mdio_read (struct net_device *dev, int phy_id, int location);
607 static void mdio_write (struct net_device *dev, int phy_id, int location,
608 int val);
609 static int rtl8139_thread (void *data);
610 static void rtl8139_tx_timeout (struct net_device *dev);
611 static void rtl8139_init_ring (struct net_device *dev);
612 static int rtl8139_start_xmit (struct sk_buff *skb,
613 struct net_device *dev);
614 static void rtl8139_interrupt (int irq, void *dev_instance,
615 struct pt_regs *regs);
616 static int rtl8139_close (struct net_device *dev);
617 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
618 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
619 static inline u32 ether_crc (int length, unsigned char *data);
620 static void rtl8139_set_rx_mode (struct net_device *dev);
621 static void rtl8139_hw_start (struct net_device *dev);
622
623 #ifdef USE_IO_OPS
624
625 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
626 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
627 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
628 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
629 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
630 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
631 #define RTL_W8_F RTL_W8
632 #define RTL_W16_F RTL_W16
633 #define RTL_W32_F RTL_W32
634 #undef readb
635 #undef readw
636 #undef readl
637 #undef writeb
638 #undef writew
639 #undef writel
640 #define readb(addr) inb((unsigned long)(addr))
641 #define readw(addr) inw((unsigned long)(addr))
642 #define readl(addr) inl((unsigned long)(addr))
643 #define writeb(val,addr) outb((val),(unsigned long)(addr))
644 #define writew(val,addr) outw((val),(unsigned long)(addr))
645 #define writel(val,addr) outl((val),(unsigned long)(addr))
646
647 #else
648
649 /* write MMIO register, with flush */
650 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
651 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
652 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
653 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
654
655
656 #define MMIO_FLUSH_AUDIT_COMPLETE 1
657 #if MMIO_FLUSH_AUDIT_COMPLETE
658
659 /* write MMIO register */
660 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
661 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
662 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
663
664 #else
665
666 /* write MMIO register, then flush */
667 #define RTL_W8 RTL_W8_F
668 #define RTL_W16 RTL_W16_F
669 #define RTL_W32 RTL_W32_F
670
671 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
672
673 /* read MMIO register */
674 #define RTL_R8(reg) readb (ioaddr + (reg))
675 #define RTL_R16(reg) readw (ioaddr + (reg))
676 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
677
678 #endif /* USE_IO_OPS */
679
680
681 static const u16 rtl8139_intr_mask =
682 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
683 TxErr | TxOK | RxErr | RxOK;
684
685 static const unsigned int rtl8139_rx_config =
686 (RX_EARLY_THRESH << RxCfgEarlyRxShift) | RxCfgRcv32K | RxNoWrap |
687 (RX_FIFO_THRESH << RxCfgFIFOShift) |
688 (RX_DMA_BURST << RxCfgDMAShift);
689
690
691 static void __rtl8139_cleanup_dev (struct net_device *dev)
692 {
693 struct rtl8139_private *tp;
694 struct pci_dev *pdev;
695
696 assert (dev != NULL);
697 assert (dev->priv != NULL);
698
699 tp = dev->priv;
700 assert (tp->pci_dev != NULL);
701 pdev = tp->pci_dev;
702
703 #ifndef USE_IO_OPS
704 if (tp->mmio_addr)
705 iounmap (tp->mmio_addr);
706 #endif /* !USE_IO_OPS */
707
708 /* it's ok to call this even if we have no regions to free */
709 pci_release_regions (pdev);
710
711 #ifndef RTL8139_NDEBUG
712 /* poison memory before freeing */
713 memset (dev, 0xBC,
714 sizeof (struct net_device) +
715 sizeof (struct rtl8139_private));
716 #endif /* RTL8139_NDEBUG */
717
718 kfree (dev);
719
720 pci_set_drvdata (pdev, NULL);
721 }
722
723
724 static void rtl8139_chip_reset (void *ioaddr)
725 {
726 int i;
727
728 /* Soft reset the chip. */
729 RTL_W8 (ChipCmd, CmdReset);
730
731 /* Check that the chip has finished the reset. */
732 for (i = 1000; i > 0; i--) {
733 barrier();
734 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
735 break;
736 udelay (10);
737 }
738 }
739
740
741 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
742 struct net_device **dev_out)
743 {
744 void *ioaddr;
745 struct net_device *dev;
746 struct rtl8139_private *tp;
747 u8 tmp8;
748 int rc;
749 unsigned int i;
750 u32 pio_start, pio_end, pio_flags, pio_len;
751 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
752 u32 tmp;
753
754 DPRINTK ("ENTER\n");
755
756 assert (pdev != NULL);
757
758 *dev_out = NULL;
759
760 /* dev and dev->priv zeroed in alloc_etherdev */
761 dev = alloc_etherdev (sizeof (*tp));
762 if (dev == NULL) {
763 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pdev->slot_name);
764 DPRINTK ("EXIT, returning -ENOMEM\n");
765 return -ENOMEM;
766 }
767 SET_MODULE_OWNER(dev);
768 tp = dev->priv;
769 tp->pci_dev = pdev;
770
771 /* enable device (incl. PCI PM wakeup and hotplug setup) */
772 rc = pci_enable_device (pdev);
773 if (rc)
774 goto err_out;
775
776 pio_start = pci_resource_start (pdev, 0);
777 pio_end = pci_resource_end (pdev, 0);
778 pio_flags = pci_resource_flags (pdev, 0);
779 pio_len = pci_resource_len (pdev, 0);
780
781 mmio_start = pci_resource_start (pdev, 1);
782 mmio_end = pci_resource_end (pdev, 1);
783 mmio_flags = pci_resource_flags (pdev, 1);
784 mmio_len = pci_resource_len (pdev, 1);
785
786 /* set this immediately, we need to know before
787 * we talk to the chip directly */
788 DPRINTK("PIO region size == 0x%02X\n", pio_len);
789 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
790
791 #ifdef USE_IO_OPS
792 /* make sure PCI base addr 0 is PIO */
793 if (!(pio_flags & IORESOURCE_IO)) {
794 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pdev->slot_name);
795 rc = -ENODEV;
796 goto err_out;
797 }
798 /* check for weird/broken PCI region reporting */
799 if (pio_len < RTL_MIN_IO_SIZE) {
800 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pdev->slot_name);
801 rc = -ENODEV;
802 goto err_out;
803 }
804 #else
805 /* make sure PCI base addr 1 is MMIO */
806 if (!(mmio_flags & IORESOURCE_MEM)) {
807 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pdev->slot_name);
808 rc = -ENODEV;
809 goto err_out;
810 }
811 if (mmio_len < RTL_MIN_IO_SIZE) {
812 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pdev->slot_name);
813 rc = -ENODEV;
814 goto err_out;
815 }
816 #endif
817
818 rc = pci_request_regions (pdev, "8139too");
819 if (rc)
820 goto err_out;
821
822 /* enable PCI bus-mastering */
823 pci_set_master (pdev);
824
825 #ifdef USE_IO_OPS
826 ioaddr = (void *) pio_start;
827 dev->base_addr = pio_start;
828 #else
829 /* ioremap MMIO region */
830 ioaddr = ioremap (mmio_start, mmio_len);
831 if (ioaddr == NULL) {
832 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pdev->slot_name);
833 rc = -EIO;
834 goto err_out;
835 }
836 dev->base_addr = (long) ioaddr;
837 tp->mmio_addr = ioaddr;
838 #endif /* USE_IO_OPS */
839
840 /* Bring old chips out of low-power mode. */
841 RTL_W8 (HltClk, 'R');
842
843 /* check for missing/broken hardware */
844 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
845 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
846 pdev->slot_name);
847 rc = -EIO;
848 goto err_out;
849 }
850
851 /* identify chip attached to board */
852 tmp = RTL_R8 (ChipVersion);
853 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
854 if (tmp == rtl_chip_info[i].version) {
855 tp->chipset = i;
856 goto match;
857 }
858
859 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
860 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
861 pdev->slot_name);
862 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pdev->slot_name, RTL_R32 (TxConfig));
863 tp->chipset = 0;
864
865 match:
866 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
867 tmp,
868 tp->chipset,
869 rtl_chip_info[tp->chipset].name);
870
871 if (tp->chipset >= CH_8139B) {
872 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
873 DPRINTK("PCI PM wakeup\n");
874 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
875 (tmp8 & LWAKE))
876 new_tmp8 &= ~LWAKE;
877 new_tmp8 |= Cfg1_PM_Enable;
878 if (new_tmp8 != tmp8) {
879 RTL_W8 (Cfg9346, Cfg9346_Unlock);
880 RTL_W8 (Config1, tmp8);
881 RTL_W8 (Cfg9346, Cfg9346_Lock);
882 }
883 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
884 tmp8 = RTL_R8 (Config4);
885 if (tmp8 & LWPTN)
886 RTL_W8 (Config4, tmp8 & ~LWPTN);
887 }
888 } else {
889 DPRINTK("Old chip wakeup\n");
890 tmp8 = RTL_R8 (Config1);
891 tmp8 &= ~(SLEEP | PWRDN);
892 RTL_W8 (Config1, tmp8);
893 }
894
895 rtl8139_chip_reset (ioaddr);
896
897 DPRINTK ("EXIT, returning 0\n");
898 *dev_out = dev;
899 return 0;
900
901 err_out:
902 __rtl8139_cleanup_dev (dev);
903 DPRINTK ("EXIT, returning %d\n", rc);
904 return rc;
905 }
906
907
908 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
909 const struct pci_device_id *ent)
910 {
911 struct net_device *dev = NULL;
912 struct rtl8139_private *tp;
913 int i, addr_len, option;
914 void *ioaddr;
915 static int board_idx = -1;
916
917 DPRINTK ("ENTER\n");
918
919 assert (pdev != NULL);
920 assert (ent != NULL);
921
922 board_idx++;
923
924 /* when we're built into the kernel, the driver version message
925 * is only printed if at least one 8139 board has been found
926 */
927 #ifndef MODULE
928 {
929 static int printed_version;
930 if (!printed_version++)
931 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
932 }
933 #endif
934
935 i = rtl8139_init_board (pdev, &dev);
936 if (i < 0) {
937 DPRINTK ("EXIT, returning %d\n", i);
938 return i;
939 }
940
941 tp = dev->priv;
942 ioaddr = tp->mmio_addr;
943
944 assert (ioaddr != NULL);
945 assert (dev != NULL);
946 assert (tp != NULL);
947
948 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
949 for (i = 0; i < 3; i++)
950 ((u16 *) (dev->dev_addr))[i] =
951 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
952
953 /* The Rtl8139-specific entries in the device structure. */
954 dev->open = rtl8139_open;
955 dev->hard_start_xmit = rtl8139_start_xmit;
956 dev->stop = rtl8139_close;
957 dev->get_stats = rtl8139_get_stats;
958 dev->set_multicast_list = rtl8139_set_rx_mode;
959 dev->do_ioctl = netdev_ioctl;
960 dev->tx_timeout = rtl8139_tx_timeout;
961 dev->watchdog_timeo = TX_TIMEOUT;
962
963 dev->irq = pdev->irq;
964
965 /* dev->priv/tp zeroed and aligned in init_etherdev */
966 tp = dev->priv;
967
968 /* note: tp->chipset set in rtl8139_init_board */
969 tp->drv_flags = board_info[ent->driver_data].hw_flags;
970 tp->mmio_addr = ioaddr;
971 spin_lock_init (&tp->lock);
972 init_waitqueue_head (&tp->thr_wait);
973 init_completion (&tp->thr_exited);
974
975 /* dev is fully set up and ready to use now */
976 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
977 i = register_netdev (dev);
978 if (i) goto err_out;
979
980 pci_set_drvdata (pdev, dev);
981
982 printk (KERN_INFO "%s: %s at 0x%lx, "
983 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
984 "IRQ %d\n",
985 dev->name,
986 board_info[ent->driver_data].name,
987 dev->base_addr,
988 dev->dev_addr[0], dev->dev_addr[1],
989 dev->dev_addr[2], dev->dev_addr[3],
990 dev->dev_addr[4], dev->dev_addr[5],
991 dev->irq);
992
993 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
994 dev->name, rtl_chip_info[tp->chipset].name);
995
996 /* Find the connected MII xcvrs.
997 Doing this in open() would allow detecting external xcvrs later, but
998 takes too much time. */
999 #ifdef CONFIG_8139TOO_8129
1000 if (tp->drv_flags & HAS_MII_XCVR) {
1001 int phy, phy_idx = 0;
1002 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1003 int mii_status = mdio_read(dev, phy, 1);
1004 if (mii_status != 0xffff && mii_status != 0x0000) {
1005 u16 advertising = mdio_read(dev, phy, 4);
1006 tp->phys[phy_idx++] = phy;
1007 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1008 "advertising %4.4x.\n",
1009 dev->name, phy, mii_status, advertising);
1010 }
1011 }
1012 if (phy_idx == 0) {
1013 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1014 "transceiver.\n",
1015 dev->name);
1016 tp->phys[0] = 32;
1017 }
1018 } else
1019 #endif
1020 tp->phys[0] = 32;
1021
1022 /* The lower four bits are the media type. */
1023 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1024 if (option > 0) {
1025 tp->full_duplex = (option & 0x210) ? 1 : 0;
1026 tp->default_port = option & 0xFF;
1027 if (tp->default_port)
1028 tp->medialock = 1;
1029 }
1030 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1031 tp->full_duplex = full_duplex[board_idx];
1032 if (tp->full_duplex) {
1033 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1034 /* Changing the MII-advertised media because might prevent
1035 re-connection. */
1036 tp->duplex_lock = 1;
1037 }
1038 if (tp->default_port) {
1039 printk(KERN_INFO " Forcing %dMbs %s-duplex operation.\n",
1040 (option & 0x20 ? 100 : 10),
1041 (option & 0x10 ? "full" : "half"));
1042 mdio_write(dev, tp->phys[0], 0,
1043 ((option & 0x20) ? 0x2000 : 0) | /* 100mbps? */
1044 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1045 }
1046
1047 /* Put the chip into low-power mode. */
1048 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1049 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1050
1051 DPRINTK ("EXIT - returning 0\n");
1052 return 0;
1053
1054 err_out:
1055 __rtl8139_cleanup_dev (dev);
1056 DPRINTK ("EXIT - returning %d\n", i);
1057 return i;
1058 }
1059
1060
1061 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1062 {
1063 struct net_device *dev = pci_get_drvdata (pdev);
1064 struct rtl8139_private *np;
1065
1066 DPRINTK ("ENTER\n");
1067
1068 assert (dev != NULL);
1069 np = dev->priv;
1070 assert (np != NULL);
1071
1072 unregister_netdev (dev);
1073
1074 __rtl8139_cleanup_dev (dev);
1075
1076 DPRINTK ("EXIT\n");
1077 }
1078
1079
1080 /* Serial EEPROM section. */
1081
1082 /* EEPROM_Ctrl bits. */
1083 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1084 #define EE_CS 0x08 /* EEPROM chip select. */
1085 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1086 #define EE_WRITE_0 0x00
1087 #define EE_WRITE_1 0x02
1088 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1089 #define EE_ENB (0x80 | EE_CS)
1090
1091 /* Delay between EEPROM clock transitions.
1092 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1093 */
1094
1095 #define eeprom_delay() readl(ee_addr)
1096
1097 /* The EEPROM commands include the alway-set leading bit. */
1098 #define EE_WRITE_CMD (5)
1099 #define EE_READ_CMD (6)
1100 #define EE_ERASE_CMD (7)
1101
1102 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1103 {
1104 int i;
1105 unsigned retval = 0;
1106 void *ee_addr = ioaddr + Cfg9346;
1107 int read_cmd = location | (EE_READ_CMD << addr_len);
1108
1109 DPRINTK ("ENTER\n");
1110
1111 writeb (EE_ENB & ~EE_CS, ee_addr);
1112 writeb (EE_ENB, ee_addr);
1113 eeprom_delay ();
1114
1115 /* Shift the read command bits out. */
1116 for (i = 4 + addr_len; i >= 0; i--) {
1117 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1118 writeb (EE_ENB | dataval, ee_addr);
1119 eeprom_delay ();
1120 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1121 eeprom_delay ();
1122 }
1123 writeb (EE_ENB, ee_addr);
1124 eeprom_delay ();
1125
1126 for (i = 16; i > 0; i--) {
1127 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1128 eeprom_delay ();
1129 retval =
1130 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1131 0);
1132 writeb (EE_ENB, ee_addr);
1133 eeprom_delay ();
1134 }
1135
1136 /* Terminate the EEPROM access. */
1137 writeb (~EE_CS, ee_addr);
1138 eeprom_delay ();
1139
1140 DPRINTK ("EXIT - returning %d\n", retval);
1141 return retval;
1142 }
1143
1144 /* MII serial management: mostly bogus for now. */
1145 /* Read and write the MII management registers using software-generated
1146 serial MDIO protocol.
1147 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1148 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1149 "overclocking" issues. */
1150 #define MDIO_DIR 0x80
1151 #define MDIO_DATA_OUT 0x04
1152 #define MDIO_DATA_IN 0x02
1153 #define MDIO_CLK 0x01
1154 #define MDIO_WRITE0 (MDIO_DIR)
1155 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1156
1157 #define mdio_delay(mdio_addr) readb(mdio_addr)
1158
1159
1160 static char mii_2_8139_map[8] = {
1161 BasicModeCtrl,
1162 BasicModeStatus,
1163 0,
1164 0,
1165 NWayAdvert,
1166 NWayLPAR,
1167 NWayExpansion,
1168 0
1169 };
1170
1171
1172 #ifdef CONFIG_8139TOO_8129
1173 /* Syncronize the MII management interface by shifting 32 one bits out. */
1174 static void mdio_sync (void *mdio_addr)
1175 {
1176 int i;
1177
1178 DPRINTK ("ENTER\n");
1179
1180 for (i = 32; i >= 0; i--) {
1181 writeb (MDIO_WRITE1, mdio_addr);
1182 mdio_delay (mdio_addr);
1183 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1184 mdio_delay (mdio_addr);
1185 }
1186
1187 DPRINTK ("EXIT\n");
1188 }
1189 #endif
1190
1191 static int mdio_read (struct net_device *dev, int phy_id, int location)
1192 {
1193 struct rtl8139_private *tp = dev->priv;
1194 int retval = 0;
1195 #ifdef CONFIG_8139TOO_8129
1196 void *mdio_addr = tp->mmio_addr + Config4;
1197 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1198 int i;
1199 #endif
1200
1201 DPRINTK ("ENTER\n");
1202
1203 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1204 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1205 return location < 8 && mii_2_8139_map[location] ?
1206 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1207 }
1208
1209 #ifdef CONFIG_8139TOO_8129
1210 mdio_sync (mdio_addr);
1211 /* Shift the read command bits out. */
1212 for (i = 15; i >= 0; i--) {
1213 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1214
1215 writeb (MDIO_DIR | dataval, mdio_addr);
1216 mdio_delay (mdio_addr);
1217 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1218 mdio_delay (mdio_addr);
1219 }
1220
1221 /* Read the two transition, 16 data, and wire-idle bits. */
1222 for (i = 19; i > 0; i--) {
1223 writeb (0, mdio_addr);
1224 mdio_delay (mdio_addr);
1225 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1226 writeb (MDIO_CLK, mdio_addr);
1227 mdio_delay (mdio_addr);
1228 }
1229 #endif
1230
1231 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1232 return (retval >> 1) & 0xffff;
1233 }
1234
1235
1236 static void mdio_write (struct net_device *dev, int phy_id, int location,
1237 int value)
1238 {
1239 struct rtl8139_private *tp = dev->priv;
1240 #ifdef CONFIG_8139TOO_8129
1241 void *mdio_addr = tp->mmio_addr + Config4;
1242 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1243 int i;
1244 #endif
1245
1246 DPRINTK ("ENTER\n");
1247
1248 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1249 void *ioaddr = tp->mmio_addr;
1250 if (location == 0) {
1251 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1252 RTL_W16 (BasicModeCtrl, value);
1253 RTL_W8 (Cfg9346, Cfg9346_Lock);
1254 } else if (location < 8 && mii_2_8139_map[location])
1255 RTL_W16 (mii_2_8139_map[location], value);
1256 return;
1257 }
1258
1259 #ifdef CONFIG_8139TOO_8129
1260 mdio_sync (mdio_addr);
1261
1262 /* Shift the command bits out. */
1263 for (i = 31; i >= 0; i--) {
1264 int dataval =
1265 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1266 writeb (dataval, mdio_addr);
1267 mdio_delay (mdio_addr);
1268 writeb (dataval | MDIO_CLK, mdio_addr);
1269 mdio_delay (mdio_addr);
1270 }
1271 /* Clear out extra bits. */
1272 for (i = 2; i > 0; i--) {
1273 writeb (0, mdio_addr);
1274 mdio_delay (mdio_addr);
1275 writeb (MDIO_CLK, mdio_addr);
1276 mdio_delay (mdio_addr);
1277 }
1278 #endif
1279 }
1280
1281
1282 static int rtl8139_open (struct net_device *dev)
1283 {
1284 struct rtl8139_private *tp = dev->priv;
1285 int retval;
1286 #ifdef RTL8139_DEBUG
1287 void *ioaddr = tp->mmio_addr;
1288 #endif
1289
1290 DPRINTK ("ENTER\n");
1291
1292 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1293 if (retval) {
1294 DPRINTK ("EXIT, returning %d\n", retval);
1295 return retval;
1296 }
1297
1298 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1299 &tp->tx_bufs_dma);
1300 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1301 &tp->rx_ring_dma);
1302 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1303 free_irq(dev->irq, dev);
1304
1305 if (tp->tx_bufs)
1306 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1307 tp->tx_bufs, tp->tx_bufs_dma);
1308 if (tp->rx_ring)
1309 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1310 tp->rx_ring, tp->rx_ring_dma);
1311
1312 DPRINTK ("EXIT, returning -ENOMEM\n");
1313 return -ENOMEM;
1314
1315 }
1316
1317 tp->full_duplex = tp->duplex_lock;
1318 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1319 tp->twistie = 1;
1320
1321 rtl8139_init_ring (dev);
1322 rtl8139_hw_start (dev);
1323
1324 DPRINTK ("%s: rtl8139_open() ioaddr %#lx IRQ %d"
1325 " GP Pins %2.2x %s-duplex.\n",
1326 dev->name, pci_resource_start (tp->pci_dev, 1),
1327 dev->irq, RTL_R8 (MediaStatus),
1328 tp->full_duplex ? "full" : "half");
1329
1330 tp->thr_pid = kernel_thread (rtl8139_thread, dev, CLONE_FS | CLONE_FILES);
1331 if (tp->thr_pid < 0)
1332 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1333 dev->name);
1334
1335 DPRINTK ("EXIT, returning 0\n");
1336 return 0;
1337 }
1338
1339
1340 static void rtl_check_media (struct net_device *dev)
1341 {
1342 struct rtl8139_private *tp = dev->priv;
1343
1344 DPRINTK("ENTER\n");
1345
1346 if (tp->phys[0] >= 0) {
1347 u16 mii_reg5 = mdio_read(dev, tp->phys[0], 5);
1348 if (mii_reg5 == 0xffff)
1349 ; /* Not there */
1350 else if ((mii_reg5 & 0x0100) == 0x0100
1351 || (mii_reg5 & 0x00C0) == 0x0040)
1352 tp->full_duplex = 1;
1353
1354 printk (KERN_INFO"%s: Setting %s%s-duplex based on"
1355 " auto-negotiated partner ability %4.4x.\n",
1356 dev->name, mii_reg5 == 0 ? "" :
1357 (mii_reg5 & 0x0180) ? "100mbps " : "10mbps ",
1358 tp->full_duplex ? "full" : "half", mii_reg5);
1359 }
1360 }
1361
1362 /* Start the hardware at open or resume. */
1363 static void rtl8139_hw_start (struct net_device *dev)
1364 {
1365 struct rtl8139_private *tp = dev->priv;
1366 void *ioaddr = tp->mmio_addr;
1367 u32 i;
1368 u8 tmp;
1369
1370 DPRINTK ("ENTER\n");
1371
1372 /* Bring old chips out of low-power mode. */
1373 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1374 RTL_W8 (HltClk, 'R');
1375
1376 rtl8139_chip_reset (ioaddr);
1377
1378 /* unlock Config[01234] and BMCR register writes */
1379 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1380 /* Restore our idea of the MAC address. */
1381 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1382 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1383
1384 /* Must enable Tx/Rx before setting transfer thresholds! */
1385 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1386
1387 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1388 RTL_W32 (RxConfig, tp->rx_config);
1389
1390 /* Check this value: the documentation for IFG contradicts ifself. */
1391 RTL_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1392
1393 tp->cur_rx = 0;
1394
1395 rtl_check_media (dev);
1396
1397 if (tp->chipset >= CH_8139B) {
1398 /* disable magic packet scanning, which is enabled
1399 * when PM is enabled in Config1 */
1400 RTL_W8 (Config3, RTL_R8 (Config3) & ~(1<<5));
1401 }
1402
1403 DPRINTK("init buffer addresses\n");
1404
1405 /* Lock Config[01234] and BMCR register writes */
1406 RTL_W8 (Cfg9346, Cfg9346_Lock);
1407
1408 /* init Rx ring buffer DMA address */
1409 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1410
1411 /* init Tx buffer DMA addresses */
1412 for (i = 0; i < NUM_TX_DESC; i++)
1413 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1414
1415 RTL_W32 (RxMissed, 0);
1416
1417 rtl8139_set_rx_mode (dev);
1418
1419 /* no early-rx interrupts */
1420 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1421
1422 /* make sure RxTx has started */
1423 tmp = RTL_R8 (ChipCmd);
1424 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1425 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1426
1427 /* Enable all known interrupts by setting the interrupt mask. */
1428 RTL_W16 (IntrMask, rtl8139_intr_mask);
1429
1430 netif_start_queue (dev);
1431
1432 DPRINTK ("EXIT\n");
1433 }
1434
1435
1436 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1437 static void rtl8139_init_ring (struct net_device *dev)
1438 {
1439 struct rtl8139_private *tp = dev->priv;
1440 int i;
1441
1442 DPRINTK ("ENTER\n");
1443
1444 tp->cur_rx = 0;
1445 tp->cur_tx = 0;
1446 tp->dirty_tx = 0;
1447
1448 for (i = 0; i < NUM_TX_DESC; i++) {
1449 tp->tx_info[i].skb = NULL;
1450 tp->tx_info[i].mapping = 0;
1451 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1452 }
1453
1454 DPRINTK ("EXIT\n");
1455 }
1456
1457
1458 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1459 static int next_tick = 3 * HZ;
1460
1461 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1462 static inline void rtl8139_tune_twister (struct net_device *dev,
1463 struct rtl8139_private *tp) {}
1464 #else
1465 static void rtl8139_tune_twister (struct net_device *dev,
1466 struct rtl8139_private *tp)
1467 {
1468 int linkcase;
1469 void *ioaddr = tp->mmio_addr;
1470
1471 DPRINTK ("ENTER\n");
1472
1473 /* This is a complicated state machine to configure the "twister" for
1474 impedance/echos based on the cable length.
1475 All of this is magic and undocumented.
1476 */
1477 switch (tp->twistie) {
1478 case 1:
1479 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1480 /* We have link beat, let us tune the twister. */
1481 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1482 tp->twistie = 2; /* Change to state 2. */
1483 next_tick = HZ / 10;
1484 } else {
1485 /* Just put in some reasonable defaults for when beat returns. */
1486 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1487 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1488 RTL_W32 (PARA78, PARA78_default);
1489 RTL_W32 (PARA7c, PARA7c_default);
1490 tp->twistie = 0; /* Bail from future actions. */
1491 }
1492 break;
1493 case 2:
1494 /* Read how long it took to hear the echo. */
1495 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1496 if (linkcase == 0x7000)
1497 tp->twist_row = 3;
1498 else if (linkcase == 0x3000)
1499 tp->twist_row = 2;
1500 else if (linkcase == 0x1000)
1501 tp->twist_row = 1;
1502 else
1503 tp->twist_row = 0;
1504 tp->twist_col = 0;
1505 tp->twistie = 3; /* Change to state 2. */
1506 next_tick = HZ / 10;
1507 break;
1508 case 3:
1509 /* Put out four tuning parameters, one per 100msec. */
1510 if (tp->twist_col == 0)
1511 RTL_W16 (FIFOTMS, 0);
1512 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1513 [(int) tp->twist_col]);
1514 next_tick = HZ / 10;
1515 if (++tp->twist_col >= 4) {
1516 /* For short cables we are done.
1517 For long cables (row == 3) check for mistune. */
1518 tp->twistie =
1519 (tp->twist_row == 3) ? 4 : 0;
1520 }
1521 break;
1522 case 4:
1523 /* Special case for long cables: check for mistune. */
1524 if ((RTL_R16 (CSCR) &
1525 CSCR_LinkStatusBits) == 0x7000) {
1526 tp->twistie = 0;
1527 break;
1528 } else {
1529 RTL_W32 (PARA7c, 0xfb38de03);
1530 tp->twistie = 5;
1531 next_tick = HZ / 10;
1532 }
1533 break;
1534 case 5:
1535 /* Retune for shorter cable (column 2). */
1536 RTL_W32 (FIFOTMS, 0x20);
1537 RTL_W32 (PARA78, PARA78_default);
1538 RTL_W32 (PARA7c, PARA7c_default);
1539 RTL_W32 (FIFOTMS, 0x00);
1540 tp->twist_row = 2;
1541 tp->twist_col = 0;
1542 tp->twistie = 3;
1543 next_tick = HZ / 10;
1544 break;
1545
1546 default:
1547 /* do nothing */
1548 break;
1549 }
1550
1551 DPRINTK ("EXIT\n");
1552 }
1553 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1554
1555
1556 static inline void rtl8139_thread_iter (struct net_device *dev,
1557 struct rtl8139_private *tp,
1558 void *ioaddr)
1559 {
1560 int mii_reg5;
1561
1562 mii_reg5 = mdio_read (dev, tp->phys[0], 5);
1563
1564 if (!tp->duplex_lock && mii_reg5 != 0xffff) {
1565 int duplex = (mii_reg5 & 0x0100)
1566 || (mii_reg5 & 0x01C0) == 0x0040;
1567 if (tp->full_duplex != duplex) {
1568 tp->full_duplex = duplex;
1569
1570 if (mii_reg5) {
1571 printk (KERN_INFO
1572 "%s: Setting %s-duplex based on MII #%d link"
1573 " partner ability of %4.4x.\n",
1574 dev->name,
1575 tp->full_duplex ? "full" : "half",
1576 tp->phys[0], mii_reg5);
1577 } else {
1578 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1579 dev->name);
1580 }
1581 #if 0
1582 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1583 RTL_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1584 RTL_W8 (Cfg9346, Cfg9346_Lock);
1585 #endif
1586 }
1587 }
1588
1589 next_tick = HZ * 60;
1590
1591 rtl8139_tune_twister (dev, tp);
1592
1593 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1594 dev->name, RTL_R16 (NWayLPAR));
1595 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1596 " RxStatus %4.4lx.\n", dev->name,
1597 RTL_R16 (IntrMask),
1598 RTL_R16 (IntrStatus),
1599 RTL_R32 (RxEarlyStatus));
1600 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1601 dev->name, RTL_R8 (Config0),
1602 RTL_R8 (Config1));
1603 }
1604
1605
1606 static int rtl8139_thread (void *data)
1607 {
1608 struct net_device *dev = data;
1609 struct rtl8139_private *tp = dev->priv;
1610 unsigned long timeout;
1611
1612 daemonize ();
1613 reparent_to_init();
1614 spin_lock_irq(¤t->sigmask_lock);
1615 sigemptyset(¤t->blocked);
1616 recalc_sigpending(current);
1617 spin_unlock_irq(¤t->sigmask_lock);
1618
1619 strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
1620 current->comm[sizeof(current->comm) - 1] = '\0';
1621
1622 while (1) {
1623 timeout = next_tick;
1624 do {
1625 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1626 } while (!signal_pending (current) && (timeout > 0));
1627
1628 if (signal_pending (current))
1629 break;
1630
1631 rtnl_lock ();
1632 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1633 rtnl_unlock ();
1634 }
1635
1636 complete_and_exit (&tp->thr_exited, 0);
1637 }
1638
1639
1640 static void rtl8139_tx_clear (struct rtl8139_private *tp)
1641 {
1642 int i;
1643
1644 tp->cur_tx = 0;
1645 tp->dirty_tx = 0;
1646
1647 /* Dump the unsent Tx packets. */
1648 for (i = 0; i < NUM_TX_DESC; i++) {
1649 struct ring_info *rp = &tp->tx_info[i];
1650 if (rp->mapping != 0) {
1651 pci_unmap_single (tp->pci_dev, rp->mapping,
1652 rp->skb->len, PCI_DMA_TODEVICE);
1653 rp->mapping = 0;
1654 }
1655 if (rp->skb) {
1656 dev_kfree_skb (rp->skb);
1657 rp->skb = NULL;
1658 tp->stats.tx_dropped++;
1659 }
1660 }
1661 }
1662
1663
1664 static void rtl8139_tx_timeout (struct net_device *dev)
1665 {
1666 struct rtl8139_private *tp = dev->priv;
1667 void *ioaddr = tp->mmio_addr;
1668 int i;
1669 u8 tmp8;
1670 unsigned long flags;
1671
1672 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1673 "media %2.2x.\n", dev->name,
1674 RTL_R8 (ChipCmd),
1675 RTL_R16 (IntrStatus),
1676 RTL_R8 (MediaStatus));
1677
1678 tp->xstats.tx_timeouts++;
1679
1680 /* disable Tx ASAP, if not already */
1681 tmp8 = RTL_R8 (ChipCmd);
1682 if (tmp8 & CmdTxEnb)
1683 RTL_W8 (ChipCmd, CmdRxEnb);
1684
1685 /* Disable interrupts by clearing the interrupt mask. */
1686 RTL_W16 (IntrMask, 0x0000);
1687
1688 /* Emit info to figure out what went wrong. */
1689 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1690 dev->name, tp->cur_tx, tp->dirty_tx);
1691 for (i = 0; i < NUM_TX_DESC; i++)
1692 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1693 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1694 i == tp->dirty_tx % NUM_TX_DESC ?
1695 " (queue head)" : "");
1696
1697 /* Stop a shared interrupt from scavenging while we are. */
1698 spin_lock_irqsave (&tp->lock, flags);
1699 rtl8139_tx_clear (tp);
1700 spin_unlock_irqrestore (&tp->lock, flags);
1701
1702 /* ...and finally, reset everything */
1703 rtl8139_hw_start (dev);
1704
1705 netif_wake_queue (dev);
1706 }
1707
1708
1709 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1710 {
1711 struct rtl8139_private *tp = dev->priv;
1712 void *ioaddr = tp->mmio_addr;
1713 unsigned int entry;
1714 u32 dma_addr;
1715
1716 mb();
1717
1718 /* Calculate the next Tx descriptor entry. */
1719 entry = tp->cur_tx % NUM_TX_DESC;
1720
1721 assert (tp->tx_info[entry].skb == NULL);
1722 assert (tp->tx_info[entry].mapping == 0);
1723
1724 tp->tx_info[entry].skb = skb;
1725 if ((long) skb->data & 3) { /* Must use alignment buffer. */
1726 /* tp->tx_info[entry].mapping = 0; */
1727 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1728 dma_addr = tp->tx_bufs_dma + (tp->tx_buf[entry] - tp->tx_bufs);
1729 } else {
1730 tp->xstats.tx_buf_mapped++;
1731 tp->tx_info[entry].mapping =
1732 pci_map_single (tp->pci_dev, skb->data, skb->len,
1733 PCI_DMA_TODEVICE);
1734 dma_addr = tp->tx_info[entry].mapping;
1735 }
1736
1737 /* Note: the chip doesn't have auto-pad! */
1738 spin_lock_irq(&tp->lock);
1739 RTL_W32_F (TxAddr0 + (entry * 4), dma_addr);
1740 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1741 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1742
1743 dev->trans_start = jiffies;
1744
1745 tp->cur_tx++;
1746 mb();
1747 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1748 netif_stop_queue (dev);
1749 spin_unlock_irq(&tp->lock);
1750
1751 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1752 dev->name, skb->data, skb->len, entry);
1753
1754 return 0;
1755 }
1756
1757
1758 static void rtl8139_tx_interrupt (struct net_device *dev,
1759 struct rtl8139_private *tp,
1760 void *ioaddr)
1761 {
1762 unsigned long dirty_tx, tx_left;
1763
1764 assert (dev != NULL);
1765 assert (tp != NULL);
1766 assert (ioaddr != NULL);
1767
1768 dirty_tx = tp->dirty_tx;
1769 tx_left = tp->cur_tx - dirty_tx;
1770 while (tx_left > 0) {
1771 int entry = dirty_tx % NUM_TX_DESC;
1772 int txstatus;
1773
1774 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1775
1776 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1777 break; /* It still hasn't been Txed */
1778
1779 /* Note: TxCarrierLost is always asserted at 100mbps. */
1780 if (txstatus & (TxOutOfWindow | TxAborted)) {
1781 /* There was an major error, log it. */
1782 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1783 dev->name, txstatus);
1784 tp->stats.tx_errors++;
1785 if (txstatus & TxAborted) {
1786 tp->stats.tx_aborted_errors++;
1787 RTL_W32_F (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1788 }
1789 if (txstatus & TxCarrierLost)
1790 tp->stats.tx_carrier_errors++;
1791 if (txstatus & TxOutOfWindow)
1792 tp->stats.tx_window_errors++;
1793 #ifdef ETHER_STATS
1794 if ((txstatus & 0x0f000000) == 0x0f000000)
1795 tp->stats.collisions16++;
1796 #endif
1797 } else {
1798 if (txstatus & TxUnderrun) {
1799 /* Add 64 to the Tx FIFO threshold. */
1800 if (tp->tx_flag < 0x00300000)
1801 tp->tx_flag += 0x00020000;
1802 tp->stats.tx_fifo_errors++;
1803 }
1804 tp->stats.collisions += (txstatus >> 24) & 15;
1805 tp->stats.tx_bytes += txstatus & 0x7ff;
1806 tp->stats.tx_packets++;
1807 }
1808
1809 /* Free the original skb. */
1810 if (tp->tx_info[entry].mapping != 0) {
1811 pci_unmap_single(tp->pci_dev,
1812 tp->tx_info[entry].mapping,
1813 tp->tx_info[entry].skb->len,
1814 PCI_DMA_TODEVICE);
1815 tp->tx_info[entry].mapping = 0;
1816 }
1817 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1818 tp->tx_info[entry].skb = NULL;
1819
1820 dirty_tx++;
1821 tx_left--;
1822 }
1823
1824 #ifndef RTL8139_NDEBUG
1825 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1826 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1827 dev->name, dirty_tx, tp->cur_tx);
1828 dirty_tx += NUM_TX_DESC;
1829 }
1830 #endif /* RTL8139_NDEBUG */
1831
1832 /* only wake the queue if we did work, and the queue is stopped */
1833 if (tp->dirty_tx != dirty_tx) {
1834 tp->dirty_tx = dirty_tx;
1835 mb();
1836 if (netif_queue_stopped (dev))
1837 netif_wake_queue (dev);
1838 }
1839 }
1840
1841
1842 /* TODO: clean this up! Rx reset need not be this intensive */
1843 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1844 struct rtl8139_private *tp, void *ioaddr)
1845 {
1846 u8 tmp8;
1847 int tmp_work = 1000;
1848
1849 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1850 dev->name, rx_status);
1851 if (rx_status & RxTooLong) {
1852 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1853 dev->name, rx_status);
1854 /* A.C.: The chip hangs here. */
1855 }
1856 tp->stats.rx_errors++;
1857 if (rx_status & (RxBadSymbol | RxBadAlign))
1858 tp->stats.rx_frame_errors++;
1859 if (rx_status & (RxRunt | RxTooLong))
1860 tp->stats.rx_length_errors++;
1861 if (rx_status & RxCRCErr)
1862 tp->stats.rx_crc_errors++;
1863 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1864 tp->cur_rx = 0;
1865
1866 /* disable receive */
1867 RTL_W8 (ChipCmd, CmdTxEnb);
1868
1869 /* A.C.: Reset the multicast list. */
1870 rtl8139_set_rx_mode (dev);
1871
1872 /* XXX potentially temporary hack to
1873 * restart hung receiver */
1874 while (--tmp_work > 0) {
1875 barrier();
1876 tmp8 = RTL_R8 (ChipCmd);
1877 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1878 break;
1879 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1880 }
1881
1882 /* G.S.: Re-enable receiver */
1883 /* XXX temporary hack to work around receiver hang */
1884 rtl8139_set_rx_mode (dev);
1885
1886 if (tmp_work <= 0)
1887 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1888 }
1889
1890
1891 static void rtl8139_rx_interrupt (struct net_device *dev,
1892 struct rtl8139_private *tp, void *ioaddr)
1893 {
1894 unsigned char *rx_ring;
1895 u16 cur_rx;
1896
1897 assert (dev != NULL);
1898 assert (tp != NULL);
1899 assert (ioaddr != NULL);
1900
1901 rx_ring = tp->rx_ring;
1902 cur_rx = tp->cur_rx;
1903
1904 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1905 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1906 RTL_R16 (RxBufAddr),
1907 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1908
1909 while ((RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1910 int ring_offset = cur_rx % RX_BUF_LEN;
1911 u32 rx_status;
1912 unsigned int rx_size;
1913 unsigned int pkt_size;
1914 struct sk_buff *skb;
1915
1916 rmb();
1917
1918 /* read size+status of next frame from DMA ring buffer */
1919 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1920 rx_size = rx_status >> 16;
1921 pkt_size = rx_size - 4;
1922
1923 DPRINTK ("%s: rtl8139_rx() status %4.4x, size %4.4x,"
1924 " cur %4.4x.\n", dev->name, rx_status,
1925 rx_size, cur_rx);
1926 #if RTL8139_DEBUG > 2
1927 {
1928 int i;
1929 DPRINTK ("%s: Frame contents ", dev->name);
1930 for (i = 0; i < 70; i++)
1931 printk (" %2.2x",
1932 rx_ring[ring_offset + i]);
1933 printk (".\n");
1934 }
1935 #endif
1936
1937 if (rx_size == 0xfff0) { /* Early Rx in progress */
1938 tp->xstats.early_rx++;
1939 break;
1940 }
1941
1942 /* If Rx err or invalid rx_size/rx_status received
1943 * (which happens if we get lost in the ring),
1944 * Rx process gets reset, so we abort any further
1945 * Rx processing.
1946 */
1947 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1948 (rx_size < 8) ||
1949 (!(rx_status & RxStatusOK))) {
1950 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1951 return;
1952 }
1953
1954 /* Malloc up new buffer, compatible with net-2e. */
1955 /* Omit the four octet CRC from the length. */
1956
1957 /* TODO: consider allocating skb's outside of
1958 * interrupt context, both to speed interrupt processing,
1959 * and also to reduce the chances of having to
1960 * drop packets here under memory pressure.
1961 */
1962
1963 skb = dev_alloc_skb (pkt_size + 2);
1964 if (skb) {
1965 skb->dev = dev;
1966 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1967
1968 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1969 skb_put (skb, pkt_size);
1970
1971 skb->protocol = eth_type_trans (skb, dev);
1972 netif_rx (skb);
1973 dev->last_rx = jiffies;
1974 tp->stats.rx_bytes += pkt_size;
1975 tp->stats.rx_packets++;
1976 } else {
1977 printk (KERN_WARNING
1978 "%s: Memory squeeze, dropping packet.\n",
1979 dev->name);
1980 tp->stats.rx_dropped++;
1981 }
1982
1983 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1984 RTL_W16 (RxBufPtr, cur_rx - 16);
1985
1986 if (RTL_R16 (IntrStatus) & RxAckBits)
1987 RTL_W16_F (IntrStatus, RxAckBits);
1988 }
1989
1990 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1991 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1992 RTL_R16 (RxBufAddr),
1993 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1994
1995 tp->cur_rx = cur_rx;
1996
1997 if ((RTL_R8 (ChipCmd) & RxBufEmpty) &&
1998 (RTL_R16 (IntrStatus) & RxAckBits))
1999 RTL_W16_F (IntrStatus, RxAckBits);
2000 }
2001
2002
2003 static void rtl8139_weird_interrupt (struct net_device *dev,
2004 struct rtl8139_private *tp,
2005 void *ioaddr,
2006 int status, int link_changed)
2007 {
2008 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2009 dev->name, status);
2010
2011 assert (dev != NULL);
2012 assert (tp != NULL);
2013 assert (ioaddr != NULL);
2014
2015 /* Update the error count. */
2016 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2017 RTL_W32 (RxMissed, 0);
2018
2019 if ((status & RxUnderrun) && link_changed &&
2020 (tp->drv_flags & HAS_LNK_CHNG)) {
2021 /* Really link-change on new chips. */
2022 int lpar = RTL_R16 (NWayLPAR);
2023 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
2024 || tp->duplex_lock;
2025 if (tp->full_duplex != duplex) {
2026 tp->full_duplex = duplex;
2027 #if 0
2028 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2029 RTL_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
2030 RTL_W8 (Cfg9346, Cfg9346_Lock);
2031 #endif
2032 }
2033 status &= ~RxUnderrun;
2034 }
2035
2036 /* XXX along with rtl8139_rx_err, are we double-counting errors? */
2037 if (status &
2038 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
2039 tp->stats.rx_errors++;
2040
2041 if (status & (PCSTimeout))
2042 tp->stats.rx_length_errors++;
2043 if (status & (RxUnderrun | RxFIFOOver))
2044 tp->stats.rx_fifo_errors++;
2045 if (status & PCIErr) {
2046 u16 pci_cmd_status;
2047 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2048
2049 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2050 dev->name, pci_cmd_status);
2051 }
2052 }
2053
2054
2055 /* The interrupt handler does all of the Rx thread work and cleans up
2056 after the Tx thread. */
2057 static void rtl8139_interrupt (int irq, void *dev_instance,
2058 struct pt_regs *regs)
2059 {
2060 struct net_device *dev = (struct net_device *) dev_instance;
2061 struct rtl8139_private *tp = dev->priv;
2062 int boguscnt = max_interrupt_work;
2063 void *ioaddr = tp->mmio_addr;
2064 int ackstat, status;
2065 int link_changed = 0; /* avoid bogus "uninit" warning */
2066
2067 spin_lock (&tp->lock);
2068
2069 do {
2070 status = RTL_R16 (IntrStatus);
2071
2072 /* h/w no longer present (hotplug?) or major error, bail */
2073 if (status == 0xFFFF)
2074 break;
2075
2076 /* Acknowledge all of the current interrupt sources ASAP, but
2077 an first get an additional status bit from CSCR. */
2078 if (status & RxUnderrun)
2079 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2080
2081 /* The chip takes special action when we clear RxAckBits,
2082 * so we clear them later in rtl8139_rx_interrupt
2083 */
2084 ackstat = status & ~RxAckBits;
2085 RTL_W16 (IntrStatus, ackstat);
2086
2087 DPRINTK ("%s: interrupt status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
2088 dev->name, ackstat, status, RTL_R16 (IntrStatus));
2089
2090 if ((status &
2091 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2092 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
2093 break;
2094
2095 if (netif_running (dev) && (status & RxAckBits))
2096 rtl8139_rx_interrupt (dev, tp, ioaddr);
2097
2098 /* Check uncommon events with one test. */
2099 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2100 RxFIFOOver | TxErr | RxErr))
2101 rtl8139_weird_interrupt (dev, tp, ioaddr,
2102 status, link_changed);
2103
2104 if (netif_running (dev) && (status & (TxOK | TxErr)))
2105 rtl8139_tx_interrupt (dev, tp, ioaddr);
2106
2107 boguscnt--;
2108 } while (boguscnt > 0);
2109
2110 if (boguscnt <= 0) {
2111 printk (KERN_WARNING "%s: Too much work at interrupt, "
2112 "IntrStatus=0x%4.4x.\n", dev->name, status);
2113
2114 /* Clear all interrupt sources. */
2115 RTL_W16 (IntrStatus, 0xffff);
2116 }
2117
2118 spin_unlock (&tp->lock);
2119
2120 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2121 dev->name, RTL_R16 (IntrStatus));
2122 }
2123
2124
2125 static int rtl8139_close (struct net_device *dev)
2126 {
2127 struct rtl8139_private *tp = dev->priv;
2128 void *ioaddr = tp->mmio_addr;
2129 int ret = 0;
2130 unsigned long flags;
2131
2132 DPRINTK ("ENTER\n");
2133
2134 netif_stop_queue (dev);
2135
2136 if (tp->thr_pid >= 0) {
2137 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2138 if (ret) {
2139 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2140 return ret;
2141 }
2142 wait_for_completion (&tp->thr_exited);
2143 }
2144
2145 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
2146 dev->name, RTL_R16 (IntrStatus));
2147
2148 spin_lock_irqsave (&tp->lock, flags);
2149
2150 /* Stop the chip's Tx and Rx DMA processes. */
2151 RTL_W8 (ChipCmd, 0);
2152
2153 /* Disable interrupts by clearing the interrupt mask. */
2154 RTL_W16 (IntrMask, 0);
2155
2156 /* Update the error counts. */
2157 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2158 RTL_W32 (RxMissed, 0);
2159
2160 spin_unlock_irqrestore (&tp->lock, flags);
2161
2162 synchronize_irq ();
2163 free_irq (dev->irq, dev);
2164
2165 rtl8139_tx_clear (tp);
2166
2167 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2168 tp->rx_ring, tp->rx_ring_dma);
2169 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2170 tp->tx_bufs, tp->tx_bufs_dma);
2171 tp->rx_ring = NULL;
2172 tp->tx_bufs = NULL;
2173
2174 /* Green! Put the chip in low-power mode. */
2175 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2176
2177 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2178 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2179
2180 DPRINTK ("EXIT\n");
2181 return 0;
2182 }
2183
2184
2185 static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
2186 {
2187 struct rtl8139_private *np = dev->priv;
2188 u32 ethcmd;
2189
2190 if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
2191 return -EFAULT;
2192
2193 switch (ethcmd) {
2194 case ETHTOOL_GDRVINFO:
2195 {
2196 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
2197 strcpy (info.driver, DRV_NAME);
2198 strcpy (info.version, DRV_VERSION);
2199 strcpy (info.bus_info, np->pci_dev->slot_name);
2200 if (copy_to_user (useraddr, &info, sizeof (info)))
2201 return -EFAULT;
2202 return 0;
2203 }
2204
2205 default:
2206 break;
2207 }
2208
2209 return -EOPNOTSUPP;
2210 }
2211
2212 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
2213 {
2214 struct rtl8139_private *tp = dev->priv;
2215 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
2216 int rc = 0;
2217 int phy = tp->phys[0] & 0x3f;
2218
2219 DPRINTK ("ENTER\n");
2220
2221 data->phy_id &= 0x1f;
2222 data->reg_num &= 0x1f;
2223
2224 switch (cmd) {
2225 case SIOCETHTOOL:
2226 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
2227
2228 case SIOCGMIIPHY: /* Get the address of the PHY in use. */
2229 case SIOCDEVPRIVATE: /* binary compat, remove in 2.5 */
2230 data->phy_id = phy;
2231 /* Fall Through */
2232
2233 case SIOCGMIIREG: /* Read the specified MII register. */
2234 case SIOCDEVPRIVATE+1: /* binary compat, remove in 2.5 */
2235 data->val_out = mdio_read (dev, data->phy_id, data->reg_num);
2236 break;
2237
2238 case SIOCSMIIREG: /* Write the specified MII register */
2239 case SIOCDEVPRIVATE+2: /* binary compat, remove in 2.5 */
2240 if (!capable (CAP_NET_ADMIN)) {
2241 rc = -EPERM;
2242 break;
2243 }
2244
2245 if (data->phy_id == phy) {
2246 u16 value = data->val_in;
2247 switch (data->reg_num) {
2248 case 0:
2249 /* Check for autonegotiation on or reset. */
2250 tp->medialock = (value & 0x9000) ? 0 : 1;
2251 if (tp->medialock)
2252 tp->full_duplex = (value & 0x0100) ? 1 : 0;
2253 break;
2254 case 4: /* tp->advertising = value; */ break;
2255 }
2256 }
2257 mdio_write(dev, data->phy_id, data->reg_num, data->val_in);
2258 break;
2259
2260 default:
2261 rc = -EOPNOTSUPP;
2262 break;
2263 }
2264
2265 DPRINTK ("EXIT, returning %d\n", rc);
2266 return rc;
2267 }
2268
2269
2270 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2271 {
2272 struct rtl8139_private *tp = dev->priv;
2273 void *ioaddr = tp->mmio_addr;
2274 unsigned long flags;
2275
2276 DPRINTK ("ENTER\n");
2277
2278 if (netif_running(dev)) {
2279 spin_lock_irqsave (&tp->lock, flags);
2280 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2281 RTL_W32 (RxMissed, 0);
2282 spin_unlock_irqrestore (&tp->lock, flags);
2283 }
2284
2285 DPRINTK ("EXIT\n");
2286 return &tp->stats;
2287 }
2288
2289 /* Set or clear the multicast filter for this adaptor.
2290 This routine is not state sensitive and need not be SMP locked. */
2291
2292 static unsigned const ethernet_polynomial = 0x04c11db7U;
2293 static inline u32 ether_crc (int length, unsigned char *data)
2294 {
2295 int crc = -1;
2296
2297 DPRINTK ("ENTER\n");
2298
2299 while (--length >= 0) {
2300 unsigned char current_octet = *data++;
2301 int bit;
2302 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2303 crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
2304 ethernet_polynomial : 0);
2305 }
2306
2307 DPRINTK ("EXIT, returning %u\n", crc);
2308 return crc;
2309 }
2310
2311
2312 static void rtl8139_set_rx_mode (struct net_device *dev)
2313 {
2314 struct rtl8139_private *tp = dev->priv;
2315 void *ioaddr = tp->mmio_addr;
2316 unsigned long flags;
2317 u32 mc_filter[2]; /* Multicast hash filter */
2318 int i, rx_mode;
2319 u32 tmp;
2320
2321 DPRINTK ("ENTER\n");
2322
2323 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2324 dev->name, dev->flags, RTL_R32 (RxConfig));
2325
2326 /* Note: do not reorder, GCC is clever about common statements. */
2327 if (dev->flags & IFF_PROMISC) {
2328 /* Unconditionally log net taps. */
2329 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2330 dev->name);
2331 rx_mode =
2332 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2333 AcceptAllPhys;
2334 mc_filter[1] = mc_filter[0] = 0xffffffff;
2335 } else if ((dev->mc_count > multicast_filter_limit)
2336 || (dev->flags & IFF_ALLMULTI)) {
2337 /* Too many to filter perfectly -- accept all multicasts. */
2338 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2339 mc_filter[1] = mc_filter[0] = 0xffffffff;
2340 } else {
2341 struct dev_mc_list *mclist;
2342 rx_mode = AcceptBroadcast | AcceptMyPhys;
2343 mc_filter[1] = mc_filter[0] = 0;
2344 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2345 i++, mclist = mclist->next) {
2346 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2347
2348 mc_filter[bit_nr >> 5] |= cpu_to_le32(1 << (bit_nr & 31));
2349 rx_mode |= AcceptMulticast;
2350 }
2351 }
2352
2353 spin_lock_irqsave (&tp->lock, flags);
2354
2355 /* We can safely update without stopping the chip. */
2356 tmp = rtl8139_rx_config | rx_mode;
2357 if (tp->rx_config != tmp) {
2358 RTL_W32 (RxConfig, tmp);
2359 tp->rx_config = tmp;
2360 }
2361 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2362 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2363
2364 spin_unlock_irqrestore (&tp->lock, flags);
2365
2366 DPRINTK ("EXIT\n");
2367 }
2368
2369
2370 #ifdef CONFIG_PM
2371
2372 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2373 {
2374 struct net_device *dev = pci_get_drvdata (pdev);
2375 struct rtl8139_private *tp = dev->priv;
2376 void *ioaddr = tp->mmio_addr;
2377 unsigned long flags;
2378
2379 if (!netif_running (dev))
2380 return 0;
2381
2382 netif_device_detach (dev);
2383
2384 spin_lock_irqsave (&tp->lock, flags);
2385
2386 /* Disable interrupts, stop Tx and Rx. */
2387 RTL_W16 (IntrMask, 0);
2388 RTL_W8 (ChipCmd, 0);
2389
2390 /* Update the error counts. */
2391 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2392 RTL_W32 (RxMissed, 0);
2393
2394 spin_unlock_irqrestore (&tp->lock, flags);
2395 return 0;
2396 }
2397
2398
2399 static int rtl8139_resume (struct pci_dev *pdev)
2400 {
2401 struct net_device *dev = pci_get_drvdata (pdev);
2402
2403 if (!netif_running (dev))
2404 return 0;
2405 netif_device_attach (dev);
2406 rtl8139_hw_start (dev);
2407 return 0;
2408 }
2409
2410 #endif /* CONFIG_PM */
2411
2412
2413 static struct pci_driver rtl8139_pci_driver = {
2414 name: DRV_NAME,
2415 id_table: rtl8139_pci_tbl,
2416 probe: rtl8139_init_one,
2417 remove: rtl8139_remove_one,
2418 #ifdef CONFIG_PM
2419 suspend: rtl8139_suspend,
2420 resume: rtl8139_resume,
2421 #endif /* CONFIG_PM */
2422 };
2423
2424
2425 static int __init rtl8139_init_module (void)
2426 {
2427 /* when we're a module, we always print a version message,
2428 * even if no 8139 board is found.
2429 */
2430 #ifdef MODULE
2431 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2432 #endif
2433
2434 return pci_module_init (&rtl8139_pci_driver);
2435 }
2436
2437
2438 static void __exit rtl8139_cleanup_module (void)
2439 {
2440 pci_unregister_driver (&rtl8139_pci_driver);
2441 }
2442
2443
2444 module_init(rtl8139_init_module);
2445 module_exit(rtl8139_cleanup_module);
2446