File: /usr/src/linux/drivers/net/au1000_eth.h
1 /*
2 *
3 * Alchemy Semi Au1000 ethernet driver include file
4 *
5 * Author: Pete Popov <ppopov@mvista.com>
6 *
7 * Copyright 2001 MontaVista Software Inc.
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 *
24 * ########################################################################
25 *
26 *
27 */
28
29
30 #define NUM_INTERFACES 2
31 #define MAC_IOSIZE 0x10000
32 #define NUM_RX_DMA 4 /* Au1000 has 4 rx hardware descriptors */
33 #define NUM_TX_DMA 4 /* Au1000 has 4 tx hardware descriptors */
34
35 #define NUM_RX_BUFFS 4
36 #define NUM_TX_BUFFS 4
37 #define MAX_BUF_SIZE 2048
38
39 #define ETH_TX_TIMEOUT HZ/4
40 #define MAC_MIN_PKT_SIZE 64
41
42 #ifdef CONFIG_MIPS_PB1000
43 #define PHY_ADDRESS 0
44 #define PHY_CONTROL_DEFAULT 0x3000
45 #define PHY_CONTROL_REG_ADDR 0
46 #endif
47
48 #define MULTICAST_FILTER_LIMIT 64
49
50 /* FIXME
51 * The PHY defines should be in a separate file.
52 */
53
54 /* MII register offsets */
55 #define MII_CONTROL 0x0000
56 #define MII_STATUS 0x0001
57 #define MII_PHY_ID0 0x0002
58 #define MII_PHY_ID1 0x0003
59 #define MII_ANADV 0x0004
60 #define MII_ANLPAR 0x0005
61 #define MII_AEXP 0x0006
62 #define MII_ANEXT 0x0007
63 #define MII_AUX_CNTRL 0x18
64
65 /* mii registers specific to AMD 79C901 */
66 #define MII_STATUS_SUMMARY = 0x0018
67
68 /* MII Control register bit definitions. */
69 #define MII_CNTL_FDX 0x0100
70 #define MII_CNTL_RST_AUTO 0x0200
71 #define MII_CNTL_ISOLATE 0x0400
72 #define MII_CNTL_PWRDWN 0x0800
73 #define MII_CNTL_AUTO 0x1000
74 #define MII_CNTL_F100 0x2000
75 #define MII_CNTL_LPBK 0x4000
76 #define MII_CNTL_RESET 0x8000
77
78 /* MII Status register bit */
79 #define MII_STAT_EXT 0x0001
80 #define MII_STAT_JAB 0x0002
81 #define MII_STAT_LINK 0x0004
82 #define MII_STAT_CAN_AUTO 0x0008
83 #define MII_STAT_FAULT 0x0010
84 #define MII_STAT_AUTO_DONE 0x0020
85 #define MII_STAT_CAN_T 0x0800
86 #define MII_STAT_CAN_T_FDX 0x1000
87 #define MII_STAT_CAN_TX 0x2000
88 #define MII_STAT_CAN_TX_FDX 0x4000
89 #define MII_STAT_CAN_T4 0x8000
90
91
92 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
93 #define MII_ID1_MODEL 0x03F0 /* model number */
94 #define MII_ID1_REV 0x000F /* model number */
95
96 /* MII NWAY Register Bits ...
97 valid for the ANAR (Auto-Negotiation Advertisement) and
98 ANLPAR (Auto-Negotiation Link Partner) registers */
99 #define MII_NWAY_NODE_SEL 0x001f
100 #define MII_NWAY_CSMA_CD 0x0001
101 #define MII_NWAY_T 0x0020
102 #define MII_NWAY_T_FDX 0x0040
103 #define MII_NWAY_TX 0x0080
104 #define MII_NWAY_TX_FDX 0x0100
105 #define MII_NWAY_T4 0x0200
106 #define MII_NWAY_PAUSE 0x0400
107 #define MII_NWAY_RF 0x2000 /* Remote Fault */
108 #define MII_NWAY_ACK 0x4000 /* Remote Acknowledge */
109 #define MII_NWAY_NP 0x8000 /* Next Page (Enable) */
110
111 /* mii stsout register bits */
112 #define MII_STSOUT_LINK_FAIL 0x4000
113 #define MII_STSOUT_SPD 0x0080
114 #define MII_STSOUT_DPLX 0x0040
115
116 /* mii stsics register bits */
117 #define MII_STSICS_SPD 0x8000
118 #define MII_STSICS_DPLX 0x4000
119 #define MII_STSICS_LINKSTS 0x0001
120
121 /* mii stssum register bits */
122 #define MII_STSSUM_LINK 0x0008
123 #define MII_STSSUM_DPLX 0x0004
124 #define MII_STSSUM_AUTO 0x0002
125 #define MII_STSSUM_SPD 0x0001
126
127 /* Auxilliary Control/Status Register */
128 #define MII_AUX_FDX 0x0001
129 #define MII_AUX_100 0x0002
130 #define MII_AUX_F100 0x0004
131 #define MII_AUX_ANEG 0x0008
132
133 typedef struct mii_phy {
134 struct mii_phy * next;
135 struct mii_chip_info * chip_info;
136 int phy_addr;
137 u16 status;
138 } mii_phy_t;
139
140 struct phy_ops {
141 int (*phy_init) (struct net_device *, int);
142 int (*phy_reset) (struct net_device *, int);
143 int (*phy_status) (struct net_device *, int, u16 *, u16 *);
144 };
145
146 /*
147 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
148 * boundary for both, receive and transmit.
149 */
150 typedef struct db_dest {
151 struct db_dest *pnext;
152 volatile u32 *vaddr;
153 dma_addr_t dma_addr;
154 } db_dest_t;
155
156 /*
157 * The transmit and receive descriptors are memory
158 * mapped registers.
159 */
160 typedef struct tx_dma {
161 u32 status;
162 u32 buff_stat;
163 u32 len;
164 u32 pad;
165 } tx_dma_t;
166
167 typedef struct rx_dma {
168 u32 status;
169 u32 buff_stat;
170 u32 pad[2];
171 } rx_dma_t;
172
173
174 /*
175 * MAC control registers, memory mapped.
176 */
177 typedef struct mac_reg {
178 u32 control;
179 u32 mac_addr_high;
180 u32 mac_addr_low;
181 u32 multi_hash_high;
182 u32 multi_hash_low;
183 u32 mii_control;
184 u32 mii_data;
185 u32 flow_control;
186 u32 vlan1_tag;
187 u32 vlan2_tag;
188 } mac_reg_t;
189
190
191 struct au1000_private {
192
193 db_dest_t *pDBfree;
194 db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];
195 volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
196 volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA];
197 db_dest_t *rx_db_inuse[NUM_RX_DMA];
198 db_dest_t *tx_db_inuse[NUM_TX_DMA];
199 u32 rx_head;
200 u32 tx_head;
201 u32 tx_tail;
202 u32 tx_full;
203
204 mii_phy_t *mii;
205 struct phy_ops *phy_ops;
206
207 /* These variables are just for quick access to certain regs addresses. */
208 volatile mac_reg_t *mac; /* mac registers */
209 volatile u32 *enable; /* address of MAC Enable Register */
210
211 u32 vaddr; /* virtual address of rx/tx buffers */
212 dma_addr_t dma_addr; /* dma address of rx/tx buffers */
213
214 u8 *hash_table;
215 u32 hash_mode;
216 u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
217 u32 phy_addr; /* PHY address */
218 u32 options; /* User-settable misc. driver options. */
219 u32 drv_flags;
220 struct net_device_stats stats;
221 struct timer_list timer;
222 spinlock_t lock; /* Serialise access to device */
223 };
224