File: /usr/src/linux/drivers/net/au1000_eth.c
1 /*
2 *
3 * Alchemy Semi Au1000 ethernet driver
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 *
24 * ########################################################################
25 *
26 *
27 */
28
29 #ifndef __mips__
30 #error This driver only works with MIPS architectures!
31 #endif
32
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/sched.h>
37 #include <linux/string.h>
38 #include <linux/timer.h>
39 #include <linux/errno.h>
40 #include <linux/in.h>
41 #include <linux/ioport.h>
42 #include <linux/slab.h>
43 #include <linux/interrupt.h>
44 #include <linux/pci.h>
45 #include <linux/init.h>
46 #include <linux/netdevice.h>
47 #include <linux/etherdevice.h>
48 #include <linux/skbuff.h>
49 #include <linux/delay.h>
50 #include <asm/irq.h>
51 #include <asm/bitops.h>
52 #include <asm/io.h>
53
54 #include <asm/au1000.h>
55 #include "au1000_eth.h"
56
57 #ifdef AU1000_ETH_DEBUG
58 static int au1000_debug = 10;
59 #else
60 static int au1000_debug = 3;
61 #endif
62
63 // prototypes
64 static void *dma_alloc(size_t, dma_addr_t *);
65 static void dma_free(void *, size_t);
66 static void hard_stop(struct net_device *);
67 static int __init au1000_probe1(struct net_device *, long, int, int);
68 static int au1000_init(struct net_device *);
69 static int au1000_open(struct net_device *);
70 static int au1000_close(struct net_device *);
71 static int au1000_tx(struct sk_buff *, struct net_device *);
72 static int au1000_rx(struct net_device *);
73 static void au1000_interrupt(int, void *, struct pt_regs *);
74 static void au1000_tx_timeout(struct net_device *);
75 static int au1000_set_config(struct net_device *dev, struct ifmap *map);
76 static void set_rx_mode(struct net_device *);
77 static struct net_device_stats *au1000_get_stats(struct net_device *);
78 static inline void update_tx_stats(struct net_device *, u32, u32);
79 static inline void update_rx_stats(struct net_device *, u32);
80 static void au1000_timer(unsigned long);
81 static void cleanup_buffers(struct net_device *);
82 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
83 static int mdio_read(struct net_device *, int, int);
84 static void mdio_write(struct net_device *, int, int, u16);
85 static inline void sync(void);
86
87 extern void ack_rise_edge_irq(unsigned int);
88
89 static int next_dev;
90
91 /*
92 * Theory of operation
93 *
94 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
95 * There are four receive and four transmit descriptors. These
96 * descriptors are not in memory; rather, they are just a set of
97 * hardware registers.
98 *
99 * Since the Au1000 has a coherent data cache, the receive and
100 * transmit buffers are allocated from the KSEG0 segment. The
101 * hardware registers, however, are still mapped at KSEG1 to
102 * make sure there's no out-of-order writes, and that all writes
103 * complete immediately.
104 */
105
106
107 /*
108 * Base address and interupt of the Au1000 ethernet macs
109 */
110 static struct {
111 unsigned int port;
112 int irq;
113 } au1000_iflist[NUM_INTERFACES] = {
114 {AU1000_ETH0_BASE, AU1000_ETH0_IRQ},
115 {AU1000_ETH1_BASE, AU1000_ETH1_IRQ}
116 };
117
118
119 static char version[] __devinitdata =
120 "au1000eth.c:0.1 ppopov@mvista.com\n";
121
122 // FIX! Need real Ethernet addresses
123 static unsigned char au1000_mac_addr[2][6] __devinitdata = {
124 {0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00},
125 {0x00, 0x50, 0xc2, 0x0c, 0x40, 0x00}
126 };
127
128 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
129 #define RUN_AT(x) (jiffies + (x))
130
131 // For reading/writing 32-bit words from/to DMA memory
132 #define cpu_to_dma32 cpu_to_be32
133 #define dma32_to_cpu be32_to_cpu
134
135 /* CPU pipeline flush */
136 static inline void sync(void)
137 {
138 asm volatile ("sync");
139 }
140
141 /* FIXME
142 * All of the PHY code really should be detached from the MAC
143 * code.
144 */
145
146 static char *phy_link[] =
147 {"unknown",
148 "10Base2", "10BaseT",
149 "AUI",
150 "100BaseT", "100BaseTX", "100BaseFX"};
151
152 int bcm_5201_init(struct net_device *dev, int phy_addr)
153 {
154 s16 data;
155
156 /* Stop auto-negotiation */
157 //printk("bcm_5201_init\n");
158 data = mdio_read(dev, phy_addr, MII_CONTROL);
159 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
160
161 /* Set advertisement to 10/100 and Half/Full duplex
162 * (full capabilities) */
163 data = mdio_read(dev, phy_addr, MII_ANADV);
164 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
165 mdio_write(dev, phy_addr, MII_ANADV, data);
166
167 /* Restart auto-negotiation */
168 data = mdio_read(dev, phy_addr, MII_CONTROL);
169 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
170 mdio_write(dev, phy_addr, MII_CONTROL, data);
171 //dump_mii(dev, phy_addr);
172 return 0;
173 }
174
175 int bcm_5201_reset(struct net_device *dev, int phy_addr)
176 {
177 s16 mii_control, timeout;
178
179 //printk("bcm_5201_reset\n");
180 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
181 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
182 mdelay(1);
183 for (timeout = 100; timeout > 0; --timeout) {
184 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
185 if ((mii_control & MII_CNTL_RESET) == 0)
186 break;
187 mdelay(1);
188 }
189 if (mii_control & MII_CNTL_RESET) {
190 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
191 return -1;
192 }
193 return 0;
194 }
195
196 int
197 bcm_5201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
198 {
199 u16 mii_data;
200 struct au1000_private *aup;
201
202 if (!dev) {
203 printk(KERN_ERR "bcm_5201_status error: NULL dev\n");
204 return -1;
205 }
206 aup = (struct au1000_private *) dev->priv;
207
208 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
209 if (mii_data & MII_STAT_LINK) {
210 *link = 1;
211 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
212 if (mii_data & MII_AUX_100) {
213 if (mii_data & MII_AUX_FDX) {
214 *speed = IF_PORT_100BASEFX;
215 dev->if_port = IF_PORT_100BASEFX;
216 }
217 else {
218 *speed = IF_PORT_100BASETX;
219 dev->if_port = IF_PORT_100BASETX;
220 }
221 }
222 else {
223 *speed = IF_PORT_10BASET;
224 dev->if_port = IF_PORT_10BASET;
225 }
226
227 }
228 else {
229 *link = 0;
230 *speed = 0;
231 }
232 return 0;
233 }
234
235
236 int am79c901_init(struct net_device *dev, int phy_addr)
237 {
238 printk("am79c901_init\n");
239 return 0;
240 }
241
242 int am79c901_reset(struct net_device *dev, int phy_addr)
243 {
244 printk("am79c901_reset\n");
245 return 0;
246 }
247
248 int
249 am79c901_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
250 {
251 return 0;
252 }
253
254 struct phy_ops bcm_5201_ops = {
255 bcm_5201_init,
256 bcm_5201_reset,
257 bcm_5201_status,
258 };
259
260 struct phy_ops am79c901_ops = {
261 am79c901_init,
262 am79c901_reset,
263 am79c901_status,
264 };
265
266 static struct mii_chip_info {
267 const char * name;
268 u16 phy_id0;
269 u16 phy_id1;
270 struct phy_ops *phy_ops;
271 } mii_chip_table[] = {
272 {"Broadcom BCM5201 10/100 BaseT PHY", 0x0040, 0x6212, &bcm_5201_ops },
273 {"AMD 79C901 HomePNA PHY", 0x0000, 0x35c8, &am79c901_ops },
274 {0,},
275 };
276
277 static int mdio_read(struct net_device *dev, int phy_id, int reg)
278 {
279 struct au1000_private *aup = (struct au1000_private *) dev->priv;
280 u32 timedout = 20;
281 u32 mii_control;
282
283 while (aup->mac->mii_control & MAC_MII_BUSY) {
284 mdelay(1);
285 if (--timedout == 0) {
286 printk(KERN_ERR "%s: read_MII busy timeout!!\n", dev->name);
287 return -1;
288 }
289 }
290
291 mii_control = MAC_SET_MII_SELECT_REG(reg) |
292 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_READ;
293
294 aup->mac->mii_control = mii_control;
295
296 timedout = 20;
297 while (aup->mac->mii_control & MAC_MII_BUSY) {
298 mdelay(1);
299 if (--timedout == 0) {
300 printk(KERN_ERR "%s: mdio_read busy timeout!!\n", dev->name);
301 return -1;
302 }
303 }
304 return (int)aup->mac->mii_data;
305 }
306
307 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 value)
308 {
309 struct au1000_private *aup = (struct au1000_private *) dev->priv;
310 u32 timedout = 20;
311 u32 mii_control;
312
313 while (aup->mac->mii_control & MAC_MII_BUSY) {
314 mdelay(1);
315 if (--timedout == 0) {
316 printk(KERN_ERR "%s: mdio_write busy timeout!!\n", dev->name);
317 return;
318 }
319 }
320
321 mii_control = MAC_SET_MII_SELECT_REG(reg) |
322 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_WRITE;
323
324 aup->mac->mii_data = value;
325 aup->mac->mii_control = mii_control;
326 }
327
328
329 static void dump_mii(struct net_device *dev, int phy_id)
330 {
331 int i, val;
332
333 for (i = 0; i < 7; i++) {
334 if ((val = mdio_read(dev, phy_id, i)) >= 0)
335 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
336 }
337 for (i = 16; i < 25; i++) {
338 if ((val = mdio_read(dev, phy_id, i)) >= 0)
339 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
340 }
341 }
342
343 static int __init mii_probe (struct net_device * dev)
344 {
345 struct au1000_private *aup = (struct au1000_private *) dev->priv;
346 int phy_addr;
347
348 aup->mii = NULL;
349
350 /* search for total of 32 possible mii phy addresses */
351 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
352 u16 mii_status;
353 u16 phy_id0, phy_id1;
354 int i;
355
356 mii_status = mdio_read(dev, phy_addr, MII_STATUS);
357 if (mii_status == 0xffff || mii_status == 0x0000)
358 /* the mii is not accessable, try next one */
359 continue;
360
361 phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);
362 phy_id1 = mdio_read(dev, phy_addr, MII_PHY_ID1);
363
364 /* search our mii table for the current mii */
365 for (i = 0; mii_chip_table[i].phy_id1; i++)
366 if (phy_id0 == mii_chip_table[i].phy_id0 &&
367 phy_id1 == mii_chip_table[i].phy_id1) {
368 struct mii_phy * mii_phy;
369
370 printk(KERN_INFO "%s: %s found at phy address %d\n",
371 dev->name, mii_chip_table[i].name, phy_addr);
372 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) != NULL) {
373 mii_phy->chip_info = mii_chip_table+i;
374 mii_phy->phy_addr = phy_addr;
375 //mii_phy->status = mdio_read(dev, phy_addr, MII_STATUS);
376 mii_phy->next = aup->mii;
377 aup->phy_ops = mii_chip_table[i].phy_ops;
378 aup->mii = mii_phy;
379 }
380 /* the current mii is on our mii_info_table,
381 try next address */
382 break;
383 }
384 }
385
386 if (aup->mii == NULL) {
387 printk(KERN_ERR "%s: No MII transceivers found!\n", dev->name);
388 return -1;
389 }
390
391 /* use last PHY */
392 aup->phy_addr = aup->mii->phy_addr;
393 printk(KERN_INFO "%s: Using %s as default\n", dev->name, aup->mii->chip_info->name);
394
395 return 0;
396 }
397
398
399 /*
400 * Buffer allocation/deallocation routines. The buffer descriptor returned
401 * has the virtual and dma address of a buffer suitable for
402 * both, receive and transmit operations.
403 */
404 static db_dest_t *GetFreeDB(struct au1000_private *aup)
405 {
406 db_dest_t *pDB;
407 pDB = aup->pDBfree;
408
409 if (pDB) {
410 aup->pDBfree = pDB->pnext;
411 }
412 //printk("GetFreeDB: %x\n", pDB);
413 return pDB;
414 }
415
416 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
417 {
418 db_dest_t *pDBfree = aup->pDBfree;
419 if (pDBfree)
420 pDBfree->pnext = pDB;
421 aup->pDBfree = pDB;
422 }
423
424
425 /*
426 DMA memory allocation, derived from pci_alloc_consistent.
427 However, the Au1000 data cache is coherent (when programmed
428 so), therefore we return KSEG0 address, not KSEG1.
429 */
430 static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
431 {
432 void *ret;
433 int gfp = GFP_ATOMIC | GFP_DMA;
434
435 ret = (void *) __get_free_pages(gfp, get_order(size));
436
437 if (ret != NULL) {
438 memset(ret, 0, size);
439 *dma_handle = virt_to_bus(ret);
440 ret = KSEG0ADDR(ret);
441 }
442 return ret;
443 }
444
445
446 static void dma_free(void *vaddr, size_t size)
447 {
448 vaddr = KSEG0ADDR(vaddr);
449 free_pages((unsigned long) vaddr, get_order(size));
450 }
451
452
453 static void hard_stop(struct net_device *dev)
454 {
455 struct au1000_private *aup = (struct au1000_private *) dev->priv;
456
457 if (au1000_debug > 4)
458 printk(KERN_INFO "%s: hard stop\n", dev->name);
459
460 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
461 sync();
462 mdelay(10);
463 }
464
465
466 static void reset_mac(struct net_device *dev)
467 {
468 u32 flags;
469 struct au1000_private *aup = (struct au1000_private *) dev->priv;
470
471 if (au1000_debug > 4)
472 printk(KERN_INFO "%s: reset mac, aup %x\n", dev->name, (unsigned)aup);
473
474 spin_lock_irqsave(&aup->lock, flags);
475 del_timer(&aup->timer);
476 hard_stop(dev);
477 *aup->enable |= MAC_DMA_RESET;
478 sync();
479 mdelay(10);
480 aup->tx_full = 0;
481 spin_unlock_irqrestore(&aup->lock, flags);
482 }
483
484 static void cleanup_buffers(struct net_device *dev)
485 {
486 int i;
487 struct au1000_private *aup = (struct au1000_private *) dev->priv;
488
489 for (i=0; i<NUM_RX_DMA; i++) {
490 if (aup->rx_db_inuse[i]) {
491 ReleaseDB(aup, aup->rx_db_inuse[i]);
492 aup->rx_db_inuse[i] = 0;
493 }
494 }
495
496 for (i=0; i<NUM_TX_DMA; i++) {
497 if (aup->tx_db_inuse[i]) {
498 ReleaseDB(aup, aup->tx_db_inuse[i]);
499 aup->tx_db_inuse[i] = 0;
500 }
501 }
502 }
503
504
505 /*
506 * Setup the receive and transmit "rings". These pointers are the addresses
507 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
508 * these are not descriptors sitting in memory.
509 */
510 static void
511 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
512 {
513 int i;
514
515 for (i=0; i<NUM_RX_DMA; i++) {
516 aup->rx_dma_ring[i] = (volatile rx_dma_t *) ioremap_nocache((unsigned long)
517 (rx_base + sizeof(rx_dma_t)*i), sizeof(rx_dma_t));
518 }
519 for (i=0; i<NUM_TX_DMA; i++) {
520 aup->tx_dma_ring[i] = (volatile tx_dma_t *)ioremap_nocache((unsigned long)
521 (tx_base + sizeof(tx_dma_t)*i), sizeof(tx_dma_t));
522 }
523 }
524
525 /*
526 * Probe for a AU1000 ethernet controller.
527 */
528 int __init au1000_probe(struct net_device *dev)
529 {
530 int base_addr = au1000_iflist[next_dev].port;
531 int irq = au1000_iflist[next_dev].irq;
532
533 #ifndef CONFIG_MIPS_AU1000_ENET
534 return -ENODEV;
535 #endif
536
537 if (au1000_debug > 4)
538 printk(KERN_INFO "%s: au1000_probe base_addr %x\n",
539 dev->name, base_addr);
540
541 if (next_dev >= NUM_INTERFACES) {
542 return -ENODEV;
543 }
544 if (au1000_probe1(dev, base_addr, irq, next_dev) == 0) {
545 next_dev++;
546 return 0;
547 }
548 next_dev++;
549 return -ENODEV;
550 }
551
552
553
554 static int __init
555 au1000_probe1(struct net_device *dev, long ioaddr, int irq, int port_num)
556 {
557 static unsigned version_printed = 0;
558 struct au1000_private *aup = NULL;
559 int i, retval = 0;
560 db_dest_t *pDB, *pDBfree;
561 u16 link, speed;
562
563 if ((ioaddr != AU1000_ETH0_BASE) && (ioaddr != AU1000_ETH1_BASE)) {
564 return -ENODEV;
565 }
566
567 if (!request_region(ioaddr, MAC_IOSIZE, "Au1000 ENET")) {
568 return -ENODEV;
569 }
570
571 if (version_printed++ == 0) printk(version);
572
573 if (!dev) {
574 dev = init_etherdev(0, sizeof(struct au1000_private));
575 }
576 if (!dev) {
577 printk (KERN_ERR "au1000 eth: init_etherdev failed\n");
578 return -ENODEV;
579 }
580
581 printk("%s: Au1000 ethernet found at 0x%lx, irq %d\n",
582 dev->name, ioaddr, irq);
583
584
585 /* Initialize our private structure */
586 if (dev->priv == NULL) {
587 aup = (struct au1000_private *) kmalloc(sizeof(*aup), GFP_KERNEL);
588 if (aup == NULL) {
589 retval = -ENOMEM;
590 goto free_region;
591 }
592 dev->priv = aup;
593 }
594
595 aup = dev->priv;
596 memset(aup, 0, sizeof(*aup));
597
598
599 /* Allocate the data buffers */
600 aup->vaddr = (u32)dma_alloc(MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS), &aup->dma_addr);
601 if (!aup->vaddr) {
602 retval = -ENOMEM;
603 goto free_region;
604 }
605
606 /* aup->mac is the base address of the MAC's registers */
607 aup->mac = (volatile mac_reg_t *)ioremap_nocache((unsigned long)ioaddr, sizeof(*aup->mac));
608 /* Setup some variables for quick register address access */
609 if (ioaddr == AU1000_ETH0_BASE) {
610 aup->enable = (volatile u32 *)
611 ioremap_nocache((unsigned long)MAC0_ENABLE, sizeof(*aup->enable));
612 memcpy(dev->dev_addr, au1000_mac_addr[0], sizeof(dev->dev_addr));
613 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
614 }
615 else if (ioaddr == AU1000_ETH1_BASE) {
616 aup->enable = (volatile u32 *)
617 ioremap_nocache((unsigned long)MAC1_ENABLE, sizeof(*aup->enable));
618 memcpy(dev->dev_addr, au1000_mac_addr[1], sizeof(dev->dev_addr));
619 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
620 }
621 else { /* should never happen */
622 printk (KERN_ERR "au1000 eth: bad ioaddr %x\n", (unsigned)ioaddr);
623 retval = -ENODEV;
624 goto free_region;
625 }
626
627 aup->phy_addr = PHY_ADDRESS;
628 /* bring the device out of reset, otherwise probing the mii
629 * will hang */
630 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
631 MAC_EN_CLOCK_ENABLE | MAC_EN_TOSS;
632 sync();
633 mdelay(2);
634 if (mii_probe(dev) != 0) {
635 goto free_region;
636 }
637 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
638 if (!link) {
639 printk(KERN_INFO "%s: link down resetting...\n", dev->name);
640 aup->phy_ops->phy_reset(dev, aup->phy_addr);
641 aup->phy_ops->phy_init(dev, aup->phy_addr);
642 }
643 else {
644 printk(KERN_INFO "%s: link up (%s)\n", dev->name, phy_link[speed]);
645 }
646
647 pDBfree = NULL;
648 /* setup the data buffer descriptors and attach a buffer to each one */
649 pDB = aup->db;
650 for (i=0; i<(NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
651 pDB->pnext = pDBfree;
652 pDBfree = pDB;
653 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
654 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
655 pDB++;
656 }
657 aup->pDBfree = pDBfree;
658
659 for (i=0; i<NUM_RX_DMA; i++) {
660 pDB = GetFreeDB(aup);
661 if (!pDB) goto free_region;
662 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
663 aup->rx_db_inuse[i] = pDB;
664 }
665 for (i=0; i<NUM_TX_DMA; i++) {
666 pDB = GetFreeDB(aup);
667 if (!pDB) goto free_region;
668 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
669 aup->tx_dma_ring[i]->len = 0;
670 aup->tx_db_inuse[i] = pDB;
671 }
672
673 spin_lock_init(&aup->lock);
674 dev->base_addr = ioaddr;
675 dev->irq = irq;
676 dev->open = au1000_open;
677 dev->hard_start_xmit = au1000_tx;
678 dev->stop = au1000_close;
679 dev->get_stats = au1000_get_stats;
680 dev->set_multicast_list = &set_rx_mode;
681 dev->do_ioctl = &au1000_ioctl;
682 dev->set_config = &au1000_set_config;
683 dev->tx_timeout = au1000_tx_timeout;
684 dev->watchdog_timeo = ETH_TX_TIMEOUT;
685
686
687 /* Fill in the fields of the device structure with ethernet values. */
688 ether_setup(dev);
689
690 /*
691 * The boot code uses the ethernet controller, so reset it to start fresh.
692 * au1000_init() expects that the device is in reset state.
693 */
694 reset_mac(dev);
695
696 return 0;
697
698 free_region:
699 release_region(ioaddr, MAC_IOSIZE);
700 unregister_netdev(dev);
701 if (aup->vaddr)
702 dma_free((void *)aup->vaddr, MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS));
703 if (dev->priv != NULL)
704 kfree(dev->priv);
705 kfree(dev);
706 printk(KERN_ERR "%s: au1000_probe1 failed. Returns %d\n",
707 dev->name, retval);
708 return retval;
709 }
710
711
712 /*
713 * Initialize the interface.
714 *
715 * When the device powers up, the clocks are disabled and the
716 * mac is in reset state. When the interface is closed, we
717 * do the same -- reset the device and disable the clocks to
718 * conserve power. Thus, whenever au1000_init() is called,
719 * the device should already be in reset state.
720 */
721 static int au1000_init(struct net_device *dev)
722 {
723 struct au1000_private *aup = (struct au1000_private *) dev->priv;
724 u32 flags;
725 int i;
726 u32 value, control;
727
728 if (au1000_debug > 4) printk("%s: au1000_init", dev->name);
729
730 spin_lock_irqsave(&aup->lock, flags);
731
732 /* bring the device out of reset */
733 value = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
734 MAC_EN_CLOCK_ENABLE | MAC_EN_TOSS;
735 *aup->enable = value;
736 sync();
737 mdelay(200);
738
739 aup->mac->control = 0;
740 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
741 aup->tx_tail = aup->tx_head;
742 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
743
744 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
745 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
746 dev->dev_addr[1]<<8 | dev->dev_addr[0];
747
748 for (i=0; i<NUM_RX_DMA; i++) {
749 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
750 }
751
752 sync();
753 control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
754 #ifndef CONFIG_CPU_LITTLE_ENDIAN
755 control |= MAC_BIG_ENDIAN;
756 #endif
757 aup->mac->control = control;
758
759 spin_unlock_irqrestore(&aup->lock, flags);
760 return 0;
761 }
762
763 static void au1000_timer(unsigned long data)
764 {
765 struct net_device *dev = (struct net_device *)data;
766 struct au1000_private *aup = (struct au1000_private *) dev->priv;
767 u16 mii_data, link, speed;
768
769 if (!dev) {
770 /* fatal error, don't restart the timer */
771 printk(KERN_ERR "au1000_timer error: NULL dev\n");
772 return;
773 }
774 if (!(dev->flags & IFF_UP)) {
775 goto set_timer;
776 }
777
778 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
779 if (link) {
780 if (!(dev->flags & IFF_RUNNING)) {
781 netif_carrier_on(dev);
782 dev->flags |= IFF_RUNNING;
783 printk(KERN_DEBUG "%s: link up\n", dev->name);
784 }
785 }
786 else {
787 if (dev->flags & IFF_RUNNING) {
788 netif_carrier_off(dev);
789 dev->flags &= ~IFF_RUNNING;
790 dev->if_port = 0;
791 printk(KERN_DEBUG "%s: link down\n", dev->name);
792 }
793 }
794 }
795
796 set_timer:
797 aup->timer.expires = RUN_AT((1*HZ));
798 aup->timer.data = (unsigned long)dev;
799 aup->timer.function = &au1000_timer; /* timer handler */
800 add_timer(&aup->timer);
801
802 }
803
804 static int au1000_open(struct net_device *dev)
805 {
806 int retval;
807 struct au1000_private *aup = (struct au1000_private *) dev->priv;
808
809 MOD_INC_USE_COUNT;
810
811 if (au1000_debug > 4)
812 printk("%s: open: dev=%p\n", dev->name, dev);
813
814 if ((retval = au1000_init(dev))) {
815 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
816 free_irq(dev->irq, dev);
817 MOD_DEC_USE_COUNT;
818 return retval;
819 }
820 netif_start_queue(dev);
821
822 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0, dev->name, dev))) {
823 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, dev->irq);
824 MOD_DEC_USE_COUNT;
825 return retval;
826 }
827
828 aup->timer.expires = RUN_AT((3*HZ));
829 aup->timer.data = (unsigned long)dev;
830 aup->timer.function = &au1000_timer; /* timer handler */
831 add_timer(&aup->timer);
832
833 if (au1000_debug > 4)
834 printk("%s: open: Initialization done.\n", dev->name);
835
836 return 0;
837 }
838
839 static int au1000_close(struct net_device *dev)
840 {
841 u32 flags;
842 struct au1000_private *aup = (struct au1000_private *) dev->priv;
843
844 if (au1000_debug > 4)
845 printk("%s: close: dev=%p\n", dev->name, dev);
846
847 spin_lock_irqsave(&aup->lock, flags);
848
849 /* stop the device */
850 if (netif_device_present(dev)) {
851 netif_stop_queue(dev);
852 }
853
854 /* disable the interrupt */
855 free_irq(dev->irq, dev);
856 spin_unlock_irqrestore(&aup->lock, flags);
857
858 reset_mac(dev);
859 MOD_DEC_USE_COUNT;
860 return 0;
861 }
862
863
864 static inline void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
865 {
866 struct au1000_private *aup = (struct au1000_private *) dev->priv;
867 struct net_device_stats *ps = &aup->stats;
868
869 ps->tx_packets++;
870 ps->tx_bytes += pkt_len;
871
872 if (status & TX_FRAME_ABORTED) {
873 ps->tx_errors++;
874 ps->tx_aborted_errors++;
875 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
876 ps->tx_carrier_errors++;
877 }
878 }
879
880
881 /*
882 * Called from the interrupt service routine to acknowledge
883 * the TX DONE bits. This is a must if the irq is setup as
884 * edge triggered.
885 */
886 static void au1000_tx_ack(struct net_device *dev)
887 {
888 struct au1000_private *aup = (struct au1000_private *) dev->priv;
889 volatile tx_dma_t *ptxd;
890
891 ptxd = aup->tx_dma_ring[aup->tx_tail];
892
893 while (ptxd->buff_stat & TX_T_DONE) {
894 update_tx_stats(dev, ptxd->status, ptxd->len & 0x3ff);
895 ptxd->buff_stat &= ~TX_T_DONE;
896 ptxd->len = 0;
897 sync();
898
899 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
900 ptxd = aup->tx_dma_ring[aup->tx_tail];
901
902 if (aup->tx_full) {
903 aup->tx_full = 0;
904 netif_wake_queue(dev);
905 }
906 }
907 }
908
909
910 /*
911 * Au1000 transmit routine.
912 */
913 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
914 {
915 struct au1000_private *aup = (struct au1000_private *) dev->priv;
916 //unsigned long flags;
917 volatile tx_dma_t *ptxd;
918 u32 buff_stat;
919 db_dest_t *pDB;
920 int i;
921
922 if (au1000_debug > 4)
923 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
924 dev->name, (unsigned)aup, skb->len, skb->data, aup->tx_head);
925
926 /* Prevent interrupts from changing the Tx ring */
927 //spin_lock_irqsave(&aup->lock, flags);
928
929 ptxd = aup->tx_dma_ring[aup->tx_head];
930 buff_stat = ptxd->buff_stat;
931 if (buff_stat & TX_DMA_ENABLE) {
932 /* We've wrapped around and the transmitter is still busy */
933 netif_stop_queue(dev);
934 aup->tx_full = 1;
935 //spin_unlock_irqrestore(&aup->lock, flags);
936 return 1;
937 }
938 else if (buff_stat & TX_T_DONE) {
939 update_tx_stats(dev, ptxd->status, ptxd->len & 0x3ff);
940 ptxd->len = 0;
941 }
942
943 if (aup->tx_full) {
944 aup->tx_full = 0;
945 netif_wake_queue(dev);
946 }
947
948 pDB = aup->tx_db_inuse[aup->tx_head];
949 memcpy((void *)pDB->vaddr, skb->data, skb->len);
950 if (skb->len < MAC_MIN_PKT_SIZE) {
951 for (i=skb->len; i<MAC_MIN_PKT_SIZE; i++) {
952 ((char *)pDB->vaddr)[i] = 0;
953 }
954 ptxd->len = MAC_MIN_PKT_SIZE;
955 }
956 else
957 ptxd->len = skb->len;
958
959 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
960 sync();
961 dev_kfree_skb(skb);
962 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
963 dev->trans_start = jiffies;
964 //spin_unlock_irqrestore(&aup->lock, flags);
965 return 0;
966 }
967
968
969 static inline void update_rx_stats(struct net_device *dev, u32 status)
970 {
971 struct au1000_private *aup = (struct au1000_private *) dev->priv;
972 struct net_device_stats *ps = &aup->stats;
973
974 ps->rx_packets++;
975 if (status & RX_MCAST_FRAME)
976 ps->multicast++;
977
978 if (status & RX_ERROR) {
979 ps->rx_errors++;
980 if (status & RX_MISSED_FRAME)
981 ps->rx_missed_errors++;
982 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
983 ps->rx_length_errors++;
984 if (status & RX_CRC_ERROR)
985 ps->rx_crc_errors++;
986 if (status & RX_COLL)
987 ps->collisions++;
988 }
989 else
990 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
991
992 }
993
994 /*
995 * Au1000 receive routine.
996 */
997 static int au1000_rx(struct net_device *dev)
998 {
999 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1000 struct sk_buff *skb;
1001 volatile rx_dma_t *prxd;
1002 u32 buff_stat, status;
1003 db_dest_t *pDB;
1004
1005 if (au1000_debug > 4)
1006 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1007
1008 prxd = aup->rx_dma_ring[aup->rx_head];
1009 buff_stat = prxd->buff_stat;
1010 while (buff_stat & RX_T_DONE) {
1011 status = prxd->status;
1012 pDB = aup->rx_db_inuse[aup->rx_head];
1013 update_rx_stats(dev, status);
1014 if (!(status & RX_ERROR)) {
1015
1016 /* good frame */
1017 skb = dev_alloc_skb((status & RX_FRAME_LEN_MASK) + 2);
1018 if (skb == NULL) {
1019 printk(KERN_ERR
1020 "%s: Memory squeeze, dropping packet.\n",
1021 dev->name);
1022 aup->stats.rx_dropped++;
1023 continue;
1024 }
1025 skb->dev = dev;
1026 skb_reserve(skb, 2); /* 16 byte IP header align */
1027 eth_copy_and_sum(skb, (unsigned char *)pDB->vaddr,
1028 status & RX_FRAME_LEN_MASK, 0);
1029 skb_put(skb, status & RX_FRAME_LEN_MASK); /* Make room */
1030 skb->protocol = eth_type_trans(skb, dev);
1031 netif_rx(skb); /* pass the packet to upper layers */
1032 }
1033 else {
1034 if (au1000_debug > 4) {
1035 if (status & RX_MISSED_FRAME)
1036 printk("rx miss\n");
1037 if (status & RX_WDOG_TIMER)
1038 printk("rx wdog\n");
1039 if (status & RX_RUNT)
1040 printk("rx runt\n");
1041 if (status & RX_OVERLEN)
1042 printk("rx overlen\n");
1043 if (status & RX_COLL)
1044 printk("rx coll\n");
1045 if (status & RX_MII_ERROR)
1046 printk("rx mii error\n");
1047 if (status & RX_CRC_ERROR)
1048 printk("rx crc error\n");
1049 if (status & RX_LEN_ERROR)
1050 printk("rx len error\n");
1051 if (status & RX_U_CNTRL_FRAME)
1052 printk("rx u control frame\n");
1053 if (status & RX_MISSED_FRAME)
1054 printk("rx miss\n");
1055 }
1056 }
1057 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1058 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1059 sync();
1060
1061 /* next descriptor */
1062 prxd = aup->rx_dma_ring[aup->rx_head];
1063 buff_stat = prxd->buff_stat;
1064 dev->last_rx = jiffies;
1065 }
1066 return 0;
1067 }
1068
1069
1070 /*
1071 * Au1000 interrupt service routine.
1072 */
1073 void au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1074 {
1075 struct net_device *dev = (struct net_device *) dev_id;
1076
1077 if (dev == NULL) {
1078 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
1079 return;
1080 }
1081 au1000_rx(dev);
1082 au1000_tx_ack(dev);
1083 }
1084
1085
1086 /*
1087 * The Tx ring has been full longer than the watchdog timeout
1088 * value. The transmitter must be hung?
1089 */
1090 static void au1000_tx_timeout(struct net_device *dev)
1091 {
1092 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1093 reset_mac(dev);
1094 au1000_init(dev);
1095 }
1096
1097
1098 static unsigned const ethernet_polynomial = 0x04c11db7U;
1099 static inline u32 ether_crc(int length, unsigned char *data)
1100 {
1101 int crc = -1;
1102
1103 while(--length >= 0) {
1104 unsigned char current_octet = *data++;
1105 int bit;
1106 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
1107 crc = (crc << 1) ^
1108 ((crc < 0) ^ (current_octet & 1) ? ethernet_polynomial : 0);
1109 }
1110 return crc;
1111 }
1112
1113 static void set_rx_mode(struct net_device *dev)
1114 {
1115 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1116
1117 /* fixme */
1118 if (au1000_debug > 4)
1119 printk("%s: set_multicast: flags=%x\n", dev->name, dev->flags);
1120
1121 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1122 aup->mac->control |= MAC_PROMISCUOUS;
1123 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1124 } else if ((dev->flags & IFF_ALLMULTI) ||
1125 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1126 aup->mac->control |= MAC_PASS_ALL_MULTI;
1127 aup->mac->control &= ~MAC_PROMISCUOUS;
1128 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1129 } else {
1130 int i;
1131 struct dev_mc_list *mclist;
1132 u32 mc_filter[2]; /* Multicast hash filter */
1133
1134 mc_filter[1] = mc_filter[0] = 0;
1135 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1136 i++, mclist = mclist->next) {
1137 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26, mc_filter);
1138 }
1139 aup->mac->multi_hash_high = mc_filter[1];
1140 aup->mac->multi_hash_low = mc_filter[0];
1141 aup->mac->control |= MAC_HASH_MODE;
1142 }
1143 }
1144
1145
1146 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1147 {
1148 //struct au1000_private *aup = (struct au1000_private *) dev->priv;
1149 u16 *data = (u16 *)&rq->ifr_data;
1150
1151 /* fixme */
1152 switch(cmd) {
1153 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1154 data[0] = PHY_ADDRESS;
1155 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1156 //data[3] = mdio_read(ioaddr, data[0], data[1]);
1157 return 0;
1158 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1159 //mdio_write(ioaddr, data[0], data[1], data[2]);
1160 return 0;
1161 default:
1162 return -EOPNOTSUPP;
1163 }
1164 }
1165
1166
1167 static int au1000_set_config(struct net_device *dev, struct ifmap *map)
1168 {
1169 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1170 u16 control;
1171
1172 if (au1000_debug > 4) {
1173 printk("%s: set_config called: dev->if_port %d map->port %x\n",
1174 dev->name, dev->if_port, map->port);
1175 }
1176
1177 switch(map->port){
1178 case IF_PORT_UNKNOWN: /* use auto here */
1179 printk("auto\\n");
1180 dev->if_port = map->port;
1181 /* Link Down: the timer will bring it up */
1182 netif_carrier_off(dev);
1183
1184 /* read current control */
1185 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1186 control &= ~(MII_CNTL_FDX | MII_CNTL_F100);
1187
1188 /* enable auto negotiation and reset the negotiation */
1189 mdio_write(dev, aup->phy_addr,
1190 MII_CONTROL, control | MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1191
1192 break;
1193
1194 case IF_PORT_10BASET: /* 10BaseT */
1195 printk("10baseT\n");
1196 dev->if_port = map->port;
1197
1198 /* Link Down: the timer will bring it up */
1199 netif_carrier_off(dev);
1200
1201 /* set Speed to 10Mbps, Half Duplex */
1202 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1203 printk("read control %x\n", control);
1204 control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_FDX);
1205
1206 /* disable auto negotiation and force 10M/HD mode*/
1207 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1208 break;
1209
1210 case IF_PORT_100BASET: /* 100BaseT */
1211 case IF_PORT_100BASETX: /* 100BaseTx */
1212 printk("100 base T/TX\n");
1213 dev->if_port = map->port;
1214
1215 /* Link Down: the timer will bring it up */
1216 netif_carrier_off(dev);
1217
1218 /* set Speed to 100Mbps, Half Duplex */
1219 /* disable auto negotiation and enable 100MBit Mode */
1220 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1221 printk("read control %x\n", control);
1222 control &= ~(MII_CNTL_AUTO | MII_CNTL_FDX);
1223 control |= MII_CNTL_F100;
1224 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1225 break;
1226
1227 case IF_PORT_100BASEFX: /* 100BaseFx */
1228 printk("100 Base FX\n");
1229 dev->if_port = map->port;
1230
1231 /* Link Down: the timer will bring it up */
1232 netif_carrier_off(dev);
1233
1234 /* set Speed to 100Mbps, Full Duplex */
1235 /* disable auto negotiation and enable 100MBit Mode */
1236 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1237 control &= ~MII_CNTL_AUTO;
1238 control |= MII_CNTL_F100 | MII_CNTL_FDX;
1239 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1240 break;
1241 case IF_PORT_10BASE2: /* 10Base2 */
1242 case IF_PORT_AUI: /* AUI */
1243 /* These Modes are not supported (are they?)*/
1244 printk(KERN_INFO "Not supported");
1245 return -EOPNOTSUPP;
1246 break;
1247
1248 default:
1249 printk("Invalid");
1250 return -EINVAL;
1251 }
1252 return 0;
1253 }
1254
1255 static struct net_device_stats *au1000_get_stats(struct net_device *dev)
1256 {
1257 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1258
1259 if (au1000_debug > 4)
1260 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
1261
1262 if (netif_device_present(dev)) {
1263 return &aup->stats;
1264 }
1265 return 0;
1266 }
1267