File: /usr/src/linux/drivers/net/de4x5.c
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 =========================================================================
440 */
441
442 static const char *version = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
443
444 #include <linux/config.h>
445 #include <linux/module.h>
446
447 #include <linux/kernel.h>
448 #include <linux/sched.h>
449 #include <linux/string.h>
450 #include <linux/interrupt.h>
451 #include <linux/ptrace.h>
452 #include <linux/errno.h>
453 #include <linux/ioport.h>
454 #include <linux/slab.h>
455 #include <linux/pci.h>
456 #include <linux/delay.h>
457 #include <linux/init.h>
458 #include <linux/version.h>
459 #include <linux/spinlock.h>
460
461 #include <asm/bitops.h>
462 #include <asm/io.h>
463 #include <asm/dma.h>
464 #include <asm/byteorder.h>
465 #include <asm/unaligned.h>
466 #include <asm/uaccess.h>
467 #ifdef CONFIG_PPC
468 #include <asm/machdep.h>
469 #endif /* CONFIG_PPC */
470
471 #include <linux/netdevice.h>
472 #include <linux/etherdevice.h>
473 #include <linux/skbuff.h>
474
475 #include <linux/time.h>
476 #include <linux/types.h>
477 #include <linux/unistd.h>
478 #include <linux/ctype.h>
479
480 #include "de4x5.h"
481
482 #define c_char const char
483 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
484
485 /*
486 ** MII Information
487 */
488 struct phy_table {
489 int reset; /* Hard reset required? */
490 int id; /* IEEE OUI */
491 int ta; /* One cycle TA time - 802.3u is confusing here */
492 struct { /* Non autonegotiation (parallel) speed det. */
493 int reg;
494 int mask;
495 int value;
496 } spd;
497 };
498
499 struct mii_phy {
500 int reset; /* Hard reset required? */
501 int id; /* IEEE OUI */
502 int ta; /* One cycle TA time */
503 struct { /* Non autonegotiation (parallel) speed det. */
504 int reg;
505 int mask;
506 int value;
507 } spd;
508 int addr; /* MII address for the PHY */
509 u_char *gep; /* Start of GEP sequence block in SROM */
510 u_char *rst; /* Start of reset sequence in SROM */
511 u_int mc; /* Media Capabilities */
512 u_int ana; /* NWay Advertisement */
513 u_int fdx; /* Full DupleX capabilites for each media */
514 u_int ttm; /* Transmit Threshold Mode for each media */
515 u_int mci; /* 21142 MII Connector Interrupt info */
516 };
517
518 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
519
520 struct sia_phy {
521 u_char mc; /* Media Code */
522 u_char ext; /* csr13-15 valid when set */
523 int csr13; /* SIA Connectivity Register */
524 int csr14; /* SIA TX/RX Register */
525 int csr15; /* SIA General Register */
526 int gepc; /* SIA GEP Control Information */
527 int gep; /* SIA GEP Data */
528 };
529
530 /*
531 ** Define the know universe of PHY devices that can be
532 ** recognised by this driver.
533 */
534 static struct phy_table phy_info[] = {
535 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
536 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
537 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
538 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
539 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
540 };
541
542 /*
543 ** These GENERIC values assumes that the PHY devices follow 802.3u and
544 ** allow parallel detection to set the link partner ability register.
545 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
546 */
547 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
548 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
549 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
550
551 /*
552 ** Define special SROM detection cases
553 */
554 static c_char enet_det[][ETH_ALEN] = {
555 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
556 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
557 };
558
559 #define SMC 1
560 #define ACCTON 2
561
562 /*
563 ** SROM Repair definitions. If a broken SROM is detected a card may
564 ** use this information to help figure out what to do. This is a
565 ** "stab in the dark" and so far for SMC9332's only.
566 */
567 static c_char srom_repair_info[][100] = {
568 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
569 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
570 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
571 0x00,0x18,}
572 };
573
574
575 #ifdef DE4X5_DEBUG
576 static int de4x5_debug = DE4X5_DEBUG;
577 #else
578 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
579 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
580 #endif
581
582 /*
583 ** Allow per adapter set up. For modules this is simply a command line
584 ** parameter, e.g.:
585 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
586 **
587 ** For a compiled in driver, place e.g.
588 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
589 ** here
590 */
591 #ifdef DE4X5_PARM
592 static char *args = DE4X5_PARM;
593 #else
594 static char *args;
595 #endif
596
597 struct parameters {
598 int fdx;
599 int autosense;
600 };
601
602 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
603
604 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
605
606 /*
607 ** Ethernet PROM defines
608 */
609 #define PROBE_LENGTH 32
610 #define ETH_PROM_SIG 0xAA5500FFUL
611
612 /*
613 ** Ethernet Info
614 */
615 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
616 #define IEEE802_3_SZ 1518 /* Packet + CRC */
617 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
618 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
619 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
620 #define PKT_HDR_LEN 14 /* Addresses and data length info */
621 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
622 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
623
624
625 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
626 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
627
628 /*
629 ** EISA bus defines
630 */
631 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
632 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
633
634 #define MAX_EISA_SLOTS 16
635 #define EISA_SLOT_INC 0x1000
636 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
637
638 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
639 #define DE4X5_NAME_LENGTH 8
640
641 /*
642 ** Ethernet PROM defines for DC21040
643 */
644 #define PROBE_LENGTH 32
645 #define ETH_PROM_SIG 0xAA5500FFUL
646
647 /*
648 ** PCI Bus defines
649 */
650 #define PCI_MAX_BUS_NUM 8
651 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
652 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
653 #define NO_MORE_PCI -2 /* PCI bus search all done */
654
655 /*
656 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
657 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
658 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
659 ** and hence the RX descriptor ring's first entry.
660 */
661 #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
662 #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
663 #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
664 #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
665 #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
666 #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
667
668 #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
669 #define CACHE_ALIGN CAL_16LONG
670 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
671 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
672 #define DESC_ALIGN
673
674 #ifndef DEC_ONLY /* See README.de4x5 for using this */
675 static int dec_only;
676 #else
677 static int dec_only = 1;
678 #endif
679
680 /*
681 ** DE4X5 IRQ ENABLE/DISABLE
682 */
683 #define ENABLE_IRQs { \
684 imr |= lp->irq_en;\
685 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
686 }
687
688 #define DISABLE_IRQs {\
689 imr = inl(DE4X5_IMR);\
690 imr &= ~lp->irq_en;\
691 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
692 }
693
694 #define UNMASK_IRQs {\
695 imr |= lp->irq_mask;\
696 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
697 }
698
699 #define MASK_IRQs {\
700 imr = inl(DE4X5_IMR);\
701 imr &= ~lp->irq_mask;\
702 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
703 }
704
705 /*
706 ** DE4X5 START/STOP
707 */
708 #define START_DE4X5 {\
709 omr = inl(DE4X5_OMR);\
710 omr |= OMR_ST | OMR_SR;\
711 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
712 }
713
714 #define STOP_DE4X5 {\
715 omr = inl(DE4X5_OMR);\
716 omr &= ~(OMR_ST|OMR_SR);\
717 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
718 }
719
720 /*
721 ** DE4X5 SIA RESET
722 */
723 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
724
725 /*
726 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
727 */
728 #define DE4X5_AUTOSENSE_MS 250
729
730 /*
731 ** SROM Structure
732 */
733 struct de4x5_srom {
734 char sub_vendor_id[2];
735 char sub_system_id[2];
736 char reserved[12];
737 char id_block_crc;
738 char reserved2;
739 char version;
740 char num_controllers;
741 char ieee_addr[6];
742 char info[100];
743 short chksum;
744 };
745 #define SUB_VENDOR_ID 0x500a
746
747 /*
748 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
749 ** and have sizes of both a power of 2 and a multiple of 4.
750 ** A size of 256 bytes for each buffer could be chosen because over 90% of
751 ** all packets in our network are <256 bytes long and 64 longword alignment
752 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
753 ** descriptors are needed for machines with an ALPHA CPU.
754 */
755 #define NUM_RX_DESC 8 /* Number of RX descriptors */
756 #define NUM_TX_DESC 32 /* Number of TX descriptors */
757 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
758 /* Multiple of 4 for DC21040 */
759 /* Allows 512 byte alignment */
760 struct de4x5_desc {
761 volatile s32 status;
762 u32 des1;
763 u32 buf;
764 u32 next;
765 DESC_ALIGN
766 };
767
768 /*
769 ** The DE4X5 private structure
770 */
771 #define DE4X5_PKT_STAT_SZ 16
772 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
773 increase DE4X5_PKT_STAT_SZ */
774
775 struct pkt_stats {
776 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
777 u_int unicast;
778 u_int multicast;
779 u_int broadcast;
780 u_int excessive_collisions;
781 u_int tx_underruns;
782 u_int excessive_underruns;
783 u_int rx_runt_frames;
784 u_int rx_collision;
785 u_int rx_dribble;
786 u_int rx_overflow;
787 };
788
789 struct de4x5_private {
790 char adapter_name[80]; /* Adapter name */
791 u_long interrupt; /* Aligned ISR flag */
792 struct de4x5_desc *rx_ring; /* RX descriptor ring */
793 struct de4x5_desc *tx_ring; /* TX descriptor ring */
794 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
795 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
796 int rx_new, rx_old; /* RX descriptor ring pointers */
797 int tx_new, tx_old; /* TX descriptor ring pointers */
798 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
799 char frame[64]; /* Min sized packet for loopback*/
800 spinlock_t lock; /* Adapter specific spinlock */
801 struct net_device_stats stats; /* Public stats */
802 struct pkt_stats pktStats; /* Private stats counters */
803 char rxRingSize;
804 char txRingSize;
805 int bus; /* EISA or PCI */
806 int bus_num; /* PCI Bus number */
807 int device; /* Device number on PCI bus */
808 int state; /* Adapter OPENED or CLOSED */
809 int chipset; /* DC21040, DC21041 or DC21140 */
810 s32 irq_mask; /* Interrupt Mask (Enable) bits */
811 s32 irq_en; /* Summary interrupt bits */
812 int media; /* Media (eg TP), mode (eg 100B)*/
813 int c_media; /* Remember the last media conn */
814 int fdx; /* media full duplex flag */
815 int linkOK; /* Link is OK */
816 int autosense; /* Allow/disallow autosensing */
817 int tx_enable; /* Enable descriptor polling */
818 int setup_f; /* Setup frame filtering type */
819 int local_state; /* State within a 'media' state */
820 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
821 struct sia_phy sia; /* SIA PHY Information */
822 int active; /* Index to active PHY device */
823 int mii_cnt; /* Number of attached PHY's */
824 int timeout; /* Scheduling counter */
825 struct timer_list timer; /* Timer info for kernel */
826 int tmp; /* Temporary global per card */
827 struct {
828 void *priv; /* Original kmalloc'd mem addr */
829 u_long lock; /* Lock the cache accesses */
830 s32 csr0; /* Saved Bus Mode Register */
831 s32 csr6; /* Saved Operating Mode Reg. */
832 s32 csr7; /* Saved IRQ Mask Register */
833 s32 gep; /* Saved General Purpose Reg. */
834 s32 gepc; /* Control info for GEP */
835 s32 csr13; /* Saved SIA Connectivity Reg. */
836 s32 csr14; /* Saved SIA TX/RX Register */
837 s32 csr15; /* Saved SIA General Register */
838 int save_cnt; /* Flag if state already saved */
839 struct sk_buff *skb; /* Save the (re-ordered) skb's */
840 } cache;
841 struct de4x5_srom srom; /* A copy of the SROM */
842 struct net_device *next_module; /* Link to the next module */
843 int rx_ovf; /* Check for 'RX overflow' tag */
844 int useSROM; /* For non-DEC card use SROM */
845 int useMII; /* Infoblock using the MII */
846 int asBitValid; /* Autosense bits in GEP? */
847 int asPolarity; /* 0 => asserted high */
848 int asBit; /* Autosense bit number in GEP */
849 int defMedium; /* SROM default medium */
850 int tcount; /* Last infoblock number */
851 int infoblock_init; /* Initialised this infoblock? */
852 int infoleaf_offset; /* SROM infoleaf for controller */
853 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
854 int infoblock_media; /* infoblock media */
855 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
856 u_char *rst; /* Pointer to Type 5 reset info */
857 u_char ibn; /* Infoblock number */
858 struct parameters params; /* Command line/ #defined params */
859 struct pci_dev *pdev; /* Device cookie for DMA alloc */
860 dma_addr_t dma_rings; /* DMA handle for rings */
861 int dma_size; /* Size of the DMA area */
862 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
863 };
864
865 /*
866 ** Kludge to get around the fact that the CSR addresses have different
867 ** offsets in the PCI and EISA boards. Also note that the ethernet address
868 ** PROM is accessed differently.
869 */
870 static struct bus_type {
871 int bus;
872 int bus_num;
873 int device;
874 int chipset;
875 struct de4x5_srom srom;
876 int autosense;
877 int useSROM;
878 } bus;
879
880 /*
881 ** To get around certain poxy cards that don't provide an SROM
882 ** for the second and more DECchip, I have to key off the first
883 ** chip's address. I'll assume there's not a bad SROM iff:
884 **
885 ** o the chipset is the same
886 ** o the bus number is the same and > 0
887 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
888 **
889 ** Also have to save the irq for those cards whose hardware designers
890 ** can't follow the PCI to PCI Bridge Architecture spec.
891 */
892 static struct {
893 int chipset;
894 int bus;
895 int irq;
896 u_char addr[ETH_ALEN];
897 } last = {0,};
898
899 /*
900 ** The transmit ring full condition is described by the tx_old and tx_new
901 ** pointers by:
902 ** tx_old = tx_new Empty ring
903 ** tx_old = tx_new+1 Full ring
904 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
905 */
906 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
907 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
908 lp->tx_old -lp->tx_new-1)
909
910 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
911
912 /*
913 ** Public Functions
914 */
915 static int de4x5_open(struct net_device *dev);
916 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
917 static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
918 static int de4x5_close(struct net_device *dev);
919 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
920 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
921 static void set_multicast_list(struct net_device *dev);
922 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
923
924 /*
925 ** Private functions
926 */
927 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct pci_dev *pdev);
928 static int de4x5_init(struct net_device *dev);
929 static int de4x5_sw_reset(struct net_device *dev);
930 static int de4x5_rx(struct net_device *dev);
931 static int de4x5_tx(struct net_device *dev);
932 static int de4x5_ast(struct net_device *dev);
933 static int de4x5_txur(struct net_device *dev);
934 static int de4x5_rx_ovfc(struct net_device *dev);
935
936 static int autoconf_media(struct net_device *dev);
937 static void create_packet(struct net_device *dev, char *frame, int len);
938 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
939 static int dc21040_autoconf(struct net_device *dev);
940 static int dc21041_autoconf(struct net_device *dev);
941 static int dc21140m_autoconf(struct net_device *dev);
942 static int dc2114x_autoconf(struct net_device *dev);
943 static int srom_autoconf(struct net_device *dev);
944 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
945 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
946 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
947 static int test_for_100Mb(struct net_device *dev, int msec);
948 static int wait_for_link(struct net_device *dev);
949 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
950 static int is_spd_100(struct net_device *dev);
951 static int is_100_up(struct net_device *dev);
952 static int is_10_up(struct net_device *dev);
953 static int is_anc_capable(struct net_device *dev);
954 static int ping_media(struct net_device *dev, int msec);
955 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
956 static void de4x5_free_rx_buffs(struct net_device *dev);
957 static void de4x5_free_tx_buffs(struct net_device *dev);
958 static void de4x5_save_skbs(struct net_device *dev);
959 static void de4x5_rst_desc_ring(struct net_device *dev);
960 static void de4x5_cache_state(struct net_device *dev, int flag);
961 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
962 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
963 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
964 static void de4x5_setup_intr(struct net_device *dev);
965 static void de4x5_init_connection(struct net_device *dev);
966 static int de4x5_reset_phy(struct net_device *dev);
967 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
968 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
969 static int test_tp(struct net_device *dev, s32 msec);
970 static int EISA_signature(char *name, s32 eisa_id);
971 static int PCI_signature(char *name, struct bus_type *lp);
972 static void DevicePresent(u_long iobase);
973 static void enet_addr_rst(u_long aprom_addr);
974 static int de4x5_bad_srom(struct bus_type *lp);
975 static short srom_rd(u_long address, u_char offset);
976 static void srom_latch(u_int command, u_long address);
977 static void srom_command(u_int command, u_long address);
978 static void srom_address(u_int command, u_long address, u_char offset);
979 static short srom_data(u_int command, u_long address);
980 /*static void srom_busy(u_int command, u_long address);*/
981 static void sendto_srom(u_int command, u_long addr);
982 static int getfrom_srom(u_long addr);
983 static int srom_map_media(struct net_device *dev);
984 static int srom_infoleaf_info(struct net_device *dev);
985 static void srom_init(struct net_device *dev);
986 static void srom_exec(struct net_device *dev, u_char *p);
987 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
988 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
989 static int mii_rdata(u_long ioaddr);
990 static void mii_wdata(int data, int len, u_long ioaddr);
991 static void mii_ta(u_long rw, u_long ioaddr);
992 static int mii_swap(int data, int len);
993 static void mii_address(u_char addr, u_long ioaddr);
994 static void sendto_mii(u32 command, int data, u_long ioaddr);
995 static int getfrom_mii(u32 command, u_long ioaddr);
996 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
997 static int mii_get_phy(struct net_device *dev);
998 static void SetMulticastFilter(struct net_device *dev);
999 static int get_hw_addr(struct net_device *dev);
1000 static void srom_repair(struct net_device *dev, int card);
1001 static int test_bad_enet(struct net_device *dev, int status);
1002 static int an_exception(struct bus_type *lp);
1003 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1004 static void eisa_probe(struct net_device *dev, u_long iobase);
1005 #endif
1006 static void pci_probe(struct net_device *dev, u_long iobase);
1007 static void srom_search(struct pci_dev *pdev);
1008 static char *build_setup_frame(struct net_device *dev, int mode);
1009 static void disable_ast(struct net_device *dev);
1010 static void enable_ast(struct net_device *dev, u32 time_out);
1011 static long de4x5_switch_mac_port(struct net_device *dev);
1012 static int gep_rd(struct net_device *dev);
1013 static void gep_wr(s32 data, struct net_device *dev);
1014 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
1015 static void yawn(struct net_device *dev, int state);
1016 static void link_modules(struct net_device *dev, struct net_device *tmp);
1017 static void de4x5_parse_params(struct net_device *dev);
1018 static void de4x5_dbg_open(struct net_device *dev);
1019 static void de4x5_dbg_mii(struct net_device *dev, int k);
1020 static void de4x5_dbg_media(struct net_device *dev);
1021 static void de4x5_dbg_srom(struct de4x5_srom *p);
1022 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1023 static int de4x5_strncmp(char *a, char *b, int n);
1024 static int dc21041_infoleaf(struct net_device *dev);
1025 static int dc21140_infoleaf(struct net_device *dev);
1026 static int dc21142_infoleaf(struct net_device *dev);
1027 static int dc21143_infoleaf(struct net_device *dev);
1028 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1029 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1030 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1031 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1032 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1033 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1034 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1035
1036 #ifdef MODULE
1037 int init_module(void);
1038 void cleanup_module(void);
1039 static struct net_device *unlink_modules(struct net_device *p);
1040 static struct net_device *insert_device(struct net_device *dev, u_long iobase,
1041 int (*init)(struct net_device *));
1042 static int count_adapters(void);
1043 static int loading_module = 1;
1044 MODULE_PARM(de4x5_debug, "i");
1045 MODULE_PARM(dec_only, "i");
1046 MODULE_PARM(args, "s");
1047 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1048 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1049 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1050 # else
1051 static int loading_module;
1052 #endif /* MODULE */
1053
1054 static char name[DE4X5_NAME_LENGTH + 1];
1055 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1056 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1057 static int lastEISA;
1058 # ifdef DE4X5_FORCE_EISA /* Force an EISA bus probe or not */
1059 static int forceEISA = 1;
1060 # else
1061 static int forceEISA;
1062 # endif
1063 #endif
1064 static int num_de4x5s;
1065 static int cfrv, useSROM;
1066 static int lastPCI = -1;
1067 static struct net_device *lastModule;
1068 static struct pci_dev *pdev;
1069
1070 /*
1071 ** List the SROM infoleaf functions and chipsets
1072 */
1073 struct InfoLeaf {
1074 int chipset;
1075 int (*fn)(struct net_device *);
1076 };
1077 static struct InfoLeaf infoleaf_array[] = {
1078 {DC21041, dc21041_infoleaf},
1079 {DC21140, dc21140_infoleaf},
1080 {DC21142, dc21142_infoleaf},
1081 {DC21143, dc21143_infoleaf}
1082 };
1083 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1084
1085 /*
1086 ** List the SROM info block functions
1087 */
1088 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1089 type0_infoblock,
1090 type1_infoblock,
1091 type2_infoblock,
1092 type3_infoblock,
1093 type4_infoblock,
1094 type5_infoblock,
1095 compact_infoblock
1096 };
1097
1098 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1099
1100 /*
1101 ** Miscellaneous defines...
1102 */
1103 #define RESET_DE4X5 {\
1104 int i;\
1105 i=inl(DE4X5_BMR);\
1106 mdelay(1);\
1107 outl(i | BMR_SWR, DE4X5_BMR);\
1108 mdelay(1);\
1109 outl(i, DE4X5_BMR);\
1110 mdelay(1);\
1111 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1112 mdelay(1);\
1113 }
1114
1115 #define PHY_HARD_RESET {\
1116 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1117 mdelay(1); /* Assert for 1ms */\
1118 outl(0x00, DE4X5_GEP);\
1119 mdelay(2); /* Wait for 2ms */\
1120 }
1121
1122
1123 /*
1124 ** Autoprobing in modules is allowed here. See the top of the file for
1125 ** more info.
1126 */
1127 int __init
1128 de4x5_probe(struct net_device *dev)
1129 {
1130 u_long iobase = dev->base_addr;
1131
1132 pci_probe(dev, iobase);
1133 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1134 if ((lastPCI == NO_MORE_PCI) && ((num_de4x5s == 0) || forceEISA)) {
1135 eisa_probe(dev, iobase);
1136 }
1137 #endif
1138
1139 return (dev->priv ? 0 : -ENODEV);
1140 }
1141
1142 static int __init
1143 de4x5_hw_init(struct net_device *dev, u_long iobase, struct pci_dev *pdev)
1144 {
1145 struct bus_type *lp = &bus;
1146 int i, status=0;
1147 char *tmp;
1148
1149 /* Ensure we're not sleeping */
1150 if (lp->bus == EISA) {
1151 outb(WAKEUP, PCI_CFPM);
1152 } else {
1153 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1154 PCI_CFDA_PSM, WAKEUP);
1155 }
1156 mdelay(10);
1157
1158 RESET_DE4X5;
1159
1160 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1161 return -ENXIO; /* Hardware could not reset */
1162 }
1163
1164 /*
1165 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1166 */
1167 useSROM = FALSE;
1168 if (lp->bus == PCI) {
1169 PCI_signature(name, lp);
1170 } else {
1171 EISA_signature(name, EISA_ID0);
1172 }
1173
1174 if (*name == '\0') { /* Not found a board signature */
1175 return -ENXIO;
1176 }
1177
1178 dev->base_addr = iobase;
1179 if (lp->bus == EISA) {
1180 printk("%s: %s at 0x%04lx (EISA slot %ld)",
1181 dev->name, name, iobase, ((iobase>>12)&0x0f));
1182 } else { /* PCI port address */
1183 printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1184 iobase, lp->bus_num, lp->device);
1185 }
1186
1187 printk(", h/w address ");
1188 status = get_hw_addr(dev);
1189 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1190 printk("%2.2x:", dev->dev_addr[i]);
1191 }
1192 printk("%2.2x,\n", dev->dev_addr[i]);
1193
1194 if (status != 0) {
1195 printk(" which has an Ethernet PROM CRC error.\n");
1196 return -ENXIO;
1197 } else {
1198 struct de4x5_private *lp;
1199
1200 /*
1201 ** Reserve a section of kernel memory for the adapter
1202 ** private area and the TX/RX descriptor rings.
1203 */
1204 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1205 GFP_KERNEL);
1206 if (dev->priv == NULL) {
1207 return -ENOMEM;
1208 }
1209
1210 /*
1211 ** Align to a longword boundary
1212 */
1213 tmp = dev->priv;
1214 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1215 lp = (struct de4x5_private *)dev->priv;
1216 memset(dev->priv, 0, sizeof(struct de4x5_private));
1217 lp->bus = bus.bus;
1218 lp->bus_num = bus.bus_num;
1219 lp->device = bus.device;
1220 lp->chipset = bus.chipset;
1221 lp->cache.priv = tmp;
1222 lp->cache.gepc = GEP_INIT;
1223 lp->asBit = GEP_SLNK;
1224 lp->asPolarity = GEP_SLNK;
1225 lp->asBitValid = TRUE;
1226 lp->timeout = -1;
1227 lp->useSROM = useSROM;
1228 lp->pdev = pdev;
1229 memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1230 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1231 de4x5_parse_params(dev);
1232
1233 /*
1234 ** Choose correct autosensing in case someone messed up
1235 */
1236 lp->autosense = lp->params.autosense;
1237 if (lp->chipset != DC21140) {
1238 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1239 lp->params.autosense = TP;
1240 }
1241 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1242 lp->params.autosense = BNC;
1243 }
1244 }
1245 lp->fdx = lp->params.fdx;
1246 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1247
1248 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1249 #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1250 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + ALIGN;
1251 #endif
1252 lp->rx_ring = pci_alloc_consistent(pdev, lp->dma_size, &lp->dma_rings);
1253 if (lp->rx_ring == NULL) {
1254 kfree(lp->cache.priv);
1255 lp->cache.priv = NULL;
1256 return -ENOMEM;
1257 }
1258
1259 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1260
1261 /*
1262 ** Set up the RX descriptor ring (Intels)
1263 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1264 */
1265 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1266 for (i=0; i<NUM_RX_DESC; i++) {
1267 lp->rx_ring[i].status = 0;
1268 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1269 lp->rx_ring[i].buf = 0;
1270 lp->rx_ring[i].next = 0;
1271 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1272 }
1273
1274 #else
1275 {
1276 dma_addr_t dma_rx_bufs;
1277
1278 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1279 * sizeof(struct de4x5_desc);
1280 dma_rx_bufs = (dma_rx_bufs + ALIGN) & ~ALIGN;
1281 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1282 + NUM_TX_DESC) + ALIGN) & ~ALIGN);
1283 for (i=0; i<NUM_RX_DESC; i++) {
1284 lp->rx_ring[i].status = 0;
1285 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1286 lp->rx_ring[i].buf =
1287 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1288 lp->rx_ring[i].next = 0;
1289 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1290 }
1291
1292 }
1293 #endif
1294
1295 barrier();
1296
1297 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1298 DE4X5_EISA_TOTAL_SIZE),
1299 lp->adapter_name);
1300
1301 lp->rxRingSize = NUM_RX_DESC;
1302 lp->txRingSize = NUM_TX_DESC;
1303
1304 /* Write the end of list marker to the descriptor lists */
1305 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1306 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1307
1308 /* Tell the adapter where the TX/RX rings are located. */
1309 outl(lp->dma_rings, DE4X5_RRBA);
1310 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1311 DE4X5_TRBA);
1312
1313 /* Initialise the IRQ mask and Enable/Disable */
1314 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1315 lp->irq_en = IMR_NIM | IMR_AIM;
1316
1317 /* Create a loopback packet frame for later media probing */
1318 create_packet(dev, lp->frame, sizeof(lp->frame));
1319
1320 /* Check if the RX overflow bug needs testing for */
1321 i = cfrv & 0x000000fe;
1322 if ((lp->chipset == DC21140) && (i == 0x20)) {
1323 lp->rx_ovf = 1;
1324 }
1325
1326 /* Initialise the SROM pointers if possible */
1327 if (lp->useSROM) {
1328 lp->state = INITIALISED;
1329 if (srom_infoleaf_info(dev)) {
1330 return -ENXIO;
1331 }
1332 srom_init(dev);
1333 }
1334
1335 lp->state = CLOSED;
1336
1337 /*
1338 ** Check for an MII interface
1339 */
1340 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1341 mii_get_phy(dev);
1342 }
1343
1344 #ifndef __sparc_v9__
1345 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1346 #else
1347 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1348 #endif
1349 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1350 }
1351
1352 if (de4x5_debug & DEBUG_VERSION) {
1353 printk(version);
1354 }
1355
1356 /* The DE4X5-specific entries in the device structure. */
1357 dev->open = &de4x5_open;
1358 dev->hard_start_xmit = &de4x5_queue_pkt;
1359 dev->stop = &de4x5_close;
1360 dev->get_stats = &de4x5_get_stats;
1361 dev->set_multicast_list = &set_multicast_list;
1362 dev->do_ioctl = &de4x5_ioctl;
1363
1364 dev->mem_start = 0;
1365
1366 /* Fill in the generic fields of the device structure. */
1367 ether_setup(dev);
1368
1369 /* Let the adapter sleep to save power */
1370 yawn(dev, SLEEP);
1371
1372 return status;
1373 }
1374
1375
1376 static int
1377 de4x5_open(struct net_device *dev)
1378 {
1379 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1380 u_long iobase = dev->base_addr;
1381 int i, status = 0;
1382 s32 omr;
1383
1384 /* Allocate the RX buffers */
1385 for (i=0; i<lp->rxRingSize; i++) {
1386 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1387 de4x5_free_rx_buffs(dev);
1388 return -EAGAIN;
1389 }
1390 }
1391
1392 /*
1393 ** Wake up the adapter
1394 */
1395 yawn(dev, WAKEUP);
1396
1397 /*
1398 ** Re-initialize the DE4X5...
1399 */
1400 status = de4x5_init(dev);
1401 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1402 lp->state = OPEN;
1403 de4x5_dbg_open(dev);
1404
1405 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1406 lp->adapter_name, dev)) {
1407 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1408 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1409 lp->adapter_name, dev)) {
1410 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1411 disable_ast(dev);
1412 de4x5_free_rx_buffs(dev);
1413 de4x5_free_tx_buffs(dev);
1414 yawn(dev, SLEEP);
1415 lp->state = CLOSED;
1416 return -EAGAIN;
1417 } else {
1418 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1419 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1420 }
1421 }
1422
1423 lp->interrupt = UNMASK_INTERRUPTS;
1424 dev->trans_start = jiffies;
1425
1426 START_DE4X5;
1427
1428 de4x5_setup_intr(dev);
1429
1430 if (de4x5_debug & DEBUG_OPEN) {
1431 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1432 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1433 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1434 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1435 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1436 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1437 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1438 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1439 }
1440
1441 MOD_INC_USE_COUNT;
1442
1443 return status;
1444 }
1445
1446 /*
1447 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1448 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1449 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1450 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1451 ** to be data corruption problems if it is larger (UDP errors seen from a
1452 ** ttcp source).
1453 */
1454 static int
1455 de4x5_init(struct net_device *dev)
1456 {
1457 /* Lock out other processes whilst setting up the hardware */
1458 netif_stop_queue(dev);
1459
1460 de4x5_sw_reset(dev);
1461
1462 /* Autoconfigure the connected port */
1463 autoconf_media(dev);
1464
1465 return 0;
1466 }
1467
1468 static int
1469 de4x5_sw_reset(struct net_device *dev)
1470 {
1471 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1472 u_long iobase = dev->base_addr;
1473 int i, j, status = 0;
1474 s32 bmr, omr;
1475
1476 /* Select the MII or SRL port now and RESET the MAC */
1477 if (!lp->useSROM) {
1478 if (lp->phy[lp->active].id != 0) {
1479 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1480 } else {
1481 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1482 }
1483 de4x5_switch_mac_port(dev);
1484 }
1485
1486 /*
1487 ** Set the programmable burst length to 8 longwords for all the DC21140
1488 ** Fasternet chips and 4 longwords for all others: DMA errors result
1489 ** without these values. Cache align 16 long.
1490 */
1491 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1492 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1493 outl(bmr, DE4X5_BMR);
1494
1495 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1496 if (lp->chipset == DC21140) {
1497 omr |= (OMR_SDP | OMR_SB);
1498 }
1499 lp->setup_f = PERFECT;
1500 outl(lp->dma_rings, DE4X5_RRBA);
1501 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1502 DE4X5_TRBA);
1503
1504 lp->rx_new = lp->rx_old = 0;
1505 lp->tx_new = lp->tx_old = 0;
1506
1507 for (i = 0; i < lp->rxRingSize; i++) {
1508 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1509 }
1510
1511 for (i = 0; i < lp->txRingSize; i++) {
1512 lp->tx_ring[i].status = cpu_to_le32(0);
1513 }
1514
1515 barrier();
1516
1517 /* Build the setup frame depending on filtering mode */
1518 SetMulticastFilter(dev);
1519
1520 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1521 outl(omr|OMR_ST, DE4X5_OMR);
1522
1523 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1524 sti(); /* Ensure timer interrupts */
1525 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1526 mdelay(1);
1527 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1528 }
1529 outl(omr, DE4X5_OMR); /* Stop everything! */
1530
1531 if (j == 0) {
1532 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1533 inl(DE4X5_STS));
1534 status = -EIO;
1535 }
1536
1537 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1538 lp->tx_old = lp->tx_new;
1539
1540 return status;
1541 }
1542
1543 /*
1544 ** Writes a socket buffer address to the next available transmit descriptor.
1545 */
1546 static int
1547 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1548 {
1549 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1550 u_long iobase = dev->base_addr;
1551 int status = 0;
1552 u_long flags = 0;
1553
1554 netif_stop_queue(dev);
1555 if (lp->tx_enable == NO) { /* Cannot send for now */
1556 return -1;
1557 }
1558
1559 /*
1560 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1561 ** interrupts are lost by delayed descriptor status updates relative to
1562 ** the irq assertion, especially with a busy PCI bus.
1563 */
1564 spin_lock_irqsave(&lp->lock, flags);
1565 de4x5_tx(dev);
1566 spin_unlock_irqrestore(&lp->lock, flags);
1567
1568 /* Test if cache is already locked - requeue skb if so */
1569 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1570 return -1;
1571
1572 /* Transmit descriptor ring full or stale skb */
1573 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1574 if (lp->interrupt) {
1575 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1576 } else {
1577 de4x5_put_cache(dev, skb);
1578 }
1579 if (de4x5_debug & DEBUG_TX) {
1580 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1581 }
1582 } else if (skb->len > 0) {
1583 /* If we already have stuff queued locally, use that first */
1584 if (lp->cache.skb && !lp->interrupt) {
1585 de4x5_put_cache(dev, skb);
1586 skb = de4x5_get_cache(dev);
1587 }
1588
1589 while (skb && !netif_queue_stopped(dev) &&
1590 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1591 spin_lock_irqsave(&lp->lock, flags);
1592 netif_stop_queue(dev);
1593 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1594 lp->stats.tx_bytes += skb->len;
1595 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1596
1597 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1598 dev->trans_start = jiffies;
1599
1600 if (TX_BUFFS_AVAIL) {
1601 netif_start_queue(dev); /* Another pkt may be queued */
1602 }
1603 skb = de4x5_get_cache(dev);
1604 spin_unlock_irqrestore(&lp->lock, flags);
1605 }
1606 if (skb) de4x5_putb_cache(dev, skb);
1607 }
1608
1609 lp->cache.lock = 0;
1610
1611 return status;
1612 }
1613
1614 /*
1615 ** The DE4X5 interrupt handler.
1616 **
1617 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1618 ** so that the asserted interrupt always has some real data to work with -
1619 ** if these I/O accesses are ever changed to memory accesses, ensure the
1620 ** STS write is read immediately to complete the transaction if the adapter
1621 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1622 ** is high and descriptor status bits cannot be set before the associated
1623 ** interrupt is asserted and this routine entered.
1624 */
1625 static void
1626 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1627 {
1628 struct net_device *dev = (struct net_device *)dev_id;
1629 struct de4x5_private *lp;
1630 s32 imr, omr, sts, limit;
1631 u_long iobase;
1632
1633 if (dev == NULL) {
1634 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1635 return;
1636 }
1637 lp = (struct de4x5_private *)dev->priv;
1638 spin_lock(&lp->lock);
1639 iobase = dev->base_addr;
1640
1641 DISABLE_IRQs; /* Ensure non re-entrancy */
1642
1643 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1644 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1645
1646 synchronize_irq();
1647
1648 for (limit=0; limit<8; limit++) {
1649 sts = inl(DE4X5_STS); /* Read IRQ status */
1650 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1651
1652 if (!(sts & lp->irq_mask)) break;/* All done */
1653
1654 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1655 de4x5_rx(dev);
1656
1657 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1658 de4x5_tx(dev);
1659
1660 if (sts & STS_LNF) { /* TP Link has failed */
1661 lp->irq_mask &= ~IMR_LFM;
1662 }
1663
1664 if (sts & STS_UNF) { /* Transmit underrun */
1665 de4x5_txur(dev);
1666 }
1667
1668 if (sts & STS_SE) { /* Bus Error */
1669 STOP_DE4X5;
1670 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1671 dev->name, sts);
1672 spin_unlock(&lp->lock);
1673 return;
1674 }
1675 }
1676
1677 /* Load the TX ring with any locally stored packets */
1678 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1679 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1680 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1681 }
1682 lp->cache.lock = 0;
1683 }
1684
1685 lp->interrupt = UNMASK_INTERRUPTS;
1686 ENABLE_IRQs;
1687 spin_unlock(&lp->lock);
1688
1689 return;
1690 }
1691
1692 static int
1693 de4x5_rx(struct net_device *dev)
1694 {
1695 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1696 u_long iobase = dev->base_addr;
1697 int entry;
1698 s32 status;
1699
1700 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1701 entry=lp->rx_new) {
1702 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1703
1704 if (lp->rx_ovf) {
1705 if (inl(DE4X5_MFC) & MFC_FOCM) {
1706 de4x5_rx_ovfc(dev);
1707 break;
1708 }
1709 }
1710
1711 if (status & RD_FS) { /* Remember the start of frame */
1712 lp->rx_old = entry;
1713 }
1714
1715 if (status & RD_LS) { /* Valid frame status */
1716 if (lp->tx_enable) lp->linkOK++;
1717 if (status & RD_ES) { /* There was an error. */
1718 lp->stats.rx_errors++; /* Update the error stats. */
1719 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1720 if (status & RD_CE) lp->stats.rx_crc_errors++;
1721 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1722 if (status & RD_TL) lp->stats.rx_length_errors++;
1723 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1724 if (status & RD_CS) lp->pktStats.rx_collision++;
1725 if (status & RD_DB) lp->pktStats.rx_dribble++;
1726 if (status & RD_OF) lp->pktStats.rx_overflow++;
1727 } else { /* A valid frame received */
1728 struct sk_buff *skb;
1729 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1730 >> 16) - 4;
1731
1732 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1733 printk("%s: Insufficient memory; nuking packet.\n",
1734 dev->name);
1735 lp->stats.rx_dropped++;
1736 } else {
1737 de4x5_dbg_rx(skb, pkt_len);
1738
1739 /* Push up the protocol stack */
1740 skb->protocol=eth_type_trans(skb,dev);
1741 de4x5_local_stats(dev, skb->data, pkt_len);
1742 netif_rx(skb);
1743
1744 /* Update stats */
1745 dev->last_rx = jiffies;
1746 lp->stats.rx_packets++;
1747 lp->stats.rx_bytes += pkt_len;
1748 }
1749 }
1750
1751 /* Change buffer ownership for this frame, back to the adapter */
1752 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1753 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1754 barrier();
1755 }
1756 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1757 barrier();
1758 }
1759
1760 /*
1761 ** Update entry information
1762 */
1763 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1764 }
1765
1766 return 0;
1767 }
1768
1769 static inline void
1770 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1771 {
1772 pci_unmap_single(lp->pdev, le32_to_cpu(lp->tx_ring[entry].buf),
1773 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1774 PCI_DMA_TODEVICE);
1775 if ((u_long) lp->tx_skb[entry] > 1)
1776 dev_kfree_skb_irq(lp->tx_skb[entry]);
1777 lp->tx_skb[entry] = NULL;
1778 }
1779
1780 /*
1781 ** Buffer sent - check for TX buffer errors.
1782 */
1783 static int
1784 de4x5_tx(struct net_device *dev)
1785 {
1786 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1787 u_long iobase = dev->base_addr;
1788 int entry;
1789 s32 status;
1790
1791 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1792 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1793 if (status < 0) { /* Buffer not sent yet */
1794 break;
1795 } else if (status != 0x7fffffff) { /* Not setup frame */
1796 if (status & TD_ES) { /* An error happened */
1797 lp->stats.tx_errors++;
1798 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1799 if (status & TD_LC) lp->stats.tx_window_errors++;
1800 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1801 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1802 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1803
1804 if (TX_PKT_PENDING) {
1805 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1806 }
1807 } else { /* Packet sent */
1808 lp->stats.tx_packets++;
1809 if (lp->tx_enable) lp->linkOK++;
1810 }
1811 /* Update the collision counter */
1812 lp->stats.collisions += ((status & TD_EC) ? 16 :
1813 ((status & TD_CC) >> 3));
1814
1815 /* Free the buffer. */
1816 if (lp->tx_skb[entry] != NULL)
1817 de4x5_free_tx_buff(lp, entry);
1818 }
1819
1820 /* Update all the pointers */
1821 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1822 }
1823
1824 /* Any resources available? */
1825 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1826 if (lp->interrupt)
1827 netif_wake_queue(dev);
1828 else
1829 netif_start_queue(dev);
1830 }
1831
1832 return 0;
1833 }
1834
1835 static int
1836 de4x5_ast(struct net_device *dev)
1837 {
1838 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1839 int next_tick = DE4X5_AUTOSENSE_MS;
1840
1841 disable_ast(dev);
1842
1843 if (lp->useSROM) {
1844 next_tick = srom_autoconf(dev);
1845 } else if (lp->chipset == DC21140) {
1846 next_tick = dc21140m_autoconf(dev);
1847 } else if (lp->chipset == DC21041) {
1848 next_tick = dc21041_autoconf(dev);
1849 } else if (lp->chipset == DC21040) {
1850 next_tick = dc21040_autoconf(dev);
1851 }
1852 lp->linkOK = 0;
1853 enable_ast(dev, next_tick);
1854
1855 return 0;
1856 }
1857
1858 static int
1859 de4x5_txur(struct net_device *dev)
1860 {
1861 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1862 u_long iobase = dev->base_addr;
1863 int omr;
1864
1865 omr = inl(DE4X5_OMR);
1866 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1867 omr &= ~(OMR_ST|OMR_SR);
1868 outl(omr, DE4X5_OMR);
1869 while (inl(DE4X5_STS) & STS_TS);
1870 if ((omr & OMR_TR) < OMR_TR) {
1871 omr += 0x4000;
1872 } else {
1873 omr |= OMR_SF;
1874 }
1875 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1876 }
1877
1878 return 0;
1879 }
1880
1881 static int
1882 de4x5_rx_ovfc(struct net_device *dev)
1883 {
1884 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1885 u_long iobase = dev->base_addr;
1886 int omr;
1887
1888 omr = inl(DE4X5_OMR);
1889 outl(omr & ~OMR_SR, DE4X5_OMR);
1890 while (inl(DE4X5_STS) & STS_RS);
1891
1892 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1893 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1894 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1895 }
1896
1897 outl(omr, DE4X5_OMR);
1898
1899 return 0;
1900 }
1901
1902 static int
1903 de4x5_close(struct net_device *dev)
1904 {
1905 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1906 u_long iobase = dev->base_addr;
1907 s32 imr, omr;
1908
1909 disable_ast(dev);
1910
1911 netif_stop_queue(dev);
1912
1913 if (de4x5_debug & DEBUG_CLOSE) {
1914 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1915 dev->name, inl(DE4X5_STS));
1916 }
1917
1918 /*
1919 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1920 */
1921 DISABLE_IRQs;
1922 STOP_DE4X5;
1923
1924 /* Free the associated irq */
1925 free_irq(dev->irq, dev);
1926 lp->state = CLOSED;
1927
1928 /* Free any socket buffers */
1929 de4x5_free_rx_buffs(dev);
1930 de4x5_free_tx_buffs(dev);
1931
1932 MOD_DEC_USE_COUNT;
1933
1934 /* Put the adapter to sleep to save power */
1935 yawn(dev, SLEEP);
1936
1937 return 0;
1938 }
1939
1940 static struct net_device_stats *
1941 de4x5_get_stats(struct net_device *dev)
1942 {
1943 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1944 u_long iobase = dev->base_addr;
1945
1946 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1947
1948 return &lp->stats;
1949 }
1950
1951 static void
1952 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1953 {
1954 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1955 int i;
1956
1957 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1958 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1959 lp->pktStats.bins[i]++;
1960 i = DE4X5_PKT_STAT_SZ;
1961 }
1962 }
1963 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1964 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1965 lp->pktStats.broadcast++;
1966 } else {
1967 lp->pktStats.multicast++;
1968 }
1969 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1970 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1971 lp->pktStats.unicast++;
1972 }
1973
1974 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1975 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1976 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1977 }
1978
1979 return;
1980 }
1981
1982 /*
1983 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1984 ** If the flag is changed on a descriptor that is being read by the hardware,
1985 ** I assume PCI transaction ordering will mean you are either successful or
1986 ** just miss asserting the change to the hardware. Anyway you're messing with
1987 ** a descriptor you don't own, but this shouldn't kill the chip provided
1988 ** the descriptor register is read only to the hardware.
1989 */
1990 static void
1991 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1992 {
1993 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1994 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1995 dma_addr_t buf_dma = pci_map_single(lp->pdev, buf, flags & TD_TBS1, PCI_DMA_TODEVICE);
1996
1997 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1998 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1999 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
2000 lp->tx_skb[lp->tx_new] = skb;
2001 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
2002 barrier();
2003
2004 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
2005 barrier();
2006 }
2007
2008 /*
2009 ** Set or clear the multicast filter for this adaptor.
2010 */
2011 static void
2012 set_multicast_list(struct net_device *dev)
2013 {
2014 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2015 u_long iobase = dev->base_addr;
2016
2017 /* First, double check that the adapter is open */
2018 if (lp->state == OPEN) {
2019 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
2020 u32 omr;
2021 omr = inl(DE4X5_OMR);
2022 omr |= OMR_PR;
2023 outl(omr, DE4X5_OMR);
2024 } else {
2025 SetMulticastFilter(dev);
2026 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
2027 SETUP_FRAME_LEN, (struct sk_buff *)1);
2028
2029 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2030 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
2031 dev->trans_start = jiffies;
2032 }
2033 }
2034
2035 return;
2036 }
2037
2038 /*
2039 ** Calculate the hash code and update the logical address filter
2040 ** from a list of ethernet multicast addresses.
2041 ** Little endian crc one liner from Matt Thomas, DEC.
2042 */
2043 static void
2044 SetMulticastFilter(struct net_device *dev)
2045 {
2046 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2047 struct dev_mc_list *dmi=dev->mc_list;
2048 u_long iobase = dev->base_addr;
2049 int i, j, bit, byte;
2050 u16 hashcode;
2051 u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
2052 char *pa;
2053 unsigned char *addrs;
2054
2055 omr = inl(DE4X5_OMR);
2056 omr &= ~(OMR_PR | OMR_PM);
2057 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
2058
2059 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
2060 omr |= OMR_PM; /* Pass all multicasts */
2061 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
2062 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
2063 addrs=dmi->dmi_addr;
2064 dmi=dmi->next;
2065 if ((*addrs & 0x01) == 1) { /* multicast address? */
2066 crc = 0xffffffff; /* init CRC for each address */
2067 for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
2068 /* process each address bit */
2069 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
2070 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
2071 }
2072 }
2073 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
2074
2075 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
2076 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2077
2078 byte <<= 1; /* calc offset into setup frame */
2079 if (byte & 0x02) {
2080 byte -= 1;
2081 }
2082 lp->setup_frame[byte] |= bit;
2083 }
2084 }
2085 } else { /* Perfect filtering */
2086 for (j=0; j<dev->mc_count; j++) {
2087 addrs=dmi->dmi_addr;
2088 dmi=dmi->next;
2089 for (i=0; i<ETH_ALEN; i++) {
2090 *(pa + (i&1)) = *addrs++;
2091 if (i & 0x01) pa += 4;
2092 }
2093 }
2094 }
2095 outl(omr, DE4X5_OMR);
2096
2097 return;
2098 }
2099
2100 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
2101 /*
2102 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2103 ** the motherboard. Upto 15 EISA devices are supported.
2104 */
2105 static void __init
2106 eisa_probe(struct net_device *dev, u_long ioaddr)
2107 {
2108 int i, maxSlots, status, device;
2109 u_char irq;
2110 u_short vendor;
2111 u32 cfid;
2112 u_long iobase;
2113 struct bus_type *lp = &bus;
2114 char name[DE4X5_STRLEN];
2115
2116 if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2117
2118 lp->bus = EISA;
2119
2120 if (ioaddr == 0) { /* Autoprobing */
2121 iobase = EISA_SLOT_INC; /* Get the first slot address */
2122 i = 1;
2123 maxSlots = MAX_EISA_SLOTS;
2124 } else { /* Probe a specific location */
2125 iobase = ioaddr;
2126 i = (ioaddr >> 12);
2127 maxSlots = i + 1;
2128 }
2129
2130 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2131 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE)) continue;
2132 if (!EISA_signature(name, EISA_ID)) continue;
2133
2134 cfid = (u32) inl(PCI_CFID);
2135 cfrv = (u_short) inl(PCI_CFRV);
2136 device = (cfid >> 8) & 0x00ffff00;
2137 vendor = (u_short) cfid;
2138
2139 /* Read the EISA Configuration Registers */
2140 irq = inb(EISA_REG0);
2141 irq = de4x5_irq[(irq >> 1) & 0x03];
2142
2143 if (is_DC2114x) {
2144 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2145 }
2146 lp->chipset = device;
2147
2148 /* Write the PCI Configuration Registers */
2149 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2150 outl(0x00006000, PCI_CFLT);
2151 outl(iobase, PCI_CBIO);
2152
2153 DevicePresent(EISA_APROM);
2154
2155 dev->irq = irq;
2156 if ((status = de4x5_hw_init(dev, iobase, NULL)) == 0) {
2157 num_de4x5s++;
2158 if (loading_module) link_modules(lastModule, dev);
2159 lastEISA = i;
2160 return;
2161 }
2162 }
2163
2164 if (ioaddr == 0) lastEISA = i;
2165
2166 return;
2167 }
2168 #endif /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__) */
2169
2170 /*
2171 ** PCI bus I/O device probe
2172 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2173 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2174 ** enabled by the user first in the set up utility. Hence we just check for
2175 ** enabled features and silently ignore the card if they're not.
2176 **
2177 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2178 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2179 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2180 ** PC doesn't conform to the PCI standard)!
2181 **
2182 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2183 ** kernels use the V0.535[n] drivers.
2184 */
2185 #define PCI_LAST_DEV 32
2186
2187 static void __init
2188 pci_probe(struct net_device *dev, u_long ioaddr)
2189 {
2190 u_char pb, pbus, dev_num, dnum, timer;
2191 u_short vendor, index, status;
2192 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2193 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2194 struct bus_type *lp = &bus;
2195
2196 if (lastPCI == NO_MORE_PCI) return;
2197
2198 if (!pcibios_present()) {
2199 lastPCI = NO_MORE_PCI;
2200 return; /* No PCI bus in this machine! */
2201 }
2202
2203 lp->bus = PCI;
2204 lp->bus_num = 0;
2205
2206 if ((ioaddr < 0x1000) && loading_module) {
2207 pbus = (u_short)(ioaddr >> 8);
2208 dnum = (u_short)(ioaddr & 0xff);
2209 } else {
2210 pbus = 0;
2211 dnum = 0;
2212 }
2213
2214 for (index=lastPCI+1;(pdev = pci_find_class(class, pdev))!=NULL;index++) {
2215 dev_num = PCI_SLOT(pdev->devfn);
2216 pb = pdev->bus->number;
2217 if ((pbus || dnum) && ((pbus != pb) || (dnum != dev_num))) continue;
2218
2219 vendor = pdev->vendor;
2220 device = pdev->device << 8;
2221 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2222
2223 /* Search for an SROM on this bus */
2224 if (lp->bus_num != pb) {
2225 lp->bus_num = pb;
2226 srom_search(pdev);
2227 }
2228
2229 /* Get the chip configuration revision register */
2230 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2231
2232 /* Set the device number information */
2233 lp->device = dev_num;
2234 lp->bus_num = pb;
2235
2236 /* Set the chipset information */
2237 if (is_DC2114x) {
2238 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2239 }
2240 lp->chipset = device;
2241
2242 /* Get the board I/O address (64 bits on sparc64) */
2243 iobase = pci_resource_start(pdev, 0);
2244
2245 /* Fetch the IRQ to be used */
2246 irq = pdev->irq;
2247 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2248
2249 /* Check if I/O accesses and Bus Mastering are enabled */
2250 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2251 #ifdef __powerpc__
2252 if (!(status & PCI_COMMAND_IO)) {
2253 status |= PCI_COMMAND_IO;
2254 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2255 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2256 }
2257 #endif /* __powerpc__ */
2258 if (!(status & PCI_COMMAND_IO)) continue;
2259
2260 if (!(status & PCI_COMMAND_MASTER)) {
2261 status |= PCI_COMMAND_MASTER;
2262 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2263 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2264 }
2265 if (!(status & PCI_COMMAND_MASTER)) continue;
2266
2267 /* Check the latency timer for values >= 0x60 */
2268 pcibios_read_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, &timer);
2269 if (timer < 0x60) {
2270 pcibios_write_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, 0x60);
2271 }
2272
2273 DevicePresent(DE4X5_APROM);
2274 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2275 dev->irq = irq;
2276 if ((status = de4x5_hw_init(dev, iobase, pdev)) == 0) {
2277 num_de4x5s++;
2278 lastPCI = index;
2279 if (loading_module) link_modules(lastModule, dev);
2280 return;
2281 }
2282 } else if (ioaddr != 0) {
2283 printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2284 iobase);
2285 }
2286 }
2287
2288 lastPCI = NO_MORE_PCI;
2289
2290 return;
2291 }
2292
2293 /*
2294 ** This function searches the current bus (which is >0) for a DECchip with an
2295 ** SROM, so that in multiport cards that have one SROM shared between multiple
2296 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2297 ** For single port cards this is a time waster...
2298 */
2299 static void __init
2300 srom_search(struct pci_dev *dev)
2301 {
2302 u_char pb;
2303 u_short vendor, status;
2304 u_int irq = 0, device;
2305 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2306 int i, j;
2307 struct bus_type *lp = &bus;
2308 struct list_head *walk = &dev->bus_list;
2309
2310 for (walk = walk->next; walk != &dev->bus_list; walk = walk->next) {
2311 struct pci_dev *this_dev = pci_dev_b(walk);
2312
2313 /* Skip the pci_bus list entry */
2314 if (list_entry(walk, struct pci_bus, devices) == dev->bus) continue;
2315
2316 vendor = this_dev->vendor;
2317 device = this_dev->device << 8;
2318 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2319
2320 /* Get the chip configuration revision register */
2321 pb = this_dev->bus->number;
2322 pcibios_read_config_dword(pb, this_dev->devfn, PCI_REVISION_ID, &cfrv);
2323
2324 /* Set the device number information */
2325 lp->device = PCI_SLOT(this_dev->devfn);
2326 lp->bus_num = pb;
2327
2328 /* Set the chipset information */
2329 if (is_DC2114x) {
2330 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2331 }
2332 lp->chipset = device;
2333
2334 /* Get the board I/O address (64 bits on sparc64) */
2335 iobase = pci_resource_start(this_dev, 0);
2336
2337 /* Fetch the IRQ to be used */
2338 irq = this_dev->irq;
2339 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2340
2341 /* Check if I/O accesses are enabled */
2342 pcibios_read_config_word(pb, this_dev->devfn, PCI_COMMAND, &status);
2343 if (!(status & PCI_COMMAND_IO)) continue;
2344
2345 /* Search for a valid SROM attached to this DECchip */
2346 DevicePresent(DE4X5_APROM);
2347 for (j=0, i=0; i<ETH_ALEN; i++) {
2348 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2349 }
2350 if ((j != 0) && (j != 0x5fa)) {
2351 last.chipset = device;
2352 last.bus = pb;
2353 last.irq = irq;
2354 for (i=0; i<ETH_ALEN; i++) {
2355 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2356 }
2357 return;
2358 }
2359 }
2360
2361 return;
2362 }
2363
2364 static void __init
2365 link_modules(struct net_device *dev, struct net_device *tmp)
2366 {
2367 struct net_device *p=dev;
2368
2369 if (p) {
2370 while (((struct de4x5_private *)(p->priv))->next_module) {
2371 p = ((struct de4x5_private *)(p->priv))->next_module;
2372 }
2373
2374 if (dev != tmp) {
2375 ((struct de4x5_private *)(p->priv))->next_module = tmp;
2376 } else {
2377 ((struct de4x5_private *)(p->priv))->next_module = NULL;
2378 }
2379 }
2380
2381 return;
2382 }
2383
2384 /*
2385 ** Auto configure the media here rather than setting the port at compile
2386 ** time. This routine is called by de4x5_init() and when a loss of media is
2387 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2388 ** [TP] or no recent receive activity) to check whether the user has been
2389 ** sneaky and changed the port on us.
2390 */
2391 static int
2392 autoconf_media(struct net_device *dev)
2393 {
2394 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2395 u_long iobase = dev->base_addr;
2396 int next_tick = DE4X5_AUTOSENSE_MS;
2397
2398 lp->linkOK = 0;
2399 lp->c_media = AUTO; /* Bogus last media */
2400 disable_ast(dev);
2401 inl(DE4X5_MFC); /* Zero the lost frames counter */
2402 lp->media = INIT;
2403 lp->tcount = 0;
2404
2405 if (lp->useSROM) {
2406 next_tick = srom_autoconf(dev);
2407 } else if (lp->chipset == DC21040) {
2408 next_tick = dc21040_autoconf(dev);
2409 } else if (lp->chipset == DC21041) {
2410 next_tick = dc21041_autoconf(dev);
2411 } else if (lp->chipset == DC21140) {
2412 next_tick = dc21140m_autoconf(dev);
2413 }
2414
2415 enable_ast(dev, next_tick);
2416
2417 return (lp->media);
2418 }
2419
2420 /*
2421 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2422 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2423 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2424 ** The only way to test for that is to place a loopback packet onto the
2425 ** network and watch for errors. Since we're messing with the interrupt mask
2426 ** register, disable the board interrupts and do not allow any more packets to
2427 ** be queued to the hardware. Re-enable everything only when the media is
2428 ** found.
2429 ** I may have to "age out" locally queued packets so that the higher layer
2430 ** timeouts don't effectively duplicate packets on the network.
2431 */
2432 static int
2433 dc21040_autoconf(struct net_device *dev)
2434 {
2435 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2436 u_long iobase = dev->base_addr;
2437 int next_tick = DE4X5_AUTOSENSE_MS;
2438 s32 imr;
2439
2440 switch (lp->media) {
2441 case INIT:
2442 DISABLE_IRQs;
2443 lp->tx_enable = NO;
2444 lp->timeout = -1;
2445 de4x5_save_skbs(dev);
2446 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2447 lp->media = TP;
2448 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2449 lp->media = BNC_AUI;
2450 } else if (lp->autosense == EXT_SIA) {
2451 lp->media = EXT_SIA;
2452 } else {
2453 lp->media = NC;
2454 }
2455 lp->local_state = 0;
2456 next_tick = dc21040_autoconf(dev);
2457 break;
2458
2459 case TP:
2460 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2461 TP_SUSPECT, test_tp);
2462 break;
2463
2464 case TP_SUSPECT:
2465 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2466 break;
2467
2468 case BNC:
2469 case AUI:
2470 case BNC_AUI:
2471 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2472 BNC_AUI_SUSPECT, ping_media);
2473 break;
2474
2475 case BNC_AUI_SUSPECT:
2476 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2477 break;
2478
2479 case EXT_SIA:
2480 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2481 NC, EXT_SIA_SUSPECT, ping_media);
2482 break;
2483
2484 case EXT_SIA_SUSPECT:
2485 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2486 break;
2487
2488 case NC:
2489 /* default to TP for all */
2490 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2491 if (lp->media != lp->c_media) {
2492 de4x5_dbg_media(dev);
2493 lp->c_media = lp->media;
2494 }
2495 lp->media = INIT;
2496 lp->tx_enable = NO;
2497 break;
2498 }
2499
2500 return next_tick;
2501 }
2502
2503 static int
2504 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2505 int next_state, int suspect_state,
2506 int (*fn)(struct net_device *, int))
2507 {
2508 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2509 int next_tick = DE4X5_AUTOSENSE_MS;
2510 int linkBad;
2511
2512 switch (lp->local_state) {
2513 case 0:
2514 reset_init_sia(dev, csr13, csr14, csr15);
2515 lp->local_state++;
2516 next_tick = 500;
2517 break;
2518
2519 case 1:
2520 if (!lp->tx_enable) {
2521 linkBad = fn(dev, timeout);
2522 if (linkBad < 0) {
2523 next_tick = linkBad & ~TIMER_CB;
2524 } else {
2525 if (linkBad && (lp->autosense == AUTO)) {
2526 lp->local_state = 0;
2527 lp->media = next_state;
2528 } else {
2529 de4x5_init_connection(dev);
2530 }
2531 }
2532 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2533 lp->media = suspect_state;
2534 next_tick = 3000;
2535 }
2536 break;
2537 }
2538
2539 return next_tick;
2540 }
2541
2542 static int
2543 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2544 int (*fn)(struct net_device *, int),
2545 int (*asfn)(struct net_device *))
2546 {
2547 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2548 int next_tick = DE4X5_AUTOSENSE_MS;
2549 int linkBad;
2550
2551 switch (lp->local_state) {
2552 case 1:
2553 if (lp->linkOK) {
2554 lp->media = prev_state;
2555 } else {
2556 lp->local_state++;
2557 next_tick = asfn(dev);
2558 }
2559 break;
2560
2561 case 2:
2562 linkBad = fn(dev, timeout);
2563 if (linkBad < 0) {
2564 next_tick = linkBad & ~TIMER_CB;
2565 } else if (!linkBad) {
2566 lp->local_state--;
2567 lp->media = prev_state;
2568 } else {
2569 lp->media = INIT;
2570 lp->tcount++;
2571 }
2572 }
2573
2574 return next_tick;
2575 }
2576
2577 /*
2578 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2579 ** before BNC, because the BNC port will indicate activity if it's not
2580 ** terminated correctly. The only way to test for that is to place a loopback
2581 ** packet onto the network and watch for errors. Since we're messing with
2582 ** the interrupt mask register, disable the board interrupts and do not allow
2583 ** any more packets to be queued to the hardware. Re-enable everything only
2584 ** when the media is found.
2585 */
2586 static int
2587 dc21041_autoconf(struct net_device *dev)
2588 {
2589 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2590 u_long iobase = dev->base_addr;
2591 s32 sts, irqs, irq_mask, imr, omr;
2592 int next_tick = DE4X5_AUTOSENSE_MS;
2593
2594 switch (lp->media) {
2595 case INIT:
2596 DISABLE_IRQs;
2597 lp->tx_enable = NO;
2598 lp->timeout = -1;
2599 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2600 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2601 lp->media = TP; /* On chip auto negotiation is broken */
2602 } else if (lp->autosense == TP) {
2603 lp->media = TP;
2604 } else if (lp->autosense == BNC) {
2605 lp->media = BNC;
2606 } else if (lp->autosense == AUI) {
2607 lp->media = AUI;
2608 } else {
2609 lp->media = NC;
2610 }
2611 lp->local_state = 0;
2612 next_tick = dc21041_autoconf(dev);
2613 break;
2614
2615 case TP_NW:
2616 if (lp->timeout < 0) {
2617 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2618 outl(omr | OMR_FDX, DE4X5_OMR);
2619 }
2620 irqs = STS_LNF | STS_LNP;
2621 irq_mask = IMR_LFM | IMR_LPM;
2622 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2623 if (sts < 0) {
2624 next_tick = sts & ~TIMER_CB;
2625 } else {
2626 if (sts & STS_LNP) {
2627 lp->media = ANS;
2628 } else {
2629 lp->media = AUI;
2630 }
2631 next_tick = dc21041_autoconf(dev);
2632 }
2633 break;
2634
2635 case ANS:
2636 if (!lp->tx_enable) {
2637 irqs = STS_LNP;
2638 irq_mask = IMR_LPM;
2639 sts = test_ans(dev, irqs, irq_mask, 3000);
2640 if (sts < 0) {
2641 next_tick = sts & ~TIMER_CB;
2642 } else {
2643 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2644 lp->media = TP;
2645 next_tick = dc21041_autoconf(dev);
2646 } else {
2647 lp->local_state = 1;
2648 de4x5_init_connection(dev);
2649 }
2650 }
2651 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2652 lp->media = ANS_SUSPECT;
2653 next_tick = 3000;
2654 }
2655 break;
2656
2657 case ANS_SUSPECT:
2658 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2659 break;
2660
2661 case TP:
2662 if (!lp->tx_enable) {
2663 if (lp->timeout < 0) {
2664 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2665 outl(omr & ~OMR_FDX, DE4X5_OMR);
2666 }
2667 irqs = STS_LNF | STS_LNP;
2668 irq_mask = IMR_LFM | IMR_LPM;
2669 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2670 if (sts < 0) {
2671 next_tick = sts & ~TIMER_CB;
2672 } else {
2673 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2674 if (inl(DE4X5_SISR) & SISR_NRA) {
2675 lp->media = AUI; /* Non selected port activity */
2676 } else {
2677 lp->media = BNC;
2678 }
2679 next_tick = dc21041_autoconf(dev);
2680 } else {
2681 lp->local_state = 1;
2682 de4x5_init_connection(dev);
2683 }
2684 }
2685 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2686 lp->media = TP_SUSPECT;
2687 next_tick = 3000;
2688 }
2689 break;
2690
2691 case TP_SUSPECT:
2692 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2693 break;
2694
2695 case AUI:
2696 if (!lp->tx_enable) {
2697 if (lp->timeout < 0) {
2698 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2699 outl(omr & ~OMR_FDX, DE4X5_OMR);
2700 }
2701 irqs = 0;
2702 irq_mask = 0;
2703 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2704 if (sts < 0) {
2705 next_tick = sts & ~TIMER_CB;
2706 } else {
2707 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2708 lp->media = BNC;
2709 next_tick = dc21041_autoconf(dev);
2710 } else {
2711 lp->local_state = 1;
2712 de4x5_init_connection(dev);
2713 }
2714 }
2715 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2716 lp->media = AUI_SUSPECT;
2717 next_tick = 3000;
2718 }
2719 break;
2720
2721 case AUI_SUSPECT:
2722 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2723 break;
2724
2725 case BNC:
2726 switch (lp->local_state) {
2727 case 0:
2728 if (lp->timeout < 0) {
2729 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2730 outl(omr & ~OMR_FDX, DE4X5_OMR);
2731 }
2732 irqs = 0;
2733 irq_mask = 0;
2734 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2735 if (sts < 0) {
2736 next_tick = sts & ~TIMER_CB;
2737 } else {
2738 lp->local_state++; /* Ensure media connected */
2739 next_tick = dc21041_autoconf(dev);
2740 }
2741 break;
2742
2743 case 1:
2744 if (!lp->tx_enable) {
2745 if ((sts = ping_media(dev, 3000)) < 0) {
2746 next_tick = sts & ~TIMER_CB;
2747 } else {
2748 if (sts) {
2749 lp->local_state = 0;
2750 lp->media = NC;
2751 } else {
2752 de4x5_init_connection(dev);
2753 }
2754 }
2755 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2756 lp->media = BNC_SUSPECT;
2757 next_tick = 3000;
2758 }
2759 break;
2760 }
2761 break;
2762
2763 case BNC_SUSPECT:
2764 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2765 break;
2766
2767 case NC:
2768 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2769 outl(omr | OMR_FDX, DE4X5_OMR);
2770 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2771 if (lp->media != lp->c_media) {
2772 de4x5_dbg_media(dev);
2773 lp->c_media = lp->media;
2774 }
2775 lp->media = INIT;
2776 lp->tx_enable = NO;
2777 break;
2778 }
2779
2780 return next_tick;
2781 }
2782
2783 /*
2784 ** Some autonegotiation chips are broken in that they do not return the
2785 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2786 ** register, except at the first power up negotiation.
2787 */
2788 static int
2789 dc21140m_autoconf(struct net_device *dev)
2790 {
2791 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2792 int ana, anlpa, cap, cr, slnk, sr;
2793 int next_tick = DE4X5_AUTOSENSE_MS;
2794 u_long imr, omr, iobase = dev->base_addr;
2795
2796 switch(lp->media) {
2797 case INIT:
2798 if (lp->timeout < 0) {
2799 DISABLE_IRQs;
2800 lp->tx_enable = FALSE;
2801 lp->linkOK = 0;
2802 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2803 }
2804 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2805 next_tick &= ~TIMER_CB;
2806 } else {
2807 if (lp->useSROM) {
2808 if (srom_map_media(dev) < 0) {
2809 lp->tcount++;
2810 return next_tick;
2811 }
2812 srom_exec(dev, lp->phy[lp->active].gep);
2813 if (lp->infoblock_media == ANS) {
2814 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2815 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2816 }
2817 } else {
2818 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2819 SET_10Mb;
2820 if (lp->autosense == _100Mb) {
2821 lp->media = _100Mb;
2822 } else if (lp->autosense == _10Mb) {
2823 lp->media = _10Mb;
2824 } else if ((lp->autosense == AUTO) &&
2825 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2826 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2827 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2828 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2829 lp->media = ANS;
2830 } else if (lp->autosense == AUTO) {
2831 lp->media = SPD_DET;
2832 } else if (is_spd_100(dev) && is_100_up(dev)) {
2833 lp->media = _100Mb;
2834 } else {
2835 lp->media = NC;
2836 }
2837 }
2838 lp->local_state = 0;
2839 next_tick = dc21140m_autoconf(dev);
2840 }
2841 break;
2842
2843 case ANS:
2844 switch (lp->local_state) {
2845 case 0:
2846 if (lp->timeout < 0) {
2847 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2848 }
2849 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2850 if (cr < 0) {
2851 next_tick = cr & ~TIMER_CB;
2852 } else {
2853 if (cr) {
2854 lp->local_state = 0;
2855 lp->media = SPD_DET;
2856 } else {
2857 lp->local_state++;
2858 }
2859 next_tick = dc21140m_autoconf(dev);
2860 }
2861 break;
2862
2863 case 1:
2864 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2865 next_tick = sr & ~TIMER_CB;
2866 } else {
2867 lp->media = SPD_DET;
2868 lp->local_state = 0;
2869 if (sr) { /* Success! */
2870 lp->tmp = MII_SR_ASSC;
2871 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2872 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2873 if (!(anlpa & MII_ANLPA_RF) &&
2874 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2875 if (cap & MII_ANA_100M) {
2876 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2877 lp->media = _100Mb;
2878 } else if (cap & MII_ANA_10M) {
2879 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2880
2881 lp->media = _10Mb;
2882 }
2883 }
2884 } /* Auto Negotiation failed to finish */
2885 next_tick = dc21140m_autoconf(dev);
2886 } /* Auto Negotiation failed to start */
2887 break;
2888 }
2889 break;
2890
2891 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2892 if (lp->timeout < 0) {
2893 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2894 (~gep_rd(dev) & GEP_LNP));
2895 SET_100Mb_PDET;
2896 }
2897 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2898 next_tick = slnk & ~TIMER_CB;
2899 } else {
2900 if (is_spd_100(dev) && is_100_up(dev)) {
2901 lp->media = _100Mb;
2902 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2903 lp->media = _10Mb;
2904 } else {
2905 lp->media = NC;
2906 }
2907 next_tick = dc21140m_autoconf(dev);
2908 }
2909 break;
2910
2911 case _100Mb: /* Set 100Mb/s */
2912 next_tick = 3000;
2913 if (!lp->tx_enable) {
2914 SET_100Mb;
2915 de4x5_init_connection(dev);
2916 } else {
2917 if (!lp->linkOK && (lp->autosense == AUTO)) {
2918 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2919 lp->media = INIT;
2920 lp->tcount++;
2921 next_tick = DE4X5_AUTOSENSE_MS;
2922 }
2923 }
2924 }
2925 break;
2926
2927 case BNC:
2928 case AUI:
2929 case _10Mb: /* Set 10Mb/s */
2930 next_tick = 3000;
2931 if (!lp->tx_enable) {
2932 SET_10Mb;
2933 de4x5_init_connection(dev);
2934 } else {
2935 if (!lp->linkOK && (lp->autosense == AUTO)) {
2936 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2937 lp->media = INIT;
2938 lp->tcount++;
2939 next_tick = DE4X5_AUTOSENSE_MS;
2940 }
2941 }
2942 }
2943 break;
2944
2945 case NC:
2946 if (lp->media != lp->c_media) {
2947 de4x5_dbg_media(dev);
2948 lp->c_media = lp->media;
2949 }
2950 lp->media = INIT;
2951 lp->tx_enable = FALSE;
2952 break;
2953 }
2954
2955 return next_tick;
2956 }
2957
2958 /*
2959 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2960 ** changing how I figure out the media - but trying to keep it backwards
2961 ** compatible with the de500-xa and de500-aa.
2962 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2963 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2964 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2965 ** active.
2966 ** When autonegotiation is working, the ANS part searches the SROM for
2967 ** the highest common speed (TP) link that both can run and if that can
2968 ** be full duplex. That infoblock is executed and then the link speed set.
2969 **
2970 ** Only _10Mb and _100Mb are tested here.
2971 */
2972 static int
2973 dc2114x_autoconf(struct net_device *dev)
2974 {
2975 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2976 u_long iobase = dev->base_addr;
2977 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2978 int next_tick = DE4X5_AUTOSENSE_MS;
2979
2980 switch (lp->media) {
2981 case INIT:
2982 if (lp->timeout < 0) {
2983 DISABLE_IRQs;
2984 lp->tx_enable = FALSE;
2985 lp->linkOK = 0;
2986 lp->timeout = -1;
2987 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2988 if (lp->params.autosense & ~AUTO) {
2989 srom_map_media(dev); /* Fixed media requested */
2990 if (lp->media != lp->params.autosense) {
2991 lp->tcount++;
2992 lp->media = INIT;
2993 return next_tick;
2994 }
2995 lp->media = INIT;
2996 }
2997 }
2998 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2999 next_tick &= ~TIMER_CB;
3000 } else {
3001 if (lp->autosense == _100Mb) {
3002 lp->media = _100Mb;
3003 } else if (lp->autosense == _10Mb) {
3004 lp->media = _10Mb;
3005 } else if (lp->autosense == TP) {
3006 lp->media = TP;
3007 } else if (lp->autosense == BNC) {
3008 lp->media = BNC;
3009 } else if (lp->autosense == AUI) {
3010 lp->media = AUI;
3011 } else {
3012 lp->media = SPD_DET;
3013 if ((lp->infoblock_media == ANS) &&
3014 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3015 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3016 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3017 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3018 lp->media = ANS;
3019 }
3020 }
3021 lp->local_state = 0;
3022 next_tick = dc2114x_autoconf(dev);
3023 }
3024 break;
3025
3026 case ANS:
3027 switch (lp->local_state) {
3028 case 0:
3029 if (lp->timeout < 0) {
3030 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3031 }
3032 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3033 if (cr < 0) {
3034 next_tick = cr & ~TIMER_CB;
3035 } else {
3036 if (cr) {
3037 lp->local_state = 0;
3038 lp->media = SPD_DET;
3039 } else {
3040 lp->local_state++;
3041 }
3042 next_tick = dc2114x_autoconf(dev);
3043 }
3044 break;
3045
3046 case 1:
3047 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3048 next_tick = sr & ~TIMER_CB;
3049 } else {
3050 lp->media = SPD_DET;
3051 lp->local_state = 0;
3052 if (sr) { /* Success! */
3053 lp->tmp = MII_SR_ASSC;
3054 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3055 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3056 if (!(anlpa & MII_ANLPA_RF) &&
3057 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3058 if (cap & MII_ANA_100M) {
3059 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3060 lp->media = _100Mb;
3061 } else if (cap & MII_ANA_10M) {
3062 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3063 lp->media = _10Mb;
3064 }
3065 }
3066 } /* Auto Negotiation failed to finish */
3067 next_tick = dc2114x_autoconf(dev);
3068 } /* Auto Negotiation failed to start */
3069 break;
3070 }
3071 break;
3072
3073 case AUI:
3074 if (!lp->tx_enable) {
3075 if (lp->timeout < 0) {
3076 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3077 outl(omr & ~OMR_FDX, DE4X5_OMR);
3078 }
3079 irqs = 0;
3080 irq_mask = 0;
3081 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3082 if (sts < 0) {
3083 next_tick = sts & ~TIMER_CB;
3084 } else {
3085 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3086 lp->media = BNC;
3087 next_tick = dc2114x_autoconf(dev);
3088 } else {
3089 lp->local_state = 1;
3090 de4x5_init_connection(dev);
3091 }
3092 }
3093 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3094 lp->media = AUI_SUSPECT;
3095 next_tick = 3000;
3096 }
3097 break;
3098
3099 case AUI_SUSPECT:
3100 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3101 break;
3102
3103 case BNC:
3104 switch (lp->local_state) {
3105 case 0:
3106 if (lp->timeout < 0) {
3107 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3108 outl(omr & ~OMR_FDX, DE4X5_OMR);
3109 }
3110 irqs = 0;
3111 irq_mask = 0;
3112 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3113 if (sts < 0) {
3114 next_tick = sts & ~TIMER_CB;
3115 } else {
3116 lp->local_state++; /* Ensure media connected */
3117 next_tick = dc2114x_autoconf(dev);
3118 }
3119 break;
3120
3121 case 1:
3122 if (!lp->tx_enable) {
3123 if ((sts = ping_media(dev, 3000)) < 0) {
3124 next_tick = sts & ~TIMER_CB;
3125 } else {
3126 if (sts) {
3127 lp->local_state = 0;
3128 lp->tcount++;
3129 lp->media = INIT;
3130 } else {
3131 de4x5_init_connection(dev);
3132 }
3133 }
3134 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3135 lp->media = BNC_SUSPECT;
3136 next_tick = 3000;
3137 }
3138 break;
3139 }
3140 break;
3141
3142 case BNC_SUSPECT:
3143 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3144 break;
3145
3146 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3147 if (srom_map_media(dev) < 0) {
3148 lp->tcount++;
3149 lp->media = INIT;
3150 return next_tick;
3151 }
3152 if (lp->media == _100Mb) {
3153 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3154 lp->media = SPD_DET;
3155 return (slnk & ~TIMER_CB);
3156 }
3157 } else {
3158 if (wait_for_link(dev) < 0) {
3159 lp->media = SPD_DET;
3160 return PDET_LINK_WAIT;
3161 }
3162 }
3163 if (lp->media == ANS) { /* Do MII parallel detection */
3164 if (is_spd_100(dev)) {
3165 lp->media = _100Mb;
3166 } else {
3167 lp->media = _10Mb;
3168 }
3169 next_tick = dc2114x_autoconf(dev);
3170 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3171 (((lp->media == _10Mb) || (lp->media == TP) ||
3172 (lp->media == BNC) || (lp->media == AUI)) &&
3173 is_10_up(dev))) {
3174 next_tick = dc2114x_autoconf(dev);
3175 } else {
3176 lp->tcount++;
3177 lp->media = INIT;
3178 }
3179 break;
3180
3181 case _10Mb:
3182 next_tick = 3000;
3183 if (!lp->tx_enable) {
3184 SET_10Mb;
3185 de4x5_init_connection(dev);
3186 } else {
3187 if (!lp->linkOK && (lp->autosense == AUTO)) {
3188 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3189 lp->media = INIT;
3190 lp->tcount++;
3191 next_tick = DE4X5_AUTOSENSE_MS;
3192 }
3193 }
3194 }
3195 break;
3196
3197 case _100Mb:
3198 next_tick = 3000;
3199 if (!lp->tx_enable) {
3200 SET_100Mb;
3201 de4x5_init_connection(dev);
3202 } else {
3203 if (!lp->linkOK && (lp->autosense == AUTO)) {
3204 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3205 lp->media = INIT;
3206 lp->tcount++;
3207 next_tick = DE4X5_AUTOSENSE_MS;
3208 }
3209 }
3210 }
3211 break;
3212
3213 default:
3214 lp->tcount++;
3215 printk("Huh?: media:%02x\n", lp->media);
3216 lp->media = INIT;
3217 break;
3218 }
3219
3220 return next_tick;
3221 }
3222
3223 static int
3224 srom_autoconf(struct net_device *dev)
3225 {
3226 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3227
3228 return lp->infoleaf_fn(dev);
3229 }
3230
3231 /*
3232 ** This mapping keeps the original media codes and FDX flag unchanged.
3233 ** While it isn't strictly necessary, it helps me for the moment...
3234 ** The early return avoids a media state / SROM media space clash.
3235 */
3236 static int
3237 srom_map_media(struct net_device *dev)
3238 {
3239 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3240
3241 lp->fdx = 0;
3242 if (lp->infoblock_media == lp->media)
3243 return 0;
3244
3245 switch(lp->infoblock_media) {
3246 case SROM_10BASETF:
3247 if (!lp->params.fdx) return -1;
3248 lp->fdx = TRUE;
3249 case SROM_10BASET:
3250 if (lp->params.fdx && !lp->fdx) return -1;
3251 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3252 lp->media = _10Mb;
3253 } else {
3254 lp->media = TP;
3255 }
3256 break;
3257
3258 case SROM_10BASE2:
3259 lp->media = BNC;
3260 break;
3261
3262 case SROM_10BASE5:
3263 lp->media = AUI;
3264 break;
3265
3266 case SROM_100BASETF:
3267 if (!lp->params.fdx) return -1;
3268 lp->fdx = TRUE;
3269 case SROM_100BASET:
3270 if (lp->params.fdx && !lp->fdx) return -1;
3271 lp->media = _100Mb;
3272 break;
3273
3274 case SROM_100BASET4:
3275 lp->media = _100Mb;
3276 break;
3277
3278 case SROM_100BASEFF:
3279 if (!lp->params.fdx) return -1;
3280 lp->fdx = TRUE;
3281 case SROM_100BASEF:
3282 if (lp->params.fdx && !lp->fdx) return -1;
3283 lp->media = _100Mb;
3284 break;
3285
3286 case ANS:
3287 lp->media = ANS;
3288 lp->fdx = lp->params.fdx;
3289 break;
3290
3291 default:
3292 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3293 lp->infoblock_media);
3294 return -1;
3295 break;
3296 }
3297
3298 return 0;
3299 }
3300
3301 static void
3302 de4x5_init_connection(struct net_device *dev)
3303 {
3304 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3305 u_long iobase = dev->base_addr;
3306 u_long flags = 0;
3307
3308 if (lp->media != lp->c_media) {
3309 de4x5_dbg_media(dev);
3310 lp->c_media = lp->media; /* Stop scrolling media messages */
3311 }
3312
3313 spin_lock_irqsave(&lp->lock, flags);
3314 de4x5_rst_desc_ring(dev);
3315 de4x5_setup_intr(dev);
3316 lp->tx_enable = YES;
3317 spin_unlock_irqrestore(&lp->lock, flags);
3318 outl(POLL_DEMAND, DE4X5_TPD);
3319
3320 netif_wake_queue(dev);
3321
3322 return;
3323 }
3324
3325 /*
3326 ** General PHY reset function. Some MII devices don't reset correctly
3327 ** since their MII address pins can float at voltages that are dependent
3328 ** on the signal pin use. Do a double reset to ensure a reset.
3329 */
3330 static int
3331 de4x5_reset_phy(struct net_device *dev)
3332 {
3333 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3334 u_long iobase = dev->base_addr;
3335 int next_tick = 0;
3336
3337 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3338 if (lp->timeout < 0) {
3339 if (lp->useSROM) {
3340 if (lp->phy[lp->active].rst) {
3341 srom_exec(dev, lp->phy[lp->active].rst);
3342 srom_exec(dev, lp->phy[lp->active].rst);
3343 } else if (lp->rst) { /* Type 5 infoblock reset */
3344 srom_exec(dev, lp->rst);
3345 srom_exec(dev, lp->rst);
3346 }
3347 } else {
3348 PHY_HARD_RESET;
3349 }
3350 if (lp->useMII) {
3351 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3352 }
3353 }
3354 if (lp->useMII) {
3355 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3356 }
3357 } else if (lp->chipset == DC21140) {
3358 PHY_HARD_RESET;
3359 }
3360
3361 return next_tick;
3362 }
3363
3364 static int
3365 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3366 {
3367 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3368 u_long iobase = dev->base_addr;
3369 s32 sts, csr12;
3370
3371 if (lp->timeout < 0) {
3372 lp->timeout = msec/100;
3373 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3374 reset_init_sia(dev, csr13, csr14, csr15);
3375 }
3376
3377 /* set up the interrupt mask */
3378 outl(irq_mask, DE4X5_IMR);
3379
3380 /* clear all pending interrupts */
3381 sts = inl(DE4X5_STS);
3382 outl(sts, DE4X5_STS);
3383
3384 /* clear csr12 NRA and SRA bits */
3385 if ((lp->chipset == DC21041) || lp->useSROM) {
3386 csr12 = inl(DE4X5_SISR);
3387 outl(csr12, DE4X5_SISR);
3388 }
3389 }
3390
3391 sts = inl(DE4X5_STS) & ~TIMER_CB;
3392
3393 if (!(sts & irqs) && --lp->timeout) {
3394 sts = 100 | TIMER_CB;
3395 } else {
3396 lp->timeout = -1;
3397 }
3398
3399 return sts;
3400 }
3401
3402 static int
3403 test_tp(struct net_device *dev, s32 msec)
3404 {
3405 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3406 u_long iobase = dev->base_addr;
3407 int sisr;
3408
3409 if (lp->timeout < 0) {
3410 lp->timeout = msec/100;
3411 }
3412
3413 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3414
3415 if (sisr && --lp->timeout) {
3416 sisr = 100 | TIMER_CB;
3417 } else {
3418 lp->timeout = -1;
3419 }
3420
3421 return sisr;
3422 }
3423
3424 /*
3425 ** Samples the 100Mb Link State Signal. The sample interval is important
3426 ** because too fast a rate can give erroneous results and confuse the
3427 ** speed sense algorithm.
3428 */
3429 #define SAMPLE_INTERVAL 500 /* ms */
3430 #define SAMPLE_DELAY 2000 /* ms */
3431 static int
3432 test_for_100Mb(struct net_device *dev, int msec)
3433 {
3434 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3435 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3436
3437 if (lp->timeout < 0) {
3438 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3439 if (msec > SAMPLE_DELAY) {
3440 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3441 gep = SAMPLE_DELAY | TIMER_CB;
3442 return gep;
3443 } else {
3444 lp->timeout = msec/SAMPLE_INTERVAL;
3445 }
3446 }
3447
3448 if (lp->phy[lp->active].id || lp->useSROM) {
3449 gep = is_100_up(dev) | is_spd_100(dev);
3450 } else {
3451 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3452 }
3453 if (!(gep & ret) && --lp->timeout) {
3454 gep = SAMPLE_INTERVAL | TIMER_CB;
3455 } else {
3456 lp->timeout = -1;
3457 }
3458
3459 return gep;
3460 }
3461
3462 static int
3463 wait_for_link(struct net_device *dev)
3464 {
3465 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3466
3467 if (lp->timeout < 0) {
3468 lp->timeout = 1;
3469 }
3470
3471 if (lp->timeout--) {
3472 return TIMER_CB;
3473 } else {
3474 lp->timeout = -1;
3475 }
3476
3477 return 0;
3478 }
3479
3480 /*
3481 **
3482 **
3483 */
3484 static int
3485 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3486 {
3487 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3488 int test;
3489 u_long iobase = dev->base_addr;
3490
3491 if (lp->timeout < 0) {
3492 lp->timeout = msec/100;
3493 }
3494
3495 if (pol) pol = ~0;
3496 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3497 test = (reg ^ pol) & mask;
3498
3499 if (test && --lp->timeout) {
3500 reg = 100 | TIMER_CB;
3501 } else {
3502 lp->timeout = -1;
3503 }
3504
3505 return reg;
3506 }
3507
3508 static int
3509 is_spd_100(struct net_device *dev)
3510 {
3511 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3512 u_long iobase = dev->base_addr;
3513 int spd;
3514
3515 if (lp->useMII) {
3516 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3517 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3518 spd &= lp->phy[lp->active].spd.mask;
3519 } else if (!lp->useSROM) { /* de500-xa */
3520 spd = ((~gep_rd(dev)) & GEP_SLNK);
3521 } else {
3522 if ((lp->ibn == 2) || !lp->asBitValid)
3523 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3524
3525 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3526 (lp->linkOK & ~lp->asBitValid);
3527 }
3528
3529 return spd;
3530 }
3531
3532 static int
3533 is_100_up(struct net_device *dev)
3534 {
3535 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3536 u_long iobase = dev->base_addr;
3537
3538 if (lp->useMII) {
3539 /* Double read for sticky bits & temporary drops */
3540 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3541 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3542 } else if (!lp->useSROM) { /* de500-xa */
3543 return ((~gep_rd(dev)) & GEP_SLNK);
3544 } else {
3545 if ((lp->ibn == 2) || !lp->asBitValid)
3546 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3547
3548 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3549 (lp->linkOK & ~lp->asBitValid));
3550 }
3551 }
3552
3553 static int
3554 is_10_up(struct net_device *dev)
3555 {
3556 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3557 u_long iobase = dev->base_addr;
3558
3559 if (lp->useMII) {
3560 /* Double read for sticky bits & temporary drops */
3561 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3562 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3563 } else if (!lp->useSROM) { /* de500-xa */
3564 return ((~gep_rd(dev)) & GEP_LNP);
3565 } else {
3566 if ((lp->ibn == 2) || !lp->asBitValid)
3567 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3568 (~inl(DE4X5_SISR)&SISR_LS10):
3569 0);
3570
3571 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3572 (lp->linkOK & ~lp->asBitValid));
3573 }
3574 }
3575
3576 static int
3577 is_anc_capable(struct net_device *dev)
3578 {
3579 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3580 u_long iobase = dev->base_addr;
3581
3582 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3583 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3584 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3585 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3586 } else {
3587 return 0;
3588 }
3589 }
3590
3591 /*
3592 ** Send a packet onto the media and watch for send errors that indicate the
3593 ** media is bad or unconnected.
3594 */
3595 static int
3596 ping_media(struct net_device *dev, int msec)
3597 {
3598 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3599 u_long iobase = dev->base_addr;
3600 int sisr;
3601
3602 if (lp->timeout < 0) {
3603 lp->timeout = msec/100;
3604
3605 lp->tmp = lp->tx_new; /* Remember the ring position */
3606 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3607 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3608 outl(POLL_DEMAND, DE4X5_TPD);
3609 }
3610
3611 sisr = inl(DE4X5_SISR);
3612
3613 if ((!(sisr & SISR_NCR)) &&
3614 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3615 (--lp->timeout)) {
3616 sisr = 100 | TIMER_CB;
3617 } else {
3618 if ((!(sisr & SISR_NCR)) &&
3619 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3620 lp->timeout) {
3621 sisr = 0;
3622 } else {
3623 sisr = 1;
3624 }
3625 lp->timeout = -1;
3626 }
3627
3628 return sisr;
3629 }
3630
3631 /*
3632 ** This function does 2 things: on Intels it kmalloc's another buffer to
3633 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3634 ** into which the packet is copied.
3635 */
3636 static struct sk_buff *
3637 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3638 {
3639 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3640 struct sk_buff *p;
3641
3642 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3643 struct sk_buff *ret;
3644 u_long i=0, tmp;
3645
3646 p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3647 if (!p) return NULL;
3648
3649 p->dev = dev;
3650 tmp = virt_to_bus(p->data);
3651 i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3652 skb_reserve(p, i);
3653 lp->rx_ring[index].buf = tmp + i;
3654
3655 ret = lp->rx_skb[index];
3656 lp->rx_skb[index] = p;
3657
3658 if ((u_long) ret > 1) {
3659 skb_put(ret, len);
3660 }
3661
3662 return ret;
3663
3664 #else
3665 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3666
3667 p = dev_alloc_skb(len + 2);
3668 if (!p) return NULL;
3669
3670 p->dev = dev;
3671 skb_reserve(p, 2); /* Align */
3672 if (index < lp->rx_old) { /* Wrapped buffer */
3673 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3674 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3675 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3676 } else { /* Linear buffer */
3677 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3678 }
3679
3680 return p;
3681 #endif
3682 }
3683
3684 static void
3685 de4x5_free_rx_buffs(struct net_device *dev)
3686 {
3687 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3688 int i;
3689
3690 for (i=0; i<lp->rxRingSize; i++) {
3691 if ((u_long) lp->rx_skb[i] > 1) {
3692 dev_kfree_skb(lp->rx_skb[i]);
3693 }
3694 lp->rx_ring[i].status = 0;
3695 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3696 }
3697
3698 return;
3699 }
3700
3701 static void
3702 de4x5_free_tx_buffs(struct net_device *dev)
3703 {
3704 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3705 int i;
3706
3707 for (i=0; i<lp->txRingSize; i++) {
3708 if (lp->tx_skb[i])
3709 de4x5_free_tx_buff(lp, i);
3710 lp->tx_ring[i].status = 0;
3711 }
3712
3713 /* Unload the locally queued packets */
3714 while (lp->cache.skb) {
3715 dev_kfree_skb(de4x5_get_cache(dev));
3716 }
3717
3718 return;
3719 }
3720
3721 /*
3722 ** When a user pulls a connection, the DECchip can end up in a
3723 ** 'running - waiting for end of transmission' state. This means that we
3724 ** have to perform a chip soft reset to ensure that we can synchronize
3725 ** the hardware and software and make any media probes using a loopback
3726 ** packet meaningful.
3727 */
3728 static void
3729 de4x5_save_skbs(struct net_device *dev)
3730 {
3731 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3732 u_long iobase = dev->base_addr;
3733 s32 omr;
3734
3735 if (!lp->cache.save_cnt) {
3736 STOP_DE4X5;
3737 de4x5_tx(dev); /* Flush any sent skb's */
3738 de4x5_free_tx_buffs(dev);
3739 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3740 de4x5_sw_reset(dev);
3741 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3742 lp->cache.save_cnt++;
3743 START_DE4X5;
3744 }
3745
3746 return;
3747 }
3748
3749 static void
3750 de4x5_rst_desc_ring(struct net_device *dev)
3751 {
3752 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3753 u_long iobase = dev->base_addr;
3754 int i;
3755 s32 omr;
3756
3757 if (lp->cache.save_cnt) {
3758 STOP_DE4X5;
3759 outl(lp->dma_rings, DE4X5_RRBA);
3760 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3761 DE4X5_TRBA);
3762
3763 lp->rx_new = lp->rx_old = 0;
3764 lp->tx_new = lp->tx_old = 0;
3765
3766 for (i = 0; i < lp->rxRingSize; i++) {
3767 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3768 }
3769
3770 for (i = 0; i < lp->txRingSize; i++) {
3771 lp->tx_ring[i].status = cpu_to_le32(0);
3772 }
3773
3774 barrier();
3775 lp->cache.save_cnt--;
3776 START_DE4X5;
3777 }
3778
3779 return;
3780 }
3781
3782 static void
3783 de4x5_cache_state(struct net_device *dev, int flag)
3784 {
3785 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3786 u_long iobase = dev->base_addr;
3787
3788 switch(flag) {
3789 case DE4X5_SAVE_STATE:
3790 lp->cache.csr0 = inl(DE4X5_BMR);
3791 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3792 lp->cache.csr7 = inl(DE4X5_IMR);
3793 break;
3794
3795 case DE4X5_RESTORE_STATE:
3796 outl(lp->cache.csr0, DE4X5_BMR);
3797 outl(lp->cache.csr6, DE4X5_OMR);
3798 outl(lp->cache.csr7, DE4X5_IMR);
3799 if (lp->chipset == DC21140) {
3800 gep_wr(lp->cache.gepc, dev);
3801 gep_wr(lp->cache.gep, dev);
3802 } else {
3803 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3804 lp->cache.csr15);
3805 }
3806 break;
3807 }
3808
3809 return;
3810 }
3811
3812 static void
3813 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3814 {
3815 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3816 struct sk_buff *p;
3817
3818 if (lp->cache.skb) {
3819 for (p=lp->cache.skb; p->next; p=p->next);
3820 p->next = skb;
3821 } else {
3822 lp->cache.skb = skb;
3823 }
3824 skb->next = NULL;
3825
3826 return;
3827 }
3828
3829 static void
3830 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3831 {
3832 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3833 struct sk_buff *p = lp->cache.skb;
3834
3835 lp->cache.skb = skb;
3836 skb->next = p;
3837
3838 return;
3839 }
3840
3841 static struct sk_buff *
3842 de4x5_get_cache(struct net_device *dev)
3843 {
3844 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3845 struct sk_buff *p = lp->cache.skb;
3846
3847 if (p) {
3848 lp->cache.skb = p->next;
3849 p->next = NULL;
3850 }
3851
3852 return p;
3853 }
3854
3855 /*
3856 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3857 ** is received and the auto-negotiation status is NWAY OK.
3858 */
3859 static int
3860 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3861 {
3862 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3863 u_long iobase = dev->base_addr;
3864 s32 sts, ans;
3865
3866 if (lp->timeout < 0) {
3867 lp->timeout = msec/100;
3868 outl(irq_mask, DE4X5_IMR);
3869
3870 /* clear all pending interrupts */
3871 sts = inl(DE4X5_STS);
3872 outl(sts, DE4X5_STS);
3873 }
3874
3875 ans = inl(DE4X5_SISR) & SISR_ANS;
3876 sts = inl(DE4X5_STS) & ~TIMER_CB;
3877
3878 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3879 sts = 100 | TIMER_CB;
3880 } else {
3881 lp->timeout = -1;
3882 }
3883
3884 return sts;
3885 }
3886
3887 static void
3888 de4x5_setup_intr(struct net_device *dev)
3889 {
3890 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3891 u_long iobase = dev->base_addr;
3892 s32 imr, sts;
3893
3894 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3895 imr = 0;
3896 UNMASK_IRQs;
3897 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3898 outl(sts, DE4X5_STS);
3899 ENABLE_IRQs;
3900 }
3901
3902 return;
3903 }
3904
3905 /*
3906 **
3907 */
3908 static void
3909 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3910 {
3911 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3912 u_long iobase = dev->base_addr;
3913
3914 RESET_SIA;
3915 if (lp->useSROM) {
3916 if (lp->ibn == 3) {
3917 srom_exec(dev, lp->phy[lp->active].rst);
3918 srom_exec(dev, lp->phy[lp->active].gep);
3919 outl(1, DE4X5_SICR);
3920 return;
3921 } else {
3922 csr15 = lp->cache.csr15;
3923 csr14 = lp->cache.csr14;
3924 csr13 = lp->cache.csr13;
3925 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3926 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3927 }
3928 } else {
3929 outl(csr15, DE4X5_SIGR);
3930 }
3931 outl(csr14, DE4X5_STRR);
3932 outl(csr13, DE4X5_SICR);
3933
3934 mdelay(10);
3935
3936 return;
3937 }
3938
3939 /*
3940 ** Create a loopback ethernet packet
3941 */
3942 static void
3943 create_packet(struct net_device *dev, char *frame, int len)
3944 {
3945 int i;
3946 char *buf = frame;
3947
3948 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3949 *buf++ = dev->dev_addr[i];
3950 }
3951 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3952 *buf++ = dev->dev_addr[i];
3953 }
3954
3955 *buf++ = 0; /* Packet length (2 bytes) */
3956 *buf++ = 1;
3957
3958 return;
3959 }
3960
3961 /*
3962 ** Look for a particular board name in the EISA configuration space
3963 */
3964 static int
3965 EISA_signature(char *name, s32 eisa_id)
3966 {
3967 static c_char *signatures[] = DE4X5_SIGNATURE;
3968 char ManCode[DE4X5_STRLEN];
3969 union {
3970 s32 ID;
3971 char Id[4];
3972 } Eisa;
3973 int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3974
3975 *name = '\0';
3976 Eisa.ID = inl(eisa_id);
3977
3978 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3979 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3980 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3981 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3982 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3983 ManCode[5]='\0';
3984
3985 for (i=0;i<siglen;i++) {
3986 if (strstr(ManCode, signatures[i]) != NULL) {
3987 strcpy(name,ManCode);
3988 status = 1;
3989 break;
3990 }
3991 }
3992
3993 return status; /* return the device name string */
3994 }
3995
3996 /*
3997 ** Look for a particular board name in the PCI configuration space
3998 */
3999 static int
4000 PCI_signature(char *name, struct bus_type *lp)
4001 {
4002 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
4003 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
4004
4005 if (lp->chipset == DC21040) {
4006 strcpy(name, "DE434/5");
4007 return status;
4008 } else { /* Search for a DEC name in the SROM */
4009 int i = *((char *)&lp->srom + 19) * 3;
4010 strncpy(name, (char *)&lp->srom + 26 + i, 8);
4011 }
4012 name[8] = '\0';
4013 for (i=0; i<siglen; i++) {
4014 if (strstr(name,de4x5_signatures[i])!=NULL) break;
4015 }
4016 if (i == siglen) {
4017 if (dec_only) {
4018 *name = '\0';
4019 } else { /* Use chip name to avoid confusion */
4020 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
4021 ((lp->chipset == DC21041) ? "DC21041" :
4022 ((lp->chipset == DC21140) ? "DC21140" :
4023 ((lp->chipset == DC21142) ? "DC21142" :
4024 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4025 )))))));
4026 }
4027 if (lp->chipset != DC21041) {
4028 useSROM = TRUE; /* card is not recognisably DEC */
4029 }
4030 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4031 useSROM = TRUE;
4032 }
4033
4034 return status;
4035 }
4036
4037 /*
4038 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4039 ** the DC21040, else read the SROM for the other chips.
4040 ** The SROM may not be present in a multi-MAC card, so first read the
4041 ** MAC address and check for a bad address. If there is a bad one then exit
4042 ** immediately with the prior srom contents intact (the h/w address will
4043 ** be fixed up later).
4044 */
4045 static void
4046 DevicePresent(u_long aprom_addr)
4047 {
4048 int i, j=0;
4049 struct bus_type *lp = &bus;
4050
4051 if (lp->chipset == DC21040) {
4052 if (lp->bus == EISA) {
4053 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4054 } else {
4055 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4056 }
4057 } else { /* Read new srom */
4058 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4059 for (i=0; i<(ETH_ALEN>>1); i++) {
4060 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4061 *p = le16_to_cpu(tmp);
4062 j += *p++;
4063 }
4064 if ((j == 0) || (j == 0x2fffd)) {
4065 return;
4066 }
4067
4068 p=(short *)&lp->srom;
4069 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4070 tmp = srom_rd(aprom_addr, i);
4071 *p++ = le16_to_cpu(tmp);
4072 }
4073 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4074 }
4075
4076 return;
4077 }
4078
4079 /*
4080 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4081 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4082 ** it...from depca.c.
4083 */
4084 static void
4085 enet_addr_rst(u_long aprom_addr)
4086 {
4087 union {
4088 struct {
4089 u32 a;
4090 u32 b;
4091 } llsig;
4092 char Sig[sizeof(u32) << 1];
4093 } dev;
4094 short sigLength=0;
4095 s8 data;
4096 int i, j;
4097
4098 dev.llsig.a = ETH_PROM_SIG;
4099 dev.llsig.b = ETH_PROM_SIG;
4100 sigLength = sizeof(u32) << 1;
4101
4102 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4103 data = inb(aprom_addr);
4104 if (dev.Sig[j] == data) { /* track signature */
4105 j++;
4106 } else { /* lost signature; begin search again */
4107 if (data == dev.Sig[0]) { /* rare case.... */
4108 j=1;
4109 } else {
4110 j=0;
4111 }
4112 }
4113 }
4114
4115 return;
4116 }
4117
4118 /*
4119 ** For the bad status case and no SROM, then add one to the previous
4120 ** address. However, need to add one backwards in case we have 0xff
4121 ** as one or more of the bytes. Only the last 3 bytes should be checked
4122 ** as the first three are invariant - assigned to an organisation.
4123 */
4124 static int
4125 get_hw_addr(struct net_device *dev)
4126 {
4127 u_long iobase = dev->base_addr;
4128 int broken, i, k, tmp, status = 0;
4129 u_short j,chksum;
4130 struct bus_type *lp = &bus;
4131
4132 broken = de4x5_bad_srom(lp);
4133
4134 for (i=0,k=0,j=0;j<3;j++) {
4135 k <<= 1;
4136 if (k > 0xffff) k-=0xffff;
4137
4138 if (lp->bus == PCI) {
4139 if (lp->chipset == DC21040) {
4140 while ((tmp = inl(DE4X5_APROM)) < 0);
4141 k += (u_char) tmp;
4142 dev->dev_addr[i++] = (u_char) tmp;
4143 while ((tmp = inl(DE4X5_APROM)) < 0);
4144 k += (u_short) (tmp << 8);
4145 dev->dev_addr[i++] = (u_char) tmp;
4146 } else if (!broken) {
4147 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4148 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4149 } else if ((broken == SMC) || (broken == ACCTON)) {
4150 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4151 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4152 }
4153 } else {
4154 k += (u_char) (tmp = inb(EISA_APROM));
4155 dev->dev_addr[i++] = (u_char) tmp;
4156 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4157 dev->dev_addr[i++] = (u_char) tmp;
4158 }
4159
4160 if (k > 0xffff) k-=0xffff;
4161 }
4162 if (k == 0xffff) k=0;
4163
4164 if (lp->bus == PCI) {
4165 if (lp->chipset == DC21040) {
4166 while ((tmp = inl(DE4X5_APROM)) < 0);
4167 chksum = (u_char) tmp;
4168 while ((tmp = inl(DE4X5_APROM)) < 0);
4169 chksum |= (u_short) (tmp << 8);
4170 if ((k != chksum) && (dec_only)) status = -1;
4171 }
4172 } else {
4173 chksum = (u_char) inb(EISA_APROM);
4174 chksum |= (u_short) (inb(EISA_APROM) << 8);
4175 if ((k != chksum) && (dec_only)) status = -1;
4176 }
4177
4178 /* If possible, try to fix a broken card - SMC only so far */
4179 srom_repair(dev, broken);
4180
4181 #ifdef CONFIG_PPC
4182 /*
4183 ** If the address starts with 00 a0, we have to bit-reverse
4184 ** each byte of the address.
4185 */
4186 if ( (ppc_md.ppc_machine & _MACH_Pmac) &&
4187 (dev->dev_addr[0] == 0) &&
4188 (dev->dev_addr[1] == 0xa0) )
4189 {
4190 for (i = 0; i < ETH_ALEN; ++i)
4191 {
4192 int x = dev->dev_addr[i];
4193 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4194 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4195 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4196 }
4197 }
4198 #endif /* CONFIG_PPC */
4199
4200 /* Test for a bad enet address */
4201 status = test_bad_enet(dev, status);
4202
4203 return status;
4204 }
4205
4206 /*
4207 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4208 ** didn't seem to work here...?
4209 */
4210 static int
4211 de4x5_bad_srom(struct bus_type *lp)
4212 {
4213 int i, status = 0;
4214
4215 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4216 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4217 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4218 if (i == 0) {
4219 status = SMC;
4220 } else if (i == 1) {
4221 status = ACCTON;
4222 }
4223 break;
4224 }
4225 }
4226
4227 return status;
4228 }
4229
4230 static int
4231 de4x5_strncmp(char *a, char *b, int n)
4232 {
4233 int ret=0;
4234
4235 for (;n && !ret;n--) {
4236 ret = *a++ - *b++;
4237 }
4238
4239 return ret;
4240 }
4241
4242 static void
4243 srom_repair(struct net_device *dev, int card)
4244 {
4245 struct bus_type *lp = &bus;
4246
4247 switch(card) {
4248 case SMC:
4249 memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4250 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4251 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4252 useSROM = TRUE;
4253 break;
4254 }
4255
4256 return;
4257 }
4258
4259 /*
4260 ** Assume that the irq's do not follow the PCI spec - this is seems
4261 ** to be true so far (2 for 2).
4262 */
4263 static int
4264 test_bad_enet(struct net_device *dev, int status)
4265 {
4266 struct bus_type *lp = &bus;
4267 int i, tmp;
4268
4269 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4270 if ((tmp == 0) || (tmp == 0x5fa)) {
4271 if ((lp->chipset == last.chipset) &&
4272 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4273 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4274 for (i=ETH_ALEN-1; i>2; --i) {
4275 dev->dev_addr[i] += 1;
4276 if (dev->dev_addr[i] != 0) break;
4277 }
4278 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4279 if (!an_exception(lp)) {
4280 dev->irq = last.irq;
4281 }
4282
4283 status = 0;
4284 }
4285 } else if (!status) {
4286 last.chipset = lp->chipset;
4287 last.bus = lp->bus_num;
4288 last.irq = dev->irq;
4289 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4290 }
4291
4292 return status;
4293 }
4294
4295 /*
4296 ** List of board exceptions with correctly wired IRQs
4297 */
4298 static int
4299 an_exception(struct bus_type *lp)
4300 {
4301 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4302 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4303 return -1;
4304 }
4305
4306 return 0;
4307 }
4308
4309 /*
4310 ** SROM Read
4311 */
4312 static short
4313 srom_rd(u_long addr, u_char offset)
4314 {
4315 sendto_srom(SROM_RD | SROM_SR, addr);
4316
4317 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4318 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4319 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4320
4321 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4322 }
4323
4324 static void
4325 srom_latch(u_int command, u_long addr)
4326 {
4327 sendto_srom(command, addr);
4328 sendto_srom(command | DT_CLK, addr);
4329 sendto_srom(command, addr);
4330
4331 return;
4332 }
4333
4334 static void
4335 srom_command(u_int command, u_long addr)
4336 {
4337 srom_latch(command, addr);
4338 srom_latch(command, addr);
4339 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4340
4341 return;
4342 }
4343
4344 static void
4345 srom_address(u_int command, u_long addr, u_char offset)
4346 {
4347 int i, a;
4348
4349 a = offset << 2;
4350 for (i=0; i<6; i++, a <<= 1) {
4351 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4352 }
4353 udelay(1);
4354
4355 i = (getfrom_srom(addr) >> 3) & 0x01;
4356
4357 return;
4358 }
4359
4360 static short
4361 srom_data(u_int command, u_long addr)
4362 {
4363 int i;
4364 short word = 0;
4365 s32 tmp;
4366
4367 for (i=0; i<16; i++) {
4368 sendto_srom(command | DT_CLK, addr);
4369 tmp = getfrom_srom(addr);
4370 sendto_srom(command, addr);
4371
4372 word = (word << 1) | ((tmp >> 3) & 0x01);
4373 }
4374
4375 sendto_srom(command & 0x0000ff00, addr);
4376
4377 return word;
4378 }
4379
4380 /*
4381 static void
4382 srom_busy(u_int command, u_long addr)
4383 {
4384 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4385
4386 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4387 mdelay(1);
4388 }
4389
4390 sendto_srom(command & 0x0000ff00, addr);
4391
4392 return;
4393 }
4394 */
4395
4396 static void
4397 sendto_srom(u_int command, u_long addr)
4398 {
4399 outl(command, addr);
4400 udelay(1);
4401
4402 return;
4403 }
4404
4405 static int
4406 getfrom_srom(u_long addr)
4407 {
4408 s32 tmp;
4409
4410 tmp = inl(addr);
4411 udelay(1);
4412
4413 return tmp;
4414 }
4415
4416 static int
4417 srom_infoleaf_info(struct net_device *dev)
4418 {
4419 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4420 int i, count;
4421 u_char *p;
4422
4423 /* Find the infoleaf decoder function that matches this chipset */
4424 for (i=0; i<INFOLEAF_SIZE; i++) {
4425 if (lp->chipset == infoleaf_array[i].chipset) break;
4426 }
4427 if (i == INFOLEAF_SIZE) {
4428 lp->useSROM = FALSE;
4429 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4430 dev->name);
4431 return -ENXIO;
4432 }
4433
4434 lp->infoleaf_fn = infoleaf_array[i].fn;
4435
4436 /* Find the information offset that this function should use */
4437 count = *((u_char *)&lp->srom + 19);
4438 p = (u_char *)&lp->srom + 26;
4439
4440 if (count > 1) {
4441 for (i=count; i; --i, p+=3) {
4442 if (lp->device == *p) break;
4443 }
4444 if (i == 0) {
4445 lp->useSROM = FALSE;
4446 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4447 dev->name, lp->device);
4448 return -ENXIO;
4449 }
4450 }
4451
4452 lp->infoleaf_offset = TWIDDLE(p+1);
4453
4454 return 0;
4455 }
4456
4457 /*
4458 ** This routine loads any type 1 or 3 MII info into the mii device
4459 ** struct and executes any type 5 code to reset PHY devices for this
4460 ** controller.
4461 ** The info for the MII devices will be valid since the index used
4462 ** will follow the discovery process from MII address 1-31 then 0.
4463 */
4464 static void
4465 srom_init(struct net_device *dev)
4466 {
4467 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4468 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4469 u_char count;
4470
4471 p+=2;
4472 if (lp->chipset == DC21140) {
4473 lp->cache.gepc = (*p++ | GEP_CTRL);
4474 gep_wr(lp->cache.gepc, dev);
4475 }
4476
4477 /* Block count */
4478 count = *p++;
4479
4480 /* Jump the infoblocks to find types */
4481 for (;count; --count) {
4482 if (*p < 128) {
4483 p += COMPACT_LEN;
4484 } else if (*(p+1) == 5) {
4485 type5_infoblock(dev, 1, p);
4486 p += ((*p & BLOCK_LEN) + 1);
4487 } else if (*(p+1) == 4) {
4488 p += ((*p & BLOCK_LEN) + 1);
4489 } else if (*(p+1) == 3) {
4490 type3_infoblock(dev, 1, p);
4491 p += ((*p & BLOCK_LEN) + 1);
4492 } else if (*(p+1) == 2) {
4493 p += ((*p & BLOCK_LEN) + 1);
4494 } else if (*(p+1) == 1) {
4495 type1_infoblock(dev, 1, p);
4496 p += ((*p & BLOCK_LEN) + 1);
4497 } else {
4498 p += ((*p & BLOCK_LEN) + 1);
4499 }
4500 }
4501
4502 return;
4503 }
4504
4505 /*
4506 ** A generic routine that writes GEP control, data and reset information
4507 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4508 */
4509 static void
4510 srom_exec(struct net_device *dev, u_char *p)
4511 {
4512 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4513 u_long iobase = dev->base_addr;
4514 u_char count = (p ? *p++ : 0);
4515 u_short *w = (u_short *)p;
4516
4517 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4518
4519 if (lp->chipset != DC21140) RESET_SIA;
4520
4521 while (count--) {
4522 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4523 *p++ : TWIDDLE(w++)), dev);
4524 mdelay(2); /* 2ms per action */
4525 }
4526
4527 if (lp->chipset != DC21140) {
4528 outl(lp->cache.csr14, DE4X5_STRR);
4529 outl(lp->cache.csr13, DE4X5_SICR);
4530 }
4531
4532 return;
4533 }
4534
4535 /*
4536 ** Basically this function is a NOP since it will never be called,
4537 ** unless I implement the DC21041 SROM functions. There's no need
4538 ** since the existing code will be satisfactory for all boards.
4539 */
4540 static int
4541 dc21041_infoleaf(struct net_device *dev)
4542 {
4543 return DE4X5_AUTOSENSE_MS;
4544 }
4545
4546 static int
4547 dc21140_infoleaf(struct net_device *dev)
4548 {
4549 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4550 u_char count = 0;
4551 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4552 int next_tick = DE4X5_AUTOSENSE_MS;
4553
4554 /* Read the connection type */
4555 p+=2;
4556
4557 /* GEP control */
4558 lp->cache.gepc = (*p++ | GEP_CTRL);
4559
4560 /* Block count */
4561 count = *p++;
4562
4563 /* Recursively figure out the info blocks */
4564 if (*p < 128) {
4565 next_tick = dc_infoblock[COMPACT](dev, count, p);
4566 } else {
4567 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4568 }
4569
4570 if (lp->tcount == count) {
4571 lp->media = NC;
4572 if (lp->media != lp->c_media) {
4573 de4x5_dbg_media(dev);
4574 lp->c_media = lp->media;
4575 }
4576 lp->media = INIT;
4577 lp->tcount = 0;
4578 lp->tx_enable = FALSE;
4579 }
4580
4581 return next_tick & ~TIMER_CB;
4582 }
4583
4584 static int
4585 dc21142_infoleaf(struct net_device *dev)
4586 {
4587 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4588 u_char count = 0;
4589 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4590 int next_tick = DE4X5_AUTOSENSE_MS;
4591
4592 /* Read the connection type */
4593 p+=2;
4594
4595 /* Block count */
4596 count = *p++;
4597
4598 /* Recursively figure out the info blocks */
4599 if (*p < 128) {
4600 next_tick = dc_infoblock[COMPACT](dev, count, p);
4601 } else {
4602 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4603 }
4604
4605 if (lp->tcount == count) {
4606 lp->media = NC;
4607 if (lp->media != lp->c_media) {
4608 de4x5_dbg_media(dev);
4609 lp->c_media = lp->media;
4610 }
4611 lp->media = INIT;
4612 lp->tcount = 0;
4613 lp->tx_enable = FALSE;
4614 }
4615
4616 return next_tick & ~TIMER_CB;
4617 }
4618
4619 static int
4620 dc21143_infoleaf(struct net_device *dev)
4621 {
4622 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4623 u_char count = 0;
4624 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4625 int next_tick = DE4X5_AUTOSENSE_MS;
4626
4627 /* Read the connection type */
4628 p+=2;
4629
4630 /* Block count */
4631 count = *p++;
4632
4633 /* Recursively figure out the info blocks */
4634 if (*p < 128) {
4635 next_tick = dc_infoblock[COMPACT](dev, count, p);
4636 } else {
4637 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4638 }
4639 if (lp->tcount == count) {
4640 lp->media = NC;
4641 if (lp->media != lp->c_media) {
4642 de4x5_dbg_media(dev);
4643 lp->c_media = lp->media;
4644 }
4645 lp->media = INIT;
4646 lp->tcount = 0;
4647 lp->tx_enable = FALSE;
4648 }
4649
4650 return next_tick & ~TIMER_CB;
4651 }
4652
4653 /*
4654 ** The compact infoblock is only designed for DC21140[A] chips, so
4655 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4656 */
4657 static int
4658 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4659 {
4660 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4661 u_char flags, csr6;
4662
4663 /* Recursively figure out the info blocks */
4664 if (--count > lp->tcount) {
4665 if (*(p+COMPACT_LEN) < 128) {
4666 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4667 } else {
4668 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4669 }
4670 }
4671
4672 if ((lp->media == INIT) && (lp->timeout < 0)) {
4673 lp->ibn = COMPACT;
4674 lp->active = 0;
4675 gep_wr(lp->cache.gepc, dev);
4676 lp->infoblock_media = (*p++) & COMPACT_MC;
4677 lp->cache.gep = *p++;
4678 csr6 = *p++;
4679 flags = *p++;
4680
4681 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4682 lp->defMedium = (flags & 0x40) ? -1 : 0;
4683 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4684 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4685 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4686 lp->useMII = FALSE;
4687
4688 de4x5_switch_mac_port(dev);
4689 }
4690
4691 return dc21140m_autoconf(dev);
4692 }
4693
4694 /*
4695 ** This block describes non MII media for the DC21140[A] only.
4696 */
4697 static int
4698 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4699 {
4700 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4701 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4702
4703 /* Recursively figure out the info blocks */
4704 if (--count > lp->tcount) {
4705 if (*(p+len) < 128) {
4706 return dc_infoblock[COMPACT](dev, count, p+len);
4707 } else {
4708 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4709 }
4710 }
4711
4712 if ((lp->media == INIT) && (lp->timeout < 0)) {
4713 lp->ibn = 0;
4714 lp->active = 0;
4715 gep_wr(lp->cache.gepc, dev);
4716 p+=2;
4717 lp->infoblock_media = (*p++) & BLOCK0_MC;
4718 lp->cache.gep = *p++;
4719 csr6 = *p++;
4720 flags = *p++;
4721
4722 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4723 lp->defMedium = (flags & 0x40) ? -1 : 0;
4724 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4725 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4726 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4727 lp->useMII = FALSE;
4728
4729 de4x5_switch_mac_port(dev);
4730 }
4731
4732 return dc21140m_autoconf(dev);
4733 }
4734
4735 /* These functions are under construction! */
4736
4737 static int
4738 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4739 {
4740 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4741 u_char len = (*p & BLOCK_LEN)+1;
4742
4743 /* Recursively figure out the info blocks */
4744 if (--count > lp->tcount) {
4745 if (*(p+len) < 128) {
4746 return dc_infoblock[COMPACT](dev, count, p+len);
4747 } else {
4748 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4749 }
4750 }
4751
4752 p += 2;
4753 if (lp->state == INITIALISED) {
4754 lp->ibn = 1;
4755 lp->active = *p++;
4756 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4757 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4758 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4759 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4760 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4761 lp->phy[lp->active].ttm = TWIDDLE(p);
4762 return 0;
4763 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4764 lp->ibn = 1;
4765 lp->active = *p;
4766 lp->infoblock_csr6 = OMR_MII_100;
4767 lp->useMII = TRUE;
4768 lp->infoblock_media = ANS;
4769
4770 de4x5_switch_mac_port(dev);
4771 }
4772
4773 return dc21140m_autoconf(dev);
4774 }
4775
4776 static int
4777 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4778 {
4779 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4780 u_char len = (*p & BLOCK_LEN)+1;
4781
4782 /* Recursively figure out the info blocks */
4783 if (--count > lp->tcount) {
4784 if (*(p+len) < 128) {
4785 return dc_infoblock[COMPACT](dev, count, p+len);
4786 } else {
4787 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4788 }
4789 }
4790
4791 if ((lp->media == INIT) && (lp->timeout < 0)) {
4792 lp->ibn = 2;
4793 lp->active = 0;
4794 p += 2;
4795 lp->infoblock_media = (*p) & MEDIA_CODE;
4796
4797 if ((*p++) & EXT_FIELD) {
4798 lp->cache.csr13 = TWIDDLE(p); p += 2;
4799 lp->cache.csr14 = TWIDDLE(p); p += 2;
4800 lp->cache.csr15 = TWIDDLE(p); p += 2;
4801 } else {
4802 lp->cache.csr13 = CSR13;
4803 lp->cache.csr14 = CSR14;
4804 lp->cache.csr15 = CSR15;
4805 }
4806 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4807 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4808 lp->infoblock_csr6 = OMR_SIA;
4809 lp->useMII = FALSE;
4810
4811 de4x5_switch_mac_port(dev);
4812 }
4813
4814 return dc2114x_autoconf(dev);
4815 }
4816
4817 static int
4818 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4819 {
4820 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4821 u_char len = (*p & BLOCK_LEN)+1;
4822
4823 /* Recursively figure out the info blocks */
4824 if (--count > lp->tcount) {
4825 if (*(p+len) < 128) {
4826 return dc_infoblock[COMPACT](dev, count, p+len);
4827 } else {
4828 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4829 }
4830 }
4831
4832 p += 2;
4833 if (lp->state == INITIALISED) {
4834 lp->ibn = 3;
4835 lp->active = *p++;
4836 if (MOTO_SROM_BUG) lp->active = 0;
4837 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4838 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4839 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4840 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4841 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4842 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4843 lp->phy[lp->active].mci = *p;
4844 return 0;
4845 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4846 lp->ibn = 3;
4847 lp->active = *p;
4848 if (MOTO_SROM_BUG) lp->active = 0;
4849 lp->infoblock_csr6 = OMR_MII_100;
4850 lp->useMII = TRUE;
4851 lp->infoblock_media = ANS;
4852
4853 de4x5_switch_mac_port(dev);
4854 }
4855
4856 return dc2114x_autoconf(dev);
4857 }
4858
4859 static int
4860 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4861 {
4862 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4863 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4864
4865 /* Recursively figure out the info blocks */
4866 if (--count > lp->tcount) {
4867 if (*(p+len) < 128) {
4868 return dc_infoblock[COMPACT](dev, count, p+len);
4869 } else {
4870 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4871 }
4872 }
4873
4874 if ((lp->media == INIT) && (lp->timeout < 0)) {
4875 lp->ibn = 4;
4876 lp->active = 0;
4877 p+=2;
4878 lp->infoblock_media = (*p++) & MEDIA_CODE;
4879 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4880 lp->cache.csr14 = CSR14;
4881 lp->cache.csr15 = CSR15;
4882 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4883 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4884 csr6 = *p++;
4885 flags = *p++;
4886
4887 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4888 lp->defMedium = (flags & 0x40) ? -1 : 0;
4889 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4890 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4891 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4892 lp->useMII = FALSE;
4893
4894 de4x5_switch_mac_port(dev);
4895 }
4896
4897 return dc2114x_autoconf(dev);
4898 }
4899
4900 /*
4901 ** This block type provides information for resetting external devices
4902 ** (chips) through the General Purpose Register.
4903 */
4904 static int
4905 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4906 {
4907 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4908 u_char len = (*p & BLOCK_LEN)+1;
4909
4910 /* Recursively figure out the info blocks */
4911 if (--count > lp->tcount) {
4912 if (*(p+len) < 128) {
4913 return dc_infoblock[COMPACT](dev, count, p+len);
4914 } else {
4915 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4916 }
4917 }
4918
4919 /* Must be initializing to run this code */
4920 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4921 p+=2;
4922 lp->rst = p;
4923 srom_exec(dev, lp->rst);
4924 }
4925
4926 return DE4X5_AUTOSENSE_MS;
4927 }
4928
4929 /*
4930 ** MII Read/Write
4931 */
4932
4933 static int
4934 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4935 {
4936 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4937 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4938 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4939 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4940 mii_address(phyreg, ioaddr); /* PHY Register to read */
4941 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4942
4943 return mii_rdata(ioaddr); /* Read data */
4944 }
4945
4946 static void
4947 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4948 {
4949 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4950 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4951 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4952 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4953 mii_address(phyreg, ioaddr); /* PHY Register to write */
4954 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4955 data = mii_swap(data, 16); /* Swap data bit ordering */
4956 mii_wdata(data, 16, ioaddr); /* Write data */
4957
4958 return;
4959 }
4960
4961 static int
4962 mii_rdata(u_long ioaddr)
4963 {
4964 int i;
4965 s32 tmp = 0;
4966
4967 for (i=0; i<16; i++) {
4968 tmp <<= 1;
4969 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4970 }
4971
4972 return tmp;
4973 }
4974
4975 static void
4976 mii_wdata(int data, int len, u_long ioaddr)
4977 {
4978 int i;
4979
4980 for (i=0; i<len; i++) {
4981 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4982 data >>= 1;
4983 }
4984
4985 return;
4986 }
4987
4988 static void
4989 mii_address(u_char addr, u_long ioaddr)
4990 {
4991 int i;
4992
4993 addr = mii_swap(addr, 5);
4994 for (i=0; i<5; i++) {
4995 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4996 addr >>= 1;
4997 }
4998
4999 return;
5000 }
5001
5002 static void
5003 mii_ta(u_long rw, u_long ioaddr)
5004 {
5005 if (rw == MII_STWR) {
5006 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
5007 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
5008 } else {
5009 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
5010 }
5011
5012 return;
5013 }
5014
5015 static int
5016 mii_swap(int data, int len)
5017 {
5018 int i, tmp = 0;
5019
5020 for (i=0; i<len; i++) {
5021 tmp <<= 1;
5022 tmp |= (data & 1);
5023 data >>= 1;
5024 }
5025
5026 return tmp;
5027 }
5028
5029 static void
5030 sendto_mii(u32 command, int data, u_long ioaddr)
5031 {
5032 u32 j;
5033
5034 j = (data & 1) << 17;
5035 outl(command | j, ioaddr);
5036 udelay(1);
5037 outl(command | MII_MDC | j, ioaddr);
5038 udelay(1);
5039
5040 return;
5041 }
5042
5043 static int
5044 getfrom_mii(u32 command, u_long ioaddr)
5045 {
5046 outl(command, ioaddr);
5047 udelay(1);
5048 outl(command | MII_MDC, ioaddr);
5049 udelay(1);
5050
5051 return ((inl(ioaddr) >> 19) & 1);
5052 }
5053
5054 /*
5055 ** Here's 3 ways to calculate the OUI from the ID registers.
5056 */
5057 static int
5058 mii_get_oui(u_char phyaddr, u_long ioaddr)
5059 {
5060 /*
5061 union {
5062 u_short reg;
5063 u_char breg[2];
5064 } a;
5065 int i, r2, r3, ret=0;*/
5066 int r2, r3;
5067
5068 /* Read r2 and r3 */
5069 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5070 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5071 /* SEEQ and Cypress way * /
5072 / * Shuffle r2 and r3 * /
5073 a.reg=0;
5074 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5075 r2 = ((r2>>2)&0x3fff);
5076
5077 / * Bit reverse r3 * /
5078 for (i=0;i<8;i++) {
5079 ret<<=1;
5080 ret |= (r3&1);
5081 r3>>=1;
5082 }
5083
5084 / * Bit reverse r2 * /
5085 for (i=0;i<16;i++) {
5086 a.reg<<=1;
5087 a.reg |= (r2&1);
5088 r2>>=1;
5089 }
5090
5091 / * Swap r2 bytes * /
5092 i=a.breg[0];
5093 a.breg[0]=a.breg[1];
5094 a.breg[1]=i;
5095
5096 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5097 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5098 return r2; /* (I did it) My way */
5099 }
5100
5101 /*
5102 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5103 */
5104 static int
5105 mii_get_phy(struct net_device *dev)
5106 {
5107 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5108 u_long iobase = dev->base_addr;
5109 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5110 int id;
5111
5112 lp->active = 0;
5113 lp->useMII = TRUE;
5114
5115 /* Search the MII address space for possible PHY devices */
5116 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5117 lp->phy[lp->active].addr = i;
5118 if (i==0) n++; /* Count cycles */
5119 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5120 id = mii_get_oui(i, DE4X5_MII);
5121 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5122 for (j=0; j<limit; j++) { /* Search PHY table */
5123 if (id != phy_info[j].id) continue; /* ID match? */
5124 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5125 if (k < DE4X5_MAX_PHY) {
5126 memcpy((char *)&lp->phy[k],
5127 (char *)&phy_info[j], sizeof(struct phy_table));
5128 lp->phy[k].addr = i;
5129 lp->mii_cnt++;
5130 lp->active++;
5131 } else {
5132 goto purgatory; /* Stop the search */
5133 }
5134 break;
5135 }
5136 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5137 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5138 lp->phy[k].addr = i;
5139 lp->phy[k].id = id;
5140 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5141 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5142 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5143 lp->mii_cnt++;
5144 lp->active++;
5145 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5146 j = de4x5_debug;
5147 de4x5_debug |= DEBUG_MII;
5148 de4x5_dbg_mii(dev, k);
5149 de4x5_debug = j;
5150 printk("\n");
5151 }
5152 }
5153 purgatory:
5154 lp->active = 0;
5155 if (lp->phy[0].id) { /* Reset the PHY devices */
5156 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5157 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5158 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5159
5160 de4x5_dbg_mii(dev, k);
5161 }
5162 }
5163 if (!lp->mii_cnt) lp->useMII = FALSE;
5164
5165 return lp->mii_cnt;
5166 }
5167
5168 static char *
5169 build_setup_frame(struct net_device *dev, int mode)
5170 {
5171 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5172 int i;
5173 char *pa = lp->setup_frame;
5174
5175 /* Initialise the setup frame */
5176 if (mode == ALL) {
5177 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5178 }
5179
5180 if (lp->setup_f == HASH_PERF) {
5181 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5182 *(pa + i) = dev->dev_addr[i]; /* Host address */
5183 if (i & 0x01) pa += 2;
5184 }
5185 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5186 } else {
5187 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5188 *(pa + (i&1)) = dev->dev_addr[i];
5189 if (i & 0x01) pa += 4;
5190 }
5191 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5192 *(pa + (i&1)) = (char) 0xff;
5193 if (i & 0x01) pa += 4;
5194 }
5195 }
5196
5197 return pa; /* Points to the next entry */
5198 }
5199
5200 static void
5201 enable_ast(struct net_device *dev, u32 time_out)
5202 {
5203 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5204
5205 return;
5206 }
5207
5208 static void
5209 disable_ast(struct net_device *dev)
5210 {
5211 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5212
5213 del_timer(&lp->timer);
5214
5215 return;
5216 }
5217
5218 static long
5219 de4x5_switch_mac_port(struct net_device *dev)
5220 {
5221 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5222 u_long iobase = dev->base_addr;
5223 s32 omr;
5224
5225 STOP_DE4X5;
5226
5227 /* Assert the OMR_PS bit in CSR6 */
5228 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5229 OMR_FDX));
5230 omr |= lp->infoblock_csr6;
5231 if (omr & OMR_PS) omr |= OMR_HBD;
5232 outl(omr, DE4X5_OMR);
5233
5234 /* Soft Reset */
5235 RESET_DE4X5;
5236
5237 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5238 if (lp->chipset == DC21140) {
5239 gep_wr(lp->cache.gepc, dev);
5240 gep_wr(lp->cache.gep, dev);
5241 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5242 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5243 }
5244
5245 /* Restore CSR6 */
5246 outl(omr, DE4X5_OMR);
5247
5248 /* Reset CSR8 */
5249 inl(DE4X5_MFC);
5250
5251 return omr;
5252 }
5253
5254 static void
5255 gep_wr(s32 data, struct net_device *dev)
5256 {
5257 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5258 u_long iobase = dev->base_addr;
5259
5260 if (lp->chipset == DC21140) {
5261 outl(data, DE4X5_GEP);
5262 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5263 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5264 }
5265
5266 return;
5267 }
5268
5269 static int
5270 gep_rd(struct net_device *dev)
5271 {
5272 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5273 u_long iobase = dev->base_addr;
5274
5275 if (lp->chipset == DC21140) {
5276 return inl(DE4X5_GEP);
5277 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5278 return (inl(DE4X5_SIGR) & 0x000fffff);
5279 }
5280
5281 return 0;
5282 }
5283
5284 static void
5285 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5286 {
5287 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5288 int dt;
5289
5290 /* First, cancel any pending timer events */
5291 del_timer(&lp->timer);
5292
5293 /* Convert msec to ticks */
5294 dt = (msec * HZ) / 1000;
5295 if (dt==0) dt=1;
5296
5297 /* Set up timer */
5298 lp->timer.expires = jiffies + dt;
5299 lp->timer.function = fn;
5300 lp->timer.data = data;
5301 add_timer(&lp->timer);
5302
5303 return;
5304 }
5305
5306 static void
5307 yawn(struct net_device *dev, int state)
5308 {
5309 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5310 u_long iobase = dev->base_addr;
5311
5312 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5313
5314 if(lp->bus == EISA) {
5315 switch(state) {
5316 case WAKEUP:
5317 outb(WAKEUP, PCI_CFPM);
5318 mdelay(10);
5319 break;
5320
5321 case SNOOZE:
5322 outb(SNOOZE, PCI_CFPM);
5323 break;
5324
5325 case SLEEP:
5326 outl(0, DE4X5_SICR);
5327 outb(SLEEP, PCI_CFPM);
5328 break;
5329 }
5330 } else {
5331 switch(state) {
5332 case WAKEUP:
5333 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5334 PCI_CFDA_PSM, WAKEUP);
5335 mdelay(10);
5336 break;
5337
5338 case SNOOZE:
5339 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5340 PCI_CFDA_PSM, SNOOZE);
5341 break;
5342
5343 case SLEEP:
5344 outl(0, DE4X5_SICR);
5345 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5346 PCI_CFDA_PSM, SLEEP);
5347 break;
5348 }
5349 }
5350
5351 return;
5352 }
5353
5354 static void
5355 de4x5_parse_params(struct net_device *dev)
5356 {
5357 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5358 char *p, *q, t;
5359
5360 lp->params.fdx = 0;
5361 lp->params.autosense = AUTO;
5362
5363 if (args == NULL) return;
5364
5365 if ((p = strstr(args, dev->name))) {
5366 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5367 t = *q;
5368 *q = '\0';
5369
5370 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5371 if (strstr(p, "force_eisa") || strstr(p, "FORCE_EISA")) forceEISA = 1;
5372 #endif
5373 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5374
5375 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5376 if (strstr(p, "TP")) {
5377 lp->params.autosense = TP;
5378 } else if (strstr(p, "TP_NW")) {
5379 lp->params.autosense = TP_NW;
5380 } else if (strstr(p, "BNC")) {
5381 lp->params.autosense = BNC;
5382 } else if (strstr(p, "AUI")) {
5383 lp->params.autosense = AUI;
5384 } else if (strstr(p, "BNC_AUI")) {
5385 lp->params.autosense = BNC;
5386 } else if (strstr(p, "10Mb")) {
5387 lp->params.autosense = _10Mb;
5388 } else if (strstr(p, "100Mb")) {
5389 lp->params.autosense = _100Mb;
5390 } else if (strstr(p, "AUTO")) {
5391 lp->params.autosense = AUTO;
5392 }
5393 }
5394 *q = t;
5395 }
5396
5397 return;
5398 }
5399
5400 static void
5401 de4x5_dbg_open(struct net_device *dev)
5402 {
5403 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5404 int i;
5405
5406 if (de4x5_debug & DEBUG_OPEN) {
5407 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5408 printk("\tphysical address: ");
5409 for (i=0;i<6;i++) {
5410 printk("%2.2x:",(short)dev->dev_addr[i]);
5411 }
5412 printk("\n");
5413 printk("Descriptor head addresses:\n");
5414 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5415 printk("Descriptor addresses:\nRX: ");
5416 for (i=0;i<lp->rxRingSize-1;i++){
5417 if (i < 3) {
5418 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5419 }
5420 }
5421 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5422 printk("TX: ");
5423 for (i=0;i<lp->txRingSize-1;i++){
5424 if (i < 3) {
5425 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5426 }
5427 }
5428 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5429 printk("Descriptor buffers:\nRX: ");
5430 for (i=0;i<lp->rxRingSize-1;i++){
5431 if (i < 3) {
5432 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5433 }
5434 }
5435 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5436 printk("TX: ");
5437 for (i=0;i<lp->txRingSize-1;i++){
5438 if (i < 3) {
5439 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5440 }
5441 }
5442 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5443 printk("Ring size: \nRX: %d\nTX: %d\n",
5444 (short)lp->rxRingSize,
5445 (short)lp->txRingSize);
5446 }
5447
5448 return;
5449 }
5450
5451 static void
5452 de4x5_dbg_mii(struct net_device *dev, int k)
5453 {
5454 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5455 u_long iobase = dev->base_addr;
5456
5457 if (de4x5_debug & DEBUG_MII) {
5458 printk("\nMII device address: %d\n", lp->phy[k].addr);
5459 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5460 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5461 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5462 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5463 if (lp->phy[k].id != BROADCOM_T4) {
5464 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5465 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5466 }
5467 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5468 if (lp->phy[k].id != BROADCOM_T4) {
5469 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5470 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5471 } else {
5472 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5473 }
5474 }
5475
5476 return;
5477 }
5478
5479 static void
5480 de4x5_dbg_media(struct net_device *dev)
5481 {
5482 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5483
5484 if (lp->media != lp->c_media) {
5485 if (de4x5_debug & DEBUG_MEDIA) {
5486 printk("%s: media is %s%s\n", dev->name,
5487 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5488 (lp->media == TP ? "TP" :
5489 (lp->media == ANS ? "TP/Nway" :
5490 (lp->media == BNC ? "BNC" :
5491 (lp->media == AUI ? "AUI" :
5492 (lp->media == BNC_AUI ? "BNC/AUI" :
5493 (lp->media == EXT_SIA ? "EXT SIA" :
5494 (lp->media == _100Mb ? "100Mb/s" :
5495 (lp->media == _10Mb ? "10Mb/s" :
5496 "???"
5497 ))))))))), (lp->fdx?" full duplex.":"."));
5498 }
5499 lp->c_media = lp->media;
5500 }
5501
5502 return;
5503 }
5504
5505 static void
5506 de4x5_dbg_srom(struct de4x5_srom *p)
5507 {
5508 int i;
5509
5510 if (de4x5_debug & DEBUG_SROM) {
5511 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5512 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5513 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5514 printk("SROM version: %02x\n", (u_char)(p->version));
5515 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5516
5517 printk("Hardware Address: ");
5518 for (i=0;i<ETH_ALEN-1;i++) {
5519 printk("%02x:", (u_char)*(p->ieee_addr+i));
5520 }
5521 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5522 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5523 for (i=0; i<64; i++) {
5524 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5525 }
5526 }
5527
5528 return;
5529 }
5530
5531 static void
5532 de4x5_dbg_rx(struct sk_buff *skb, int len)
5533 {
5534 int i, j;
5535
5536 if (de4x5_debug & DEBUG_RX) {
5537 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5538 (u_char)skb->data[0],
5539 (u_char)skb->data[1],
5540 (u_char)skb->data[2],
5541 (u_char)skb->data[3],
5542 (u_char)skb->data[4],
5543 (u_char)skb->data[5],
5544 (u_char)skb->data[6],
5545 (u_char)skb->data[7],
5546 (u_char)skb->data[8],
5547 (u_char)skb->data[9],
5548 (u_char)skb->data[10],
5549 (u_char)skb->data[11],
5550 (u_char)skb->data[12],
5551 (u_char)skb->data[13],
5552 len);
5553 for (j=0; len>0;j+=16, len-=16) {
5554 printk(" %03x: ",j);
5555 for (i=0; i<16 && i<len; i++) {
5556 printk("%02x ",(u_char)skb->data[i+j]);
5557 }
5558 printk("\n");
5559 }
5560 }
5561
5562 return;
5563 }
5564
5565 /*
5566 ** Perform IOCTL call functions here. Some are privileged operations and the
5567 ** effective uid is checked in those cases. In the normal course of events
5568 ** this function is only used for my testing.
5569 */
5570 static int
5571 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5572 {
5573 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5574 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5575 u_long iobase = dev->base_addr;
5576 int i, j, status = 0;
5577 s32 omr;
5578 union {
5579 u8 addr[144];
5580 u16 sval[72];
5581 u32 lval[36];
5582 } tmp;
5583 u_long flags = 0;
5584
5585 switch(ioc->cmd) {
5586 case DE4X5_GET_HWADDR: /* Get the hardware address */
5587 ioc->len = ETH_ALEN;
5588 for (i=0; i<ETH_ALEN; i++) {
5589 tmp.addr[i] = dev->dev_addr[i];
5590 }
5591 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5592 break;
5593
5594 case DE4X5_SET_HWADDR: /* Set the hardware address */
5595 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5596 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5597 if (netif_queue_stopped(dev))
5598 return -EBUSY;
5599 netif_stop_queue(dev);
5600 for (i=0; i<ETH_ALEN; i++) {
5601 dev->dev_addr[i] = tmp.addr[i];
5602 }
5603 build_setup_frame(dev, PHYS_ADDR_ONLY);
5604 /* Set up the descriptor and give ownership to the card */
5605 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5606 SETUP_FRAME_LEN, (struct sk_buff *)1);
5607 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5608 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5609 netif_wake_queue(dev); /* Unlock the TX ring */
5610 break;
5611
5612 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5613 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5614 omr = inl(DE4X5_OMR);
5615 omr |= OMR_PR;
5616 outl(omr, DE4X5_OMR);
5617 dev->flags |= IFF_PROMISC;
5618 break;
5619
5620 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5621 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5622 omr = inl(DE4X5_OMR);
5623 omr &= ~OMR_PR;
5624 outb(omr, DE4X5_OMR);
5625 dev->flags &= ~IFF_PROMISC;
5626 break;
5627
5628 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5629 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5630 printk("%s: Boo!\n", dev->name);
5631 break;
5632
5633 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5634 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5635 omr = inl(DE4X5_OMR);
5636 omr |= OMR_PM;
5637 outl(omr, DE4X5_OMR);
5638 break;
5639
5640 case DE4X5_GET_STATS: /* Get the driver statistics */
5641 {
5642 struct pkt_stats statbuf;
5643 ioc->len = sizeof(statbuf);
5644 spin_lock_irqsave(&lp->lock, flags);
5645 memcpy(&statbuf, &lp->pktStats, ioc->len);
5646 spin_unlock_irqrestore(&lp->lock, flags);
5647 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5648 return -EFAULT;
5649 break;
5650 }
5651 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5652 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5653 spin_lock_irqsave(&lp->lock, flags);
5654 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5655 spin_unlock_irqrestore(&lp->lock, flags);
5656 break;
5657
5658 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5659 tmp.addr[0] = inl(DE4X5_OMR);
5660 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5661 break;
5662
5663 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5664 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5665 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5666 outl(tmp.addr[0], DE4X5_OMR);
5667 break;
5668
5669 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5670 j = 0;
5671 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5672 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5673 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5674 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5675 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5676 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5677 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5678 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5679 ioc->len = j;
5680 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5681 break;
5682
5683 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5684 /*
5685 case DE4X5_DUMP:
5686 j = 0;
5687 tmp.addr[j++] = dev->irq;
5688 for (i=0; i<ETH_ALEN; i++) {
5689 tmp.addr[j++] = dev->dev_addr[i];
5690 }
5691 tmp.addr[j++] = lp->rxRingSize;
5692 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5693 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5694
5695 for (i=0;i<lp->rxRingSize-1;i++){
5696 if (i < 3) {
5697 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5698 }
5699 }
5700 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5701 for (i=0;i<lp->txRingSize-1;i++){
5702 if (i < 3) {
5703 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5704 }
5705 }
5706 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5707
5708 for (i=0;i<lp->rxRingSize-1;i++){
5709 if (i < 3) {
5710 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5711 }
5712 }
5713 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5714 for (i=0;i<lp->txRingSize-1;i++){
5715 if (i < 3) {
5716 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5717 }
5718 }
5719 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5720
5721 for (i=0;i<lp->rxRingSize;i++){
5722 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5723 }
5724 for (i=0;i<lp->txRingSize;i++){
5725 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5726 }
5727
5728 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5729 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5730 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5731 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5732 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5733 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5734 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5735 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5736 tmp.lval[j>>2] = lp->chipset; j+=4;
5737 if (lp->chipset == DC21140) {
5738 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5739 } else {
5740 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5741 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5742 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5743 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5744 }
5745 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5746 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5747 tmp.lval[j>>2] = lp->active; j+=4;
5748 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5749 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5750 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5751 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5752 if (lp->phy[lp->active].id != BROADCOM_T4) {
5753 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5754 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5755 }
5756 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5757 if (lp->phy[lp->active].id != BROADCOM_T4) {
5758 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5759 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5760 } else {
5761 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5762 }
5763 }
5764
5765 tmp.addr[j++] = lp->txRingSize;
5766 tmp.addr[j++] = netif_queue_stopped(dev);
5767
5768 ioc->len = j;
5769 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5770 break;
5771
5772 */
5773 default:
5774 return -EOPNOTSUPP;
5775 }
5776
5777 return status;
5778 }
5779
5780 #ifdef MODULE
5781 /*
5782 ** Note now that module autoprobing is allowed under EISA and PCI. The
5783 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5784 ** to "do the right thing".
5785 */
5786 #define LP(a) ((struct de4x5_private *)(a))
5787 static struct net_device *mdev = NULL;
5788 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5789 MODULE_PARM(io, "i");
5790 MODULE_PARM_DESC(io, "de4x5 I/O base address");
5791
5792 int
5793 init_module(void)
5794 {
5795 int i, num, status = -EIO;
5796 struct net_device *p;
5797
5798 num = count_adapters();
5799
5800 for (i=0; i<num; i++) {
5801 if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5802 return -ENOMEM;
5803
5804 if (!mdev) mdev = p;
5805
5806 if (register_netdev(p) != 0) {
5807 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5808 if (lp) {
5809 release_region(p->base_addr, (lp->bus == PCI ?
5810 DE4X5_PCI_TOTAL_SIZE :
5811 DE4X5_EISA_TOTAL_SIZE));
5812 if (lp->cache.priv) { /* Private area allocated? */
5813 kfree(lp->cache.priv); /* Free the private area */
5814 }
5815 if (lp->rx_ring) {
5816 pci_free_consistent(lp->pdev, lp->dma_size, lp->rx_ring,
5817 lp->dma_rings);
5818 }
5819 }
5820 kfree(p);
5821 } else {
5822 status = 0; /* At least one adapter will work */
5823 lastModule = p;
5824 }
5825 }
5826
5827 return status;
5828 }
5829
5830 void
5831 cleanup_module(void)
5832 {
5833 while (mdev != NULL) {
5834 mdev = unlink_modules(mdev);
5835 }
5836
5837 return;
5838 }
5839
5840 static struct net_device *
5841 unlink_modules(struct net_device *p)
5842 {
5843 struct net_device *next = NULL;
5844
5845 if (p->priv) { /* Private areas allocated? */
5846 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5847
5848 next = lp->next_module;
5849 if (lp->rx_ring) {
5850 pci_free_consistent(lp->pdev, lp->dma_size, lp->rx_ring,
5851 lp->dma_rings);
5852 }
5853 release_region(p->base_addr, (lp->bus == PCI ?
5854 DE4X5_PCI_TOTAL_SIZE :
5855 DE4X5_EISA_TOTAL_SIZE));
5856 kfree(lp->cache.priv); /* Free the private area */
5857 }
5858 unregister_netdev(p);
5859 kfree(p); /* Free the device structure */
5860
5861 return next;
5862 }
5863
5864 static int
5865 count_adapters(void)
5866 {
5867 int i, j=0;
5868 u_short vendor;
5869 u_int class = DE4X5_CLASS_CODE;
5870 u_int device;
5871
5872 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5873 char name[DE4X5_STRLEN];
5874 u_long iobase = 0x1000;
5875
5876 for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5877 if (EISA_signature(name, EISA_ID)) j++;
5878 }
5879 #endif
5880 if (!pcibios_present()) return j;
5881
5882 for (i=0; (pdev=pci_find_class(class, pdev))!= NULL; i++) {
5883 vendor = pdev->vendor;
5884 device = pdev->device << 8;
5885 if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5886 }
5887
5888 return j;
5889 }
5890
5891 /*
5892 ** If at end of eth device list and can't use current entry, malloc
5893 ** one up. If memory could not be allocated, print an error message.
5894 */
5895 static struct net_device * __init
5896 insert_device(struct net_device *dev, u_long iobase, int (*init)(struct net_device *))
5897 {
5898 struct net_device *new;
5899
5900 new = (struct net_device *)kmalloc(sizeof(struct net_device), GFP_KERNEL);
5901 if (new == NULL) {
5902 printk("de4x5.c: Device not initialised, insufficient memory\n");
5903 return NULL;
5904 } else {
5905 memset((char *)new, 0, sizeof(struct net_device));
5906 new->base_addr = iobase; /* assign the io address */
5907 new->init = init; /* initialisation routine */
5908 }
5909
5910 return new;
5911 }
5912
5913 #endif /* MODULE */
5914
5915
5916 /*
5917 * Local variables:
5918 *
5919 * Delete -DMODVERSIONS below if you didn't define this in your kernel
5920 *
5921 * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -DMODVERSIONS -include /linux/include/linux/modversions.h -c de4x5.c"
5922 * End:
5923 */
5924