File: /usr/src/linux/drivers/net/defxx.c
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * Maintainers:
19 * LVS Lawrence V. Stefani
20 *
21 * Contact:
22 * The author may be reached at:
23 *
24 * Inet: stefani@lkg.dec.com
25 * (NOTE! this address no longer works -jgarzik)
26 *
27 * Mail: Digital Equipment Corporation
28 * 550 King Street
29 * M/S: LKG1-3/M07
30 * Littleton, MA 01460
31 *
32 * Credits:
33 * I'd like to thank Patricia Cross for helping me get started with
34 * Linux, David Davies for a lot of help upgrading and configuring
35 * my development system and for answering many OS and driver
36 * development questions, and Alan Cox for recommendations and
37 * integration help on getting FDDI support into Linux. LVS
38 *
39 * Driver Architecture:
40 * The driver architecture is largely based on previous driver work
41 * for other operating systems. The upper edge interface and
42 * functions were largely taken from existing Linux device drivers
43 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
44 * driver.
45 *
46 * Adapter Probe -
47 * The driver scans for supported EISA adapters by reading the
48 * SLOT ID register for each EISA slot and making a match
49 * against the expected value.
50 *
51 * Bus-Specific Initialization -
52 * This driver currently supports both EISA and PCI controller
53 * families. While the custom DMA chip and FDDI logic is similar
54 * or identical, the bus logic is very different. After
55 * initialization, the only bus-specific differences is in how the
56 * driver enables and disables interrupts. Other than that, the
57 * run-time critical code behaves the same on both families.
58 * It's important to note that both adapter families are configured
59 * to I/O map, rather than memory map, the adapter registers.
60 *
61 * Driver Open/Close -
62 * In the driver open routine, the driver ISR (interrupt service
63 * routine) is registered and the adapter is brought to an
64 * operational state. In the driver close routine, the opposite
65 * occurs; the driver ISR is deregistered and the adapter is
66 * brought to a safe, but closed state. Users may use consecutive
67 * commands to bring the adapter up and down as in the following
68 * example:
69 * ifconfig fddi0 up
70 * ifconfig fddi0 down
71 * ifconfig fddi0 up
72 *
73 * Driver Shutdown -
74 * Apparently, there is no shutdown or halt routine support under
75 * Linux. This routine would be called during "reboot" or
76 * "shutdown" to allow the driver to place the adapter in a safe
77 * state before a warm reboot occurs. To be really safe, the user
78 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
79 * to ensure that the adapter DMA engine is taken off-line. However,
80 * the current driver code anticipates this problem and always issues
81 * a soft reset of the adapter at the beginning of driver initialization.
82 * A future driver enhancement in this area may occur in 2.1.X where
83 * Alan indicated that a shutdown handler may be implemented.
84 *
85 * Interrupt Service Routine -
86 * The driver supports shared interrupts, so the ISR is registered for
87 * each board with the appropriate flag and the pointer to that board's
88 * device structure. This provides the context during interrupt
89 * processing to support shared interrupts and multiple boards.
90 *
91 * Interrupt enabling/disabling can occur at many levels. At the host
92 * end, you can disable system interrupts, or disable interrupts at the
93 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
94 * have a bus-logic chip interrupt enable/disable as well as a DMA
95 * controller interrupt enable/disable.
96 *
97 * The driver currently enables and disables adapter interrupts at the
98 * bus-logic chip and assumes that Linux will take care of clearing or
99 * acknowledging any host-based interrupt chips.
100 *
101 * Control Functions -
102 * Control functions are those used to support functions such as adding
103 * or deleting multicast addresses, enabling or disabling packet
104 * reception filters, or other custom/proprietary commands. Presently,
105 * the driver supports the "get statistics", "set multicast list", and
106 * "set mac address" functions defined by Linux. A list of possible
107 * enhancements include:
108 *
109 * - Custom ioctl interface for executing port interface commands
110 * - Custom ioctl interface for adding unicast addresses to
111 * adapter CAM (to support bridge functions).
112 * - Custom ioctl interface for supporting firmware upgrades.
113 *
114 * Hardware (port interface) Support Routines -
115 * The driver function names that start with "dfx_hw_" represent
116 * low-level port interface routines that are called frequently. They
117 * include issuing a DMA or port control command to the adapter,
118 * resetting the adapter, or reading the adapter state. Since the
119 * driver initialization and run-time code must make calls into the
120 * port interface, these routines were written to be as generic and
121 * usable as possible.
122 *
123 * Receive Path -
124 * The adapter DMA engine supports a 256 entry receive descriptor block
125 * of which up to 255 entries can be used at any given time. The
126 * architecture is a standard producer, consumer, completion model in
127 * which the driver "produces" receive buffers to the adapter, the
128 * adapter "consumes" the receive buffers by DMAing incoming packet data,
129 * and the driver "completes" the receive buffers by servicing the
130 * incoming packet, then "produces" a new buffer and starts the cycle
131 * again. Receive buffers can be fragmented in up to 16 fragments
132 * (descriptor entries). For simplicity, this driver posts
133 * single-fragment receive buffers of 4608 bytes, then allocates a
134 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
135 * utilization, a better approach would be to pass up the receive
136 * buffer (no extra copy) then allocate and post a replacement buffer.
137 * This is a performance enhancement that should be looked into at
138 * some point.
139 *
140 * Transmit Path -
141 * Like the receive path, the adapter DMA engine supports a 256 entry
142 * transmit descriptor block of which up to 255 entries can be used at
143 * any given time. Transmit buffers can be fragmented in up to 255
144 * fragments (descriptor entries). This driver always posts one
145 * fragment per transmit packet request.
146 *
147 * The fragment contains the entire packet from FC to end of data.
148 * Before posting the buffer to the adapter, the driver sets a three-byte
149 * packet request header (PRH) which is required by the Motorola MAC chip
150 * used on the adapters. The PRH tells the MAC the type of token to
151 * receive/send, whether or not to generate and append the CRC, whether
152 * synchronous or asynchronous framing is used, etc. Since the PRH
153 * definition is not necessarily consistent across all FDDI chipsets,
154 * the driver, rather than the common FDDI packet handler routines,
155 * sets these bytes.
156 *
157 * To reduce the amount of descriptor fetches needed per transmit request,
158 * the driver takes advantage of the fact that there are at least three
159 * bytes available before the skb->data field on the outgoing transmit
160 * request. This is guaranteed by having fddi_setup() in net_init.c set
161 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
162 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
163 * bytes which we'll use to store the PRH.
164 *
165 * There's a subtle advantage to adding these pad bytes to the
166 * hard_header_len, it ensures that the data portion of the packet for
167 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
168 * implementations may not need the extra padding and can start copying
169 * or DMAing directly from the FC byte which starts at skb->data. Should
170 * another driver implementation need ADDITIONAL padding, the net_init.c
171 * module should be updated and dev->hard_header_len should be increased.
172 * NOTE: To maintain the alignment on the data portion of the packet,
173 * dev->hard_header_len should always be evenly divisible by 4 and at
174 * least 24 bytes in size.
175 *
176 * Modification History:
177 * Date Name Description
178 * 16-Aug-96 LVS Created.
179 * 20-Aug-96 LVS Updated dfx_probe so that version information
180 * string is only displayed if 1 or more cards are
181 * found. Changed dfx_rcv_queue_process to copy
182 * 3 NULL bytes before FC to ensure that data is
183 * longword aligned in receive buffer.
184 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
185 * LLC group promiscuous mode if multicast list
186 * is too large. LLC individual/group promiscuous
187 * mode is now disabled if IFF_PROMISC flag not set.
188 * dfx_xmt_queue_pkt no longer checks for NULL skb
189 * on Alan Cox recommendation. Added node address
190 * override support.
191 * 12-Sep-96 LVS Reset current address to factory address during
192 * device open. Updated transmit path to post a
193 * single fragment which includes PRH->end of data.
194 * Mar 2000 AC Did various cleanups for 2.3.x
195 * Jun 2000 jgarzik PCI and resource alloc cleanups
196 * Jul 2000 tjeerd Much cleanup and some bug fixes
197 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
198 * Feb 2001 Skb allocation fixes
199 * Feb 2001 davej PCI enable cleanups.
200 */
201
202 /* Include files */
203
204 #include <linux/module.h>
205
206 #include <linux/kernel.h>
207 #include <linux/sched.h>
208 #include <linux/string.h>
209 #include <linux/ptrace.h>
210 #include <linux/errno.h>
211 #include <linux/ioport.h>
212 #include <linux/slab.h>
213 #include <linux/interrupt.h>
214 #include <linux/pci.h>
215 #include <linux/delay.h>
216 #include <linux/init.h>
217 #include <linux/netdevice.h>
218 #include <asm/byteorder.h>
219 #include <asm/bitops.h>
220 #include <asm/io.h>
221
222 #include <linux/fddidevice.h>
223 #include <linux/skbuff.h>
224
225 #include "defxx.h"
226
227 /* Version information string - should be updated prior to each new release!!! */
228
229 static char version[] __devinitdata =
230 "defxx.c:v1.05e 2001/02/03 Lawrence V. Stefani and others\n";
231
232 #define DYNAMIC_BUFFERS 1
233
234 #define SKBUFF_RX_COPYBREAK 200
235 /*
236 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
237 * alignment for compatibility with old EISA boards.
238 */
239 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
240
241 /* Define module-wide (static) routines */
242
243 static void dfx_bus_init(struct net_device *dev);
244 static void dfx_bus_config_check(DFX_board_t *bp);
245
246 static int dfx_driver_init(struct net_device *dev);
247 static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
248
249 static int dfx_open(struct net_device *dev);
250 static int dfx_close(struct net_device *dev);
251
252 static void dfx_int_pr_halt_id(DFX_board_t *bp);
253 static void dfx_int_type_0_process(DFX_board_t *bp);
254 static void dfx_int_common(struct net_device *dev);
255 static void dfx_interrupt(int irq, void *dev_id, struct pt_regs *regs);
256
257 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
258 static void dfx_ctl_set_multicast_list(struct net_device *dev);
259 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
260 static int dfx_ctl_update_cam(DFX_board_t *bp);
261 static int dfx_ctl_update_filters(DFX_board_t *bp);
262
263 static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
264 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
265 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
266 static int dfx_hw_adap_state_rd(DFX_board_t *bp);
267 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
268
269 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
270 static void dfx_rcv_queue_process(DFX_board_t *bp);
271 static void dfx_rcv_flush(DFX_board_t *bp);
272
273 static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
274 static int dfx_xmt_done(DFX_board_t *bp);
275 static void dfx_xmt_flush(DFX_board_t *bp);
276
277 /* Define module-wide (static) variables */
278
279 static struct net_device *root_dfx_eisa_dev;
280
281
282 /*
283 * =======================
284 * = dfx_port_write_byte =
285 * = dfx_port_read_byte =
286 * = dfx_port_write_long =
287 * = dfx_port_read_long =
288 * =======================
289 *
290 * Overview:
291 * Routines for reading and writing values from/to adapter
292 *
293 * Returns:
294 * None
295 *
296 * Arguments:
297 * bp - pointer to board information
298 * offset - register offset from base I/O address
299 * data - for dfx_port_write_byte and dfx_port_write_long, this
300 * is a value to write.
301 * for dfx_port_read_byte and dfx_port_read_byte, this
302 * is a pointer to store the read value.
303 *
304 * Functional Description:
305 * These routines perform the correct operation to read or write
306 * the adapter register.
307 *
308 * EISA port block base addresses are based on the slot number in which the
309 * controller is installed. For example, if the EISA controller is installed
310 * in slot 4, the port block base address is 0x4000. If the controller is
311 * installed in slot 2, the port block base address is 0x2000, and so on.
312 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
313 * registers using the register offsets defined in DEFXX.H.
314 *
315 * PCI port block base addresses are assigned by the PCI BIOS or system
316 * firmware. There is one 128 byte port block which can be accessed. It
317 * allows for I/O mapping of both PDQ and PFI registers using the register
318 * offsets defined in DEFXX.H.
319 *
320 * Return Codes:
321 * None
322 *
323 * Assumptions:
324 * bp->base_addr is a valid base I/O address for this adapter.
325 * offset is a valid register offset for this adapter.
326 *
327 * Side Effects:
328 * Rather than produce macros for these functions, these routines
329 * are defined using "inline" to ensure that the compiler will
330 * generate inline code and not waste a procedure call and return.
331 * This provides all the benefits of macros, but with the
332 * advantage of strict data type checking.
333 */
334
335 static inline void dfx_port_write_byte(
336 DFX_board_t *bp,
337 int offset,
338 u8 data
339 )
340
341 {
342 u16 port = bp->base_addr + offset;
343
344 outb(data, port);
345 }
346
347 static inline void dfx_port_read_byte(
348 DFX_board_t *bp,
349 int offset,
350 u8 *data
351 )
352
353 {
354 u16 port = bp->base_addr + offset;
355
356 *data = inb(port);
357 }
358
359 static inline void dfx_port_write_long(
360 DFX_board_t *bp,
361 int offset,
362 u32 data
363 )
364
365 {
366 u16 port = bp->base_addr + offset;
367
368 outl(data, port);
369 }
370
371 static inline void dfx_port_read_long(
372 DFX_board_t *bp,
373 int offset,
374 u32 *data
375 )
376
377 {
378 u16 port = bp->base_addr + offset;
379
380 *data = inl(port);
381 }
382
383
384 /*
385 * =============
386 * = dfx_init_one_pci_or_eisa =
387 * =============
388 *
389 * Overview:
390 * Initializes a supported FDDI EISA or PCI controller
391 *
392 * Returns:
393 * Condition code
394 *
395 * Arguments:
396 * pdev - pointer to pci device information (NULL for EISA)
397 * ioaddr - pointer to port (NULL for PCI)
398 *
399 * Functional Description:
400 *
401 * Return Codes:
402 * 0 - This device (fddi0, fddi1, etc) configured successfully
403 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
404 *
405 * Assumptions:
406 * It compiles so it should work :-( (PCI cards do :-)
407 *
408 * Side Effects:
409 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
410 * initialized and the board resources are read and stored in
411 * the device structure.
412 */
413 static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr)
414 {
415 struct net_device *dev;
416 DFX_board_t *bp; /* board pointer */
417 int err;
418
419 #ifndef MODULE
420 static int version_disp;
421
422 if (!version_disp) /* display version info if adapter is found */
423 {
424 version_disp = 1; /* set display flag to TRUE so that */
425 printk(version); /* we only display this string ONCE */
426 }
427 #endif
428
429 /*
430 * init_fddidev() allocates a device structure with private data, clears the device structure and private data,
431 * and calls fddi_setup() and register_netdev(). Not much left to do for us here.
432 */
433 dev = init_fddidev(NULL, sizeof(*bp));
434 if (!dev) {
435 printk (KERN_ERR "defxx: unable to allocate fddidev, aborting\n");
436 return -ENOMEM;
437 }
438
439 /* Enable PCI device. */
440 if (pdev != NULL) {
441 err = pci_enable_device (pdev);
442 if (err) goto err_out;
443 ioaddr = pci_resource_start (pdev, 1);
444 }
445
446 SET_MODULE_OWNER(dev);
447
448 bp = dev->priv;
449
450 if (!request_region (ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, dev->name)) {
451 printk (KERN_ERR "%s: Cannot reserve I/O resource 0x%x @ 0x%lx, aborting\n",
452 dev->name, PFI_K_CSR_IO_LEN, ioaddr);
453 err = -EBUSY;
454 goto err_out;
455 }
456
457 /* Initialize new device structure */
458
459 dev->base_addr = ioaddr; /* save port (I/O) base address */
460
461 dev->get_stats = dfx_ctl_get_stats;
462 dev->open = dfx_open;
463 dev->stop = dfx_close;
464 dev->hard_start_xmit = dfx_xmt_queue_pkt;
465 dev->set_multicast_list = dfx_ctl_set_multicast_list;
466 dev->set_mac_address = dfx_ctl_set_mac_address;
467
468 if (pdev == NULL) {
469 /* EISA board */
470 bp->bus_type = DFX_BUS_TYPE_EISA;
471 bp->next = root_dfx_eisa_dev;
472 root_dfx_eisa_dev = dev;
473 } else {
474 /* PCI board */
475 bp->bus_type = DFX_BUS_TYPE_PCI;
476 bp->pci_dev = pdev;
477 pci_set_drvdata (pdev, dev);
478 pci_set_master (pdev);
479 }
480
481 if (dfx_driver_init(dev) != DFX_K_SUCCESS) {
482 err = -ENODEV;
483 goto err_out_region;
484 }
485
486 return 0;
487
488 err_out_region:
489 release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN);
490 err_out:
491 unregister_netdev(dev);
492 kfree(dev);
493 return err;
494 }
495
496 static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
497 {
498 return dfx_init_one_pci_or_eisa(pdev, 0);
499 }
500
501 static int __init dfx_eisa_init(void)
502 {
503 int rc = -NODEV;
504 int i; /* used in for loops */
505 u16 port; /* temporary I/O (port) address */
506 u32 slot_id; /* EISA hardware (slot) ID read from adapter */
507
508 DBG_printk("In dfx_eisa_init...\n");
509
510 /* Scan for FDDI EISA controllers */
511
512 for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */
513 {
514 port = (i << 12) + PI_ESIC_K_SLOT_ID; /* port = I/O address for reading slot ID */
515 slot_id = inl(port); /* read EISA HW (slot) ID */
516 if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID)
517 {
518 port = (i << 12); /* recalc base addr */
519
520 if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0;
521 }
522 }
523 return rc;
524 }
525
526 /*
527 * ================
528 * = dfx_bus_init =
529 * ================
530 *
531 * Overview:
532 * Initializes EISA and PCI controller bus-specific logic.
533 *
534 * Returns:
535 * None
536 *
537 * Arguments:
538 * dev - pointer to device information
539 *
540 * Functional Description:
541 * Determine and save adapter IRQ in device table,
542 * then perform bus-specific logic initialization.
543 *
544 * Return Codes:
545 * None
546 *
547 * Assumptions:
548 * dev->base_addr has already been set with the proper
549 * base I/O address for this device.
550 *
551 * Side Effects:
552 * Interrupts are enabled at the adapter bus-specific logic.
553 * Note: Interrupts at the DMA engine (PDQ chip) are not
554 * enabled yet.
555 */
556
557 static void __devinit dfx_bus_init(struct net_device *dev)
558 {
559 DFX_board_t *bp = dev->priv;
560 u8 val; /* used for I/O read/writes */
561
562 DBG_printk("In dfx_bus_init...\n");
563
564 /*
565 * Initialize base I/O address field in bp structure
566 *
567 * Note: bp->base_addr is the same as dev->base_addr.
568 * It's useful because often we'll need to read
569 * or write registers where we already have the
570 * bp pointer instead of the dev pointer. Having
571 * the base address in the bp structure will
572 * save a pointer dereference.
573 *
574 * IMPORTANT!! This field must be defined before
575 * any of the dfx_port_* inline functions are
576 * called.
577 */
578
579 bp->base_addr = dev->base_addr;
580
581 /* And a pointer back to the net_device struct */
582 bp->dev = dev;
583
584 /* Initialize adapter based on bus type */
585
586 if (bp->bus_type == DFX_BUS_TYPE_EISA)
587 {
588 /* Get the interrupt level from the ESIC chip */
589
590 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
591 switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ)
592 {
593 case PI_CONFIG_STAT_0_IRQ_K_9:
594 dev->irq = 9;
595 break;
596
597 case PI_CONFIG_STAT_0_IRQ_K_10:
598 dev->irq = 10;
599 break;
600
601 case PI_CONFIG_STAT_0_IRQ_K_11:
602 dev->irq = 11;
603 break;
604
605 case PI_CONFIG_STAT_0_IRQ_K_15:
606 dev->irq = 15;
607 break;
608 }
609
610 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
611
612 dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB);
613
614 /* Set the I/O decode range of the board */
615
616 val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT);
617 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val);
618 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val);
619
620 /* Enable access to rest of module (including PDQ and packet memory) */
621
622 dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB);
623
624 /*
625 * Map PDQ registers into I/O space. This is done by clearing a bit
626 * in Burst Holdoff register.
627 */
628
629 dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val);
630 dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP));
631
632 /* Enable interrupts at EISA bus interface chip (ESIC) */
633
634 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
635 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB));
636 }
637 else
638 {
639 struct pci_dev *pdev = bp->pci_dev;
640
641 /* Get the interrupt level from the PCI Configuration Table */
642
643 dev->irq = pdev->irq;
644
645 /* Check Latency Timer and set if less than minimal */
646
647 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
648 if (val < PFI_K_LAT_TIMER_MIN) /* if less than min, override with default */
649 {
650 val = PFI_K_LAT_TIMER_DEF;
651 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
652 }
653
654 /* Enable interrupts at PCI bus interface chip (PFI) */
655
656 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB));
657 }
658 }
659
660
661 /*
662 * ========================
663 * = dfx_bus_config_check =
664 * ========================
665 *
666 * Overview:
667 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
668 * are illegal, then this routine will set new defaults.
669 *
670 * Returns:
671 * None
672 *
673 * Arguments:
674 * bp - pointer to board information
675 *
676 * Functional Description:
677 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
678 * PDQ, and all FDDI PCI controllers, all values are legal.
679 *
680 * Return Codes:
681 * None
682 *
683 * Assumptions:
684 * dfx_adap_init has NOT been called yet so burst size and other items have
685 * not been set.
686 *
687 * Side Effects:
688 * None
689 */
690
691 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
692 {
693 int status; /* return code from adapter port control call */
694 u32 slot_id; /* EISA-bus hardware id (DEC3001, DEC3002,...) */
695 u32 host_data; /* LW data returned from port control call */
696
697 DBG_printk("In dfx_bus_config_check...\n");
698
699 /* Configuration check only valid for EISA adapter */
700
701 if (bp->bus_type == DFX_BUS_TYPE_EISA)
702 {
703 dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id);
704
705 /*
706 * First check if revision 2 EISA controller. Rev. 1 cards used
707 * PDQ revision B, so no workaround needed in this case. Rev. 3
708 * cards used PDQ revision E, so no workaround needed in this
709 * case, either. Only Rev. 2 cards used either Rev. D or E
710 * chips, so we must verify the chip revision on Rev. 2 cards.
711 */
712
713 if (slot_id == DEFEA_PROD_ID_2)
714 {
715 /*
716 * Revision 2 FDDI EISA controller found, so let's check PDQ
717 * revision of adapter.
718 */
719
720 status = dfx_hw_port_ctrl_req(bp,
721 PI_PCTRL_M_SUB_CMD,
722 PI_SUB_CMD_K_PDQ_REV_GET,
723 0,
724 &host_data);
725 if ((status != DFX_K_SUCCESS) || (host_data == 2))
726 {
727 /*
728 * Either we couldn't determine the PDQ revision, or
729 * we determined that it is at revision D. In either case,
730 * we need to implement the workaround.
731 */
732
733 /* Ensure that the burst size is set to 8 longwords or less */
734
735 switch (bp->burst_size)
736 {
737 case PI_PDATA_B_DMA_BURST_SIZE_32:
738 case PI_PDATA_B_DMA_BURST_SIZE_16:
739 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
740 break;
741
742 default:
743 break;
744 }
745
746 /* Ensure that full-duplex mode is not enabled */
747
748 bp->full_duplex_enb = PI_SNMP_K_FALSE;
749 }
750 }
751 }
752 }
753
754
755 /*
756 * ===================
757 * = dfx_driver_init =
758 * ===================
759 *
760 * Overview:
761 * Initializes remaining adapter board structure information
762 * and makes sure adapter is in a safe state prior to dfx_open().
763 *
764 * Returns:
765 * Condition code
766 *
767 * Arguments:
768 * dev - pointer to device information
769 *
770 * Functional Description:
771 * This function allocates additional resources such as the host memory
772 * blocks needed by the adapter (eg. descriptor and consumer blocks).
773 * Remaining bus initialization steps are also completed. The adapter
774 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
775 * must call dfx_open() to open the adapter and bring it on-line.
776 *
777 * Return Codes:
778 * DFX_K_SUCCESS - initialization succeeded
779 * DFX_K_FAILURE - initialization failed - could not allocate memory
780 * or read adapter MAC address
781 *
782 * Assumptions:
783 * Memory allocated from kmalloc() call is physically contiguous, locked
784 * memory whose physical address equals its virtual address.
785 *
786 * Side Effects:
787 * Adapter is reset and should be in DMA_UNAVAILABLE state before
788 * returning from this routine.
789 */
790
791 static int __devinit dfx_driver_init(struct net_device *dev)
792 {
793 DFX_board_t *bp = dev->priv;
794 int alloc_size; /* total buffer size needed */
795 char *top_v, *curr_v; /* virtual addrs into memory block */
796 u32 top_p, curr_p; /* physical addrs into memory block */
797 u32 data; /* host data register value */
798
799 DBG_printk("In dfx_driver_init...\n");
800
801 /* Initialize bus-specific hardware registers */
802
803 dfx_bus_init(dev);
804
805 /*
806 * Initialize default values for configurable parameters
807 *
808 * Note: All of these parameters are ones that a user may
809 * want to customize. It'd be nice to break these
810 * out into Space.c or someplace else that's more
811 * accessible/understandable than this file.
812 */
813
814 bp->full_duplex_enb = PI_SNMP_K_FALSE;
815 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
816 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
817 bp->rcv_bufs_to_post = RCV_BUFS_DEF;
818
819 /*
820 * Ensure that HW configuration is OK
821 *
822 * Note: Depending on the hardware revision, we may need to modify
823 * some of the configurable parameters to workaround hardware
824 * limitations. We'll perform this configuration check AFTER
825 * setting the parameters to their default values.
826 */
827
828 dfx_bus_config_check(bp);
829
830 /* Disable PDQ interrupts first */
831
832 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
833
834 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
835
836 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
837
838 /* Read the factory MAC address from the adapter then save it */
839
840 if (dfx_hw_port_ctrl_req(bp,
841 PI_PCTRL_M_MLA,
842 PI_PDATA_A_MLA_K_LO,
843 0,
844 &data) != DFX_K_SUCCESS)
845 {
846 printk("%s: Could not read adapter factory MAC address!\n", dev->name);
847 return(DFX_K_FAILURE);
848 }
849 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
850
851 if (dfx_hw_port_ctrl_req(bp,
852 PI_PCTRL_M_MLA,
853 PI_PDATA_A_MLA_K_HI,
854 0,
855 &data) != DFX_K_SUCCESS)
856 {
857 printk("%s: Could not read adapter factory MAC address!\n", dev->name);
858 return(DFX_K_FAILURE);
859 }
860 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
861
862 /*
863 * Set current address to factory address
864 *
865 * Note: Node address override support is handled through
866 * dfx_ctl_set_mac_address.
867 */
868
869 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
870 if (bp->bus_type == DFX_BUS_TYPE_EISA)
871 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
872 dev->name,
873 dev->base_addr,
874 dev->irq,
875 dev->dev_addr[0],
876 dev->dev_addr[1],
877 dev->dev_addr[2],
878 dev->dev_addr[3],
879 dev->dev_addr[4],
880 dev->dev_addr[5]);
881 else
882 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
883 dev->name,
884 dev->base_addr,
885 dev->irq,
886 dev->dev_addr[0],
887 dev->dev_addr[1],
888 dev->dev_addr[2],
889 dev->dev_addr[3],
890 dev->dev_addr[4],
891 dev->dev_addr[5]);
892
893 /*
894 * Get memory for descriptor block, consumer block, and other buffers
895 * that need to be DMA read or written to by the adapter.
896 */
897
898 alloc_size = sizeof(PI_DESCR_BLOCK) +
899 PI_CMD_REQ_K_SIZE_MAX +
900 PI_CMD_RSP_K_SIZE_MAX +
901 #ifndef DYNAMIC_BUFFERS
902 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
903 #endif
904 sizeof(PI_CONSUMER_BLOCK) +
905 (PI_ALIGN_K_DESC_BLK - 1);
906 bp->kmalloced = top_v = (char *) kmalloc(alloc_size, GFP_KERNEL);
907 if (top_v == NULL)
908 {
909 printk("%s: Could not allocate memory for host buffers and structures!\n", dev->name);
910 return(DFX_K_FAILURE);
911 }
912 memset(top_v, 0, alloc_size); /* zero out memory before continuing */
913 top_p = virt_to_bus(top_v); /* get physical address of buffer */
914
915 /*
916 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
917 * plus the amount of memory needed was allocated. The physical address
918 * is now 8K aligned. By carving up the memory in a specific order,
919 * we'll guarantee the alignment requirements for all other structures.
920 *
921 * Note: If the assumptions change regarding the non-paged, non-cached,
922 * physically contiguous nature of the memory block or the address
923 * alignments, then we'll need to implement a different algorithm
924 * for allocating the needed memory.
925 */
926
927 curr_p = (u32) (ALIGN(top_p, PI_ALIGN_K_DESC_BLK));
928 curr_v = top_v + (curr_p - top_p);
929
930 /* Reserve space for descriptor block */
931
932 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
933 bp->descr_block_phys = curr_p;
934 curr_v += sizeof(PI_DESCR_BLOCK);
935 curr_p += sizeof(PI_DESCR_BLOCK);
936
937 /* Reserve space for command request buffer */
938
939 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
940 bp->cmd_req_phys = curr_p;
941 curr_v += PI_CMD_REQ_K_SIZE_MAX;
942 curr_p += PI_CMD_REQ_K_SIZE_MAX;
943
944 /* Reserve space for command response buffer */
945
946 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
947 bp->cmd_rsp_phys = curr_p;
948 curr_v += PI_CMD_RSP_K_SIZE_MAX;
949 curr_p += PI_CMD_RSP_K_SIZE_MAX;
950
951 /* Reserve space for the LLC host receive queue buffers */
952
953 bp->rcv_block_virt = curr_v;
954 bp->rcv_block_phys = curr_p;
955
956 #ifndef DYNAMIC_BUFFERS
957 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
958 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
959 #endif
960
961 /* Reserve space for the consumer block */
962
963 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
964 bp->cons_block_phys = curr_p;
965
966 /* Display virtual and physical addresses if debug driver */
967
968 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys);
969 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
970 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
971 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
972 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys);
973
974 return(DFX_K_SUCCESS);
975 }
976
977
978 /*
979 * =================
980 * = dfx_adap_init =
981 * =================
982 *
983 * Overview:
984 * Brings the adapter to the link avail/link unavailable state.
985 *
986 * Returns:
987 * Condition code
988 *
989 * Arguments:
990 * bp - pointer to board information
991 * get_buffers - non-zero if buffers to be allocated
992 *
993 * Functional Description:
994 * Issues the low-level firmware/hardware calls necessary to bring
995 * the adapter up, or to properly reset and restore adapter during
996 * run-time.
997 *
998 * Return Codes:
999 * DFX_K_SUCCESS - Adapter brought up successfully
1000 * DFX_K_FAILURE - Adapter initialization failed
1001 *
1002 * Assumptions:
1003 * bp->reset_type should be set to a valid reset type value before
1004 * calling this routine.
1005 *
1006 * Side Effects:
1007 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1008 * upon a successful return of this routine.
1009 */
1010
1011 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1012 {
1013 DBG_printk("In dfx_adap_init...\n");
1014
1015 /* Disable PDQ interrupts first */
1016
1017 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1018
1019 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1020
1021 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1022 {
1023 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1024 return(DFX_K_FAILURE);
1025 }
1026
1027 /*
1028 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1029 * so we'll acknowledge all Type 0 interrupts now before continuing.
1030 */
1031
1032 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1033
1034 /*
1035 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1036 *
1037 * Note: We only need to clear host copies of these registers. The PDQ reset
1038 * takes care of the on-board register values.
1039 */
1040
1041 bp->cmd_req_reg.lword = 0;
1042 bp->cmd_rsp_reg.lword = 0;
1043 bp->rcv_xmt_reg.lword = 0;
1044
1045 /* Clear consumer block before going to DMA_AVAILABLE state */
1046
1047 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1048
1049 /* Initialize the DMA Burst Size */
1050
1051 if (dfx_hw_port_ctrl_req(bp,
1052 PI_PCTRL_M_SUB_CMD,
1053 PI_SUB_CMD_K_BURST_SIZE_SET,
1054 bp->burst_size,
1055 NULL) != DFX_K_SUCCESS)
1056 {
1057 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1058 return(DFX_K_FAILURE);
1059 }
1060
1061 /*
1062 * Set base address of Consumer Block
1063 *
1064 * Assumption: 32-bit physical address of consumer block is 64 byte
1065 * aligned. That is, bits 0-5 of the address must be zero.
1066 */
1067
1068 if (dfx_hw_port_ctrl_req(bp,
1069 PI_PCTRL_M_CONS_BLOCK,
1070 bp->cons_block_phys,
1071 0,
1072 NULL) != DFX_K_SUCCESS)
1073 {
1074 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1075 return(DFX_K_FAILURE);
1076 }
1077
1078 /*
1079 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1080 *
1081 * Note: We also set the literal and data swapping requirements in this
1082 * command. Since this driver presently runs on Intel platforms
1083 * which are Little Endian, we'll tell the adapter to byte swap
1084 * data only. This code will need to change when we support
1085 * Big Endian systems (eg. PowerPC).
1086 *
1087 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1088 * aligned. That is, bits 0-12 of the address must be zero.
1089 */
1090
1091 if (dfx_hw_port_ctrl_req(bp,
1092 PI_PCTRL_M_INIT,
1093 (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA),
1094 0,
1095 NULL) != DFX_K_SUCCESS)
1096 {
1097 printk("%s: Could not set descriptor block address!\n", bp->dev->name);
1098 return(DFX_K_FAILURE);
1099 }
1100
1101 /* Set transmit flush timeout value */
1102
1103 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1104 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
1105 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
1106 bp->cmd_req_virt->char_set.item[0].item_index = 0;
1107 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
1108 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1109 {
1110 printk("%s: DMA command request failed!\n", bp->dev->name);
1111 return(DFX_K_FAILURE);
1112 }
1113
1114 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1115
1116 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1117 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
1118 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
1119 bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
1120 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
1121 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
1122 bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
1123 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
1124 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1125 {
1126 printk("%s: DMA command request failed!\n", bp->dev->name);
1127 return(DFX_K_FAILURE);
1128 }
1129
1130 /* Initialize adapter CAM */
1131
1132 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1133 {
1134 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1135 return(DFX_K_FAILURE);
1136 }
1137
1138 /* Initialize adapter filters */
1139
1140 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1141 {
1142 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1143 return(DFX_K_FAILURE);
1144 }
1145
1146 /*
1147 * Remove any existing dynamic buffers (i.e. if the adapter is being
1148 * reinitialized)
1149 */
1150
1151 if (get_buffers)
1152 dfx_rcv_flush(bp);
1153
1154 /* Initialize receive descriptor block and produce buffers */
1155
1156 if (dfx_rcv_init(bp, get_buffers))
1157 {
1158 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1159 if (get_buffers)
1160 dfx_rcv_flush(bp);
1161 return(DFX_K_FAILURE);
1162 }
1163
1164 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1165
1166 bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1167 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1168 {
1169 printk("%s: Start command failed\n", bp->dev->name);
1170 if (get_buffers)
1171 dfx_rcv_flush(bp);
1172 return(DFX_K_FAILURE);
1173 }
1174
1175 /* Initialization succeeded, reenable PDQ interrupts */
1176
1177 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1178 return(DFX_K_SUCCESS);
1179 }
1180
1181
1182 /*
1183 * ============
1184 * = dfx_open =
1185 * ============
1186 *
1187 * Overview:
1188 * Opens the adapter
1189 *
1190 * Returns:
1191 * Condition code
1192 *
1193 * Arguments:
1194 * dev - pointer to device information
1195 *
1196 * Functional Description:
1197 * This function brings the adapter to an operational state.
1198 *
1199 * Return Codes:
1200 * 0 - Adapter was successfully opened
1201 * -EAGAIN - Could not register IRQ or adapter initialization failed
1202 *
1203 * Assumptions:
1204 * This routine should only be called for a device that was
1205 * initialized successfully.
1206 *
1207 * Side Effects:
1208 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1209 * if the open is successful.
1210 */
1211
1212 static int dfx_open(struct net_device *dev)
1213 {
1214 int ret;
1215 DFX_board_t *bp = dev->priv;
1216
1217 DBG_printk("In dfx_open...\n");
1218
1219 /* Register IRQ - support shared interrupts by passing device ptr */
1220
1221 ret = request_irq(dev->irq, (void *)dfx_interrupt, SA_SHIRQ, dev->name, dev);
1222 if (ret) {
1223 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1224 return ret;
1225 }
1226
1227 /*
1228 * Set current address to factory MAC address
1229 *
1230 * Note: We've already done this step in dfx_driver_init.
1231 * However, it's possible that a user has set a node
1232 * address override, then closed and reopened the
1233 * adapter. Unless we reset the device address field
1234 * now, we'll continue to use the existing modified
1235 * address.
1236 */
1237
1238 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1239
1240 /* Clear local unicast/multicast address tables and counts */
1241
1242 memset(bp->uc_table, 0, sizeof(bp->uc_table));
1243 memset(bp->mc_table, 0, sizeof(bp->mc_table));
1244 bp->uc_count = 0;
1245 bp->mc_count = 0;
1246
1247 /* Disable promiscuous filter settings */
1248
1249 bp->ind_group_prom = PI_FSTATE_K_BLOCK;
1250 bp->group_prom = PI_FSTATE_K_BLOCK;
1251
1252 spin_lock_init(&bp->lock);
1253
1254 /* Reset and initialize adapter */
1255
1256 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
1257 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1258 {
1259 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1260 free_irq(dev->irq, dev);
1261 return -EAGAIN;
1262 }
1263
1264 /* Set device structure info */
1265 netif_start_queue(dev);
1266 return(0);
1267 }
1268
1269
1270 /*
1271 * =============
1272 * = dfx_close =
1273 * =============
1274 *
1275 * Overview:
1276 * Closes the device/module.
1277 *
1278 * Returns:
1279 * Condition code
1280 *
1281 * Arguments:
1282 * dev - pointer to device information
1283 *
1284 * Functional Description:
1285 * This routine closes the adapter and brings it to a safe state.
1286 * The interrupt service routine is deregistered with the OS.
1287 * The adapter can be opened again with another call to dfx_open().
1288 *
1289 * Return Codes:
1290 * Always return 0.
1291 *
1292 * Assumptions:
1293 * No further requests for this adapter are made after this routine is
1294 * called. dfx_open() can be called to reset and reinitialize the
1295 * adapter.
1296 *
1297 * Side Effects:
1298 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1299 * routine.
1300 */
1301
1302 static int dfx_close(struct net_device *dev)
1303 {
1304 DFX_board_t *bp = dev->priv;
1305
1306 DBG_printk("In dfx_close...\n");
1307
1308 /* Disable PDQ interrupts first */
1309
1310 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1311
1312 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1313
1314 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1315
1316 /*
1317 * Flush any pending transmit buffers
1318 *
1319 * Note: It's important that we flush the transmit buffers
1320 * BEFORE we clear our copy of the Type 2 register.
1321 * Otherwise, we'll have no idea how many buffers
1322 * we need to free.
1323 */
1324
1325 dfx_xmt_flush(bp);
1326
1327 /*
1328 * Clear Type 1 and Type 2 registers after adapter reset
1329 *
1330 * Note: Even though we're closing the adapter, it's
1331 * possible that an interrupt will occur after
1332 * dfx_close is called. Without some assurance to
1333 * the contrary we want to make sure that we don't
1334 * process receive and transmit LLC frames and update
1335 * the Type 2 register with bad information.
1336 */
1337
1338 bp->cmd_req_reg.lword = 0;
1339 bp->cmd_rsp_reg.lword = 0;
1340 bp->rcv_xmt_reg.lword = 0;
1341
1342 /* Clear consumer block for the same reason given above */
1343
1344 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1345
1346 /* Release all dynamically allocate skb in the receive ring. */
1347
1348 dfx_rcv_flush(bp);
1349
1350 /* Clear device structure flags */
1351
1352 netif_stop_queue(dev);
1353
1354 /* Deregister (free) IRQ */
1355
1356 free_irq(dev->irq, dev);
1357
1358 return(0);
1359 }
1360
1361
1362 /*
1363 * ======================
1364 * = dfx_int_pr_halt_id =
1365 * ======================
1366 *
1367 * Overview:
1368 * Displays halt id's in string form.
1369 *
1370 * Returns:
1371 * None
1372 *
1373 * Arguments:
1374 * bp - pointer to board information
1375 *
1376 * Functional Description:
1377 * Determine current halt id and display appropriate string.
1378 *
1379 * Return Codes:
1380 * None
1381 *
1382 * Assumptions:
1383 * None
1384 *
1385 * Side Effects:
1386 * None
1387 */
1388
1389 static void dfx_int_pr_halt_id(DFX_board_t *bp)
1390 {
1391 PI_UINT32 port_status; /* PDQ port status register value */
1392 PI_UINT32 halt_id; /* PDQ port status halt ID */
1393
1394 /* Read the latest port status */
1395
1396 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1397
1398 /* Display halt state transition information */
1399
1400 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1401 switch (halt_id)
1402 {
1403 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1404 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1405 break;
1406
1407 case PI_HALT_ID_K_PARITY_ERROR:
1408 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1409 break;
1410
1411 case PI_HALT_ID_K_HOST_DIR_HALT:
1412 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1413 break;
1414
1415 case PI_HALT_ID_K_SW_FAULT:
1416 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1417 break;
1418
1419 case PI_HALT_ID_K_HW_FAULT:
1420 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1421 break;
1422
1423 case PI_HALT_ID_K_PC_TRACE:
1424 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1425 break;
1426
1427 case PI_HALT_ID_K_DMA_ERROR:
1428 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1429 break;
1430
1431 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1432 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1433 break;
1434
1435 case PI_HALT_ID_K_BUS_EXCEPTION:
1436 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1437 break;
1438
1439 default:
1440 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1441 break;
1442 }
1443 }
1444
1445
1446 /*
1447 * ==========================
1448 * = dfx_int_type_0_process =
1449 * ==========================
1450 *
1451 * Overview:
1452 * Processes Type 0 interrupts.
1453 *
1454 * Returns:
1455 * None
1456 *
1457 * Arguments:
1458 * bp - pointer to board information
1459 *
1460 * Functional Description:
1461 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1462 * is a serious fault on the adapter, then an error message is displayed
1463 * and the adapter is reset.
1464 *
1465 * One tricky potential timing window is the rapid succession of "link avail"
1466 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1467 * interrupt must be done before reading the state from the Port Status
1468 * register. This is true because a state change could occur after reading
1469 * the data, but before acknowledging the interrupt. If this state change
1470 * does happen, it would be lost because the driver is using the old state,
1471 * and it will never know about the new state because it subsequently
1472 * acknowledges the state change interrupt.
1473 *
1474 * INCORRECT CORRECT
1475 * read type 0 int reasons read type 0 int reasons
1476 * read adapter state ack type 0 interrupts
1477 * ack type 0 interrupts read adapter state
1478 * ... process interrupt ... ... process interrupt ...
1479 *
1480 * Return Codes:
1481 * None
1482 *
1483 * Assumptions:
1484 * None
1485 *
1486 * Side Effects:
1487 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1488 * or if the port status indicates that the adapter is halted. The driver
1489 * is responsible for reinitializing the adapter with the current CAM
1490 * contents and adapter filter settings.
1491 */
1492
1493 static void dfx_int_type_0_process(DFX_board_t *bp)
1494
1495 {
1496 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
1497 PI_UINT32 state; /* current adap state (from port status) */
1498
1499 /*
1500 * Read host interrupt Type 0 register to determine which Type 0
1501 * interrupts are pending. Immediately write it back out to clear
1502 * those interrupts.
1503 */
1504
1505 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1506 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1507
1508 /* Check for Type 0 error interrupts */
1509
1510 if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1511 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1512 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1513 {
1514 /* Check for Non-Existent Memory error */
1515
1516 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1517 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1518
1519 /* Check for Packet Memory Parity error */
1520
1521 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1522 printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1523
1524 /* Check for Host Bus Parity error */
1525
1526 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1527 printk("%s: Host Bus Parity Error\n", bp->dev->name);
1528
1529 /* Reset adapter and bring it back on-line */
1530
1531 bp->link_available = PI_K_FALSE; /* link is no longer available */
1532 bp->reset_type = 0; /* rerun on-board diagnostics */
1533 printk("%s: Resetting adapter...\n", bp->dev->name);
1534 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1535 {
1536 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1537 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1538 return;
1539 }
1540 printk("%s: Adapter reset successful!\n", bp->dev->name);
1541 return;
1542 }
1543
1544 /* Check for transmit flush interrupt */
1545
1546 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1547 {
1548 /* Flush any pending xmt's and acknowledge the flush interrupt */
1549
1550 bp->link_available = PI_K_FALSE; /* link is no longer available */
1551 dfx_xmt_flush(bp); /* flush any outstanding packets */
1552 (void) dfx_hw_port_ctrl_req(bp,
1553 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1554 0,
1555 0,
1556 NULL);
1557 }
1558
1559 /* Check for adapter state change */
1560
1561 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1562 {
1563 /* Get latest adapter state */
1564
1565 state = dfx_hw_adap_state_rd(bp); /* get adapter state */
1566 if (state == PI_STATE_K_HALTED)
1567 {
1568 /*
1569 * Adapter has transitioned to HALTED state, try to reset
1570 * adapter to bring it back on-line. If reset fails,
1571 * leave the adapter in the broken state.
1572 */
1573
1574 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1575 dfx_int_pr_halt_id(bp); /* display halt id as string */
1576
1577 /* Reset adapter and bring it back on-line */
1578
1579 bp->link_available = PI_K_FALSE; /* link is no longer available */
1580 bp->reset_type = 0; /* rerun on-board diagnostics */
1581 printk("%s: Resetting adapter...\n", bp->dev->name);
1582 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1583 {
1584 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1585 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1586 return;
1587 }
1588 printk("%s: Adapter reset successful!\n", bp->dev->name);
1589 }
1590 else if (state == PI_STATE_K_LINK_AVAIL)
1591 {
1592 bp->link_available = PI_K_TRUE; /* set link available flag */
1593 }
1594 }
1595 }
1596
1597
1598 /*
1599 * ==================
1600 * = dfx_int_common =
1601 * ==================
1602 *
1603 * Overview:
1604 * Interrupt service routine (ISR)
1605 *
1606 * Returns:
1607 * None
1608 *
1609 * Arguments:
1610 * bp - pointer to board information
1611 *
1612 * Functional Description:
1613 * This is the ISR which processes incoming adapter interrupts.
1614 *
1615 * Return Codes:
1616 * None
1617 *
1618 * Assumptions:
1619 * This routine assumes PDQ interrupts have not been disabled.
1620 * When interrupts are disabled at the PDQ, the Port Status register
1621 * is automatically cleared. This routine uses the Port Status
1622 * register value to determine whether a Type 0 interrupt occurred,
1623 * so it's important that adapter interrupts are not normally
1624 * enabled/disabled at the PDQ.
1625 *
1626 * It's vital that this routine is NOT reentered for the
1627 * same board and that the OS is not in another section of
1628 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1629 * different thread.
1630 *
1631 * Side Effects:
1632 * Pending interrupts are serviced. Depending on the type of
1633 * interrupt, acknowledging and clearing the interrupt at the
1634 * PDQ involves writing a register to clear the interrupt bit
1635 * or updating completion indices.
1636 */
1637
1638 static void dfx_int_common(struct net_device *dev)
1639 {
1640 DFX_board_t *bp = dev->priv;
1641 PI_UINT32 port_status; /* Port Status register */
1642
1643 /* Process xmt interrupts - frequent case, so always call this routine */
1644
1645 if(dfx_xmt_done(bp)) /* free consumed xmt packets */
1646 netif_wake_queue(dev);
1647
1648 /* Process rcv interrupts - frequent case, so always call this routine */
1649
1650 dfx_rcv_queue_process(bp); /* service received LLC frames */
1651
1652 /*
1653 * Transmit and receive producer and completion indices are updated on the
1654 * adapter by writing to the Type 2 Producer register. Since the frequent
1655 * case is that we'll be processing either LLC transmit or receive buffers,
1656 * we'll optimize I/O writes by doing a single register write here.
1657 */
1658
1659 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1660
1661 /* Read PDQ Port Status register to find out which interrupts need processing */
1662
1663 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1664
1665 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1666
1667 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1668 dfx_int_type_0_process(bp); /* process Type 0 interrupts */
1669 }
1670
1671
1672 /*
1673 * =================
1674 * = dfx_interrupt =
1675 * =================
1676 *
1677 * Overview:
1678 * Interrupt processing routine
1679 *
1680 * Returns:
1681 * None
1682 *
1683 * Arguments:
1684 * irq - interrupt vector
1685 * dev_id - pointer to device information
1686 * regs - pointer to registers structure
1687 *
1688 * Functional Description:
1689 * This routine calls the interrupt processing routine for this adapter. It
1690 * disables and reenables adapter interrupts, as appropriate. We can support
1691 * shared interrupts since the incoming dev_id pointer provides our device
1692 * structure context.
1693 *
1694 * Return Codes:
1695 * None
1696 *
1697 * Assumptions:
1698 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1699 * on Intel-based systems) is done by the operating system outside this
1700 * routine.
1701 *
1702 * System interrupts are enabled through this call.
1703 *
1704 * Side Effects:
1705 * Interrupts are disabled, then reenabled at the adapter.
1706 */
1707
1708 static void dfx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1709 {
1710 struct net_device *dev = dev_id;
1711 DFX_board_t *bp; /* private board structure pointer */
1712 u8 tmp; /* used for disabling/enabling ints */
1713
1714 /* Get board pointer only if device structure is valid */
1715
1716 bp = dev->priv;
1717
1718 spin_lock(&bp->lock);
1719
1720 /* See if we're already servicing an interrupt */
1721
1722 /* Service adapter interrupts */
1723
1724 if (bp->bus_type == DFX_BUS_TYPE_PCI)
1725 {
1726 /* Disable PDQ-PFI interrupts at PFI */
1727
1728 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, PFI_MODE_M_DMA_ENB);
1729
1730 /* Call interrupt service routine for this adapter */
1731
1732 dfx_int_common(dev);
1733
1734 /* Clear PDQ interrupt status bit and reenable interrupts */
1735
1736 dfx_port_write_long(bp, PFI_K_REG_STATUS, PFI_STATUS_M_PDQ_INT);
1737 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1738 (PFI_MODE_M_PDQ_INT_ENB + PFI_MODE_M_DMA_ENB));
1739 }
1740 else
1741 {
1742 /* Disable interrupts at the ESIC */
1743
1744 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &tmp);
1745 tmp &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1746 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, tmp);
1747
1748 /* Call interrupt service routine for this adapter */
1749
1750 dfx_int_common(dev);
1751
1752 /* Reenable interrupts at the ESIC */
1753
1754 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &tmp);
1755 tmp |= PI_CONFIG_STAT_0_M_INT_ENB;
1756 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, tmp);
1757 }
1758
1759 spin_unlock(&bp->lock);
1760 }
1761
1762
1763 /*
1764 * =====================
1765 * = dfx_ctl_get_stats =
1766 * =====================
1767 *
1768 * Overview:
1769 * Get statistics for FDDI adapter
1770 *
1771 * Returns:
1772 * Pointer to FDDI statistics structure
1773 *
1774 * Arguments:
1775 * dev - pointer to device information
1776 *
1777 * Functional Description:
1778 * Gets current MIB objects from adapter, then
1779 * returns FDDI statistics structure as defined
1780 * in if_fddi.h.
1781 *
1782 * Note: Since the FDDI statistics structure is
1783 * still new and the device structure doesn't
1784 * have an FDDI-specific get statistics handler,
1785 * we'll return the FDDI statistics structure as
1786 * a pointer to an Ethernet statistics structure.
1787 * That way, at least the first part of the statistics
1788 * structure can be decoded properly, and it allows
1789 * "smart" applications to perform a second cast to
1790 * decode the FDDI-specific statistics.
1791 *
1792 * We'll have to pay attention to this routine as the
1793 * device structure becomes more mature and LAN media
1794 * independent.
1795 *
1796 * Return Codes:
1797 * None
1798 *
1799 * Assumptions:
1800 * None
1801 *
1802 * Side Effects:
1803 * None
1804 */
1805
1806 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
1807 {
1808 DFX_board_t *bp = dev->priv;
1809
1810 /* Fill the bp->stats structure with driver-maintained counters */
1811
1812 bp->stats.rx_packets = bp->rcv_total_frames;
1813 bp->stats.tx_packets = bp->xmt_total_frames;
1814 bp->stats.rx_bytes = bp->rcv_total_bytes;
1815 bp->stats.tx_bytes = bp->xmt_total_bytes;
1816 bp->stats.rx_errors = (u32)(bp->rcv_crc_errors + bp->rcv_frame_status_errors + bp->rcv_length_errors);
1817 bp->stats.tx_errors = bp->xmt_length_errors;
1818 bp->stats.rx_dropped = bp->rcv_discards;
1819 bp->stats.tx_dropped = bp->xmt_discards;
1820 bp->stats.multicast = bp->rcv_multicast_frames;
1821 bp->stats.transmit_collision = 0; /* always zero (0) for FDDI */
1822
1823 /* Get FDDI SMT MIB objects */
1824
1825 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
1826 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1827 return((struct net_device_stats *) &bp->stats);
1828
1829 /* Fill the bp->stats structure with the SMT MIB object values */
1830
1831 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1832 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
1833 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
1834 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
1835 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1836 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
1837 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
1838 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
1839 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
1840 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
1841 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
1842 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
1843 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
1844 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
1845 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
1846 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
1847 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
1848 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
1849 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
1850 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1851 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
1852 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
1853 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
1854 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1855 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1856 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
1857 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
1858 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
1859 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
1860 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1861 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1862 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1863 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1864 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
1865 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
1866 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
1867 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1868 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
1869 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
1870 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
1871 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
1872 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
1873 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
1874 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
1875 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
1876 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
1877 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
1878 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
1879 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
1880 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
1881 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
1882 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
1883 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
1884 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1885 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
1886 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
1887 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
1888 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
1889 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1890 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1891 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
1892 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
1893 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
1894 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
1895 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1896 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1897 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
1898 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
1899 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
1900 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
1901 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
1902 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
1903 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1904 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1905 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
1906 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
1907 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
1908 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
1909 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
1910 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
1911 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
1912 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
1913 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
1914 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
1915 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
1916 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
1917 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
1918 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
1919 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
1920 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
1921 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
1922 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
1923
1924 /* Get FDDI counters */
1925
1926 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
1927 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1928 return((struct net_device_stats *) &bp->stats);
1929
1930 /* Fill the bp->stats structure with the FDDI counter values */
1931
1932 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
1933 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
1934 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
1935 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
1936 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
1937 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
1938 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
1939 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
1940 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
1941 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
1942 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
1943
1944 return((struct net_device_stats *) &bp->stats);
1945 }
1946
1947
1948 /*
1949 * ==============================
1950 * = dfx_ctl_set_multicast_list =
1951 * ==============================
1952 *
1953 * Overview:
1954 * Enable/Disable LLC frame promiscuous mode reception
1955 * on the adapter and/or update multicast address table.
1956 *
1957 * Returns:
1958 * None
1959 *
1960 * Arguments:
1961 * dev - pointer to device information
1962 *
1963 * Functional Description:
1964 * This routine follows a fairly simple algorithm for setting the
1965 * adapter filters and CAM:
1966 *
1967 * if IFF_PROMISC flag is set
1968 * enable LLC individual/group promiscuous mode
1969 * else
1970 * disable LLC individual/group promiscuous mode
1971 * if number of incoming multicast addresses >
1972 * (CAM max size - number of unicast addresses in CAM)
1973 * enable LLC group promiscuous mode
1974 * set driver-maintained multicast address count to zero
1975 * else
1976 * disable LLC group promiscuous mode
1977 * set driver-maintained multicast address count to incoming count
1978 * update adapter CAM
1979 * update adapter filters
1980 *
1981 * Return Codes:
1982 * None
1983 *
1984 * Assumptions:
1985 * Multicast addresses are presented in canonical (LSB) format.
1986 *
1987 * Side Effects:
1988 * On-board adapter CAM and filters are updated.
1989 */
1990
1991 static void dfx_ctl_set_multicast_list(struct net_device *dev)
1992 {
1993 DFX_board_t *bp = dev->priv;
1994 int i; /* used as index in for loop */
1995 struct dev_mc_list *dmi; /* ptr to multicast addr entry */
1996
1997 /* Enable LLC frame promiscuous mode, if necessary */
1998
1999 if (dev->flags & IFF_PROMISC)
2000 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
2001
2002 /* Else, update multicast address table */
2003
2004 else
2005 {
2006 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
2007 /*
2008 * Check whether incoming multicast address count exceeds table size
2009 *
2010 * Note: The adapters utilize an on-board 64 entry CAM for
2011 * supporting perfect filtering of multicast packets
2012 * and bridge functions when adding unicast addresses.
2013 * There is no hash function available. To support
2014 * additional multicast addresses, the all multicast
2015 * filter (LLC group promiscuous mode) must be enabled.
2016 *
2017 * The firmware reserves two CAM entries for SMT-related
2018 * multicast addresses, which leaves 62 entries available.
2019 * The following code ensures that we're not being asked
2020 * to add more than 62 addresses to the CAM. If we are,
2021 * the driver will enable the all multicast filter.
2022 * Should the number of multicast addresses drop below
2023 * the high water mark, the filter will be disabled and
2024 * perfect filtering will be used.
2025 */
2026
2027 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2028 {
2029 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2030 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2031 }
2032 else
2033 {
2034 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
2035 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */
2036 }
2037
2038 /* Copy addresses to multicast address table, then update adapter CAM */
2039
2040 dmi = dev->mc_list; /* point to first multicast addr */
2041 for (i=0; i < bp->mc_count; i++)
2042 {
2043 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2044 dmi = dmi->next; /* point to next multicast addr */
2045 }
2046 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2047 {
2048 DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2049 }
2050 else
2051 {
2052 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2053 }
2054 }
2055
2056 /* Update adapter filters */
2057
2058 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2059 {
2060 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2061 }
2062 else
2063 {
2064 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2065 }
2066 }
2067
2068
2069 /*
2070 * ===========================
2071 * = dfx_ctl_set_mac_address =
2072 * ===========================
2073 *
2074 * Overview:
2075 * Add node address override (unicast address) to adapter
2076 * CAM and update dev_addr field in device table.
2077 *
2078 * Returns:
2079 * None
2080 *
2081 * Arguments:
2082 * dev - pointer to device information
2083 * addr - pointer to sockaddr structure containing unicast address to add
2084 *
2085 * Functional Description:
2086 * The adapter supports node address overrides by adding one or more
2087 * unicast addresses to the adapter CAM. This is similar to adding
2088 * multicast addresses. In this routine we'll update the driver and
2089 * device structures with the new address, then update the adapter CAM
2090 * to ensure that the adapter will copy and strip frames destined and
2091 * sourced by that address.
2092 *
2093 * Return Codes:
2094 * Always returns zero.
2095 *
2096 * Assumptions:
2097 * The address pointed to by addr->sa_data is a valid unicast
2098 * address and is presented in canonical (LSB) format.
2099 *
2100 * Side Effects:
2101 * On-board adapter CAM is updated. On-board adapter filters
2102 * may be updated.
2103 */
2104
2105 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2106 {
2107 DFX_board_t *bp = dev->priv;
2108 struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2109
2110 /* Copy unicast address to driver-maintained structs and update count */
2111
2112 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
2113 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
2114 bp->uc_count = 1;
2115
2116 /*
2117 * Verify we're not exceeding the CAM size by adding unicast address
2118 *
2119 * Note: It's possible that before entering this routine we've
2120 * already filled the CAM with 62 multicast addresses.
2121 * Since we need to place the node address override into
2122 * the CAM, we have to check to see that we're not
2123 * exceeding the CAM size. If we are, we have to enable
2124 * the LLC group (multicast) promiscuous mode filter as
2125 * in dfx_ctl_set_multicast_list.
2126 */
2127
2128 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2129 {
2130 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2131 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2132
2133 /* Update adapter filters */
2134
2135 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2136 {
2137 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2138 }
2139 else
2140 {
2141 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2142 }
2143 }
2144
2145 /* Update adapter CAM with new unicast address */
2146
2147 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2148 {
2149 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2150 }
2151 else
2152 {
2153 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2154 }
2155 return(0); /* always return zero */
2156 }
2157
2158
2159 /*
2160 * ======================
2161 * = dfx_ctl_update_cam =
2162 * ======================
2163 *
2164 * Overview:
2165 * Procedure to update adapter CAM (Content Addressable Memory)
2166 * with desired unicast and multicast address entries.
2167 *
2168 * Returns:
2169 * Condition code
2170 *
2171 * Arguments:
2172 * bp - pointer to board information
2173 *
2174 * Functional Description:
2175 * Updates adapter CAM with current contents of board structure
2176 * unicast and multicast address tables. Since there are only 62
2177 * free entries in CAM, this routine ensures that the command
2178 * request buffer is not overrun.
2179 *
2180 * Return Codes:
2181 * DFX_K_SUCCESS - Request succeeded
2182 * DFX_K_FAILURE - Request failed
2183 *
2184 * Assumptions:
2185 * All addresses being added (unicast and multicast) are in canonical
2186 * order.
2187 *
2188 * Side Effects:
2189 * On-board adapter CAM is updated.
2190 */
2191
2192 static int dfx_ctl_update_cam(DFX_board_t *bp)
2193 {
2194 int i; /* used as index */
2195 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
2196
2197 /*
2198 * Fill in command request information
2199 *
2200 * Note: Even though both the unicast and multicast address
2201 * table entries are stored as contiguous 6 byte entries,
2202 * the firmware address filter set command expects each
2203 * entry to be two longwords (8 bytes total). We must be
2204 * careful to only copy the six bytes of each unicast and
2205 * multicast table entry into each command entry. This
2206 * is also why we must first clear the entire command
2207 * request buffer.
2208 */
2209
2210 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
2211 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2212 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2213
2214 /* Now add unicast addresses to command request buffer, if any */
2215
2216 for (i=0; i < (int)bp->uc_count; i++)
2217 {
2218 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2219 {
2220 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2221 p_addr++; /* point to next command entry */
2222 }
2223 }
2224
2225 /* Now add multicast addresses to command request buffer, if any */
2226
2227 for (i=0; i < (int)bp->mc_count; i++)
2228 {
2229 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2230 {
2231 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2232 p_addr++; /* point to next command entry */
2233 }
2234 }
2235
2236 /* Issue command to update adapter CAM, then return */
2237
2238 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2239 return(DFX_K_FAILURE);
2240 return(DFX_K_SUCCESS);
2241 }
2242
2243
2244 /*
2245 * ==========================
2246 * = dfx_ctl_update_filters =
2247 * ==========================
2248 *
2249 * Overview:
2250 * Procedure to update adapter filters with desired
2251 * filter settings.
2252 *
2253 * Returns:
2254 * Condition code
2255 *
2256 * Arguments:
2257 * bp - pointer to board information
2258 *
2259 * Functional Description:
2260 * Enables or disables filter using current filter settings.
2261 *
2262 * Return Codes:
2263 * DFX_K_SUCCESS - Request succeeded.
2264 * DFX_K_FAILURE - Request failed.
2265 *
2266 * Assumptions:
2267 * We must always pass up packets destined to the broadcast
2268 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2269 * broadcast filter enabled.
2270 *
2271 * Side Effects:
2272 * On-board adapter filters are updated.
2273 */
2274
2275 static int dfx_ctl_update_filters(DFX_board_t *bp)
2276 {
2277 int i = 0; /* used as index */
2278
2279 /* Fill in command request information */
2280
2281 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2282
2283 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2284
2285 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
2286 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
2287
2288 /* Initialize LLC Individual/Group Promiscuous filter */
2289
2290 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
2291 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
2292
2293 /* Initialize LLC Group Promiscuous filter */
2294
2295 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
2296 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
2297
2298 /* Terminate the item code list */
2299
2300 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
2301
2302 /* Issue command to update adapter filters, then return */
2303
2304 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2305 return(DFX_K_FAILURE);
2306 return(DFX_K_SUCCESS);
2307 }
2308
2309
2310 /*
2311 * ======================
2312 * = dfx_hw_dma_cmd_req =
2313 * ======================
2314 *
2315 * Overview:
2316 * Sends PDQ DMA command to adapter firmware
2317 *
2318 * Returns:
2319 * Condition code
2320 *
2321 * Arguments:
2322 * bp - pointer to board information
2323 *
2324 * Functional Description:
2325 * The command request and response buffers are posted to the adapter in the manner
2326 * described in the PDQ Port Specification:
2327 *
2328 * 1. Command Response Buffer is posted to adapter.
2329 * 2. Command Request Buffer is posted to adapter.
2330 * 3. Command Request consumer index is polled until it indicates that request
2331 * buffer has been DMA'd to adapter.
2332 * 4. Command Response consumer index is polled until it indicates that response
2333 * buffer has been DMA'd from adapter.
2334 *
2335 * This ordering ensures that a response buffer is already available for the firmware
2336 * to use once it's done processing the request buffer.
2337 *
2338 * Return Codes:
2339 * DFX_K_SUCCESS - DMA command succeeded
2340 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2341 * DFX_K_HW_TIMEOUT - DMA command timed out
2342 *
2343 * Assumptions:
2344 * Command request buffer has already been filled with desired DMA command.
2345 *
2346 * Side Effects:
2347 * None
2348 */
2349
2350 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2351 {
2352 int status; /* adapter status */
2353 int timeout_cnt; /* used in for loops */
2354
2355 /* Make sure the adapter is in a state that we can issue the DMA command in */
2356
2357 status = dfx_hw_adap_state_rd(bp);
2358 if ((status == PI_STATE_K_RESET) ||
2359 (status == PI_STATE_K_HALTED) ||
2360 (status == PI_STATE_K_DMA_UNAVAIL) ||
2361 (status == PI_STATE_K_UPGRADE))
2362 return(DFX_K_OUTSTATE);
2363
2364 /* Put response buffer on the command response queue */
2365
2366 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2367 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2368 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2369
2370 /* Bump (and wrap) the producer index and write out to register */
2371
2372 bp->cmd_rsp_reg.index.prod += 1;
2373 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2374 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2375
2376 /* Put request buffer on the command request queue */
2377
2378 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2379 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2380 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2381
2382 /* Bump (and wrap) the producer index and write out to register */
2383
2384 bp->cmd_req_reg.index.prod += 1;
2385 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2386 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2387
2388 /*
2389 * Here we wait for the command request consumer index to be equal
2390 * to the producer, indicating that the adapter has DMAed the request.
2391 */
2392
2393 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2394 {
2395 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2396 break;
2397 udelay(100); /* wait for 100 microseconds */
2398 }
2399 if (timeout_cnt == 0)
2400 return(DFX_K_HW_TIMEOUT);
2401
2402 /* Bump (and wrap) the completion index and write out to register */
2403
2404 bp->cmd_req_reg.index.comp += 1;
2405 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2406 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2407
2408 /*
2409 * Here we wait for the command response consumer index to be equal
2410 * to the producer, indicating that the adapter has DMAed the response.
2411 */
2412
2413 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2414 {
2415 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2416 break;
2417 udelay(100); /* wait for 100 microseconds */
2418 }
2419 if (timeout_cnt == 0)
2420 return(DFX_K_HW_TIMEOUT);
2421
2422 /* Bump (and wrap) the completion index and write out to register */
2423
2424 bp->cmd_rsp_reg.index.comp += 1;
2425 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2426 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2427 return(DFX_K_SUCCESS);
2428 }
2429
2430
2431 /*
2432 * ========================
2433 * = dfx_hw_port_ctrl_req =
2434 * ========================
2435 *
2436 * Overview:
2437 * Sends PDQ port control command to adapter firmware
2438 *
2439 * Returns:
2440 * Host data register value in host_data if ptr is not NULL
2441 *
2442 * Arguments:
2443 * bp - pointer to board information
2444 * command - port control command
2445 * data_a - port data A register value
2446 * data_b - port data B register value
2447 * host_data - ptr to host data register value
2448 *
2449 * Functional Description:
2450 * Send generic port control command to adapter by writing
2451 * to various PDQ port registers, then polling for completion.
2452 *
2453 * Return Codes:
2454 * DFX_K_SUCCESS - port control command succeeded
2455 * DFX_K_HW_TIMEOUT - port control command timed out
2456 *
2457 * Assumptions:
2458 * None
2459 *
2460 * Side Effects:
2461 * None
2462 */
2463
2464 static int dfx_hw_port_ctrl_req(
2465 DFX_board_t *bp,
2466 PI_UINT32 command,
2467 PI_UINT32 data_a,
2468 PI_UINT32 data_b,
2469 PI_UINT32 *host_data
2470 )
2471
2472 {
2473 PI_UINT32 port_cmd; /* Port Control command register value */
2474 int timeout_cnt; /* used in for loops */
2475
2476 /* Set Command Error bit in command longword */
2477
2478 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2479
2480 /* Issue port command to the adapter */
2481
2482 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2483 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2484 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2485
2486 /* Now wait for command to complete */
2487
2488 if (command == PI_PCTRL_M_BLAST_FLASH)
2489 timeout_cnt = 600000; /* set command timeout count to 60 seconds */
2490 else
2491 timeout_cnt = 20000; /* set command timeout count to 2 seconds */
2492
2493 for (; timeout_cnt > 0; timeout_cnt--)
2494 {
2495 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2496 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2497 break;
2498 udelay(100); /* wait for 100 microseconds */
2499 }
2500 if (timeout_cnt == 0)
2501 return(DFX_K_HW_TIMEOUT);
2502
2503 /*
2504 * If the address of host_data is non-zero, assume caller has supplied a
2505 * non NULL pointer, and return the contents of the HOST_DATA register in
2506 * it.
2507 */
2508
2509 if (host_data != NULL)
2510 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2511 return(DFX_K_SUCCESS);
2512 }
2513
2514
2515 /*
2516 * =====================
2517 * = dfx_hw_adap_reset =
2518 * =====================
2519 *
2520 * Overview:
2521 * Resets adapter
2522 *
2523 * Returns:
2524 * None
2525 *
2526 * Arguments:
2527 * bp - pointer to board information
2528 * type - type of reset to perform
2529 *
2530 * Functional Description:
2531 * Issue soft reset to adapter by writing to PDQ Port Reset
2532 * register. Use incoming reset type to tell adapter what
2533 * kind of reset operation to perform.
2534 *
2535 * Return Codes:
2536 * None
2537 *
2538 * Assumptions:
2539 * This routine merely issues a soft reset to the adapter.
2540 * It is expected that after this routine returns, the caller
2541 * will appropriately poll the Port Status register for the
2542 * adapter to enter the proper state.
2543 *
2544 * Side Effects:
2545 * Internal adapter registers are cleared.
2546 */
2547
2548 static void dfx_hw_adap_reset(
2549 DFX_board_t *bp,
2550 PI_UINT32 type
2551 )
2552
2553 {
2554 /* Set Reset type and assert reset */
2555
2556 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
2557 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2558
2559 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2560
2561 udelay(20);
2562
2563 /* Deassert reset */
2564
2565 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2566 }
2567
2568
2569 /*
2570 * ========================
2571 * = dfx_hw_adap_state_rd =
2572 * ========================
2573 *
2574 * Overview:
2575 * Returns current adapter state
2576 *
2577 * Returns:
2578 * Adapter state per PDQ Port Specification
2579 *
2580 * Arguments:
2581 * bp - pointer to board information
2582 *
2583 * Functional Description:
2584 * Reads PDQ Port Status register and returns adapter state.
2585 *
2586 * Return Codes:
2587 * None
2588 *
2589 * Assumptions:
2590 * None
2591 *
2592 * Side Effects:
2593 * None
2594 */
2595
2596 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2597 {
2598 PI_UINT32 port_status; /* Port Status register value */
2599
2600 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2601 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2602 }
2603
2604
2605 /*
2606 * =====================
2607 * = dfx_hw_dma_uninit =
2608 * =====================
2609 *
2610 * Overview:
2611 * Brings adapter to DMA_UNAVAILABLE state
2612 *
2613 * Returns:
2614 * Condition code
2615 *
2616 * Arguments:
2617 * bp - pointer to board information
2618 * type - type of reset to perform
2619 *
2620 * Functional Description:
2621 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2622 * 1. Set reset type bit in Port Data A Register then reset adapter.
2623 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2624 *
2625 * Return Codes:
2626 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2627 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2628 *
2629 * Assumptions:
2630 * None
2631 *
2632 * Side Effects:
2633 * Internal adapter registers are cleared.
2634 */
2635
2636 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2637 {
2638 int timeout_cnt; /* used in for loops */
2639
2640 /* Set reset type bit and reset adapter */
2641
2642 dfx_hw_adap_reset(bp, type);
2643
2644 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2645
2646 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2647 {
2648 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2649 break;
2650 udelay(100); /* wait for 100 microseconds */
2651 }
2652 if (timeout_cnt == 0)
2653 return(DFX_K_HW_TIMEOUT);
2654 return(DFX_K_SUCCESS);
2655 }
2656
2657 /*
2658 * Align an sk_buff to a boundary power of 2
2659 *
2660 */
2661
2662 static void my_skb_align(struct sk_buff *skb, int n)
2663 {
2664 u32 x=(u32)skb->data; /* We only want the low bits .. */
2665 u32 v;
2666
2667 v=(x+n-1)&~(n-1); /* Where we want to be */
2668
2669 skb_reserve(skb, v-x);
2670 }
2671
2672
2673 /*
2674 * ================
2675 * = dfx_rcv_init =
2676 * ================
2677 *
2678 * Overview:
2679 * Produces buffers to adapter LLC Host receive descriptor block
2680 *
2681 * Returns:
2682 * None
2683 *
2684 * Arguments:
2685 * bp - pointer to board information
2686 * get_buffers - non-zero if buffers to be allocated
2687 *
2688 * Functional Description:
2689 * This routine can be called during dfx_adap_init() or during an adapter
2690 * reset. It initializes the descriptor block and produces all allocated
2691 * LLC Host queue receive buffers.
2692 *
2693 * Return Codes:
2694 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2695 * dynamic buffer allocation). If the buffer allocation failed, the
2696 * already allocated buffers will not be released and the caller should do
2697 * this.
2698 *
2699 * Assumptions:
2700 * The PDQ has been reset and the adapter and driver maintained Type 2
2701 * register indices are cleared.
2702 *
2703 * Side Effects:
2704 * Receive buffers are posted to the adapter LLC queue and the adapter
2705 * is notified.
2706 */
2707
2708 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2709 {
2710 int i, j; /* used in for loop */
2711
2712 /*
2713 * Since each receive buffer is a single fragment of same length, initialize
2714 * first longword in each receive descriptor for entire LLC Host descriptor
2715 * block. Also initialize second longword in each receive descriptor with
2716 * physical address of receive buffer. We'll always allocate receive
2717 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2718 * block and produce new receive buffers by simply updating the receive
2719 * producer index.
2720 *
2721 * Assumptions:
2722 * To support all shipping versions of PDQ, the receive buffer size
2723 * must be mod 128 in length and the physical address must be 128 byte
2724 * aligned. In other words, bits 0-6 of the length and address must
2725 * be zero for the following descriptor field entries to be correct on
2726 * all PDQ-based boards. We guaranteed both requirements during
2727 * driver initialization when we allocated memory for the receive buffers.
2728 */
2729
2730 if (get_buffers) {
2731 #ifdef DYNAMIC_BUFFERS
2732 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2733 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2734 {
2735 struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
2736 if (!newskb)
2737 return -ENOMEM;
2738 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2739 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2740 /*
2741 * align to 128 bytes for compatibility with
2742 * the old EISA boards.
2743 */
2744
2745 my_skb_align(newskb, 128);
2746 bp->descr_block_virt->rcv_data[i+j].long_1 = virt_to_bus(newskb->data);
2747 /*
2748 * p_rcv_buff_va is only used inside the
2749 * kernel so we put the skb pointer here.
2750 */
2751 bp->p_rcv_buff_va[i+j] = (char *) newskb;
2752 }
2753 #else
2754 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2755 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2756 {
2757 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2758 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2759 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2760 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2761 }
2762 #endif
2763 }
2764
2765 /* Update receive producer and Type 2 register */
2766
2767 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2768 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2769 return 0;
2770 }
2771
2772
2773 /*
2774 * =========================
2775 * = dfx_rcv_queue_process =
2776 * =========================
2777 *
2778 * Overview:
2779 * Process received LLC frames.
2780 *
2781 * Returns:
2782 * None
2783 *
2784 * Arguments:
2785 * bp - pointer to board information
2786 *
2787 * Functional Description:
2788 * Received LLC frames are processed until there are no more consumed frames.
2789 * Once all frames are processed, the receive buffers are returned to the
2790 * adapter. Note that this algorithm fixes the length of time that can be spent
2791 * in this routine, because there are a fixed number of receive buffers to
2792 * process and buffers are not produced until this routine exits and returns
2793 * to the ISR.
2794 *
2795 * Return Codes:
2796 * None
2797 *
2798 * Assumptions:
2799 * None
2800 *
2801 * Side Effects:
2802 * None
2803 */
2804
2805 static void dfx_rcv_queue_process(
2806 DFX_board_t *bp
2807 )
2808
2809 {
2810 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
2811 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
2812 u32 descr, pkt_len; /* FMC descriptor field and packet length */
2813 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */
2814
2815 /* Service all consumed LLC receive frames */
2816
2817 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
2818 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
2819 {
2820 /* Process any errors */
2821
2822 int entry;
2823
2824 entry = bp->rcv_xmt_reg.index.rcv_comp;
2825 #ifdef DYNAMIC_BUFFERS
2826 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
2827 #else
2828 p_buff = (char *) bp->p_rcv_buff_va[entry];
2829 #endif
2830 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
2831
2832 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
2833 {
2834 if (descr & PI_FMC_DESCR_M_RCC_CRC)
2835 bp->rcv_crc_errors++;
2836 else
2837 bp->rcv_frame_status_errors++;
2838 }
2839 else
2840 {
2841 int rx_in_place = 0;
2842
2843 /* The frame was received without errors - verify packet length */
2844
2845 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
2846 pkt_len -= 4; /* subtract 4 byte CRC */
2847 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
2848 bp->rcv_length_errors++;
2849 else{
2850 #ifdef DYNAMIC_BUFFERS
2851 if (pkt_len > SKBUFF_RX_COPYBREAK) {
2852 struct sk_buff *newskb;
2853
2854 newskb = dev_alloc_skb(NEW_SKB_SIZE);
2855 if (newskb){
2856 rx_in_place = 1;
2857
2858 my_skb_align(newskb, 128);
2859 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
2860 skb_reserve(skb, RCV_BUFF_K_PADDING);
2861 bp->p_rcv_buff_va[entry] = (char *)newskb;
2862 bp->descr_block_virt->rcv_data[entry].long_1 = virt_to_bus(newskb->data);
2863 } else
2864 skb = NULL;
2865 } else
2866 #endif
2867 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
2868 if (skb == NULL)
2869 {
2870 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
2871 bp->rcv_discards++;
2872 break;
2873 }
2874 else {
2875 #ifndef DYNAMIC_BUFFERS
2876 if (! rx_in_place)
2877 #endif
2878 {
2879 /* Receive buffer allocated, pass receive packet up */
2880
2881 memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3);
2882 }
2883
2884 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
2885 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
2886 skb->dev = bp->dev; /* pass up device pointer */
2887
2888 skb->protocol = fddi_type_trans(skb, bp->dev);
2889 bp->rcv_total_bytes += skb->len;
2890 netif_rx(skb);
2891
2892 /* Update the rcv counters */
2893 bp->dev->last_rx = jiffies;
2894 bp->rcv_total_frames++;
2895 if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
2896 bp->rcv_multicast_frames++;
2897 }
2898 }
2899 }
2900
2901 /*
2902 * Advance the producer (for recycling) and advance the completion
2903 * (for servicing received frames). Note that it is okay to
2904 * advance the producer without checking that it passes the
2905 * completion index because they are both advanced at the same
2906 * rate.
2907 */
2908
2909 bp->rcv_xmt_reg.index.rcv_prod += 1;
2910 bp->rcv_xmt_reg.index.rcv_comp += 1;
2911 }
2912 }
2913
2914
2915 /*
2916 * =====================
2917 * = dfx_xmt_queue_pkt =
2918 * =====================
2919 *
2920 * Overview:
2921 * Queues packets for transmission
2922 *
2923 * Returns:
2924 * Condition code
2925 *
2926 * Arguments:
2927 * skb - pointer to sk_buff to queue for transmission
2928 * dev - pointer to device information
2929 *
2930 * Functional Description:
2931 * Here we assume that an incoming skb transmit request
2932 * is contained in a single physically contiguous buffer
2933 * in which the virtual address of the start of packet
2934 * (skb->data) can be converted to a physical address
2935 * by using virt_to_bus().
2936 *
2937 * Since the adapter architecture requires a three byte
2938 * packet request header to prepend the start of packet,
2939 * we'll write the three byte field immediately prior to
2940 * the FC byte. This assumption is valid because we've
2941 * ensured that dev->hard_header_len includes three pad
2942 * bytes. By posting a single fragment to the adapter,
2943 * we'll reduce the number of descriptor fetches and
2944 * bus traffic needed to send the request.
2945 *
2946 * Also, we can't free the skb until after it's been DMA'd
2947 * out by the adapter, so we'll queue it in the driver and
2948 * return it in dfx_xmt_done.
2949 *
2950 * Return Codes:
2951 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2952 * 1 - caller should requeue the sk_buff for later transmission
2953 *
2954 * Assumptions:
2955 * First and foremost, we assume the incoming skb pointer
2956 * is NOT NULL and is pointing to a valid sk_buff structure.
2957 *
2958 * The outgoing packet is complete, starting with the
2959 * frame control byte including the last byte of data,
2960 * but NOT including the 4 byte CRC. We'll let the
2961 * adapter hardware generate and append the CRC.
2962 *
2963 * The entire packet is stored in one physically
2964 * contiguous buffer which is not cached and whose
2965 * 32-bit physical address can be determined.
2966 *
2967 * It's vital that this routine is NOT reentered for the
2968 * same board and that the OS is not in another section of
2969 * code (eg. dfx_int_common) for the same board on a
2970 * different thread.
2971 *
2972 * Side Effects:
2973 * None
2974 */
2975
2976 static int dfx_xmt_queue_pkt(
2977 struct sk_buff *skb,
2978 struct net_device *dev
2979 )
2980
2981 {
2982 DFX_board_t *bp = dev->priv;
2983 u8 prod; /* local transmit producer index */
2984 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
2985 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
2986 unsigned long flags;
2987
2988 netif_stop_queue(dev);
2989
2990 /*
2991 * Verify that incoming transmit request is OK
2992 *
2993 * Note: The packet size check is consistent with other
2994 * Linux device drivers, although the correct packet
2995 * size should be verified before calling the
2996 * transmit routine.
2997 */
2998
2999 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3000 {
3001 printk("%s: Invalid packet length - %u bytes\n",
3002 dev->name, skb->len);
3003 bp->xmt_length_errors++; /* bump error counter */
3004 netif_wake_queue(dev);
3005 dev_kfree_skb(skb);
3006 return(0); /* return "success" */
3007 }
3008 /*
3009 * See if adapter link is available, if not, free buffer
3010 *
3011 * Note: If the link isn't available, free buffer and return 0
3012 * rather than tell the upper layer to requeue the packet.
3013 * The methodology here is that by the time the link
3014 * becomes available, the packet to be sent will be
3015 * fairly stale. By simply dropping the packet, the
3016 * higher layer protocols will eventually time out
3017 * waiting for response packets which it won't receive.
3018 */
3019
3020 if (bp->link_available == PI_K_FALSE)
3021 {
3022 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
3023 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
3024 else
3025 {
3026 bp->xmt_discards++; /* bump error counter */
3027 dev_kfree_skb(skb); /* free sk_buff now */
3028 netif_wake_queue(dev);
3029 return(0); /* return "success" */
3030 }
3031 }
3032
3033 spin_lock_irqsave(&bp->lock, flags);
3034
3035 /* Get the current producer and the next free xmt data descriptor */
3036
3037 prod = bp->rcv_xmt_reg.index.xmt_prod;
3038 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3039
3040 /*
3041 * Get pointer to auxiliary queue entry to contain information
3042 * for this packet.
3043 *
3044 * Note: The current xmt producer index will become the
3045 * current xmt completion index when we complete this
3046 * packet later on. So, we'll get the pointer to the
3047 * next auxiliary queue entry now before we bump the
3048 * producer index.
3049 */
3050
3051 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
3052
3053 /* Write the three PRH bytes immediately before the FC byte */
3054
3055 skb_push(skb,3);
3056 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
3057 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
3058 skb->data[2] = DFX_PRH2_BYTE; /* specification */
3059
3060 /*
3061 * Write the descriptor with buffer info and bump producer
3062 *
3063 * Note: Since we need to start DMA from the packet request
3064 * header, we'll add 3 bytes to the DMA buffer length,
3065 * and we'll determine the physical address of the
3066 * buffer from the PRH, not skb->data.
3067 *
3068 * Assumptions:
3069 * 1. Packet starts with the frame control (FC) byte
3070 * at skb->data.
3071 * 2. The 4-byte CRC is not appended to the buffer or
3072 * included in the length.
3073 * 3. Packet length (skb->len) is from FC to end of
3074 * data, inclusive.
3075 * 4. The packet length does not exceed the maximum
3076 * FDDI LLC frame length of 4491 bytes.
3077 * 5. The entire packet is contained in a physically
3078 * contiguous, non-cached, locked memory space
3079 * comprised of a single buffer pointed to by
3080 * skb->data.
3081 * 6. The physical address of the start of packet
3082 * can be determined from the virtual address
3083 * by using virt_to_bus() and is only 32-bits
3084 * wide.
3085 */
3086
3087 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3088 p_xmt_descr->long_1 = (u32) virt_to_bus(skb->data);
3089
3090 /*
3091 * Verify that descriptor is actually available
3092 *
3093 * Note: If descriptor isn't available, return 1 which tells
3094 * the upper layer to requeue the packet for later
3095 * transmission.
3096 *
3097 * We need to ensure that the producer never reaches the
3098 * completion, except to indicate that the queue is empty.
3099 */
3100
3101 if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3102 {
3103 skb_pull(skb,3);
3104 spin_unlock_irqrestore(&bp->lock, flags);
3105 return(1); /* requeue packet for later */
3106 }
3107
3108 /*
3109 * Save info for this packet for xmt done indication routine
3110 *
3111 * Normally, we'd save the producer index in the p_xmt_drv_descr
3112 * structure so that we'd have it handy when we complete this
3113 * packet later (in dfx_xmt_done). However, since the current
3114 * transmit architecture guarantees a single fragment for the
3115 * entire packet, we can simply bump the completion index by
3116 * one (1) for each completed packet.
3117 *
3118 * Note: If this assumption changes and we're presented with
3119 * an inconsistent number of transmit fragments for packet
3120 * data, we'll need to modify this code to save the current
3121 * transmit producer index.
3122 */
3123
3124 p_xmt_drv_descr->p_skb = skb;
3125
3126 /* Update Type 2 register */
3127
3128 bp->rcv_xmt_reg.index.xmt_prod = prod;
3129 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3130 spin_unlock_irqrestore(&bp->lock, flags);
3131 netif_wake_queue(dev);
3132 return(0); /* packet queued to adapter */
3133 }
3134
3135
3136 /*
3137 * ================
3138 * = dfx_xmt_done =
3139 * ================
3140 *
3141 * Overview:
3142 * Processes all frames that have been transmitted.
3143 *
3144 * Returns:
3145 * None
3146 *
3147 * Arguments:
3148 * bp - pointer to board information
3149 *
3150 * Functional Description:
3151 * For all consumed transmit descriptors that have not
3152 * yet been completed, we'll free the skb we were holding
3153 * onto using dev_kfree_skb and bump the appropriate
3154 * counters.
3155 *
3156 * Return Codes:
3157 * None
3158 *
3159 * Assumptions:
3160 * The Type 2 register is not updated in this routine. It is
3161 * assumed that it will be updated in the ISR when dfx_xmt_done
3162 * returns.
3163 *
3164 * Side Effects:
3165 * None
3166 */
3167
3168 static int dfx_xmt_done(DFX_board_t *bp)
3169 {
3170 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3171 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
3172 int freed = 0; /* buffers freed */
3173
3174 /* Service all consumed transmit frames */
3175
3176 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3177 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3178 {
3179 /* Get pointer to the transmit driver descriptor block information */
3180
3181 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3182
3183 /* Increment transmit counters */
3184
3185 bp->xmt_total_frames++;
3186 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3187
3188 /* Return skb to operating system */
3189
3190 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3191
3192 /*
3193 * Move to start of next packet by updating completion index
3194 *
3195 * Here we assume that a transmit packet request is always
3196 * serviced by posting one fragment. We can therefore
3197 * simplify the completion code by incrementing the
3198 * completion index by one. This code will need to be
3199 * modified if this assumption changes. See comments
3200 * in dfx_xmt_queue_pkt for more details.
3201 */
3202
3203 bp->rcv_xmt_reg.index.xmt_comp += 1;
3204 freed++;
3205 }
3206 return freed;
3207 }
3208
3209
3210 /*
3211 * =================
3212 * = dfx_rcv_flush =
3213 * =================
3214 *
3215 * Overview:
3216 * Remove all skb's in the receive ring.
3217 *
3218 * Returns:
3219 * None
3220 *
3221 * Arguments:
3222 * bp - pointer to board information
3223 *
3224 * Functional Description:
3225 * Free's all the dynamically allocated skb's that are
3226 * currently attached to the device receive ring. This
3227 * function is typically only used when the device is
3228 * initialized or reinitialized.
3229 *
3230 * Return Codes:
3231 * None
3232 *
3233 * Side Effects:
3234 * None
3235 */
3236 #ifdef DYNAMIC_BUFFERS
3237 static void dfx_rcv_flush( DFX_board_t *bp )
3238 {
3239 int i, j;
3240
3241 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3242 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3243 {
3244 struct sk_buff *skb;
3245 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3246 if (skb)
3247 dev_kfree_skb(skb);
3248 bp->p_rcv_buff_va[i+j] = NULL;
3249 }
3250
3251 }
3252 #else
3253 static inline void dfx_rcv_flush( DFX_board_t *bp )
3254 {
3255 }
3256 #endif /* DYNAMIC_BUFFERS */
3257
3258 /*
3259 * =================
3260 * = dfx_xmt_flush =
3261 * =================
3262 *
3263 * Overview:
3264 * Processes all frames whether they've been transmitted
3265 * or not.
3266 *
3267 * Returns:
3268 * None
3269 *
3270 * Arguments:
3271 * bp - pointer to board information
3272 *
3273 * Functional Description:
3274 * For all produced transmit descriptors that have not
3275 * yet been completed, we'll free the skb we were holding
3276 * onto using dev_kfree_skb and bump the appropriate
3277 * counters. Of course, it's possible that some of
3278 * these transmit requests actually did go out, but we
3279 * won't make that distinction here. Finally, we'll
3280 * update the consumer index to match the producer.
3281 *
3282 * Return Codes:
3283 * None
3284 *
3285 * Assumptions:
3286 * This routine does NOT update the Type 2 register. It
3287 * is assumed that this routine is being called during a
3288 * transmit flush interrupt, or a shutdown or close routine.
3289 *
3290 * Side Effects:
3291 * None
3292 */
3293
3294 static void dfx_xmt_flush( DFX_board_t *bp )
3295 {
3296 u32 prod_cons; /* rcv/xmt consumer block longword */
3297 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3298
3299 /* Flush all outstanding transmit frames */
3300
3301 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3302 {
3303 /* Get pointer to the transmit driver descriptor block information */
3304
3305 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3306
3307 /* Return skb to operating system */
3308
3309 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3310
3311 /* Increment transmit error counter */
3312
3313 bp->xmt_discards++;
3314
3315 /*
3316 * Move to start of next packet by updating completion index
3317 *
3318 * Here we assume that a transmit packet request is always
3319 * serviced by posting one fragment. We can therefore
3320 * simplify the completion code by incrementing the
3321 * completion index by one. This code will need to be
3322 * modified if this assumption changes. See comments
3323 * in dfx_xmt_queue_pkt for more details.
3324 */
3325
3326 bp->rcv_xmt_reg.index.xmt_comp += 1;
3327 }
3328
3329 /* Update the transmit consumer index in the consumer block */
3330
3331 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3332 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3333 bp->cons_block_virt->xmt_rcv_data = prod_cons;
3334 }
3335
3336 static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev)
3337 {
3338 DFX_board_t *bp = dev->priv;
3339
3340 unregister_netdev(dev);
3341 release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN );
3342 if (bp->kmalloced) kfree(bp->kmalloced);
3343 kfree(dev);
3344 }
3345
3346 static void __devexit dfx_remove_one (struct pci_dev *pdev)
3347 {
3348 struct net_device *dev = pci_get_drvdata(pdev);
3349
3350 dfx_remove_one_pci_or_eisa(pdev, dev);
3351 pci_set_drvdata(pdev, NULL);
3352 }
3353
3354 static struct pci_device_id dfx_pci_tbl[] __devinitdata = {
3355 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, },
3356 { 0, }
3357 };
3358 MODULE_DEVICE_TABLE(pci, dfx_pci_tbl);
3359
3360 static struct pci_driver dfx_driver = {
3361 name: "defxx",
3362 probe: dfx_init_one,
3363 remove: dfx_remove_one,
3364 id_table: dfx_pci_tbl,
3365 };
3366
3367 static int dfx_have_pci;
3368 static int dfx_have_eisa;
3369
3370
3371 static void __exit dfx_eisa_cleanup(void)
3372 {
3373 struct net_device *dev = root_dfx_eisa_dev;
3374
3375 while (dev)
3376 {
3377 struct net_device *tmp;
3378 DFX_board_t *bp;
3379
3380 bp = (DFX_board_t*)dev->priv;
3381 tmp = bp->next;
3382 dfx_remove_one_pci_or_eisa(NULL, dev);
3383 dev = tmp;
3384 }
3385 }
3386
3387 static int __init dfx_init(void)
3388 {
3389 int rc_pci, rc_eisa;
3390
3391 /* when a module, this is printed whether or not devices are found in probe */
3392 #ifdef MODULE
3393 printk(version);
3394 #endif
3395
3396 rc_pci = pci_module_init(&dfx_driver);
3397 if (rc_pci >= 0) dfx_have_pci = 1;
3398
3399 rc_eisa = dfx_eisa_init();
3400 if (rc_eisa >= 0) dfx_have_eisa = 1;
3401
3402 return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci);
3403 }
3404
3405 static void __exit dfx_cleanup(void)
3406 {
3407 if (dfx_have_pci)
3408 pci_unregister_driver(&dfx_driver);
3409 if (dfx_have_eisa)
3410 dfx_eisa_cleanup();
3411
3412 }
3413
3414 module_init(dfx_init);
3415 module_exit(dfx_cleanup);
3416
3417
3418 /*
3419 * Local variables:
3420 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3421 * End:
3422 */
3423