File: /usr/src/linux/drivers/net/dl2k.h
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12
13 #ifndef __DL2K_H__
14 #define __DL2K_H__
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/string.h>
19 #include <linux/timer.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/init.h>
29 #include <asm/processor.h> /* Processor type for cache alignment. */
30 #include <asm/bitops.h>
31 #include <asm/io.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/time.h>
35 #define TX_RING_SIZE 128
36 #define TX_QUEUE_LEN 96 /* Limit ring entries actually used. */
37 #define RX_RING_SIZE 128
38 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
39 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
40
41 /* This driver was written to use PCI memory space, however x86-oriented
42 hardware often uses I/O space accesses. */
43 #ifdef USE_IO_OPS
44 #undef readb
45 #undef readw
46 #undef readl
47 #undef writeb
48 #undef writew
49 #undef writel
50 #define readb inb
51 #define readw inw
52 #define readl inl
53 #define writeb outb
54 #define writew outw
55 #define writel outl
56 #endif
57
58 /* Offsets to the device registers.
59 Unlike software-only systems, device drivers interact with complex hardware.
60 It's not useful to define symbolic names for every register bit in the
61 device. The name can only partially document the semantics and make
62 the driver longer and more difficult to read.
63 In general, only the important configuration values or bits changed
64 multiple times should be defined symbolically.
65 */
66 enum dl2x_offsets {
67 /* I/O register offsets */
68 DMACtrl = 0x00,
69 RxDMAStatus = 0x08,
70 TFDListPtr0 = 0x10,
71 TFDListPtr1 = 0x14,
72 TxDMABurstThresh = 0x18,
73 TxDMAUrgentThresh = 0x19,
74 TxDMAPollPeriod = 0x1a,
75 RFDListPtr0 = 0x1c,
76 RFDListPtr1 = 0x20,
77 RxDMABurstThresh = 0x24,
78 RxDMAUrgentThresh = 0x25,
79 RxDMAPollPeriod = 0x26,
80 RxDMAIntCtrl = 0x28,
81 DebugCtrl = 0x2c,
82 ASICCtrl = 0x30,
83 FifoCtrl = 0x38,
84 RxEarlyThresh = 0x3a,
85 FlowOffThresh = 0x3c,
86 FlowOnThresh = 0x3e,
87 TxStartThresh = 0x44,
88 EepromData = 0x48,
89 EepromCtrl = 0x4a,
90 ExpromAddr = 0x4c,
91 Exprodata = 0x50,
92 WakeEvent0x51,
93 CountDown = 0x54,
94 IntStatusAck = 0x5a,
95 IntEnable = 0x5c,
96 IntStatus = 0x5e,
97 TxStatus = 0x60,
98 MACCtrl = 0x6c,
99 VLANTag = 0x70,
100 PhyCtrl = 0x76,
101 StationAddr0 = 0x78,
102 StationAddr1 = 0x7a,
103 StationAddr2 = 0x7c,
104 VLANId = 0x80,
105 MaxFrameSize = 0x86,
106 ReceiveMode = 0x88,
107 HashTable0 = 0x8c,
108 HashTable1 = 0x90,
109 RmonStatMask = 0x98,
110 StatMask = 0x9c,
111 RxJumboFrames = 0xbc,
112 TCPCheckSumErrors = 0xc0,
113 IPCheckSumErrors = 0xc2,
114 UDPCheckSumErrors = 0xc4,
115 TxJumboFrames = 0xf4,
116 /* Ethernet MIB statistic register offsets */
117 OctetRcvOk = 0xa8,
118 McstOctetRcvOk = 0xac,
119 BcstOctetRcvOk = 0xb0,
120 FramesRcvOk = 0xb4,
121 McstFramesRcvOk = 0xb8,
122 BcstFramesRcvOk = 0xbe,
123 MacControlFramesRcvd = 0xc6,
124 FrameTooLongErrors = 0xc8,
125 InRangeLengthErrors = 0xca,
126 FrameCheckSeqError = 0xcc,
127 FrameLostRxError = 0xce,
128 OctetXmtOk = 0xd0,
129 McstOctetXmtOk = 0xd4,
130 BcstOctetXmtOk = 0xd8,
131 FramesXmtOk = 0xdc,
132 McstFramesXmtdOk = 0xe0,
133 FramesWDeferredXmt = 0xe4,
134 LateCollisions = 0xe8,
135 MultiColFrames = 0xec,
136 SingleColFrames = 0xf0,
137 BcstFramesXmtdOk = 0xf6,
138 CarrierSenseErrors = 0xf8,
139 MacControlFramesXmtd = 0xfa,
140 FramesAbortXSColls = 0xfc,
141 FramesWEXDeferal = 0xfe,
142 /* RMON statistic register offsets */
143 EtherStatsCollisions = 0x100,
144 EtherStatsOctetsTransmit = 0x104,
145 EtherStatsPktsTransmit = 0x108,
146 EtherStatsPkts64OctetTransmit = 0x10c,
147 EtherStats65to127OctetsTransmit = 0x110,
148 EtherStatsPkts128to255OctetsTransmit = 0x114,
149 EtherStatsPkts256to511OctetsTransmit = 0x118,
150 EtherStatsPkts512to1023OctetsTransmit = 0x11c,
151 EtherStatsPkts1024to1518OctetsTransmit = 0x120,
152 EtherStatsCRCAlignErrors = 0x124,
153 EtherStatsUndersizePkts = 0x128,
154 EtherStatsFragments = 0x12c,
155 EtherStatsJabbers = 0x130,
156 EtherStatsOctets = 0x134,
157 EtherStatsPkts = 0x138,
158 EtherStats64Octets = 0x13c,
159 EtherStatsPkts65to127Octets = 0x140,
160 EtherStatsPkts128to255Octets = 0x144,
161 EtherStatsPkts256to511Octets = 0x148,
162 EtherStatsPkts512to1023Octets = 0x14c,
163 EtherStatsPkts1024to1518Octets = 0x150,
164 };
165
166 /* Bits in the interrupt status/mask registers. */
167 enum IntStatus_bits {
168 InterruptStatus = 0x0001,
169 HostError = 0x0002,
170 MACCtrlFrame = 0x0008,
171 TxComplete = 0x0004,
172 RxComplete = 0x0010,
173 RxEarly = 0x0020,
174 IntRequested = 0x0040,
175 UpdateStats = 0x0080,
176 LinkEvent = 0x0100,
177 TxDMAComplete = 0x0200,
178 RxDMAComplete = 0x0400,
179 RFDListEnd = 0x0800,
180 RxDMAPriority = 0x1000,
181 };
182
183 /* Bits in the ReceiveMode register. */
184 enum ReceiveMode_bits {
185 ReceiveIPMulticast = 0x0020,
186 ReceiveMulticastHash = 0x0010,
187 ReceiveAllFrames = 0x0008,
188 ReceiveBroadcast = 0x0004,
189 ReceiveMulticast = 0x0002,
190 ReceiveUnicast = 0x0001,
191 ReceiveVLANMatch = 0x0100,
192 ReceiveVLANHash = 0x0200,
193 };
194 /* Bits in MACCtrl. */
195 enum MACCtrl_bits {
196 DuplexSelect = 0x20,
197 TxFlowControlEnable = 0x80,
198 RxFlowControlEnable = 0x0100,
199 RcvFCS = 0x200,
200 AutoVLANtagging = 0x1000,
201 AutoVLANuntagging = 0x2000,
202 StatsEnable = 0x00200000,
203 StatsDisable = 0x00400000,
204 StatsEnabled = 0x00800000,
205 TxEnable = 0x01000000,
206 TxDisable = 0x02000000,
207 TxEnabled = 0x04000000,
208 RxEnable = 0x08000000,
209 RxDisable = 0x10000000,
210 RxEnabled = 0x20000000,
211 };
212 enum ASICCtrl_HiWord_bits {
213 GlobalReset = 0x0001,
214 RxReset = 0x0002,
215 TxReset = 0x0004,
216 DMAReset = 0x0008,
217 FIFOReset = 0x0010,
218 NetworkReset = 0x0020,
219 HostReset = 0x0040,
220 ResetBusy = 0x0400,
221 };
222
223 /* Transmit Frame Control bits */
224 enum TFC_bits {
225 DwordAlign = 0x00000000,
226 WordAlignDisable = 0x00030000,
227 WordAlign = 0x00020000,
228 TCPChecksumEnable = 0x00040000,
229 UDPChecksumEnable = 0x00080000,
230 IPChecksumEnable = 0x00100000,
231 FCSAppendDisable = 0x00200000,
232 TxIndicate = 0x00400000,
233 TxDMAIndicate = 0x00800000,
234 FragCountShift = 24,
235 VLANTagInsert = 0x0000000010000000,
236 TFDDone = 0x80000000,
237 VIDShift = 32,
238 CFI = 0x0000100000000000,
239 UsePriorityShift = 48,
240 };
241
242 /* Receive Frames Status bits */
243 enum RFS_bits {
244 RxFIFOOverrun = 0x00010000,
245 RxRuntFrame = 0x00020000,
246 RxAlignmentError = 0x00040000,
247 RxFCSError = 0x00080000,
248 RxOverSizedFrame = 0x00100000,
249 RxLengthError = 0x00200000,
250 VLANDetected = 0x00400000,
251 TCPDetected = 0x00800000,
252 TCPError = 0x01000000,
253 UDPDetected = 0x02000000,
254 UDPError = 0x04000000,
255 IPDetected = 0x08000000,
256 IPError = 0x10000000,
257 FrameStart = 0x20000000,
258 FrameEnd = 0x40000000,
259 RFDDone = 0x80000000,
260 TCIShift = 32,
261 };
262
263 #define MII_RESET_TIME_OUT 10000
264 /* MII register */
265 enum _mii_reg {
266 MII_BMCR = 0,
267 MII_BMSR = 1,
268 MII_PHY_ID1 = 2,
269 MII_PHY_ID2 = 3,
270 MII_ANAR = 4,
271 MII_ANLPAR = 5,
272 MII_ANER = 6,
273 MII_ANNPT = 7,
274 MII_ANLPRNP = 8,
275 MII_MSCR = 9,
276 MII_MSSR = 10,
277 MII_ESR = 15,
278 MII_PHY_SCR = 16,
279 };
280
281 /* Basic Mode Control Register */
282 typedef union t_MII_BMCR {
283 u16 image;
284 struct {
285 u16 _bit_5_0:6; // bit 5:0
286 u16 speed1000:1; // bit 6
287 u16 col_test_enable:1; // bit 7
288 u16 duplex_mode:1; // bit 8
289 u16 restart_an:1; // bit 9
290 u16 isolate:1; // bit 10
291 u16 power_down:1; // bit 11
292 u16 an_enable:1; // bit 12
293 u16 speed100:1; // bit 13
294 u16 loopback:1; // bit 14
295 u16 reset:1; // bit 15
296 } bits;
297 } BMCR_t, *PBMCR_t;
298
299 enum _mii_bmcr {
300 MII_BMCR_RESET = 0x8000,
301 MII_BMCR_LOOP_BACK = 0x4000,
302 MII_BMCR_SPEED_LSB = 0x2000,
303 MII_BMCR_AN_ENABLE = 0x1000,
304 MII_BMCR_POWER_DOWN = 0x0800,
305 MII_BMCR_ISOLATE = 0x0400,
306 MII_BMCR_RESTART_AN = 0x0200,
307 MII_BMCR_DUPLEX_MODE = 0x0100,
308 MII_BMCR_COL_TEST = 0x0080,
309 MII_BMCR_SPEED_MSB = 0x0040,
310 MII_BMCR_SPEED_RESERVED = 0x003f,
311 MII_BMCR_SPEED_10 = 0,
312 MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
313 MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
314 };
315
316 /* Basic Mode Status Register */
317 typedef union t_MII_BMSR {
318 u16 image;
319 struct {
320 u16 ext_capability:1; // bit 0
321 u16 japper_detect:1; // bit 1
322 u16 link_status:1; // bit 2
323 u16 an_ability:1; // bit 3
324 u16 remote_fault:1; // bit 4
325 u16 an_complete:1; // bit 5
326 u16 preamble_supp:1; // bit 6
327 u16 _bit_7:1; // bit 7
328 u16 ext_status:1; // bit 8
329 u16 media_100BT2_HD:1; // bit 9
330 u16 media_100BT2_FD:1; // bit 10
331 u16 media_10BT_HD:1; // bit 11
332 u16 media_10BT_FD:1; // bit 12
333 u16 media_100BX_HD:1; // bit 13
334 u16 media_100BX_FD:1; // bit 14
335 u16 media_100BT4:1; // bit 15
336 } bits;
337 } BMSR_t, *PBMSR_t;
338
339 enum _mii_bmsr {
340 MII_BMSR_100BT4 = 0x8000,
341 MII_BMSR_100BX_FD = 0x4000,
342 MII_BMSR_100BX_HD = 0x2000,
343 MII_BMSR_10BT_FD = 0x1000,
344 MII_BMSR_10BT_HD = 0x0800,
345 MII_BMSR_100BT2_FD = 0x0400,
346 MII_BMSR_100BT2_HD = 0x0200,
347 MII_BMSR_EXT_STATUS = 0x0100,
348 MII_BMSR_PREAMBLE_SUPP = 0x0040,
349 MII_BMSR_AN_COMPLETE = 0x0020,
350 MII_BMSR_REMOTE_FAULT = 0x0010,
351 MII_BMSR_AN_ABILITY = 0x0008,
352 MII_BMSR_LINK_STATUS = 0x0004,
353 MII_BMSR_JABBER_DETECT = 0x0002,
354 MII_BMSR_EXT_CAP = 0x0001,
355 };
356
357 /* ANAR */
358 typedef union t_MII_ANAR {
359 u16 image;
360 struct {
361 u16 selector:5; // bit 4:0
362 u16 media_10BT_HD:1; // bit 5
363 u16 media_10BT_FD:1; // bit 6
364 u16 media_100BX_HD:1; // bit 7
365 u16 media_100BX_FD:1; // bit 8
366 u16 media_100BT4:1; // bit 9
367 u16 pause:1; // bit 10
368 u16 asymmetric:1; // bit 11
369 u16 _bit12:1; // bit 12
370 u16 remote_fault:1; // bit 13
371 u16 _bit14:1; // bit 14
372 u16 next_page:1; // bit 15
373 } bits;
374 } ANAR_t, *PANAR_t;
375
376 enum _mii_anar {
377 MII_ANAR_NEXT_PAGE = 0x8000,
378 MII_ANAR_REMOTE_FAULT = 0x4000,
379 MII_ANAR_ASYMMETRIC = 0x0800,
380 MII_ANAR_PAUSE = 0x0400,
381 MII_ANAR_100BT4 = 0x0200,
382 MII_ANAR_100BX_FD = 0x0100,
383 MII_ANAR_100BX_HD = 0x0080,
384 MII_ANAR_10BT_FD = 0x0020,
385 MII_ANAR_10BT_HD = 0x0010,
386 MII_ANAR_SELECTOR = 0x001f,
387 MII_IEEE8023_CSMACD = 0x0001,
388 };
389
390 /* ANLPAR */
391 typedef union t_MII_ANLPAR {
392 u16 image;
393 struct {
394 u16 selector:5; // bit 4:0
395 u16 media_10BT_HD:1; // bit 5
396 u16 media_10BT_FD:1; // bit 6
397 u16 media_100BX_HD:1; // bit 7
398 u16 media_100BX_FD:1; // bit 8
399 u16 media_100BT4:1; // bit 9
400 u16 pause:1; // bit 10
401 u16 asymmetric:1; // bit 11
402 u16 _bit12:1; // bit 12
403 u16 remote_fault:1; // bit 13
404 u16 _bit14:1; // bit 14
405 u16 next_page:1; // bit 15
406 } bits;
407 } ANLPAR_t, *PANLPAR_t;
408
409 enum _mii_anlpar {
410 MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
411 MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
412 MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
413 MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
414 MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
415 MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
416 MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
417 MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
418 MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
419 MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
420 };
421
422 /* Auto-Negotiation Expansion Register */
423 typedef union t_MII_ANER {
424 u16 image;
425 struct {
426 u16 lp_negotiable:1; // bit 0
427 u16 page_received:1; // bit 1
428 u16 nextpagable:1; // bit 2
429 u16 lp_nextpagable:1; // bit 3
430 u16 pdetect_fault:1; // bit 4
431 u16 _bit15_5:11; // bit 15:5
432 } bits;
433 } ANER_t, *PANER_t;
434
435 enum _mii_aner {
436 MII_ANER_PAR_DETECT_FAULT = 0x0010,
437 MII_ANER_LP_NEXTPAGABLE = 0x0008,
438 MII_ANER_NETXTPAGABLE = 0x0004,
439 MII_ANER_PAGE_RECEIVED = 0x0002,
440 MII_ANER_LP_NEGOTIABLE = 0x0001,
441 };
442
443 /* MASTER-SLAVE Control Register */
444 typedef union t_MII_MSCR {
445 u16 image;
446 struct {
447 u16 _bit_7_0:8; // bit 7:0
448 u16 media_1000BT_HD:1; // bit 8
449 u16 media_1000BT_FD:1; // bit 9
450 u16 port_type:1; // bit 10
451 u16 cfg_value:1; // bit 11
452 u16 cfg_enable:1; // bit 12
453 u16 test_mode:3; // bit 15:13
454 } bits;
455 } MSCR_t, *PMSCR_t;
456
457 enum _mii_mscr {
458 MII_MSCR_TEST_MODE = 0xe000,
459 MII_MSCR_CFG_ENABLE = 0x1000,
460 MII_MSCR_CFG_VALUE = 0x0800,
461 MII_MSCR_PORT_VALUE = 0x0400,
462 MII_MSCR_1000BT_FD = 0x0200,
463 MII_MSCR_1000BT_HD = 0X0100,
464 };
465
466 /* MASTER-SLAVE Status Register */
467 typedef union t_MII_MSSR {
468 u16 image;
469 struct {
470 u16 idle_err_count:8; // bit 7:0
471 u16 _bit_9_8:2; // bit 9:8
472 u16 lp_1000BT_HD:1; // bit 10
473 u16 lp_1000BT_FD:1; // bit 11
474 u16 remote_rcv_status:1; // bit 12
475 u16 local_rcv_status:1; // bit 13
476 u16 cfg_resolution:1; // bit 14
477 u16 cfg_fault:1; // bit 15
478 } bits;
479 } MSSR_t, *PMSSR_t;
480
481 enum _mii_mssr {
482 MII_MSSR_CFG_FAULT = 0x8000,
483 MII_MSSR_CFG_RES = 0x4000,
484 MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
485 MII_MSSR_REMOTE_RCVR = 0x1000,
486 MII_MSSR_LP_1000BT_HD = 0x0800,
487 MII_MSSR_LP_1000BT_FD = 0x0400,
488 MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
489 };
490
491 /* IEEE Extened Status Register */
492 typedef union t_MII_ESR {
493 u16 image;
494 struct {
495 u16 _bit_11_0:12; // bit 11:0
496 u16 media_1000BT_HD:2; // bit 12
497 u16 media_1000BT_FD:1; // bit 13
498 u16 media_1000BX_HD:1; // bit 14
499 u16 media_1000BX_FD:1; // bit 15
500 } bits;
501 } ESR_t, *PESR_t;
502
503 enum _mii_esr {
504 MII_ESR_1000BX_FD = 0x8000,
505 MII_ESR_1000BX_HD = 0x4000,
506 MII_ESR_1000BT_FD = 0x2000,
507 MII_ESR_1000BT_HD = 0x1000,
508 };
509 /* PHY Specific Control Register */
510 typedef union t_MII_PHY_SCR {
511 u16 image;
512 struct {
513 u16 disable_jabber:1; // bit 0
514 u16 polarity_reversal:1; // bit 1
515 u16 SEQ_test:1; // bit 2
516 u16 _bit_3:1; // bit 3
517 u16 disable_CLK125:1; // bit 4
518 u16 mdi_crossover_mode:2; // bit 6:5
519 u16 enable_ext_dist:1; // bit 7
520 u16 _bit_8_9:2; // bit 9:8
521 u16 force_link:1; // bit 10
522 u16 assert_CRS:1; // bit 11
523 u16 rcv_fifo_depth:2; // bit 13:12
524 u16 xmit_fifo_depth:2; // bit 15:14
525 } bits;
526 } PHY_SCR_t, *PPHY_SCR_t;
527
528 typedef enum t_MII_ADMIN_STATUS {
529 adm_reset,
530 adm_operational,
531 adm_loopback,
532 adm_power_down,
533 adm_isolate
534 } MII_ADMIN_t, *PMII_ADMIN_t;
535
536 typedef struct t_SROM {
537 u16 config_param; /* 0x00 */
538 u16 asic_ctrl; /* 0x02 */
539 u16 sub_vendor_id; /* 0x04 */
540 u16 sub_system_id; /* 0x06 */
541 u16 reserved1[12]; /* 0x08-0x1f */
542 u8 mac_addr[6]; /* 0x20-0x25 */
543 u8 reserved2[10]; /* 0x26-0x2f */
544 u8 sib[204]; /* 0x30-0xfb */
545 u32 crc; /* 0xfc-0xff */
546 } SROM_t, *PSROM_t;
547
548 /* Ioctl custom data */
549 struct ioctl_data {
550 char signature[10];
551 int cmd;
552 int len;
553 char *data;
554 };
555
556 struct mii_data {
557 __u16 reserved;
558 __u16 reg_num;
559 __u16 in_value;
560 __u16 out_value;
561 };
562
563 /* The Rx and Tx buffer descriptors. */
564 struct netdev_desc {
565 u64 next_desc;
566 u64 status;
567 u64 fraginfo;
568 };
569
570 #define PRIV_ALIGN 15 /* Required alignment mask */
571 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
572 within the structure. */
573 struct netdev_private {
574 /* Descriptor rings first for alignment. */
575 struct netdev_desc *rx_ring;
576 struct netdev_desc *tx_ring;
577 struct sk_buff *rx_skbuff[RX_RING_SIZE];
578 struct sk_buff *tx_skbuff[TX_RING_SIZE];
579 dma_addr_t tx_ring_dma;
580 dma_addr_t rx_ring_dma;
581 struct pci_dev *pdev;
582 spinlock_t lock;
583 struct net_device_stats stats;
584 unsigned int rx_buf_sz; /* Based on MTU+slack. */
585 unsigned int tx_full:1; /* The Tx queue is full. */
586 unsigned int full_duplex:1; /* Full-duplex operation requested. */
587 unsigned int speed; /* Operating speed */
588 unsigned int vlan; /* VLAN Id */
589 unsigned int an_enable; /* Auto-Negotiated Enable */
590 unsigned int chip_id; /* PCI table chip id */
591 unsigned int jumbo;
592 unsigned int int_count;
593 unsigned int int_timeout;
594 unsigned int coalesce:1;
595 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
596 unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */
597 unsigned long cur_tx, old_tx;
598 int wake_polarity;
599 char name[256]; /* net device description */
600 u8 duplex_polarity;
601 u16 mcast_filter[4];
602 u16 advertising; /* NWay media advertisement */
603 u16 negotiate; /* Negotiated media */
604 int phy_addr; /* PHY addresses. */
605 int tx_debug;
606 int rx_debug;
607 };
608
609 /* The station address location in the EEPROM. */
610 #ifdef USE_IO_OPS
611 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
612 #else
613 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
614 #endif
615 /* The struct pci_device_id consist of:
616 vendor, device Vendor and device ID to match (or PCI_ANY_ID)
617 subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID)
618 class Device class to match. The class_mask tells which bits
619 class_mask of the class are honored during the comparison.
620 driver_data Data private to the driver.
621 */
622 static struct pci_device_id rio_pci_tbl[] __devinitdata = {
623 {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
624 {0,}
625 };
626 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
627 #define TX_TIMEOUT (4*HZ)
628 #define PACKET_SIZE 1536
629 #define RIO_IO_SIZE 340
630 #ifdef RIO_DEBUG
631 #define DEBUG_TFD_DUMP(x) debug_tfd_dump(x)
632 #define DEBUG_RFD_DUMP(x,flag) debug_rfd_dump(x,flag)
633 #define DEBUG_PKT_DUMP(x,len) debug_pkt_dump(x,len)
634 #define DEBUG_PRINT printk
635
636 static inline void
637 debug_tfd_dump (struct netdev_private *np)
638 {
639 int i;
640 struct netdev_desc *desc;
641
642 if (np->tx_debug == 6) {
643 printk ("TFDone Dump: ");
644 for (i = 0; i < TX_RING_SIZE; i++) {
645 desc = &np->tx_ring[i];
646 if ((desc->fraginfo & 0xffffffffff) == 0)
647 printk ("X");
648 else
649 printk ("%d", (desc->status & TFDDone) ? 1 : 0);
650 }
651 printk ("\n");
652 }
653 if (np->tx_debug == 5) {
654 for (i = 0; i < TX_RING_SIZE; i++) {
655 desc = &np->tx_ring[i];
656 printk
657 ("cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
658 (u32) np->tx_ring_dma + i * sizeof (*desc),
659 (u32) desc->next_desc, (u32) desc->status,
660 (u32) (desc->fraginfo >> 32),
661 (u32) desc->fraginfo);
662 printk ("\n");
663 }
664 printk ("\n");
665 }
666 }
667 static inline void
668 debug_rfd_dump (struct netdev_private *np, int flag)
669 {
670 int i;
671 struct netdev_desc *desc;
672 int entry = np->cur_rx % RX_RING_SIZE;
673
674 if (np->rx_debug == 5) {
675 for (i = 0; i < RX_RING_SIZE; i++) {
676 desc = &np->rx_ring[i];
677 printk
678 ("cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
679 (u32) np->rx_ring_dma + i * sizeof (*desc),
680 (u32) desc->next_desc, (u32) desc->status,
681 (u32) (desc->fraginfo >> 32),
682 (u32) desc->fraginfo);
683 printk ("\n");
684 }
685 printk ("\n");
686 }
687
688 if (np->rx_debug == 6) {
689 if (flag == 1)
690 printk ("RFDone Dump: ");
691 else if (flag == 2)
692 printk ("Re-Filling: ");
693 for (i = 0; i < RX_RING_SIZE; i++) {
694 desc = &np->rx_ring[i];
695 printk ("%d", (desc->status & RFDDone) ? 1 : 0);
696 }
697 printk ("\n");
698 }
699 if (np->rx_debug == 7) {
700 printk (" In rcv_pkt(), entry %d status %4.4x %4.4x.\n",
701 entry, (u32) (np->rx_ring[entry].status >> 32),
702 (u32) np->rx_ring[entry].status);
703 }
704
705 }
706
707 static inline void
708 debug_pkt_dump (struct netdev_private *np, int pkt_len)
709 {
710 int entry = np->cur_rx % RX_RING_SIZE;
711 struct netdev_desc *desc = &np->rx_ring[entry];
712 u64 frame_status = le64_to_cpu (desc->status);
713 unsigned char *pchar;
714 unsigned char *phead;
715 int i;
716
717 if (np->rx_debug == 4) {
718 printk (" rcv_pkt: status was %4.4x %4.4x.\n",
719 (u32) (frame_status >> 32), (u32) frame_status);
720 }
721 if (np->rx_debug == 7) {
722
723 phead =
724 bus_to_virt (le64_to_cpu (desc->fraginfo & 0xffffffffff));
725 for (pchar = phead, i = 0; i < pkt_len; i++, pchar++) {
726 printk ("%02x ", *pchar);
727 if ((i + 1) % 20 == 0)
728 printk ("\n");
729 }
730 }
731 }
732 #else
733 #define DEBUG_TFD_DUMP(x) {}
734 #define DEBUG_RFD_DUMP(x,flag) {}
735 #define DEBUG_PKT_DUMP(x,len) {}
736 #define DEBUG_PRINT() {}
737 #endif
738
739 #endif /* __DL2K_H__ */
740