File: /usr/src/linux/drivers/net/dmfe.c
1 /*
2 dmfe.c: Version 1.36p1 2001-05-12 for Linux kernel 2.4.x
3
4 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
5 ethernet driver for Linux.
6 Copyright (C) 1997 Sten Wang
7
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License
10 as published by the Free Software Foundation; either version 2
11 of the License, or (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 DAVICOM Web-Site: www.davicom.com.tw
19
20 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
21 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
22
23 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
24
25 Marcelo Tosatti <marcelo@conectiva.com.br> :
26 Made it compile in 2.3 (device to net_device)
27
28 Alan Cox <alan@redhat.com> :
29 Cleaned up for kernel merge.
30 Removed the back compatibility support
31 Reformatted, fixing spelling etc as I went
32 Removed IRQ 0-15 assumption
33
34 Jeff Garzik <jgarzik@mandrakesoft.com> :
35 Updated to use new PCI driver API.
36 Resource usage cleanups.
37 Report driver version to user.
38
39 Tobias Ringstrom <tori@unhappy.mine.nu> :
40 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
41 Andrew Morton and Frank Davis for the SMP safety fixes.
42
43 TODO
44
45 Implement pci_driver::suspend() and pci_driver::resume()
46 power management methods.
47
48 Check and fix on 64bit and big endian boxes.
49
50 Test and make sure PCI latency is now correct for all cases.
51 */
52
53 #define DMFE_VERSION "1.36p1 (May 12, 2001)"
54
55 #include <linux/module.h>
56
57 #include <linux/kernel.h>
58 #include <linux/sched.h>
59 #include <linux/string.h>
60 #include <linux/timer.h>
61 #include <linux/ptrace.h>
62 #include <linux/errno.h>
63 #include <linux/ioport.h>
64 #include <linux/slab.h>
65 #include <linux/interrupt.h>
66 #include <linux/pci.h>
67 #include <linux/init.h>
68 #include <linux/version.h>
69 #include <linux/netdevice.h>
70 #include <linux/etherdevice.h>
71 #include <linux/skbuff.h>
72 #include <linux/delay.h>
73 #include <linux/spinlock.h>
74
75 #include <asm/processor.h>
76 #include <asm/bitops.h>
77 #include <asm/io.h>
78 #include <asm/dma.h>
79
80 #if BITS_PER_LONG == 64
81 #error FIXME: driver does not support 64-bit platforms
82 #endif
83
84
85 /* Board/System/Debug information/definition ---------------- */
86 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
87 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
88 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
89 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
90
91 #define DMFE_SUCC 0
92 #define DM9102_IO_SIZE 0x80
93 #define DM9102A_IO_SIZE 0x100
94 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
95 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
96 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
97 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
98 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
99 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
100 #define TX_BUF_ALLOC 0x600
101 #define RX_ALLOC_SIZE 0x620
102 #define DM910X_RESET 1
103 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
104 #define CR6_DEFAULT 0x00080000 /* HD */
105 #define CR7_DEFAULT 0x180c1
106 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
107 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
108 #define MAX_PACKET_SIZE 1514
109 #define DMFE_MAX_MULTICAST 14
110 #define RX_COPY_SIZE 100
111 #define MAX_CHECK_PACKET 0x8000
112 #define DM9801_NOISE_FLOOR 8
113 #define DM9802_NOISE_FLOOR 5
114
115 #define DMFE_10MHF 0
116 #define DMFE_100MHF 1
117 #define DMFE_10MFD 4
118 #define DMFE_100MFD 5
119 #define DMFE_AUTO 8
120 #define DMFE_1M_HPNA 0x10
121
122 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
123 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
124 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
125 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
126 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
127 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
128
129 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
130 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
131 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
132
133 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR "<DMFE>: %s %lx\n", (msg), (long) (value))
134
135 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR "<DMFE>: Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
136
137
138 /* CR9 definition: SROM/MII */
139 #define CR9_SROM_READ 0x4800
140 #define CR9_SRCS 0x1
141 #define CR9_SRCLK 0x2
142 #define CR9_CRDOUT 0x8
143 #define SROM_DATA_0 0x0
144 #define SROM_DATA_1 0x4
145 #define PHY_DATA_1 0x20000
146 #define PHY_DATA_0 0x00000
147 #define MDCLKH 0x10000
148
149 #define PHY_POWER_DOWN 0x800
150
151 #define SROM_V41_CODE 0x14
152
153 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
154
155 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
156 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
157
158 /* Sten Check */
159 #define DEVICE net_device
160
161 /* Structure/enum declaration ------------------------------- */
162 struct tx_desc {
163 u32 tdes0, tdes1, tdes2, tdes3;
164 u32 tx_skb_ptr;
165 u32 tx_buf_ptr;
166 u32 next_tx_desc;
167 u32 reserved;
168 };
169
170 struct rx_desc {
171 u32 rdes0, rdes1, rdes2, rdes3;
172 u32 rx_skb_ptr;
173 u32 rx_buf_ptr;
174 u32 next_rx_desc;
175 u32 reserved;
176 };
177
178 struct dmfe_board_info {
179 u32 chip_id; /* Chip vendor/Device ID */
180 u32 chip_revision; /* Chip revision */
181 struct DEVICE *next_dev; /* next device */
182 struct pci_dev * net_dev; /* PCI device */
183 spinlock_t lock;
184
185 long ioaddr; /* I/O base address */
186 u32 cr0_data;
187 u32 cr5_data;
188 u32 cr6_data;
189 u32 cr7_data;
190 u32 cr15_data;
191
192 /* pointer for memory physical address */
193 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
194 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
195 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
196 dma_addr_t first_tx_desc_dma;
197 dma_addr_t first_rx_desc_dma;
198
199 /* descriptor pointer */
200 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
201 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
202 unsigned char *desc_pool_ptr; /* descriptor pool memory */
203 struct tx_desc *first_tx_desc;
204 struct tx_desc *tx_insert_ptr;
205 struct tx_desc *tx_remove_ptr;
206 struct rx_desc *first_rx_desc;
207 struct rx_desc *rx_insert_ptr;
208 struct rx_desc *rx_ready_ptr; /* packet come pointer */
209 unsigned long tx_packet_cnt; /* transmitted packet count */
210 unsigned long tx_queue_cnt; /* wait to send packet count */
211 unsigned long rx_avail_cnt; /* available rx descriptor count */
212 unsigned long interval_rx_cnt; /* rx packet count a callback time */
213
214 u16 HPNA_command; /* For HPNA register 16 */
215 u16 HPNA_timer; /* For HPNA remote device check */
216 u16 dbug_cnt;
217 u16 NIC_capability; /* NIC media capability */
218 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
219
220 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
221 u8 chip_type; /* Keep DM9102A chip type */
222 u8 media_mode; /* user specify media mode */
223 u8 op_mode; /* real work media mode */
224 u8 phy_addr;
225 u8 link_failed; /* Ever link failed */
226 u8 wait_reset; /* Hardware failed, need to reset */
227 u8 dm910x_chk_mode; /* Operating mode check */
228 u8 first_in_callback; /* Flag to record state */
229 struct timer_list timer;
230
231 /* System defined statistic counter */
232 struct net_device_stats stats;
233
234 /* Driver defined statistic counter */
235 unsigned long tx_fifo_underrun;
236 unsigned long tx_loss_carrier;
237 unsigned long tx_no_carrier;
238 unsigned long tx_late_collision;
239 unsigned long tx_excessive_collision;
240 unsigned long tx_jabber_timeout;
241 unsigned long reset_count;
242 unsigned long reset_cr8;
243 unsigned long reset_fatal;
244 unsigned long reset_TXtimeout;
245
246 /* NIC SROM data */
247 unsigned char srom[128];
248 };
249
250 enum dmfe_offsets {
251 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
252 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
253 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
254 DCR15 = 0x78
255 };
256
257 enum dmfe_CR6_bits {
258 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
259 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
260 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
261 };
262
263 /* Global variable declaration ----------------------------- */
264 static int __devinitdata printed_version;
265 static char version[] __devinitdata =
266 KERN_INFO "Davicom DM9xxx net driver, version " DMFE_VERSION "\n";
267
268 static int dmfe_debug;
269 static unsigned char dmfe_media_mode = DMFE_AUTO;
270 static u32 dmfe_cr6_user_set;
271
272 /* For module input parameter */
273 static int debug;
274 static u32 cr6set;
275 static unsigned char mode = 8;
276 static u8 chkmode = 1;
277 static u8 HPNA_mode; /* Default: Low Power/High Speed */
278 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
279 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
280 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
281 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
282 4: TX pause packet */
283
284 unsigned long CrcTable[256] = {
285 0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL,
286 0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L,
287 0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L,
288 0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L,
289 0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL,
290 0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L,
291 0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL,
292 0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L,
293 0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L,
294 0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL,
295 0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L,
296 0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L,
297 0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L,
298 0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL,
299 0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L,
300 0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL,
301 0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL,
302 0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L,
303 0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L,
304 0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L,
305 0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL,
306 0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L,
307 0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL,
308 0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L,
309 0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L,
310 0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL,
311 0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L,
312 0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L,
313 0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L,
314 0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL,
315 0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L,
316 0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL,
317 0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL,
318 0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L,
319 0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L,
320 0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L,
321 0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL,
322 0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L,
323 0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL,
324 0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L,
325 0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L,
326 0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL,
327 0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L,
328 0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L,
329 0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L,
330 0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL,
331 0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L,
332 0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL,
333 0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL,
334 0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L,
335 0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L,
336 0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L,
337 0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL,
338 0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L,
339 0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL,
340 0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L,
341 0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L,
342 0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL,
343 0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L,
344 0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L,
345 0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L,
346 0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL,
347 0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L,
348 0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL
349 };
350
351 /* function declaration ------------------------------------- */
352 static int dmfe_open(struct DEVICE *);
353 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
354 static int dmfe_stop(struct DEVICE *);
355 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
356 static void dmfe_set_filter_mode(struct DEVICE *);
357 static int dmfe_do_ioctl(struct DEVICE *, struct ifreq *, int);
358 static u16 read_srom_word(long ,int);
359 static void dmfe_interrupt(int , void *, struct pt_regs *);
360 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
361 static void allocated_rx_buffer(struct dmfe_board_info *);
362 static void update_cr6(u32, unsigned long);
363 static void send_filter_frame(struct DEVICE * ,int);
364 static void dm9132_id_table(struct DEVICE * ,int);
365 static u16 phy_read(unsigned long, u8, u8, u32);
366 static void phy_write(unsigned long, u8, u8, u16, u32);
367 static void phy_write_1bit(unsigned long, u32);
368 static u16 phy_read_1bit(unsigned long);
369 static u8 dmfe_sense_speed(struct dmfe_board_info *);
370 static void dmfe_process_mode(struct dmfe_board_info *);
371 static void dmfe_timer(unsigned long);
372 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
373 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
374 static void dmfe_reused_skb(struct dmfe_board_info *, struct sk_buff *);
375 static void dmfe_dynamic_reset(struct DEVICE *);
376 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
377 static void dmfe_init_dm910x(struct DEVICE *);
378 static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
379 static void dmfe_parse_srom(struct dmfe_board_info *);
380 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
381 static void dmfe_program_DM9802(struct dmfe_board_info *);
382 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
383 static void dmfe_set_phyxcer(struct dmfe_board_info *);
384
385 /* DM910X network baord routine ---------------------------- */
386
387 /*
388 * Search DM910X board ,allocate space and register it
389 */
390
391 static int __devinit dmfe_init_one (struct pci_dev *pdev,
392 const struct pci_device_id *ent)
393 {
394 unsigned long pci_iobase;
395 u8 pci_irqline;
396 struct dmfe_board_info *db; /* board information structure */
397 int i;
398 struct net_device *dev;
399 u32 dev_rev, pci_pmr;
400
401 if (!printed_version++)
402 printk(version);
403
404 DMFE_DBUG(0, "dmfe_init_one()", 0);
405
406 /* Enable Master/IO access, Disable memory access */
407 i = pci_enable_device(pdev);
408 if (i)
409 return i;
410 pci_set_master(pdev);
411
412 pci_iobase = pci_resource_start(pdev, 0);
413 pci_irqline = pdev->irq;
414
415 /* iobase check */
416 if (pci_iobase == 0) {
417 printk(KERN_ERR "<DMFE>: I/O base is zero\n");
418 return -ENODEV;
419 }
420
421 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
422
423 /* Set Latency Timer 80h */
424 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
425 Need a PCI quirk.. */
426
427 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
428 #endif
429
430 /* Read Chip revision */
431 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
432
433 /* Init network device */
434 dev = alloc_etherdev(sizeof(*db));
435 if (dev == NULL)
436 return -ENOMEM;
437 SET_MODULE_OWNER(dev);
438
439 /* IO range check */
440 if (pci_resource_len (pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
441 printk(KERN_ERR "<DMFE>: Allocated I/O size too small\n");
442 goto err_out;
443 }
444
445 if (!request_region(pci_iobase,
446 pci_resource_len (pdev, 0),
447 dev->name)) {
448 printk(KERN_ERR "<DMFE>: I/O conflict : IO=%lx Range=%x\n",
449 pci_iobase, CHK_IO_SIZE(pdev, dev_rev));
450 goto err_out;
451 }
452
453 /* Init system & device */
454 db = dev->priv;
455
456 /* Allocated Tx/Rx descriptor memory */
457 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
458 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
459
460 db->first_tx_desc = (struct tx_desc *)db->desc_pool_ptr;
461 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
462 db->buf_pool_start = db->buf_pool_ptr;
463 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
464
465 pdev->driver_data = dev;
466
467 db->chip_id = ent->driver_data;
468 db->ioaddr = pci_iobase;
469 db->chip_revision = dev_rev;
470
471 db->net_dev = pdev;
472
473 dev->base_addr = pci_iobase;
474 dev->irq = pci_irqline;
475 pci_set_drvdata(pdev, dev);
476 dev->open = &dmfe_open;
477 dev->hard_start_xmit = &dmfe_start_xmit;
478 dev->stop = &dmfe_stop;
479 dev->get_stats = &dmfe_get_stats;
480 dev->set_multicast_list = &dmfe_set_filter_mode;
481 dev->do_ioctl = &dmfe_do_ioctl;
482 spin_lock_init(&db->lock);
483
484 pci_read_config_dword(pdev, 0x50, &pci_pmr);
485 pci_pmr &= 0x70000;
486 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
487 db->chip_type = 1; /* DM9102A E3 */
488 else
489 db->chip_type = 0;
490
491 /* read 64 word srom data */
492 for (i = 0; i < 64; i++)
493 ((u16 *) db->srom)[i] = read_srom_word(pci_iobase, i);
494
495 /* Set Node address */
496 for (i = 0; i < 6; i++)
497 dev->dev_addr[i] = db->srom[20 + i];
498
499 i = register_netdev (dev);
500 if (i) goto err_out;
501
502 printk(KERN_INFO "%s: Davicom DM%04lx at 0x%lx,",
503 dev->name,
504 ent->driver_data >> 16,
505 pci_iobase);
506 for (i = 0; i < 6; i++)
507 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
508 printk(", IRQ %d\n", pci_irqline);
509
510 return 0;
511
512 err_out:
513 pci_set_drvdata(pdev, NULL);
514 kfree(dev);
515 return -ENODEV;
516 }
517
518
519 static void __exit dmfe_remove_one (struct pci_dev *pdev)
520 {
521 struct net_device *dev = pci_get_drvdata(pdev);
522 struct dmfe_board_info *db = dev->priv;
523
524 DMFE_DBUG(0, "dmfe_remove_one()", 0);
525
526 if (dev) {
527 pci_free_consistent(db->net_dev, sizeof(struct tx_desc) *
528 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
529 db->desc_pool_dma_ptr);
530 pci_free_consistent(db->net_dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
531 db->buf_pool_ptr, db->buf_pool_dma_ptr);
532 unregister_netdev(dev);
533 release_region(dev->base_addr,
534 CHK_IO_SIZE(pdev, db->chip_revision));
535 kfree(dev); /* free board information */
536 pci_set_drvdata(pdev, NULL);
537 }
538
539 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
540 }
541
542
543 /*
544 * Open the interface.
545 * The interface is opened whenever "ifconfig" actives it.
546 */
547
548 static int dmfe_open(struct DEVICE *dev)
549 {
550 int ret;
551 struct dmfe_board_info *db = dev->priv;
552
553 DMFE_DBUG(0, "dmfe_open", 0);
554
555 ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
556 if (ret)
557 return ret;
558
559 /* system variable init */
560 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
561 db->tx_packet_cnt = 0;
562 db->tx_queue_cnt = 0;
563 db->rx_avail_cnt = 0;
564 db->link_failed = 1;
565 db->wait_reset = 0;
566
567 db->first_in_callback = 0;
568 db->NIC_capability = 0xf; /* All capability*/
569 db->PHY_reg4 = 0x1e0;
570
571 /* CR6 operation mode decision */
572 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
573 (db->chip_revision >= 0x02000030) ) {
574 db->cr6_data |= DMFE_TXTH_256;
575 db->cr0_data = CR0_DEFAULT;
576 db->dm910x_chk_mode=4; /* Enter the normal mode */
577 } else {
578 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
579 db->cr0_data = 0;
580 db->dm910x_chk_mode = 1; /* Enter the check mode */
581 }
582
583 /* Initilize DM910X board */
584 dmfe_init_dm910x(dev);
585
586 /* Active System Interface */
587 netif_wake_queue(dev);
588
589 /* set and active a timer process */
590 init_timer(&db->timer);
591 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
592 db->timer.data = (unsigned long)dev;
593 db->timer.function = &dmfe_timer;
594 add_timer(&db->timer);
595
596 return 0;
597 }
598
599
600 /* Initilize DM910X board
601 * Reset DM910X board
602 * Initilize TX/Rx descriptor chain structure
603 * Send the set-up frame
604 * Enable Tx/Rx machine
605 */
606
607 static void dmfe_init_dm910x(struct DEVICE *dev)
608 {
609 struct dmfe_board_info *db = dev->priv;
610 unsigned long ioaddr = db->ioaddr;
611
612 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
613
614 /* Reset DM910x MAC controller */
615 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
616 udelay(100);
617 outl(db->cr0_data, ioaddr + DCR0);
618 udelay(5);
619
620 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
621 db->phy_addr = 1;
622
623 /* Parser SROM and media mode */
624 dmfe_parse_srom(db);
625 db->media_mode = dmfe_media_mode;
626
627 /* RESET Phyxcer Chip by GPR port bit 7 */
628 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
629 if (db->chip_id == PCI_DM9009_ID) {
630 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
631 mdelay(300); /* Delay 300 ms */
632 }
633 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
634
635 /* Process Phyxcer Media Mode */
636 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
637 dmfe_set_phyxcer(db);
638
639 /* Media Mode Process */
640 if ( !(db->media_mode & DMFE_AUTO) )
641 db->op_mode = db->media_mode; /* Force Mode */
642
643 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
644 dmfe_descriptor_init(db, ioaddr);
645
646 /* Init CR6 to program DM910x operation */
647 update_cr6(db->cr6_data, ioaddr);
648
649 /* Send setup frame */
650 if (db->chip_id == PCI_DM9132_ID)
651 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
652 else
653 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
654
655 /* Init CR7, interrupt active bit */
656 db->cr7_data = CR7_DEFAULT;
657 outl(db->cr7_data, ioaddr + DCR7);
658
659 /* Init CR15, Tx jabber and Rx watchdog timer */
660 outl(db->cr15_data, ioaddr + DCR15);
661
662 /* Enable DM910X Tx/Rx function */
663 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
664 update_cr6(db->cr6_data, ioaddr);
665 }
666
667
668 /*
669 * Hardware start transmission.
670 * Send a packet to media from the upper layer.
671 */
672
673 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
674 {
675 struct dmfe_board_info *db = dev->priv;
676 struct tx_desc *txptr;
677 unsigned long flags;
678
679 DMFE_DBUG(0, "dmfe_start_xmit", 0);
680
681 /* Resource flag check */
682 netif_stop_queue(dev);
683
684 /* Too large packet check */
685 if (skb->len > MAX_PACKET_SIZE) {
686 printk(KERN_ERR "<DMFE>: big packet = %d\n", (u16)skb->len);
687 dev_kfree_skb(skb);
688 return 0;
689 }
690
691 spin_lock_irqsave(&db->lock, flags);
692
693 /* No Tx resource check, it never happen nromally */
694 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
695 spin_unlock_irqrestore(&db->lock, flags);
696 printk(KERN_ERR "<DMFE>: No Tx resource %ld\n", db->tx_queue_cnt);
697 return 1;
698 }
699
700 /* Disable NIC interrupt */
701 outl(0, dev->base_addr + DCR7);
702
703 /* transmit this packet */
704 txptr = db->tx_insert_ptr;
705 memcpy( (char *) txptr->tx_buf_ptr, (char *) skb->data, skb->len);
706 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
707
708 /* Point to next transmit free descriptor */
709 db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
710
711 /* Transmit Packet Process */
712 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
713 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
714 db->tx_packet_cnt++; /* Ready to send */
715 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
716 dev->trans_start = jiffies; /* saved time stamp */
717 } else {
718 db->tx_queue_cnt++; /* queue TX packet */
719 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
720 }
721
722 /* Tx resource check */
723 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
724 netif_wake_queue(dev);
725
726 /* free this SKB */
727 dev_kfree_skb(skb);
728
729 /* Restore CR7 to enable interrupt */
730 spin_unlock_irqrestore(&db->lock, flags);
731 outl(db->cr7_data, dev->base_addr + DCR7);
732
733 return 0;
734 }
735
736
737 /*
738 * Stop the interface.
739 * The interface is stopped when it is brought.
740 */
741
742 static int dmfe_stop(struct DEVICE *dev)
743 {
744 struct dmfe_board_info *db = dev->priv;
745 unsigned long ioaddr = dev->base_addr;
746
747 DMFE_DBUG(0, "dmfe_stop", 0);
748
749 /* disable system */
750 netif_stop_queue(dev);
751
752 /* deleted timer */
753 del_timer_sync(&db->timer);
754
755 /* Reset & stop DM910X board */
756 outl(DM910X_RESET, ioaddr + DCR0);
757 udelay(5);
758 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
759
760 /* free interrupt */
761 free_irq(dev->irq, dev);
762
763 /* free allocated rx buffer */
764 dmfe_free_rxbuffer(db);
765
766 #if 0
767 /* show statistic counter */
768 printk("<DMFE>: FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
769 db->tx_fifo_underrun, db->tx_excessive_collision,
770 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
771 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
772 db->reset_fatal, db->reset_TXtimeout);
773 #endif
774
775 return 0;
776 }
777
778
779 /*
780 * DM9102 insterrupt handler
781 * receive the packet to upper layer, free the transmitted packet
782 */
783
784 static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
785 {
786 struct DEVICE *dev = dev_id;
787 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
788 unsigned long ioaddr = dev->base_addr;
789 unsigned long flags;
790
791 DMFE_DBUG(0, "dmfe_interrupt()", 0);
792
793 if (!dev) {
794 DMFE_DBUG(1, "dmfe_interrupt() without DEVICE arg", 0);
795 return;
796 }
797
798 spin_lock_irqsave(&db->lock, flags);
799
800 /* Got DM910X status */
801 db->cr5_data = inl(ioaddr + DCR5);
802 outl(db->cr5_data, ioaddr + DCR5);
803 if ( !(db->cr5_data & 0xc1) ) {
804 spin_unlock_irqrestore(&db->lock, flags);
805 return;
806 }
807
808 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
809 outl(0, ioaddr + DCR7);
810
811 /* Check system status */
812 if (db->cr5_data & 0x2000) {
813 /* system bus error happen */
814 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
815 db->reset_fatal++;
816 db->wait_reset = 1; /* Need to RESET */
817 spin_unlock_irqrestore(&db->lock, flags);
818 return;
819 }
820
821 /* Received the coming packet */
822 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
823 dmfe_rx_packet(dev, db);
824
825 /* reallocated rx descriptor buffer */
826 if (db->rx_avail_cnt<RX_DESC_CNT)
827 allocated_rx_buffer(db);
828
829 /* Free the transmitted descriptor */
830 if ( db->cr5_data & 0x01)
831 dmfe_free_tx_pkt(dev, db);
832
833 /* Mode Check */
834 if (db->dm910x_chk_mode & 0x2) {
835 db->dm910x_chk_mode = 0x4;
836 db->cr6_data |= 0x100;
837 update_cr6(db->cr6_data, db->ioaddr);
838 }
839
840 /* Restore CR7 to enable interrupt mask */
841 outl(db->cr7_data, ioaddr + DCR7);
842
843 spin_unlock_irqrestore(&db->lock, flags);
844 }
845
846
847 /*
848 * Free TX resource after TX complete
849 */
850
851 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
852 {
853 struct tx_desc *txptr;
854 unsigned long ioaddr = dev->base_addr;
855
856 txptr = db->tx_remove_ptr;
857 while(db->tx_packet_cnt) {
858 /* printk("<DMFE>: tdes0=%x\n", txptr->tdes0); */
859 if (txptr->tdes0 & 0x80000000)
860 break;
861
862 /* A packet sent completed */
863 db->tx_packet_cnt--;
864 db->stats.tx_packets++;
865
866 /* Transmit statistic counter */
867 if ( txptr->tdes0 != 0x7fffffff ) {
868 /* printk("<DMFE>: tdes0=%x\n", txptr->tdes0); */
869 db->stats.collisions += (txptr->tdes0 >> 3) & 0xf;
870 db->stats.tx_bytes += txptr->tdes1 & 0x7ff;
871 if (txptr->tdes0 & TDES0_ERR_MASK) {
872 db->stats.tx_errors++;
873
874 if (txptr->tdes0 & 0x0002) { /* UnderRun */
875 db->tx_fifo_underrun++;
876 if ( !(db->cr6_data & CR6_SFT) ) {
877 db->cr6_data = db->cr6_data | CR6_SFT;
878 update_cr6(db->cr6_data, db->ioaddr);
879 }
880 }
881 if (txptr->tdes0 & 0x0100)
882 db->tx_excessive_collision++;
883 if (txptr->tdes0 & 0x0200)
884 db->tx_late_collision++;
885 if (txptr->tdes0 & 0x0400)
886 db->tx_no_carrier++;
887 if (txptr->tdes0 & 0x0800)
888 db->tx_loss_carrier++;
889 if (txptr->tdes0 & 0x4000)
890 db->tx_jabber_timeout++;
891 }
892 }
893
894 txptr = (struct tx_desc *) txptr->next_tx_desc;
895 }/* End of while */
896
897 /* Update TX remove pointer to next */
898 db->tx_remove_ptr = (struct tx_desc *) txptr;
899
900 /* Send the Tx packet in queue */
901 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
902 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
903 db->tx_packet_cnt++; /* Ready to send */
904 db->tx_queue_cnt--;
905 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
906 dev->trans_start = jiffies; /* saved time stamp */
907 }
908
909 /* Resource available check */
910 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
911 netif_wake_queue(dev); /* Active upper layer, send again */
912 }
913
914
915 /*
916 * Receive the come packet and pass to upper layer
917 */
918
919 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
920 {
921 struct rx_desc *rxptr;
922 struct sk_buff *skb;
923 int rxlen;
924
925 rxptr = db->rx_ready_ptr;
926
927 while(db->rx_avail_cnt) {
928 if (rxptr->rdes0 & 0x80000000) /* packet owner check */
929 break;
930
931 db->rx_avail_cnt--;
932 db->interval_rx_cnt++;
933
934 if ( (rxptr->rdes0 & 0x300) != 0x300) {
935 /* A packet without First/Last flag */
936 /* reused this SKB */
937 DMFE_DBUG(0, "Reused SK buffer, rdes0", rxptr->rdes0);
938 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
939 } else {
940 /* A packet with First/Last flag */
941 rxlen = ( (rxptr->rdes0 >> 16) & 0x3fff) - 4;
942
943 /* error summary bit check */
944 if (rxptr->rdes0 & 0x8000) {
945 /* This is a error packet */
946 //printk("<DMFE>: rdes0: %lx\n", rxptr->rdes0);
947 db->stats.rx_errors++;
948 if (rxptr->rdes0 & 1)
949 db->stats.rx_fifo_errors++;
950 if (rxptr->rdes0 & 2)
951 db->stats.rx_crc_errors++;
952 if (rxptr->rdes0 & 0x80)
953 db->stats.rx_length_errors++;
954 }
955
956 if ( !(rxptr->rdes0 & 0x8000) ||
957 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
958 skb = (struct sk_buff *) rxptr->rx_skb_ptr;
959
960 /* Received Packet CRC check need or not */
961 if ( (db->dm910x_chk_mode & 1) &&
962 (cal_CRC(skb->tail, rxlen, 1) !=
963 (*(unsigned long *) (skb->tail+rxlen) )
964 ) ) {
965 /* Found a error received packet */
966 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
967 db->dm910x_chk_mode = 3;
968 } else {
969 /* Good packet, send to upper layer */
970 /* Shorst packet used new SKB */
971 if ( (rxlen < RX_COPY_SIZE) &&
972 ( (skb = dev_alloc_skb(rxlen + 2) )
973 != NULL) ) {
974 /* size less than COPY_SIZE, allocated a rxlen SKB */
975 skb->dev = dev;
976 skb_reserve(skb, 2); /* 16byte align */
977 memcpy(skb_put(skb, rxlen), ((struct sk_buff *) rxptr->rx_skb_ptr)->tail, rxlen);
978 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
979 } else {
980 skb->dev = dev;
981 skb_put(skb, rxlen);
982 }
983 skb->protocol = eth_type_trans(skb, dev);
984 netif_rx(skb);
985 dev->last_rx = jiffies;
986 db->stats.rx_packets++;
987 db->stats.rx_bytes += rxlen;
988 }
989 } else {
990 /* Reuse SKB buffer when the packet is error */
991 DMFE_DBUG(0, "Reused SK buffer, rdes0", rxptr->rdes0);
992 dmfe_reused_skb(db, (struct sk_buff *) rxptr->rx_skb_ptr);
993 }
994 }
995
996 rxptr = (struct rx_desc *) rxptr->next_rx_desc;
997 }
998
999 db->rx_ready_ptr = rxptr;
1000 }
1001
1002
1003 /*
1004 * Get statistics from driver.
1005 */
1006
1007 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
1008 {
1009 struct dmfe_board_info *db = (struct dmfe_board_info *)dev->priv;
1010
1011 DMFE_DBUG(0, "dmfe_get_stats", 0);
1012 return &db->stats;
1013 }
1014
1015
1016 /*
1017 * Set DM910X multicast address
1018 */
1019
1020 static void dmfe_set_filter_mode(struct DEVICE * dev)
1021 {
1022 struct dmfe_board_info *db = dev->priv;
1023 unsigned long flags;
1024
1025 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1026 spin_lock_irqsave(&db->lock, flags);
1027
1028 if (dev->flags & IFF_PROMISC) {
1029 DMFE_DBUG(0, "Enable PROM Mode", 0);
1030 db->cr6_data |= CR6_PM | CR6_PBF;
1031 update_cr6(db->cr6_data, db->ioaddr);
1032 spin_unlock_irqrestore(&db->lock, flags);
1033 return;
1034 }
1035
1036 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1037 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1038 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1039 db->cr6_data |= CR6_PAM;
1040 spin_unlock_irqrestore(&db->lock, flags);
1041 return;
1042 }
1043
1044 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1045 if (db->chip_id == PCI_DM9132_ID)
1046 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1047 else
1048 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1049 spin_unlock_irqrestore(&db->lock, flags);
1050 }
1051
1052
1053 /*
1054 * Process the upper socket ioctl command
1055 */
1056
1057 static int dmfe_do_ioctl(struct DEVICE *dev, struct ifreq *ifr, int cmd)
1058 {
1059 DMFE_DBUG(0, "dmfe_do_ioctl()", 0);
1060 return 0;
1061 }
1062
1063
1064 /*
1065 * A periodic timer routine
1066 * Dynamic media sense, allocated Rx buffer...
1067 */
1068
1069 static void dmfe_timer(unsigned long data)
1070 {
1071 u32 tmp_cr8;
1072 unsigned char tmp_cr12;
1073 struct DEVICE *dev = (struct DEVICE *) data;
1074 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
1075 unsigned long flags;
1076
1077 DMFE_DBUG(0, "dmfe_timer()", 0);
1078 spin_lock_irqsave(&db->lock, flags);
1079
1080 /* Media mode process when Link OK before enter this route */
1081 if (db->first_in_callback == 0) {
1082 db->first_in_callback = 1;
1083 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1084 db->cr6_data &= ~0x40000;
1085 update_cr6(db->cr6_data, db->ioaddr);
1086 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1087 db->cr6_data |= 0x40000;
1088 update_cr6(db->cr6_data, db->ioaddr);
1089 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1090 add_timer(&db->timer);
1091 spin_unlock_irqrestore(&db->lock, flags);
1092 return;
1093 }
1094 }
1095
1096
1097 /* Operating Mode Check */
1098 if ( (db->dm910x_chk_mode & 0x1) &&
1099 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1100 db->dm910x_chk_mode = 0x4;
1101
1102 /* Dynamic reset DM910X : system error or transmit time-out */
1103 tmp_cr8 = inl(db->ioaddr + DCR8);
1104 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1105 db->reset_cr8++;
1106 db->wait_reset = 1;
1107 }
1108 db->interval_rx_cnt = 0;
1109
1110 /* TX polling kick monitor */
1111 if ( db->tx_packet_cnt &&
1112 ((jiffies - dev->trans_start) > DMFE_TX_KICK) ) {
1113 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1114
1115 /* TX Timeout */
1116 if ( (jiffies - dev->trans_start) > DMFE_TX_TIMEOUT ) {
1117 db->reset_TXtimeout++;
1118 db->wait_reset = 1;
1119 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1120 dev->name);
1121 }
1122 }
1123
1124 if (db->wait_reset) {
1125 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1126 db->reset_count++;
1127 dmfe_dynamic_reset(dev);
1128 db->first_in_callback = 0;
1129 db->timer.expires = DMFE_TIMER_WUT;
1130 add_timer(&db->timer);
1131 spin_unlock_irqrestore(&db->lock, flags);
1132 return;
1133 }
1134
1135 /* Link status check, Dynamic media type change */
1136 if (db->chip_id == PCI_DM9132_ID)
1137 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1138 else
1139 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1140
1141 if ( ((db->chip_id == PCI_DM9102_ID) &&
1142 (db->chip_revision == 0x02000030)) ||
1143 ((db->chip_id == PCI_DM9132_ID) &&
1144 (db->chip_revision == 0x02000010)) ) {
1145 /* DM9102A Chip */
1146 if (tmp_cr12 & 2)
1147 tmp_cr12 = 0x0; /* Link failed */
1148 else
1149 tmp_cr12 = 0x3; /* Link OK */
1150 }
1151
1152 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1153 /* Link Failed */
1154 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1155 db->link_failed = 1;
1156
1157 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1158 /* AUTO or force 1M Homerun/Longrun don't need */
1159 if ( !(db->media_mode & 0x38) )
1160 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1161
1162 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1163 if (db->media_mode & DMFE_AUTO) {
1164 /* 10/100M link failed, used 1M Home-Net */
1165 db->cr6_data|=0x00040000; /* bit18=1, MII */
1166 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1167 update_cr6(db->cr6_data, db->ioaddr);
1168 }
1169 } else
1170 if ((tmp_cr12 & 0x3) && db->link_failed) {
1171 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1172 db->link_failed = 0;
1173
1174 /* Auto Sense Speed */
1175 if ( (db->media_mode & DMFE_AUTO) &&
1176 dmfe_sense_speed(db) )
1177 db->link_failed = 1;
1178 dmfe_process_mode(db);
1179 /* SHOW_MEDIA_TYPE(db->op_mode); */
1180 }
1181
1182 /* HPNA remote command check */
1183 if (db->HPNA_command & 0xf00) {
1184 db->HPNA_timer--;
1185 if (!db->HPNA_timer)
1186 dmfe_HPNA_remote_cmd_chk(db);
1187 }
1188
1189 /* Timer active again */
1190 db->timer.expires = DMFE_TIMER_WUT;
1191 add_timer(&db->timer);
1192 spin_unlock_irqrestore(&db->lock, flags);
1193 }
1194
1195
1196 /*
1197 * Dynamic reset the DM910X board
1198 * Stop DM910X board
1199 * Free Tx/Rx allocated memory
1200 * Reset DM910X board
1201 * Re-initilize DM910X board
1202 */
1203
1204 static void dmfe_dynamic_reset(struct DEVICE *dev)
1205 {
1206 struct dmfe_board_info *db = dev->priv;
1207
1208 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1209
1210 /* Sopt MAC controller */
1211 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1212 update_cr6(db->cr6_data, dev->base_addr);
1213 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1214 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1215
1216 /* Disable upper layer interface */
1217 netif_stop_queue(dev);
1218
1219 /* Free Rx Allocate buffer */
1220 dmfe_free_rxbuffer(db);
1221
1222 /* system variable init */
1223 db->tx_packet_cnt = 0;
1224 db->tx_queue_cnt = 0;
1225 db->rx_avail_cnt = 0;
1226 db->link_failed = 1;
1227 db->wait_reset = 0;
1228
1229 /* Re-initilize DM910X board */
1230 dmfe_init_dm910x(dev);
1231
1232 /* Restart upper layer interface */
1233 netif_wake_queue(dev);
1234 }
1235
1236
1237 /*
1238 * free all allocated rx buffer
1239 */
1240
1241 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1242 {
1243 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1244
1245 /* free allocated rx buffer */
1246 while (db->rx_avail_cnt) {
1247 dev_kfree_skb( (void *) (db->rx_ready_ptr->rx_skb_ptr) );
1248 db->rx_ready_ptr = (struct rx_desc *) db->rx_ready_ptr->next_rx_desc;
1249 db->rx_avail_cnt--;
1250 }
1251 }
1252
1253
1254 /*
1255 * Reused the SK buffer
1256 */
1257
1258 static void dmfe_reused_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1259 {
1260 struct rx_desc *rxptr = db->rx_insert_ptr;
1261
1262 if (!(rxptr->rdes0 & 0x80000000)) {
1263 rxptr->rx_skb_ptr = (u32) skb;
1264 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->net_dev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1265 rxptr->rdes0 = cpu_to_le32(0x80000000);
1266 db->rx_avail_cnt++;
1267 db->rx_insert_ptr = (struct rx_desc *) rxptr->next_rx_desc;
1268 } else
1269 DMFE_DBUG(0, "SK Buffer reused method error", db->rx_avail_cnt);
1270 }
1271
1272
1273 /*
1274 * Initialize transmit/Receive descriptor
1275 * Using Chain structure, and allocated Tx/Rx buffer
1276 */
1277
1278 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1279 {
1280 struct tx_desc *tmp_tx;
1281 struct rx_desc *tmp_rx;
1282 unsigned char *tmp_buf;
1283 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1284 dma_addr_t tmp_buf_dma;
1285 int i;
1286
1287 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1288
1289 /* tx descriptor start pointer */
1290 db->tx_insert_ptr = db->first_tx_desc;
1291 db->tx_remove_ptr = db->first_tx_desc;
1292 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1293
1294 /* rx descriptor start pointer */
1295 db->first_rx_desc = (struct rx_desc *) ( (u32) db->first_tx_desc + sizeof(struct rx_desc) * TX_DESC_CNT );
1296 db->first_rx_desc_dma = ( db->first_tx_desc_dma + sizeof(struct rx_desc) * TX_DESC_CNT);
1297 db->rx_insert_ptr = db->first_rx_desc;
1298 db->rx_ready_ptr = db->first_rx_desc;
1299 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1300
1301 /* Init Transmit chain */
1302 tmp_buf = db->buf_pool_start;
1303 tmp_buf_dma = db->buf_pool_dma_start;
1304 tmp_tx_dma = db->first_tx_desc_dma;
1305 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1306 tmp_tx->tx_buf_ptr = (u32) tmp_buf;
1307 tmp_tx->tdes0 = cpu_to_le32(0);
1308 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1309 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1310 tmp_tx_dma += sizeof(struct tx_desc);
1311 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1312 tmp_tx->next_tx_desc = (u32) ((u32) tmp_tx + sizeof(struct tx_desc));
1313 tmp_buf = (unsigned char *) ((u32) tmp_buf + TX_BUF_ALLOC);
1314 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1315 }
1316 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1317 tmp_tx->next_tx_desc = (u32) db->first_tx_desc;
1318
1319 /* Init Receive descriptor chain */
1320 tmp_rx_dma=db->first_rx_desc_dma;
1321 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1322 tmp_rx->rdes0 = cpu_to_le32(0);
1323 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1324 tmp_rx_dma += sizeof(struct rx_desc);
1325 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1326 tmp_rx->next_rx_desc = (u32) ((u32) tmp_rx + sizeof(struct rx_desc));
1327 }
1328 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1329 tmp_rx->next_rx_desc = (u32) db->first_rx_desc;
1330
1331 /* pre-allocated Rx buffer */
1332 allocated_rx_buffer(db);
1333 }
1334
1335
1336 /*
1337 * Update CR6 value
1338 * Firstly stop DM910X , then written value and start
1339 */
1340
1341 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1342 {
1343 u32 cr6_tmp;
1344
1345 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1346 outl(cr6_tmp, ioaddr + DCR6);
1347 udelay(5);
1348 outl(cr6_data, ioaddr + DCR6);
1349 udelay(5);
1350 }
1351
1352
1353 /*
1354 * Send a setup frame for DM9132
1355 * This setup frame initilize DM910X addres filter mode
1356 */
1357
1358 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1359 {
1360 struct dev_mc_list *mcptr;
1361 u16 * addrptr;
1362 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1363 u32 hash_val;
1364 u16 i, hash_table[4];
1365
1366 DMFE_DBUG(0, "dm9132_id_table()", 0);
1367
1368 /* Node address */
1369 addrptr = (u16 *) dev->dev_addr;
1370 outw(addrptr[0], ioaddr);
1371 ioaddr += 4;
1372 outw(addrptr[1], ioaddr);
1373 ioaddr += 4;
1374 outw(addrptr[2], ioaddr);
1375 ioaddr += 4;
1376
1377 /* Clear Hash Table */
1378 for (i = 0; i < 4; i++)
1379 hash_table[i] = 0x0;
1380
1381 /* broadcast address */
1382 hash_table[3] = 0x8000;
1383
1384 /* the multicast address in Hash Table : 64 bits */
1385 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1386 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1387 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1388 }
1389
1390 /* Write the hash table to MAC MD table */
1391 for (i = 0; i < 4; i++, ioaddr += 4)
1392 outw(hash_table[i], ioaddr);
1393 }
1394
1395
1396 /*
1397 * Send a setup frame for DM9102/DM9102A
1398 * This setup frame initilize DM910X addres filter mode
1399 */
1400
1401 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1402 {
1403 struct dmfe_board_info *db = dev->priv;
1404 struct dev_mc_list *mcptr;
1405 struct tx_desc *txptr;
1406 u16 * addrptr;
1407 u32 * suptr;
1408 int i;
1409
1410 DMFE_DBUG(0, "send_filter_frame()", 0);
1411
1412 txptr = db->tx_insert_ptr;
1413 suptr = (u32 *) txptr->tx_buf_ptr;
1414
1415 /* Node address */
1416 addrptr = (u16 *) dev->dev_addr;
1417 *suptr++ = addrptr[0];
1418 *suptr++ = addrptr[1];
1419 *suptr++ = addrptr[2];
1420
1421 /* broadcast address */
1422 *suptr++ = 0xffff;
1423 *suptr++ = 0xffff;
1424 *suptr++ = 0xffff;
1425
1426 /* fit the multicast address */
1427 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1428 addrptr = (u16 *) mcptr->dmi_addr;
1429 *suptr++ = addrptr[0];
1430 *suptr++ = addrptr[1];
1431 *suptr++ = addrptr[2];
1432 }
1433
1434 for (; i<14; i++) {
1435 *suptr++ = 0xffff;
1436 *suptr++ = 0xffff;
1437 *suptr++ = 0xffff;
1438 }
1439
1440 /* prepare the setup frame */
1441 db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
1442 txptr->tdes1 = cpu_to_le32(0x890000c0);
1443
1444 /* Resource Check and Send the setup packet */
1445 if (!db->tx_packet_cnt) {
1446 /* Resource Empty */
1447 db->tx_packet_cnt++;
1448 txptr->tdes0 = cpu_to_le32(0x80000000);
1449 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1450 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1451 update_cr6(db->cr6_data, dev->base_addr);
1452 dev->trans_start = jiffies;
1453 } else
1454 db->tx_queue_cnt++; /* Put in TX queue */
1455 }
1456
1457
1458 /*
1459 * Allocate rx buffer,
1460 * As possible as allocated maxiumn Rx buffer
1461 */
1462
1463 static void allocated_rx_buffer(struct dmfe_board_info *db)
1464 {
1465 struct rx_desc *rxptr;
1466 struct sk_buff *skb;
1467
1468 rxptr = db->rx_insert_ptr;
1469
1470 while(db->rx_avail_cnt < RX_DESC_CNT) {
1471 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1472 break;
1473 rxptr->rx_skb_ptr = (u32) skb; /* FIXME */
1474 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->net_dev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1475 rxptr->rdes0 = cpu_to_le32(0x80000000);
1476 rxptr = (struct rx_desc *) rxptr->next_rx_desc;
1477 db->rx_avail_cnt++;
1478 }
1479
1480 db->rx_insert_ptr = rxptr;
1481 }
1482
1483
1484 /*
1485 * Read one word data from the serial ROM
1486 */
1487
1488 static u16 read_srom_word(long ioaddr, int offset)
1489 {
1490 int i;
1491 u16 srom_data = 0;
1492 long cr9_ioaddr = ioaddr + DCR9;
1493
1494 outl(CR9_SROM_READ, cr9_ioaddr);
1495 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1496
1497 /* Send the Read Command 110b */
1498 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1499 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1500 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1501
1502 /* Send the offset */
1503 for (i = 5; i >= 0; i--) {
1504 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1505 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1506 }
1507
1508 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1509
1510 for (i = 16; i > 0; i--) {
1511 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1512 udelay(5);
1513 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1514 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1515 udelay(5);
1516 }
1517
1518 outl(CR9_SROM_READ, cr9_ioaddr);
1519 return srom_data;
1520 }
1521
1522
1523 /*
1524 * Auto sense the media mode
1525 */
1526
1527 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1528 {
1529 u8 ErrFlag = 0;
1530 u16 phy_mode;
1531
1532 /* CR6 bit18=0, select 10/100M */
1533 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1534
1535 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1536 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1537
1538 if ( (phy_mode & 0x24) == 0x24 ) {
1539 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1540 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1541 else /* DM9102/DM9102A */
1542 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1543 /* printk("<DMFE>: Phy_mode %x ",phy_mode); */
1544 switch (phy_mode) {
1545 case 0x1000: db->op_mode = DMFE_10MHF; break;
1546 case 0x2000: db->op_mode = DMFE_10MFD; break;
1547 case 0x4000: db->op_mode = DMFE_100MHF; break;
1548 case 0x8000: db->op_mode = DMFE_100MFD; break;
1549 default: db->op_mode = DMFE_10MHF;
1550 ErrFlag = 1;
1551 break;
1552 }
1553 } else {
1554 db->op_mode = DMFE_10MHF;
1555 DMFE_DBUG(0, "Link Failed :", phy_mode);
1556 ErrFlag = 1;
1557 }
1558
1559 return ErrFlag;
1560 }
1561
1562
1563 /*
1564 * Set 10/100 phyxcer capability
1565 * AUTO mode : phyxcer register4 is NIC capability
1566 * Force mode: phyxcer register4 is the force media
1567 */
1568
1569 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1570 {
1571 u16 phy_reg;
1572
1573 /* Select 10/100M phyxcer */
1574 db->cr6_data &= ~0x40000;
1575 update_cr6(db->cr6_data, db->ioaddr);
1576
1577 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1578 if (db->chip_id == PCI_DM9009_ID) {
1579 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
1580 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
1581 }
1582
1583 /* Phyxcer capability setting */
1584 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1585
1586 if (db->media_mode & DMFE_AUTO) {
1587 /* AUTO Mode */
1588 phy_reg |= db->PHY_reg4;
1589 } else {
1590 /* Force Mode */
1591 switch(db->media_mode) {
1592 case DMFE_10MHF: phy_reg |= 0x20; break;
1593 case DMFE_10MFD: phy_reg |= 0x40; break;
1594 case DMFE_100MHF: phy_reg |= 0x80; break;
1595 case DMFE_100MFD: phy_reg |= 0x100; break;
1596 }
1597 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1598 }
1599
1600 /* Write new capability to Phyxcer Reg4 */
1601 if ( !(phy_reg & 0x01e0)) {
1602 phy_reg|=db->PHY_reg4;
1603 db->media_mode|=DMFE_AUTO;
1604 }
1605 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1606
1607 /* Restart Auto-Negotiation */
1608 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1609 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1610 if ( !db->chip_type )
1611 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1612 }
1613
1614
1615 /*
1616 * Process op-mode
1617 * AUTO mode : PHY controller in Auto-negotiation Mode
1618 * Force mode: PHY controller in force mode with HUB
1619 * N-way force capability with SWITCH
1620 */
1621
1622 static void dmfe_process_mode(struct dmfe_board_info *db)
1623 {
1624 u16 phy_reg;
1625
1626 /* Full Duplex Mode Check */
1627 if (db->op_mode & 0x4)
1628 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1629 else
1630 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1631
1632 /* Transciver Selection */
1633 if (db->op_mode & 0x10) /* 1M HomePNA */
1634 db->cr6_data |= 0x40000;/* External MII select */
1635 else
1636 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1637
1638 update_cr6(db->cr6_data, db->ioaddr);
1639
1640 /* 10/100M phyxcer force mode need */
1641 if ( !(db->media_mode & 0x18)) {
1642 /* Forece Mode */
1643 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1644 if ( !(phy_reg & 0x1) ) {
1645 /* parter without N-Way capability */
1646 phy_reg = 0x0;
1647 switch(db->op_mode) {
1648 case DMFE_10MHF: phy_reg = 0x0; break;
1649 case DMFE_10MFD: phy_reg = 0x100; break;
1650 case DMFE_100MHF: phy_reg = 0x2000; break;
1651 case DMFE_100MFD: phy_reg = 0x2100; break;
1652 }
1653 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1654 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1655 mdelay(20);
1656 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1657 }
1658 }
1659 }
1660
1661
1662 /*
1663 * Write a word to Phy register
1664 */
1665
1666 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1667 {
1668 u16 i;
1669 unsigned long ioaddr;
1670
1671 if (chip_id == PCI_DM9132_ID) {
1672 ioaddr = iobase + 0x80 + offset * 4;
1673 outw(phy_data, ioaddr);
1674 } else {
1675 /* DM9102/DM9102A Chip */
1676 ioaddr = iobase + DCR9;
1677
1678 /* Send 33 synchronization clock to Phy controller */
1679 for (i = 0; i < 35; i++)
1680 phy_write_1bit(ioaddr, PHY_DATA_1);
1681
1682 /* Send start command(01) to Phy */
1683 phy_write_1bit(ioaddr, PHY_DATA_0);
1684 phy_write_1bit(ioaddr, PHY_DATA_1);
1685
1686 /* Send write command(01) to Phy */
1687 phy_write_1bit(ioaddr, PHY_DATA_0);
1688 phy_write_1bit(ioaddr, PHY_DATA_1);
1689
1690 /* Send Phy addres */
1691 for (i = 0x10; i > 0; i = i >> 1)
1692 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1693
1694 /* Send register addres */
1695 for (i = 0x10; i > 0; i = i >> 1)
1696 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1697
1698 /* written trasnition */
1699 phy_write_1bit(ioaddr, PHY_DATA_1);
1700 phy_write_1bit(ioaddr, PHY_DATA_0);
1701
1702 /* Write a word data to PHY controller */
1703 for ( i = 0x8000; i > 0; i >>= 1)
1704 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1705 }
1706 }
1707
1708
1709 /*
1710 * Read a word data from phy register
1711 */
1712
1713 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1714 {
1715 int i;
1716 u16 phy_data;
1717 unsigned long ioaddr;
1718
1719 if (chip_id == PCI_DM9132_ID) {
1720 /* DM9132 Chip */
1721 ioaddr = iobase + 0x80 + offset * 4;
1722 phy_data = inw(ioaddr);
1723 } else {
1724 /* DM9102/DM9102A Chip */
1725 ioaddr = iobase + DCR9;
1726
1727 /* Send 33 synchronization clock to Phy controller */
1728 for (i = 0; i < 35; i++)
1729 phy_write_1bit(ioaddr, PHY_DATA_1);
1730
1731 /* Send start command(01) to Phy */
1732 phy_write_1bit(ioaddr, PHY_DATA_0);
1733 phy_write_1bit(ioaddr, PHY_DATA_1);
1734
1735 /* Send read command(10) to Phy */
1736 phy_write_1bit(ioaddr, PHY_DATA_1);
1737 phy_write_1bit(ioaddr, PHY_DATA_0);
1738
1739 /* Send Phy addres */
1740 for (i = 0x10; i > 0; i = i >> 1)
1741 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1742
1743 /* Send register addres */
1744 for (i = 0x10; i > 0; i = i >> 1)
1745 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1746
1747 /* Skip transition state */
1748 phy_read_1bit(ioaddr);
1749
1750 /* read 16bit data */
1751 for (phy_data = 0, i = 0; i < 16; i++) {
1752 phy_data <<= 1;
1753 phy_data |= phy_read_1bit(ioaddr);
1754 }
1755 }
1756
1757 return phy_data;
1758 }
1759
1760
1761 /*
1762 * Write one bit data to Phy Controller
1763 */
1764
1765 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1766 {
1767 outl(phy_data, ioaddr); /* MII Clock Low */
1768 udelay(1);
1769 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1770 udelay(1);
1771 outl(phy_data, ioaddr); /* MII Clock Low */
1772 udelay(1);
1773 }
1774
1775
1776 /*
1777 * Read one bit phy data from PHY controller
1778 */
1779
1780 static u16 phy_read_1bit(unsigned long ioaddr)
1781 {
1782 u16 phy_data;
1783
1784 outl(0x50000, ioaddr);
1785 udelay(1);
1786 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1787 outl(0x40000, ioaddr);
1788 udelay(1);
1789
1790 return phy_data;
1791 }
1792
1793
1794 /*
1795 * Calculate the CRC valude of the Rx packet
1796 * flag = 1 : return the reverse CRC (for the received packet CRC)
1797 * 0 : return the normal CRC (for Hash Table index)
1798 */
1799
1800 unsigned long cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
1801 {
1802 unsigned long Crc = 0xffffffff;
1803
1804 while (Len--) {
1805 Crc = CrcTable[(Crc ^ *Data++) & 0xFF] ^ (Crc >> 8);
1806 }
1807
1808 if (flag)
1809 return ~Crc;
1810 else
1811 return Crc;
1812 }
1813
1814
1815 /*
1816 * Parser SROM and media mode
1817 */
1818
1819 static void dmfe_parse_srom(struct dmfe_board_info * db)
1820 {
1821 char * srom = db->srom;
1822 int dmfe_mode, tmp_reg;
1823
1824 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1825
1826 /* Init CR15 */
1827 db->cr15_data = CR15_DEFAULT;
1828
1829 /* Check SROM Version */
1830 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1831 /* SROM V4.01 */
1832 /* Get NIC support media mode */
1833 db->NIC_capability = *(u16 *) (&srom[34]);
1834 db->PHY_reg4 = 0;
1835 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1836 switch( db->NIC_capability & tmp_reg ) {
1837 case 0x1: db->PHY_reg4 |= 0x0020; break;
1838 case 0x2: db->PHY_reg4 |= 0x0040; break;
1839 case 0x4: db->PHY_reg4 |= 0x0080; break;
1840 case 0x8: db->PHY_reg4 |= 0x0100; break;
1841 }
1842 }
1843
1844 /* Media Mode Force or not check */
1845 dmfe_mode = *( (int *) &srom[34]) & *( (int *) &srom[36] );
1846 switch(dmfe_mode) {
1847 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1848 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1849 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1850 case 0x100:
1851 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1852 }
1853
1854 /* Special Function setting */
1855 /* VLAN function */
1856 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1857 db->cr15_data |= 0x40;
1858
1859 /* Flow Control */
1860 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1861 db->cr15_data |= 0x400;
1862
1863 /* TX pause packet */
1864 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1865 db->cr15_data |= 0x9800;
1866 }
1867
1868 /* Parse HPNA parameter */
1869 db->HPNA_command = 1;
1870
1871 /* Accept remote command or not */
1872 if (HPNA_rx_cmd == 0)
1873 db->HPNA_command |= 0x8000;
1874
1875 /* Issue remote command & operation mode */
1876 if (HPNA_tx_cmd == 1)
1877 switch(HPNA_mode) { /* Issue Remote Command */
1878 case 0: db->HPNA_command |= 0x0904; break;
1879 case 1: db->HPNA_command |= 0x0a00; break;
1880 case 2: db->HPNA_command |= 0x0506; break;
1881 case 3: db->HPNA_command |= 0x0602; break;
1882 }
1883 else
1884 switch(HPNA_mode) { /* Don't Issue */
1885 case 0: db->HPNA_command |= 0x0004; break;
1886 case 1: db->HPNA_command |= 0x0000; break;
1887 case 2: db->HPNA_command |= 0x0006; break;
1888 case 3: db->HPNA_command |= 0x0002; break;
1889 }
1890
1891 /* Check DM9801 or DM9802 present or not */
1892 db->HPNA_present = 0;
1893 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1894 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1895 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1896 /* DM9801 or DM9802 present */
1897 db->HPNA_timer = 8;
1898 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1899 /* DM9801 HomeRun */
1900 db->HPNA_present = 1;
1901 dmfe_program_DM9801(db, tmp_reg);
1902 } else {
1903 /* DM9802 LongRun */
1904 db->HPNA_present = 2;
1905 dmfe_program_DM9802(db);
1906 }
1907 }
1908
1909 }
1910
1911
1912 /*
1913 * Init HomeRun DM9801
1914 */
1915
1916 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1917 {
1918 uint reg17, reg25;
1919
1920 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1921 switch(HPNA_rev) {
1922 case 0xb900: /* DM9801 E3 */
1923 db->HPNA_command |= 0x1000;
1924 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1925 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1926 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1927 break;
1928 case 0xb901: /* DM9801 E4 */
1929 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1930 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1931 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1932 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1933 break;
1934 case 0xb902: /* DM9801 E5 */
1935 case 0xb903: /* DM9801 E6 */
1936 default:
1937 db->HPNA_command |= 0x1000;
1938 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1939 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1940 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1941 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1942 break;
1943 }
1944 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1945 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1946 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1947 }
1948
1949
1950 /*
1951 * Init HomeRun DM9802
1952 */
1953
1954 static void dmfe_program_DM9802(struct dmfe_board_info * db)
1955 {
1956 uint phy_reg;
1957
1958 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1959 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1960 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1961 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
1962 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
1963 }
1964
1965
1966 /*
1967 * Check remote HPNA power and speed status. If not correct,
1968 * issue command again.
1969 */
1970
1971 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1972 {
1973 uint phy_reg;
1974
1975 /* Got remote device status */
1976 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
1977 switch(phy_reg) {
1978 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
1979 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
1980 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
1981 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
1982 }
1983
1984 /* Check remote device status match our setting ot not */
1985 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1986 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1987 db->HPNA_timer=8;
1988 } else
1989 db->HPNA_timer=600; /* Match, every 10 minutes, check */
1990 }
1991
1992
1993
1994 static struct pci_device_id dmfe_pci_tbl[] __devinitdata = {
1995 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1996 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1997 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1998 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
1999 { 0, }
2000 };
2001 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2002
2003 static struct pci_driver dmfe_driver = {
2004 name: "dmfe",
2005 id_table: dmfe_pci_tbl,
2006 probe: dmfe_init_one,
2007 remove: dmfe_remove_one,
2008 };
2009
2010 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2011 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2012 MODULE_PARM(debug, "i");
2013 MODULE_PARM(mode, "i");
2014 MODULE_PARM(cr6set, "i");
2015 MODULE_PARM(chkmode, "i");
2016 MODULE_PARM(HPNA_mode, "i");
2017 MODULE_PARM(HPNA_rx_cmd, "i");
2018 MODULE_PARM(HPNA_tx_cmd, "i");
2019 MODULE_PARM(HPNA_NoiseFloor, "i");
2020 MODULE_PARM(SF_mode, "i");
2021 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2022 MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2023 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2024
2025 /* Description:
2026 * when user used insmod to add module, system invoked init_module()
2027 * to initilize and register.
2028 */
2029
2030 static int __init dmfe_init_module(void)
2031 {
2032 int rc;
2033
2034 printk(version);
2035 printed_version = 1;
2036
2037 DMFE_DBUG(0, "init_module() ", debug);
2038
2039 if (debug)
2040 dmfe_debug = debug; /* set debug flag */
2041 if (cr6set)
2042 dmfe_cr6_user_set = cr6set;
2043
2044 switch(mode) {
2045 case DMFE_10MHF:
2046 case DMFE_100MHF:
2047 case DMFE_10MFD:
2048 case DMFE_100MFD:
2049 case DMFE_1M_HPNA:
2050 dmfe_media_mode = mode;
2051 break;
2052 default:dmfe_media_mode = DMFE_AUTO;
2053 break;
2054 }
2055
2056 if (HPNA_mode > 4)
2057 HPNA_mode = 0; /* Default: LP/HS */
2058 if (HPNA_rx_cmd > 1)
2059 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2060 if (HPNA_tx_cmd > 1)
2061 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2062 if (HPNA_NoiseFloor > 15)
2063 HPNA_NoiseFloor = 0;
2064
2065 rc = pci_module_init(&dmfe_driver);
2066 if (rc < 0)
2067 return rc;
2068
2069 return 0;
2070 }
2071
2072
2073 /*
2074 * Description:
2075 * when user used rmmod to delete module, system invoked clean_module()
2076 * to un-register all registered services.
2077 */
2078
2079 static void __exit dmfe_cleanup_module(void)
2080 {
2081 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2082 pci_unregister_driver(&dmfe_driver);
2083 }
2084
2085 module_init(dmfe_init_module);
2086 module_exit(dmfe_cleanup_module);
2087