File: /usr/src/linux/drivers/net/eepro100.c
1 /* drivers/net/eepro100.c: An Intel i82557-559 Ethernet driver for Linux. */
2 /*
3 NOTICE: For use with late 2.3 kernels only.
4 May not compile for kernels 2.3.43-47.
5 Written 1996-1999 by Donald Becker.
6
7 The driver also contains updates by different kernel developers
8 (see incomplete list below).
9 Current maintainer is Andrey V. Savochkin <saw@saw.sw.com.sg>.
10 Please use this email address and linux-kernel mailing list for bug reports.
11
12 This software may be used and distributed according to the terms
13 of the GNU General Public License, incorporated herein by reference.
14
15 This driver is for the Intel EtherExpress Pro100 (Speedo3) design.
16 It should work with all i82557/558/559 boards.
17
18 Version history:
19 1998 Apr - 2000 Feb Andrey V. Savochkin <saw@saw.sw.com.sg>
20 Serious fixes for multicast filter list setting, TX timeout routine;
21 RX ring refilling logic; other stuff
22 2000 Feb Jeff Garzik <jgarzik@mandrakesoft.com>
23 Convert to new PCI driver interface
24 2000 Mar 24 Dragan Stancevic <visitor@valinux.com>
25 Disabled FC and ER, to avoid lockups when when we get FCP interrupts.
26 2000 Jul 17 Goutham Rao <goutham.rao@intel.com>
27 PCI DMA API fixes, adding pci_dma_sync_single calls where neccesary
28 */
29
30 static const char *version =
31 "eepro100.c:v1.09j-t 9/29/99 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/eepro100.html\n"
32 "eepro100.c: $Revision: 1.36 $ 2000/11/17 Modified by Andrey V. Savochkin <saw@saw.sw.com.sg> and others\n";
33
34 /* A few user-configurable values that apply to all boards.
35 First set is undocumented and spelled per Intel recommendations. */
36
37 static int congenb /* = 0 */; /* Enable congestion control in the DP83840. */
38 static int txfifo = 8; /* Tx FIFO threshold in 4 byte units, 0-15 */
39 static int rxfifo = 8; /* Rx FIFO threshold, default 32 bytes. */
40 /* Tx/Rx DMA burst length, 0-127, 0 == no preemption, tx==128 -> disabled. */
41 static int txdmacount = 128;
42 static int rxdmacount /* = 0 */;
43
44 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx method.
45 Lower values use more memory, but are faster. */
46 #if defined(__alpha__) || defined(__sparc__) || defined(__arm__)
47 static int rx_copybreak = 1518;
48 #else
49 static int rx_copybreak = 200;
50 #endif
51
52 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
53 static int max_interrupt_work = 20;
54
55 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast) */
56 static int multicast_filter_limit = 64;
57
58 /* 'options' is used to pass a transceiver override or full-duplex flag
59 e.g. "options=16" for FD, "options=32" for 100mbps-only. */
60 static int full_duplex[] = {-1, -1, -1, -1, -1, -1, -1, -1};
61 static int options[] = {-1, -1, -1, -1, -1, -1, -1, -1};
62 static int debug = -1; /* The debug level */
63
64 /* A few values that may be tweaked. */
65 /* The ring sizes should be a power of two for efficiency. */
66 #define TX_RING_SIZE 32
67 #define RX_RING_SIZE 32
68 /* How much slots multicast filter setup may take.
69 Do not descrease without changing set_rx_mode() implementaion. */
70 #define TX_MULTICAST_SIZE 2
71 #define TX_MULTICAST_RESERV (TX_MULTICAST_SIZE*2)
72 /* Actual number of TX packets queued, must be
73 <= TX_RING_SIZE-TX_MULTICAST_RESERV. */
74 #define TX_QUEUE_LIMIT (TX_RING_SIZE-TX_MULTICAST_RESERV)
75 /* Hysteresis marking queue as no longer full. */
76 #define TX_QUEUE_UNFULL (TX_QUEUE_LIMIT-4)
77
78 /* Operational parameters that usually are not changed. */
79
80 /* Time in jiffies before concluding the transmitter is hung. */
81 #define TX_TIMEOUT (2*HZ)
82 /* Size of an pre-allocated Rx buffer: <Ethernet MTU> + slack.*/
83 #define PKT_BUF_SZ 1536
84
85 #if !defined(__OPTIMIZE__) || !defined(__KERNEL__)
86 #warning You must compile this file with the correct options!
87 #warning See the last lines of the source file.
88 #error You must compile this driver with "-O".
89 #endif
90
91 #include <linux/config.h>
92 #include <linux/version.h>
93 #include <linux/module.h>
94
95 #include <linux/kernel.h>
96 #include <linux/string.h>
97 #include <linux/errno.h>
98 #include <linux/ioport.h>
99 #include <linux/slab.h>
100 #include <linux/interrupt.h>
101 #include <linux/timer.h>
102 #include <linux/pci.h>
103 #include <linux/spinlock.h>
104 #include <linux/init.h>
105 #include <linux/mii.h>
106
107 #include <asm/bitops.h>
108 #include <asm/io.h>
109
110 #include <linux/netdevice.h>
111 #include <linux/etherdevice.h>
112 #include <linux/skbuff.h>
113 #include <linux/delay.h>
114
115 MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");
116 MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");
117 MODULE_PARM(debug, "i");
118 MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
119 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
120 MODULE_PARM(congenb, "i");
121 MODULE_PARM(txfifo, "i");
122 MODULE_PARM(rxfifo, "i");
123 MODULE_PARM(txdmacount, "i");
124 MODULE_PARM(rxdmacount, "i");
125 MODULE_PARM(rx_copybreak, "i");
126 MODULE_PARM(max_interrupt_work, "i");
127 MODULE_PARM(multicast_filter_limit, "i");
128 MODULE_PARM_DESC(debug, "eepro100 debug level (0-6)");
129 MODULE_PARM_DESC(options, "eepro100: Bits 0-3: tranceiver type, bit 4: full duplex, bit 5: 100Mbps");
130 MODULE_PARM_DESC(full_duplex, "eepro100 full duplex setting(s) (1)");
131 MODULE_PARM_DESC(congenb, "eepro100 Enable congestion control (1)");
132 MODULE_PARM_DESC(txfifo, "eepro100 Tx FIFO threshold in 4 byte units, (0-15)");
133 MODULE_PARM_DESC(rxfifo, "eepro100 Rx FIFO threshold in 4 byte units, (0-15)");
134 MODULE_PARM_DESC(txdmaccount, "eepro100 Tx DMA burst length; 128 - disable (0-128)");
135 MODULE_PARM_DESC(rxdmaccount, "eepro100 Rx DMA burst length; 128 - disable (0-128)");
136 MODULE_PARM_DESC(rx_copybreak, "eepro100 copy breakpoint for copy-only-tiny-frames");
137 MODULE_PARM_DESC(max_interrupt_work, "eepro100 maximum events handled per interrupt");
138 MODULE_PARM_DESC(multicast_filter_limit, "eepro100 maximum number of filtered multicast addresses");
139
140 #define RUN_AT(x) (jiffies + (x))
141
142 /* ACPI power states don't universally work (yet) */
143 #ifndef CONFIG_PM
144 #undef pci_set_power_state
145 #define pci_set_power_state null_set_power_state
146 static inline int null_set_power_state(struct pci_dev *dev, int state)
147 {
148 return 0;
149 }
150 #endif /* CONFIG_PM */
151
152 #define netdevice_start(dev)
153 #define netdevice_stop(dev)
154 #define netif_set_tx_timeout(dev, tf, tm) \
155 do { \
156 (dev)->tx_timeout = (tf); \
157 (dev)->watchdog_timeo = (tm); \
158 } while(0)
159
160 #ifndef PCI_DEVICE_ID_INTEL_ID1029
161 #define PCI_DEVICE_ID_INTEL_ID1029 0x1029
162 #endif
163 #ifndef PCI_DEVICE_ID_INTEL_ID1030
164 #define PCI_DEVICE_ID_INTEL_ID1030 0x1030
165 #endif
166
167
168 int speedo_debug = 1;
169
170 /*
171 Theory of Operation
172
173 I. Board Compatibility
174
175 This device driver is designed for the Intel i82557 "Speedo3" chip, Intel's
176 single-chip fast Ethernet controller for PCI, as used on the Intel
177 EtherExpress Pro 100 adapter.
178
179 II. Board-specific settings
180
181 PCI bus devices are configured by the system at boot time, so no jumpers
182 need to be set on the board. The system BIOS should be set to assign the
183 PCI INTA signal to an otherwise unused system IRQ line. While it's
184 possible to share PCI interrupt lines, it negatively impacts performance and
185 only recent kernels support it.
186
187 III. Driver operation
188
189 IIIA. General
190 The Speedo3 is very similar to other Intel network chips, that is to say
191 "apparently designed on a different planet". This chips retains the complex
192 Rx and Tx descriptors and multiple buffers pointers as previous chips, but
193 also has simplified Tx and Rx buffer modes. This driver uses the "flexible"
194 Tx mode, but in a simplified lower-overhead manner: it associates only a
195 single buffer descriptor with each frame descriptor.
196
197 Despite the extra space overhead in each receive skbuff, the driver must use
198 the simplified Rx buffer mode to assure that only a single data buffer is
199 associated with each RxFD. The driver implements this by reserving space
200 for the Rx descriptor at the head of each Rx skbuff.
201
202 The Speedo-3 has receive and command unit base addresses that are added to
203 almost all descriptor pointers. The driver sets these to zero, so that all
204 pointer fields are absolute addresses.
205
206 The System Control Block (SCB) of some previous Intel chips exists on the
207 chip in both PCI I/O and memory space. This driver uses the I/O space
208 registers, but might switch to memory mapped mode to better support non-x86
209 processors.
210
211 IIIB. Transmit structure
212
213 The driver must use the complex Tx command+descriptor mode in order to
214 have a indirect pointer to the skbuff data section. Each Tx command block
215 (TxCB) is associated with two immediately appended Tx Buffer Descriptor
216 (TxBD). A fixed ring of these TxCB+TxBD pairs are kept as part of the
217 speedo_private data structure for each adapter instance.
218
219 The newer i82558 explicitly supports this structure, and can read the two
220 TxBDs in the same PCI burst as the TxCB.
221
222 This ring structure is used for all normal transmit packets, but the
223 transmit packet descriptors aren't long enough for most non-Tx commands such
224 as CmdConfigure. This is complicated by the possibility that the chip has
225 already loaded the link address in the previous descriptor. So for these
226 commands we convert the next free descriptor on the ring to a NoOp, and point
227 that descriptor's link to the complex command.
228
229 An additional complexity of these non-transmit commands are that they may be
230 added asynchronous to the normal transmit queue, so we disable interrupts
231 whenever the Tx descriptor ring is manipulated.
232
233 A notable aspect of these special configure commands is that they do
234 work with the normal Tx ring entry scavenge method. The Tx ring scavenge
235 is done at interrupt time using the 'dirty_tx' index, and checking for the
236 command-complete bit. While the setup frames may have the NoOp command on the
237 Tx ring marked as complete, but not have completed the setup command, this
238 is not a problem. The tx_ring entry can be still safely reused, as the
239 tx_skbuff[] entry is always empty for config_cmd and mc_setup frames.
240
241 Commands may have bits set e.g. CmdSuspend in the command word to either
242 suspend or stop the transmit/command unit. This driver always flags the last
243 command with CmdSuspend, erases the CmdSuspend in the previous command, and
244 then issues a CU_RESUME.
245 Note: Watch out for the potential race condition here: imagine
246 erasing the previous suspend
247 the chip processes the previous command
248 the chip processes the final command, and suspends
249 doing the CU_RESUME
250 the chip processes the next-yet-valid post-final-command.
251 So blindly sending a CU_RESUME is only safe if we do it immediately after
252 after erasing the previous CmdSuspend, without the possibility of an
253 intervening delay. Thus the resume command is always within the
254 interrupts-disabled region. This is a timing dependence, but handling this
255 condition in a timing-independent way would considerably complicate the code.
256
257 Note: In previous generation Intel chips, restarting the command unit was a
258 notoriously slow process. This is presumably no longer true.
259
260 IIIC. Receive structure
261
262 Because of the bus-master support on the Speedo3 this driver uses the new
263 SKBUFF_RX_COPYBREAK scheme, rather than a fixed intermediate receive buffer.
264 This scheme allocates full-sized skbuffs as receive buffers. The value
265 SKBUFF_RX_COPYBREAK is used as the copying breakpoint: it is chosen to
266 trade-off the memory wasted by passing the full-sized skbuff to the queue
267 layer for all frames vs. the copying cost of copying a frame to a
268 correctly-sized skbuff.
269
270 For small frames the copying cost is negligible (esp. considering that we
271 are pre-loading the cache with immediately useful header information), so we
272 allocate a new, minimally-sized skbuff. For large frames the copying cost
273 is non-trivial, and the larger copy might flush the cache of useful data, so
274 we pass up the skbuff the packet was received into.
275
276 IV. Notes
277
278 Thanks to Steve Williams of Intel for arranging the non-disclosure agreement
279 that stated that I could disclose the information. But I still resent
280 having to sign an Intel NDA when I'm helping Intel sell their own product!
281
282 */
283
284 static int speedo_found1(struct pci_dev *pdev, long ioaddr, int fnd_cnt, int acpi_idle_state);
285
286 enum pci_flags_bit {
287 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
288 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
289 };
290
291 static inline unsigned int io_inw(unsigned long port)
292 {
293 return inw(port);
294 }
295 static inline void io_outw(unsigned int val, unsigned long port)
296 {
297 outw(val, port);
298 }
299
300 #ifndef USE_IO
301 /* Currently alpha headers define in/out macros.
302 Undefine them. 2000/03/30 SAW */
303 #undef inb
304 #undef inw
305 #undef inl
306 #undef outb
307 #undef outw
308 #undef outl
309 #define inb readb
310 #define inw readw
311 #define inl readl
312 #define outb writeb
313 #define outw writew
314 #define outl writel
315 #endif
316
317 /* How to wait for the command unit to accept a command.
318 Typically this takes 0 ticks. */
319 static inline void wait_for_cmd_done(long cmd_ioaddr)
320 {
321 int wait = 1000;
322 do ;
323 while(inb(cmd_ioaddr) && --wait >= 0);
324 #ifndef final_version
325 if (wait < 0)
326 printk(KERN_ALERT "eepro100: wait_for_cmd_done timeout!\n");
327 #endif
328 }
329
330 /* Offsets to the various registers.
331 All accesses need not be longword aligned. */
332 enum speedo_offsets {
333 SCBStatus = 0, SCBCmd = 2, /* Rx/Command Unit command and status. */
334 SCBPointer = 4, /* General purpose pointer. */
335 SCBPort = 8, /* Misc. commands and operands. */
336 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
337 SCBCtrlMDI = 16, /* MDI interface control. */
338 SCBEarlyRx = 20, /* Early receive byte count. */
339 };
340 /* Commands that can be put in a command list entry. */
341 enum commands {
342 CmdNOp = 0, CmdIASetup = 0x10000, CmdConfigure = 0x20000,
343 CmdMulticastList = 0x30000, CmdTx = 0x40000, CmdTDR = 0x50000,
344 CmdDump = 0x60000, CmdDiagnose = 0x70000,
345 CmdSuspend = 0x40000000, /* Suspend after completion. */
346 CmdIntr = 0x20000000, /* Interrupt after completion. */
347 CmdTxFlex = 0x00080000, /* Use "Flexible mode" for CmdTx command. */
348 };
349 /* Clear CmdSuspend (1<<30) avoiding interference with the card access to the
350 status bits. Previous driver versions used separate 16 bit fields for
351 commands and statuses. --SAW
352 */
353 #if defined(__alpha__)
354 # define clear_suspend(cmd) clear_bit(30, &(cmd)->cmd_status);
355 #else
356 # if defined(__LITTLE_ENDIAN)
357 # define clear_suspend(cmd) ((__u16 *)&(cmd)->cmd_status)[1] &= ~0x4000
358 # elif defined(__BIG_ENDIAN)
359 # define clear_suspend(cmd) ((__u16 *)&(cmd)->cmd_status)[1] &= ~0x0040
360 # else
361 # error Unsupported byteorder
362 # endif
363 #endif
364
365 enum SCBCmdBits {
366 SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,
367 SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400,
368 SCBTriggerIntr=0x0200, SCBMaskAll=0x0100,
369 /* The rest are Rx and Tx commands. */
370 CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050,
371 CUCmdBase=0x0060, /* CU Base address (set to zero) . */
372 CUDumpStats=0x0070, /* Dump then reset stats counters. */
373 RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006,
374 RxResumeNoResources=0x0007,
375 };
376
377 enum SCBPort_cmds {
378 PortReset=0, PortSelfTest=1, PortPartialReset=2, PortDump=3,
379 };
380
381 /* The Speedo3 Rx and Tx frame/buffer descriptors. */
382 struct descriptor { /* A generic descriptor. */
383 s32 cmd_status; /* All command and status fields. */
384 u32 link; /* struct descriptor * */
385 unsigned char params[0];
386 };
387
388 /* The Speedo3 Rx and Tx buffer descriptors. */
389 struct RxFD { /* Receive frame descriptor. */
390 s32 status;
391 u32 link; /* struct RxFD * */
392 u32 rx_buf_addr; /* void * */
393 u32 count;
394 };
395
396 /* Selected elements of the Tx/RxFD.status word. */
397 enum RxFD_bits {
398 RxComplete=0x8000, RxOK=0x2000,
399 RxErrCRC=0x0800, RxErrAlign=0x0400, RxErrTooBig=0x0200, RxErrSymbol=0x0010,
400 RxEth2Type=0x0020, RxNoMatch=0x0004, RxNoIAMatch=0x0002,
401 TxUnderrun=0x1000, StatusComplete=0x8000,
402 };
403
404 #define CONFIG_DATA_SIZE 22
405 struct TxFD { /* Transmit frame descriptor set. */
406 s32 status;
407 u32 link; /* void * */
408 u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
409 s32 count; /* # of TBD (=1), Tx start thresh., etc. */
410 /* This constitutes two "TBD" entries -- we only use one. */
411 #define TX_DESCR_BUF_OFFSET 16
412 u32 tx_buf_addr0; /* void *, frame to be transmitted. */
413 s32 tx_buf_size0; /* Length of Tx frame. */
414 u32 tx_buf_addr1; /* void *, frame to be transmitted. */
415 s32 tx_buf_size1; /* Length of Tx frame. */
416 /* the structure must have space for at least CONFIG_DATA_SIZE starting
417 * from tx_desc_addr field */
418 };
419
420 /* Multicast filter setting block. --SAW */
421 struct speedo_mc_block {
422 struct speedo_mc_block *next;
423 unsigned int tx;
424 dma_addr_t frame_dma;
425 unsigned int len;
426 struct descriptor frame __attribute__ ((__aligned__(16)));
427 };
428
429 /* Elements of the dump_statistics block. This block must be lword aligned. */
430 struct speedo_stats {
431 u32 tx_good_frames;
432 u32 tx_coll16_errs;
433 u32 tx_late_colls;
434 u32 tx_underruns;
435 u32 tx_lost_carrier;
436 u32 tx_deferred;
437 u32 tx_one_colls;
438 u32 tx_multi_colls;
439 u32 tx_total_colls;
440 u32 rx_good_frames;
441 u32 rx_crc_errs;
442 u32 rx_align_errs;
443 u32 rx_resource_errs;
444 u32 rx_overrun_errs;
445 u32 rx_colls_errs;
446 u32 rx_runt_errs;
447 u32 done_marker;
448 };
449
450 enum Rx_ring_state_bits {
451 RrNoMem=1, RrPostponed=2, RrNoResources=4, RrOOMReported=8,
452 };
453
454 /* Do not change the position (alignment) of the first few elements!
455 The later elements are grouped for cache locality.
456
457 Unfortunately, all the positions have been shifted since there.
458 A new re-alignment is required. 2000/03/06 SAW */
459 struct speedo_private {
460 struct TxFD *tx_ring; /* Commands (usually CmdTxPacket). */
461 struct RxFD *rx_ringp[RX_RING_SIZE];/* Rx descriptor, used as ring. */
462 /* The addresses of a Tx/Rx-in-place packets/buffers. */
463 struct sk_buff *tx_skbuff[TX_RING_SIZE];
464 struct sk_buff *rx_skbuff[RX_RING_SIZE];
465 /* Mapped addresses of the rings. */
466 dma_addr_t tx_ring_dma;
467 #define TX_RING_ELEM_DMA(sp, n) ((sp)->tx_ring_dma + (n)*sizeof(struct TxFD))
468 dma_addr_t rx_ring_dma[RX_RING_SIZE];
469 struct descriptor *last_cmd; /* Last command sent. */
470 unsigned int cur_tx, dirty_tx; /* The ring entries to be free()ed. */
471 spinlock_t lock; /* Group with Tx control cache line. */
472 u32 tx_threshold; /* The value for txdesc.count. */
473 struct RxFD *last_rxf; /* Last filled RX buffer. */
474 dma_addr_t last_rxf_dma;
475 unsigned int cur_rx, dirty_rx; /* The next free ring entry */
476 long last_rx_time; /* Last Rx, in jiffies, to handle Rx hang. */
477 struct net_device_stats stats;
478 struct speedo_stats *lstats;
479 dma_addr_t lstats_dma;
480 int chip_id;
481 struct pci_dev *pdev;
482 struct timer_list timer; /* Media selection timer. */
483 struct speedo_mc_block *mc_setup_head;/* Multicast setup frame list head. */
484 struct speedo_mc_block *mc_setup_tail;/* Multicast setup frame list tail. */
485 long in_interrupt; /* Word-aligned dev->interrupt */
486 unsigned char acpi_pwr;
487 signed char rx_mode; /* Current PROMISC/ALLMULTI setting. */
488 unsigned int tx_full:1; /* The Tx queue is full. */
489 unsigned int full_duplex:1; /* Full-duplex operation requested. */
490 unsigned int flow_ctrl:1; /* Use 802.3x flow control. */
491 unsigned int rx_bug:1; /* Work around receiver hang errata. */
492 unsigned char default_port:8; /* Last dev->if_port value. */
493 unsigned char rx_ring_state; /* RX ring status flags. */
494 unsigned short phy[2]; /* PHY media interfaces available. */
495 unsigned short advertising; /* Current PHY advertised caps. */
496 unsigned short partner; /* Link partner caps. */
497 };
498
499 /* The parameters for a CmdConfigure operation.
500 There are so many options that it would be difficult to document each bit.
501 We mostly use the default or recommended settings. */
502 static const char i82557_config_cmd[CONFIG_DATA_SIZE] = {
503 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
504 0, 0x2E, 0, 0x60, 0,
505 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
506 0x3f, 0x05, };
507 static const char i82558_config_cmd[CONFIG_DATA_SIZE] = {
508 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
509 0, 0x2E, 0, 0x60, 0x08, 0x88,
510 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
511 0x31, 0x05, };
512
513 /* PHY media interface chips. */
514 static const char *phys[] = {
515 "None", "i82553-A/B", "i82553-C", "i82503",
516 "DP83840", "80c240", "80c24", "i82555",
517 "unknown-8", "unknown-9", "DP83840A", "unknown-11",
518 "unknown-12", "unknown-13", "unknown-14", "unknown-15", };
519 enum phy_chips { NonSuchPhy=0, I82553AB, I82553C, I82503, DP83840, S80C240,
520 S80C24, I82555, DP83840A=10, };
521 static const char is_mii[] = { 0, 1, 1, 0, 1, 1, 0, 1 };
522 #define EE_READ_CMD (6)
523
524 static int eepro100_init_one(struct pci_dev *pdev,
525 const struct pci_device_id *ent);
526 static void eepro100_remove_one (struct pci_dev *pdev);
527 #ifdef CONFIG_PM
528 static int eepro100_suspend (struct pci_dev *pdev, u32 state);
529 static int eepro100_resume (struct pci_dev *pdev);
530 #endif
531
532 static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len);
533 static int mdio_read(long ioaddr, int phy_id, int location);
534 static int mdio_write(long ioaddr, int phy_id, int location, int value);
535 static int speedo_open(struct net_device *dev);
536 static void speedo_resume(struct net_device *dev);
537 static void speedo_timer(unsigned long data);
538 static void speedo_init_rx_ring(struct net_device *dev);
539 static void speedo_tx_timeout(struct net_device *dev);
540 static int speedo_start_xmit(struct sk_buff *skb, struct net_device *dev);
541 static void speedo_refill_rx_buffers(struct net_device *dev, int force);
542 static int speedo_rx(struct net_device *dev);
543 static void speedo_tx_buffer_gc(struct net_device *dev);
544 static void speedo_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
545 static int speedo_close(struct net_device *dev);
546 static struct net_device_stats *speedo_get_stats(struct net_device *dev);
547 static int speedo_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
548 static void set_rx_mode(struct net_device *dev);
549 static void speedo_show_state(struct net_device *dev);
550
551
552
553 #ifdef honor_default_port
554 /* Optional driver feature to allow forcing the transceiver setting.
555 Not recommended. */
556 static int mii_ctrl[8] = { 0x3300, 0x3100, 0x0000, 0x0100,
557 0x2000, 0x2100, 0x0400, 0x3100};
558 #endif
559
560 static int __devinit eepro100_init_one (struct pci_dev *pdev,
561 const struct pci_device_id *ent)
562 {
563 unsigned long ioaddr;
564 int irq;
565 int acpi_idle_state = 0, pm;
566 static int cards_found /* = 0 */;
567
568 static int did_version /* = 0 */; /* Already printed version info. */
569 if (speedo_debug > 0 && did_version++ == 0)
570 printk(version);
571
572 if (!request_region(pci_resource_start(pdev, 1),
573 pci_resource_len(pdev, 1), "eepro100")) {
574 printk (KERN_ERR "eepro100: cannot reserve I/O ports\n");
575 goto err_out_none;
576 }
577 if (!request_mem_region(pci_resource_start(pdev, 0),
578 pci_resource_len(pdev, 0), "eepro100")) {
579 printk (KERN_ERR "eepro100: cannot reserve MMIO region\n");
580 goto err_out_free_pio_region;
581 }
582
583 irq = pdev->irq;
584 #ifdef USE_IO
585 ioaddr = pci_resource_start(pdev, 1);
586 if (speedo_debug > 2)
587 printk("Found Intel i82557 PCI Speedo at I/O %#lx, IRQ %d.\n",
588 ioaddr, irq);
589 #else
590 ioaddr = (unsigned long)ioremap(pci_resource_start(pdev, 0),
591 pci_resource_len(pdev, 0));
592 if (!ioaddr) {
593 printk (KERN_ERR "eepro100: cannot remap MMIO region %lx @ %lx\n",
594 pci_resource_len(pdev, 0), pci_resource_start(pdev, 0));
595 goto err_out_free_mmio_region;
596 }
597 if (speedo_debug > 2)
598 printk("Found Intel i82557 PCI Speedo, MMIO at %#lx, IRQ %d.\n",
599 pci_resource_start(pdev, 0), irq);
600 #endif
601
602 /* save power state b4 pci_enable_device overwrites it */
603 pm = pci_find_capability(pdev, PCI_CAP_ID_PM);
604 if (pm) {
605 u16 pwr_command;
606 pci_read_config_word(pdev, pm + PCI_PM_CTRL, &pwr_command);
607 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
608 }
609
610 if (pci_enable_device(pdev))
611 goto err_out_free_mmio_region;
612
613 pci_set_master(pdev);
614
615 if (speedo_found1(pdev, ioaddr, cards_found, acpi_idle_state) == 0)
616 cards_found++;
617 else
618 goto err_out_iounmap;
619
620 return 0;
621
622 err_out_iounmap: ;
623 #ifndef USE_IO
624 iounmap ((void *)ioaddr);
625 #endif
626 err_out_free_mmio_region:
627 release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
628 err_out_free_pio_region:
629 release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
630 err_out_none:
631 return -ENODEV;
632 }
633
634 static int speedo_found1(struct pci_dev *pdev,
635 long ioaddr, int card_idx, int acpi_idle_state)
636 {
637 struct net_device *dev;
638 struct speedo_private *sp;
639 const char *product;
640 int i, option;
641 u16 eeprom[0x100];
642 int size;
643 void *tx_ring_space;
644 dma_addr_t tx_ring_dma;
645
646 size = TX_RING_SIZE * sizeof(struct TxFD) + sizeof(struct speedo_stats);
647 tx_ring_space = pci_alloc_consistent(pdev, size, &tx_ring_dma);
648 if (tx_ring_space == NULL)
649 return -1;
650
651 dev = init_etherdev(NULL, sizeof(struct speedo_private));
652 if (dev == NULL) {
653 printk(KERN_ERR "eepro100: Could not allocate ethernet device.\n");
654 pci_free_consistent(pdev, size, tx_ring_space, tx_ring_dma);
655 return -1;
656 }
657
658 if (dev->mem_start > 0)
659 option = dev->mem_start;
660 else if (card_idx >= 0 && options[card_idx] >= 0)
661 option = options[card_idx];
662 else
663 option = 0;
664
665 /* Read the station address EEPROM before doing the reset.
666 Nominally his should even be done before accepting the device, but
667 then we wouldn't have a device name with which to report the error.
668 The size test is for 6 bit vs. 8 bit address serial EEPROMs.
669 */
670 {
671 unsigned long iobase;
672 int read_cmd, ee_size;
673 u16 sum;
674 int j;
675
676 /* Use IO only to avoid postponed writes and satisfy EEPROM timing
677 requirements. */
678 iobase = pci_resource_start(pdev, 1);
679 if ((do_eeprom_cmd(iobase, EE_READ_CMD << 24, 27) & 0xffe0000)
680 == 0xffe0000) {
681 ee_size = 0x100;
682 read_cmd = EE_READ_CMD << 24;
683 } else {
684 ee_size = 0x40;
685 read_cmd = EE_READ_CMD << 22;
686 }
687
688 for (j = 0, i = 0, sum = 0; i < ee_size; i++) {
689 u16 value = do_eeprom_cmd(iobase, read_cmd | (i << 16), 27);
690 eeprom[i] = value;
691 sum += value;
692 if (i < 3) {
693 dev->dev_addr[j++] = value;
694 dev->dev_addr[j++] = value >> 8;
695 }
696 }
697 if (sum != 0xBABA)
698 printk(KERN_WARNING "%s: Invalid EEPROM checksum %#4.4x, "
699 "check settings before activating this device!\n",
700 dev->name, sum);
701 /* Don't unregister_netdev(dev); as the EEPro may actually be
702 usable, especially if the MAC address is set later.
703 On the other hand, it may be unusable if MDI data is corrupted. */
704 }
705
706 /* Reset the chip: stop Tx and Rx processes and clear counters.
707 This takes less than 10usec and will easily finish before the next
708 action. */
709 outl(PortReset, ioaddr + SCBPort);
710 inl(ioaddr + SCBPort);
711 udelay(10);
712
713 if (eeprom[3] & 0x0100)
714 product = "OEM i82557/i82558 10/100 Ethernet";
715 else
716 product = pdev->name;
717
718 printk(KERN_INFO "%s: %s, ", dev->name, product);
719
720 for (i = 0; i < 5; i++)
721 printk("%2.2X:", dev->dev_addr[i]);
722 printk("%2.2X, ", dev->dev_addr[i]);
723 #ifdef USE_IO
724 printk("I/O at %#3lx, ", ioaddr);
725 #endif
726 printk("IRQ %d.\n", pdev->irq);
727
728 #if 1 || defined(kernel_bloat)
729 /* OK, this is pure kernel bloat. I don't like it when other drivers
730 waste non-pageable kernel space to emit similar messages, but I need
731 them for bug reports. */
732 {
733 const char *connectors[] = {" RJ45", " BNC", " AUI", " MII"};
734 /* The self-test results must be paragraph aligned. */
735 volatile s32 *self_test_results;
736 int boguscnt = 16000; /* Timeout for set-test. */
737 if ((eeprom[3] & 0x03) != 0x03)
738 printk(KERN_INFO " Receiver lock-up bug exists -- enabling"
739 " work-around.\n");
740 printk(KERN_INFO " Board assembly %4.4x%2.2x-%3.3d, Physical"
741 " connectors present:",
742 eeprom[8], eeprom[9]>>8, eeprom[9] & 0xff);
743 for (i = 0; i < 4; i++)
744 if (eeprom[5] & (1<<i))
745 printk(connectors[i]);
746 printk("\n"KERN_INFO" Primary interface chip %s PHY #%d.\n",
747 phys[(eeprom[6]>>8)&15], eeprom[6] & 0x1f);
748 if (eeprom[7] & 0x0700)
749 printk(KERN_INFO " Secondary interface chip %s.\n",
750 phys[(eeprom[7]>>8)&7]);
751 if (((eeprom[6]>>8) & 0x3f) == DP83840
752 || ((eeprom[6]>>8) & 0x3f) == DP83840A) {
753 int mdi_reg23 = mdio_read(ioaddr, eeprom[6] & 0x1f, 23) | 0x0422;
754 if (congenb)
755 mdi_reg23 |= 0x0100;
756 printk(KERN_INFO" DP83840 specific setup, setting register 23 to %4.4x.\n",
757 mdi_reg23);
758 mdio_write(ioaddr, eeprom[6] & 0x1f, 23, mdi_reg23);
759 }
760 if ((option >= 0) && (option & 0x70)) {
761 printk(KERN_INFO " Forcing %dMbs %s-duplex operation.\n",
762 (option & 0x20 ? 100 : 10),
763 (option & 0x10 ? "full" : "half"));
764 mdio_write(ioaddr, eeprom[6] & 0x1f, 0,
765 ((option & 0x20) ? 0x2000 : 0) | /* 100mbps? */
766 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
767 }
768
769 /* Perform a system self-test. */
770 self_test_results = (s32*) ((((long) tx_ring_space) + 15) & ~0xf);
771 self_test_results[0] = 0;
772 self_test_results[1] = -1;
773 outl(tx_ring_dma | PortSelfTest, ioaddr + SCBPort);
774 do {
775 udelay(10);
776 } while (self_test_results[1] == -1 && --boguscnt >= 0);
777
778 if (boguscnt < 0) { /* Test optimized out. */
779 printk(KERN_ERR "Self test failed, status %8.8x:\n"
780 KERN_ERR " Failure to initialize the i82557.\n"
781 KERN_ERR " Verify that the card is a bus-master"
782 " capable slot.\n",
783 self_test_results[1]);
784 } else
785 printk(KERN_INFO " General self-test: %s.\n"
786 KERN_INFO " Serial sub-system self-test: %s.\n"
787 KERN_INFO " Internal registers self-test: %s.\n"
788 KERN_INFO " ROM checksum self-test: %s (%#8.8x).\n",
789 self_test_results[1] & 0x1000 ? "failed" : "passed",
790 self_test_results[1] & 0x0020 ? "failed" : "passed",
791 self_test_results[1] & 0x0008 ? "failed" : "passed",
792 self_test_results[1] & 0x0004 ? "failed" : "passed",
793 self_test_results[0]);
794 }
795 #endif /* kernel_bloat */
796
797 outl(PortReset, ioaddr + SCBPort);
798 inl(ioaddr + SCBPort);
799 udelay(10);
800
801 /* Return the chip to its original power state. */
802 pci_set_power_state(pdev, acpi_idle_state);
803
804 pci_set_drvdata (pdev, dev);
805
806 dev->base_addr = ioaddr;
807 dev->irq = pdev->irq;
808
809 sp = dev->priv;
810 sp->pdev = pdev;
811 sp->acpi_pwr = acpi_idle_state;
812 sp->tx_ring = tx_ring_space;
813 sp->tx_ring_dma = tx_ring_dma;
814 sp->lstats = (struct speedo_stats *)(sp->tx_ring + TX_RING_SIZE);
815 sp->lstats_dma = TX_RING_ELEM_DMA(sp, TX_RING_SIZE);
816 init_timer(&sp->timer); /* used in ioctl() */
817
818 sp->full_duplex = option >= 0 && (option & 0x10) ? 1 : 0;
819 if (card_idx >= 0) {
820 if (full_duplex[card_idx] >= 0)
821 sp->full_duplex = full_duplex[card_idx];
822 }
823 sp->default_port = option >= 0 ? (option & 0x0f) : 0;
824
825 sp->phy[0] = eeprom[6];
826 sp->phy[1] = eeprom[7];
827 sp->rx_bug = (eeprom[3] & 0x03) == 3 ? 0 : 1;
828
829 if (sp->rx_bug)
830 printk(KERN_INFO " Receiver lock-up workaround activated.\n");
831
832 /* The Speedo-specific entries in the device structure. */
833 dev->open = &speedo_open;
834 dev->hard_start_xmit = &speedo_start_xmit;
835 netif_set_tx_timeout(dev, &speedo_tx_timeout, TX_TIMEOUT);
836 dev->stop = &speedo_close;
837 dev->get_stats = &speedo_get_stats;
838 dev->set_multicast_list = &set_rx_mode;
839 dev->do_ioctl = &speedo_ioctl;
840
841 return 0;
842 }
843
844 /* Serial EEPROM section.
845 A "bit" grungy, but we work our way through bit-by-bit :->. */
846 /* EEPROM_Ctrl bits. */
847 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
848 #define EE_CS 0x02 /* EEPROM chip select. */
849 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
850 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
851 #define EE_ENB (0x4800 | EE_CS)
852 #define EE_WRITE_0 0x4802
853 #define EE_WRITE_1 0x4806
854 #define EE_OFFSET SCBeeprom
855
856 /* The fixes for the code were kindly provided by Dragan Stancevic
857 <visitor@valinux.com> to strictly follow Intel specifications of EEPROM
858 access timing.
859 The publicly available sheet 64486302 (sec. 3.1) specifies 1us access
860 interval for serial EEPROM. However, it looks like that there is an
861 additional requirement dictating larger udelay's in the code below.
862 2000/05/24 SAW */
863 static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
864 {
865 unsigned retval = 0;
866 long ee_addr = ioaddr + SCBeeprom;
867
868 io_outw(EE_ENB, ee_addr); udelay(2);
869 io_outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2);
870
871 /* Shift the command bits out. */
872 do {
873 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
874 io_outw(dataval, ee_addr); udelay(2);
875 io_outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2);
876 retval = (retval << 1) | ((io_inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
877 } while (--cmd_len >= 0);
878 io_outw(EE_ENB, ee_addr); udelay(2);
879
880 /* Terminate the EEPROM access. */
881 io_outw(EE_ENB & ~EE_CS, ee_addr);
882 return retval;
883 }
884
885 static int mdio_read(long ioaddr, int phy_id, int location)
886 {
887 int val, boguscnt = 64*10; /* <64 usec. to complete, typ 27 ticks */
888 outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI);
889 do {
890 val = inl(ioaddr + SCBCtrlMDI);
891 if (--boguscnt < 0) {
892 printk(KERN_ERR " mdio_read() timed out with val = %8.8x.\n", val);
893 break;
894 }
895 } while (! (val & 0x10000000));
896 return val & 0xffff;
897 }
898
899 static int mdio_write(long ioaddr, int phy_id, int location, int value)
900 {
901 int val, boguscnt = 64*10; /* <64 usec. to complete, typ 27 ticks */
902 outl(0x04000000 | (location<<16) | (phy_id<<21) | value,
903 ioaddr + SCBCtrlMDI);
904 do {
905 val = inl(ioaddr + SCBCtrlMDI);
906 if (--boguscnt < 0) {
907 printk(KERN_ERR" mdio_write() timed out with val = %8.8x.\n", val);
908 break;
909 }
910 } while (! (val & 0x10000000));
911 return val & 0xffff;
912 }
913
914
915 static int
916 speedo_open(struct net_device *dev)
917 {
918 struct speedo_private *sp = (struct speedo_private *)dev->priv;
919 long ioaddr = dev->base_addr;
920 int retval;
921
922 if (speedo_debug > 1)
923 printk(KERN_DEBUG "%s: speedo_open() irq %d.\n", dev->name, dev->irq);
924
925 MOD_INC_USE_COUNT;
926
927 pci_set_power_state(sp->pdev, 0);
928
929 /* Set up the Tx queue early.. */
930 sp->cur_tx = 0;
931 sp->dirty_tx = 0;
932 sp->last_cmd = 0;
933 sp->tx_full = 0;
934 spin_lock_init(&sp->lock);
935 sp->in_interrupt = 0;
936
937 /* .. we can safely take handler calls during init. */
938 retval = request_irq(dev->irq, &speedo_interrupt, SA_SHIRQ, dev->name, dev);
939 if (retval) {
940 MOD_DEC_USE_COUNT;
941 return retval;
942 }
943
944 dev->if_port = sp->default_port;
945
946 #ifdef oh_no_you_dont_unless_you_honour_the_options_passed_in_to_us
947 /* Retrigger negotiation to reset previous errors. */
948 if ((sp->phy[0] & 0x8000) == 0) {
949 int phy_addr = sp->phy[0] & 0x1f ;
950 /* Use 0x3300 for restarting NWay, other values to force xcvr:
951 0x0000 10-HD
952 0x0100 10-FD
953 0x2000 100-HD
954 0x2100 100-FD
955 */
956 #ifdef honor_default_port
957 mdio_write(ioaddr, phy_addr, 0, mii_ctrl[dev->default_port & 7]);
958 #else
959 mdio_write(ioaddr, phy_addr, 0, 0x3300);
960 #endif
961 }
962 #endif
963
964 speedo_init_rx_ring(dev);
965
966 /* Fire up the hardware. */
967 outw(SCBMaskAll, ioaddr + SCBCmd);
968 speedo_resume(dev);
969
970 netdevice_start(dev);
971 netif_start_queue(dev);
972
973 /* Setup the chip and configure the multicast list. */
974 sp->mc_setup_head = NULL;
975 sp->mc_setup_tail = NULL;
976 sp->flow_ctrl = sp->partner = 0;
977 sp->rx_mode = -1; /* Invalid -> always reset the mode. */
978 set_rx_mode(dev);
979 if ((sp->phy[0] & 0x8000) == 0)
980 sp->advertising = mdio_read(ioaddr, sp->phy[0] & 0x1f, 4);
981
982 if (speedo_debug > 2) {
983 printk(KERN_DEBUG "%s: Done speedo_open(), status %8.8x.\n",
984 dev->name, inw(ioaddr + SCBStatus));
985 }
986
987 /* Set the timer. The timer serves a dual purpose:
988 1) to monitor the media interface (e.g. link beat) and perhaps switch
989 to an alternate media type
990 2) to monitor Rx activity, and restart the Rx process if the receiver
991 hangs. */
992 sp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
993 sp->timer.data = (unsigned long)dev;
994 sp->timer.function = &speedo_timer; /* timer handler */
995 add_timer(&sp->timer);
996
997 /* No need to wait for the command unit to accept here. */
998 if ((sp->phy[0] & 0x8000) == 0)
999 mdio_read(ioaddr, sp->phy[0] & 0x1f, 0);
1000
1001 return 0;
1002 }
1003
1004 /* Start the chip hardware after a full reset. */
1005 static void speedo_resume(struct net_device *dev)
1006 {
1007 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1008 long ioaddr = dev->base_addr;
1009
1010 /* Start with a Tx threshold of 256 (0x..20.... 8 byte units). */
1011 sp->tx_threshold = 0x01208000;
1012
1013 /* Set the segment registers to '0'. */
1014 wait_for_cmd_done(ioaddr + SCBCmd);
1015 outl(0, ioaddr + SCBPointer);
1016 /* impose a delay to avoid a bug */
1017 inl(ioaddr + SCBPointer);
1018 udelay(10);
1019 outb(RxAddrLoad, ioaddr + SCBCmd);
1020 wait_for_cmd_done(ioaddr + SCBCmd);
1021 outb(CUCmdBase, ioaddr + SCBCmd);
1022
1023 /* Load the statistics block and rx ring addresses. */
1024 wait_for_cmd_done(ioaddr + SCBCmd);
1025 outl(sp->lstats_dma, ioaddr + SCBPointer);
1026 outb(CUStatsAddr, ioaddr + SCBCmd);
1027 sp->lstats->done_marker = 0;
1028
1029 if (sp->rx_ringp[sp->cur_rx % RX_RING_SIZE] == NULL) {
1030 if (speedo_debug > 2)
1031 printk(KERN_DEBUG "%s: NULL cur_rx in speedo_resume().\n",
1032 dev->name);
1033 } else {
1034 wait_for_cmd_done(ioaddr + SCBCmd);
1035 outl(sp->rx_ring_dma[sp->cur_rx % RX_RING_SIZE],
1036 ioaddr + SCBPointer);
1037 outb(RxStart, ioaddr + SCBCmd);
1038 }
1039
1040 wait_for_cmd_done(ioaddr + SCBCmd);
1041 outb(CUDumpStats, ioaddr + SCBCmd);
1042 udelay(30);
1043
1044 /* Fill the first command with our physical address. */
1045 {
1046 struct descriptor *ias_cmd;
1047
1048 ias_cmd =
1049 (struct descriptor *)&sp->tx_ring[sp->cur_tx++ % TX_RING_SIZE];
1050 /* Avoid a bug(?!) here by marking the command already completed. */
1051 ias_cmd->cmd_status = cpu_to_le32((CmdSuspend | CmdIASetup) | 0xa000);
1052 ias_cmd->link =
1053 cpu_to_le32(TX_RING_ELEM_DMA(sp, sp->cur_tx % TX_RING_SIZE));
1054 memcpy(ias_cmd->params, dev->dev_addr, 6);
1055 sp->last_cmd = ias_cmd;
1056 }
1057
1058 /* Start the chip's Tx process and unmask interrupts. */
1059 wait_for_cmd_done(ioaddr + SCBCmd);
1060 outl(TX_RING_ELEM_DMA(sp, sp->dirty_tx % TX_RING_SIZE),
1061 ioaddr + SCBPointer);
1062 /* We are not ACK-ing FCP and ER in the interrupt handler yet so they should
1063 remain masked --Dragan */
1064 outw(CUStart | SCBMaskEarlyRx | SCBMaskFlowCtl, ioaddr + SCBCmd);
1065 }
1066
1067 /* Media monitoring and control. */
1068 static void speedo_timer(unsigned long data)
1069 {
1070 struct net_device *dev = (struct net_device *)data;
1071 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1072 long ioaddr = dev->base_addr;
1073 int phy_num = sp->phy[0] & 0x1f;
1074
1075 /* We have MII and lost link beat. */
1076 if ((sp->phy[0] & 0x8000) == 0) {
1077 int partner = mdio_read(ioaddr, phy_num, 5);
1078 if (partner != sp->partner) {
1079 int flow_ctrl = sp->advertising & partner & 0x0400 ? 1 : 0;
1080 if (speedo_debug > 2) {
1081 printk(KERN_DEBUG "%s: Link status change.\n", dev->name);
1082 printk(KERN_DEBUG "%s: Old partner %x, new %x, adv %x.\n",
1083 dev->name, sp->partner, partner, sp->advertising);
1084 }
1085 sp->partner = partner;
1086 if (flow_ctrl != sp->flow_ctrl) {
1087 sp->flow_ctrl = flow_ctrl;
1088 sp->rx_mode = -1; /* Trigger a reload. */
1089 }
1090 /* Clear sticky bit. */
1091 mdio_read(ioaddr, phy_num, 1);
1092 /* If link beat has returned... */
1093 if (mdio_read(ioaddr, phy_num, 1) & 0x0004)
1094 dev->flags |= IFF_RUNNING;
1095 else
1096 dev->flags &= ~IFF_RUNNING;
1097 }
1098 }
1099 if (speedo_debug > 3) {
1100 printk(KERN_DEBUG "%s: Media control tick, status %4.4x.\n",
1101 dev->name, inw(ioaddr + SCBStatus));
1102 }
1103 if (sp->rx_mode < 0 ||
1104 (sp->rx_bug && jiffies - sp->last_rx_time > 2*HZ)) {
1105 /* We haven't received a packet in a Long Time. We might have been
1106 bitten by the receiver hang bug. This can be cleared by sending
1107 a set multicast list command. */
1108 if (speedo_debug > 3)
1109 printk(KERN_DEBUG "%s: Sending a multicast list set command"
1110 " from a timer routine,"
1111 " m=%d, j=%ld, l=%ld.\n",
1112 dev->name, sp->rx_mode, jiffies, sp->last_rx_time);
1113 set_rx_mode(dev);
1114 }
1115 /* We must continue to monitor the media. */
1116 sp->timer.expires = RUN_AT(2*HZ); /* 2.0 sec. */
1117 add_timer(&sp->timer);
1118 #if defined(timer_exit)
1119 timer_exit(&sp->timer);
1120 #endif
1121 }
1122
1123 static void speedo_show_state(struct net_device *dev)
1124 {
1125 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1126 int i;
1127
1128 /* Print a few items for debugging. */
1129 if (speedo_debug > 0) {
1130 int i;
1131 printk(KERN_DEBUG "%s: Tx ring dump, Tx queue %u / %u:\n", dev->name,
1132 sp->cur_tx, sp->dirty_tx);
1133 for (i = 0; i < TX_RING_SIZE; i++)
1134 printk(KERN_DEBUG "%s: %c%c%2d %8.8x.\n", dev->name,
1135 i == sp->dirty_tx % TX_RING_SIZE ? '*' : ' ',
1136 i == sp->cur_tx % TX_RING_SIZE ? '=' : ' ',
1137 i, sp->tx_ring[i].status);
1138 }
1139 printk(KERN_DEBUG "%s: Printing Rx ring"
1140 " (next to receive into %u, dirty index %u).\n",
1141 dev->name, sp->cur_rx, sp->dirty_rx);
1142
1143 for (i = 0; i < RX_RING_SIZE; i++)
1144 printk(KERN_DEBUG "%s: %c%c%c%2d %8.8x.\n", dev->name,
1145 sp->rx_ringp[i] == sp->last_rxf ? 'l' : ' ',
1146 i == sp->dirty_rx % RX_RING_SIZE ? '*' : ' ',
1147 i == sp->cur_rx % RX_RING_SIZE ? '=' : ' ',
1148 i, (sp->rx_ringp[i] != NULL) ?
1149 (unsigned)sp->rx_ringp[i]->status : 0);
1150
1151 #if 0
1152 {
1153 long ioaddr = dev->base_addr;
1154 int phy_num = sp->phy[0] & 0x1f;
1155 for (i = 0; i < 16; i++) {
1156 /* FIXME: what does it mean? --SAW */
1157 if (i == 6) i = 21;
1158 printk(KERN_DEBUG "%s: PHY index %d register %d is %4.4x.\n",
1159 dev->name, phy_num, i, mdio_read(ioaddr, phy_num, i));
1160 }
1161 }
1162 #endif
1163
1164 }
1165
1166 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1167 static void
1168 speedo_init_rx_ring(struct net_device *dev)
1169 {
1170 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1171 struct RxFD *rxf, *last_rxf = NULL;
1172 dma_addr_t last_rxf_dma = 0 /* to shut up the compiler */;
1173 int i;
1174
1175 sp->cur_rx = 0;
1176
1177 for (i = 0; i < RX_RING_SIZE; i++) {
1178 struct sk_buff *skb;
1179 skb = dev_alloc_skb(PKT_BUF_SZ + sizeof(struct RxFD));
1180 sp->rx_skbuff[i] = skb;
1181 if (skb == NULL)
1182 break; /* OK. Just initially short of Rx bufs. */
1183 skb->dev = dev; /* Mark as being used by this device. */
1184 rxf = (struct RxFD *)skb->tail;
1185 sp->rx_ringp[i] = rxf;
1186 sp->rx_ring_dma[i] =
1187 pci_map_single(sp->pdev, rxf,
1188 PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_BIDIRECTIONAL);
1189 skb_reserve(skb, sizeof(struct RxFD));
1190 if (last_rxf) {
1191 last_rxf->link = cpu_to_le32(sp->rx_ring_dma[i]);
1192 pci_dma_sync_single(sp->pdev, last_rxf_dma,
1193 sizeof(struct RxFD), PCI_DMA_TODEVICE);
1194 }
1195 last_rxf = rxf;
1196 last_rxf_dma = sp->rx_ring_dma[i];
1197 rxf->status = cpu_to_le32(0x00000001); /* '1' is flag value only. */
1198 rxf->link = 0; /* None yet. */
1199 /* This field unused by i82557. */
1200 rxf->rx_buf_addr = 0xffffffff;
1201 rxf->count = cpu_to_le32(PKT_BUF_SZ << 16);
1202 pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[i],
1203 sizeof(struct RxFD), PCI_DMA_TODEVICE);
1204 }
1205 sp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1206 /* Mark the last entry as end-of-list. */
1207 last_rxf->status = cpu_to_le32(0xC0000002); /* '2' is flag value only. */
1208 pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[RX_RING_SIZE-1],
1209 sizeof(struct RxFD), PCI_DMA_TODEVICE);
1210 sp->last_rxf = last_rxf;
1211 sp->last_rxf_dma = last_rxf_dma;
1212 }
1213
1214 static void speedo_purge_tx(struct net_device *dev)
1215 {
1216 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1217 int entry;
1218
1219 while ((int)(sp->cur_tx - sp->dirty_tx) > 0) {
1220 entry = sp->dirty_tx % TX_RING_SIZE;
1221 if (sp->tx_skbuff[entry]) {
1222 sp->stats.tx_errors++;
1223 pci_unmap_single(sp->pdev,
1224 le32_to_cpu(sp->tx_ring[entry].tx_buf_addr0),
1225 sp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1226 dev_kfree_skb_irq(sp->tx_skbuff[entry]);
1227 sp->tx_skbuff[entry] = 0;
1228 }
1229 sp->dirty_tx++;
1230 }
1231 while (sp->mc_setup_head != NULL) {
1232 struct speedo_mc_block *t;
1233 if (speedo_debug > 1)
1234 printk(KERN_DEBUG "%s: freeing mc frame.\n", dev->name);
1235 pci_unmap_single(sp->pdev, sp->mc_setup_head->frame_dma,
1236 sp->mc_setup_head->len, PCI_DMA_TODEVICE);
1237 t = sp->mc_setup_head->next;
1238 kfree(sp->mc_setup_head);
1239 sp->mc_setup_head = t;
1240 }
1241 sp->mc_setup_tail = NULL;
1242 sp->tx_full = 0;
1243 netif_wake_queue(dev);
1244 }
1245
1246 static void reset_mii(struct net_device *dev)
1247 {
1248 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1249 long ioaddr = dev->base_addr;
1250 /* Reset the MII transceiver, suggested by Fred Young @ scalable.com. */
1251 if ((sp->phy[0] & 0x8000) == 0) {
1252 int phy_addr = sp->phy[0] & 0x1f;
1253 int advertising = mdio_read(ioaddr, phy_addr, 4);
1254 int mii_bmcr = mdio_read(ioaddr, phy_addr, 0);
1255 mdio_write(ioaddr, phy_addr, 0, 0x0400);
1256 mdio_write(ioaddr, phy_addr, 1, 0x0000);
1257 mdio_write(ioaddr, phy_addr, 4, 0x0000);
1258 mdio_write(ioaddr, phy_addr, 0, 0x8000);
1259 #ifdef honor_default_port
1260 mdio_write(ioaddr, phy_addr, 0, mii_ctrl[dev->default_port & 7]);
1261 #else
1262 mdio_read(ioaddr, phy_addr, 0);
1263 mdio_write(ioaddr, phy_addr, 0, mii_bmcr);
1264 mdio_write(ioaddr, phy_addr, 4, advertising);
1265 #endif
1266 }
1267 }
1268
1269 static void speedo_tx_timeout(struct net_device *dev)
1270 {
1271 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1272 long ioaddr = dev->base_addr;
1273 int status = inw(ioaddr + SCBStatus);
1274 unsigned long flags;
1275
1276 printk(KERN_WARNING "%s: Transmit timed out: status %4.4x "
1277 " %4.4x at %d/%d command %8.8x.\n",
1278 dev->name, status, inw(ioaddr + SCBCmd),
1279 sp->dirty_tx, sp->cur_tx,
1280 sp->tx_ring[sp->dirty_tx % TX_RING_SIZE].status);
1281
1282 speedo_show_state(dev);
1283 #if 0
1284 if ((status & 0x00C0) != 0x0080
1285 && (status & 0x003C) == 0x0010) {
1286 /* Only the command unit has stopped. */
1287 printk(KERN_WARNING "%s: Trying to restart the transmitter...\n",
1288 dev->name);
1289 outl(TX_RING_ELEM_DMA(sp, dirty_tx % TX_RING_SIZE]),
1290 ioaddr + SCBPointer);
1291 outw(CUStart, ioaddr + SCBCmd);
1292 reset_mii(dev);
1293 } else {
1294 #else
1295 {
1296 #endif
1297 del_timer_sync(&sp->timer);
1298 /* Reset the Tx and Rx units. */
1299 outl(PortReset, ioaddr + SCBPort);
1300 /* We may get spurious interrupts here. But I don't think that they
1301 may do much harm. 1999/12/09 SAW */
1302 udelay(10);
1303 /* Disable interrupts. */
1304 outw(SCBMaskAll, ioaddr + SCBCmd);
1305 synchronize_irq();
1306 speedo_tx_buffer_gc(dev);
1307 /* Free as much as possible.
1308 It helps to recover from a hang because of out-of-memory.
1309 It also simplifies speedo_resume() in case TX ring is full or
1310 close-to-be full. */
1311 speedo_purge_tx(dev);
1312 speedo_refill_rx_buffers(dev, 1);
1313 spin_lock_irqsave(&sp->lock, flags);
1314 speedo_resume(dev);
1315 sp->rx_mode = -1;
1316 dev->trans_start = jiffies;
1317 spin_unlock_irqrestore(&sp->lock, flags);
1318 set_rx_mode(dev); /* it takes the spinlock itself --SAW */
1319 /* Reset MII transceiver. Do it before starting the timer to serialize
1320 mdio_xxx operations. Yes, it's a paranoya :-) 2000/05/09 SAW */
1321 reset_mii(dev);
1322 sp->timer.expires = RUN_AT(2*HZ);
1323 add_timer(&sp->timer);
1324 }
1325 return;
1326 }
1327
1328 static int
1329 speedo_start_xmit(struct sk_buff *skb, struct net_device *dev)
1330 {
1331 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1332 long ioaddr = dev->base_addr;
1333 int entry;
1334
1335 { /* Prevent interrupts from changing the Tx ring from underneath us. */
1336 unsigned long flags;
1337
1338 spin_lock_irqsave(&sp->lock, flags);
1339
1340 /* Check if there are enough space. */
1341 if ((int)(sp->cur_tx - sp->dirty_tx) >= TX_QUEUE_LIMIT) {
1342 printk(KERN_ERR "%s: incorrect tbusy state, fixed.\n", dev->name);
1343 netif_stop_queue(dev);
1344 sp->tx_full = 1;
1345 spin_unlock_irqrestore(&sp->lock, flags);
1346 return 1;
1347 }
1348
1349 /* Calculate the Tx descriptor entry. */
1350 entry = sp->cur_tx++ % TX_RING_SIZE;
1351
1352 sp->tx_skbuff[entry] = skb;
1353 sp->tx_ring[entry].status =
1354 cpu_to_le32(CmdSuspend | CmdTx | CmdTxFlex);
1355 if (!(entry & ((TX_RING_SIZE>>2)-1)))
1356 sp->tx_ring[entry].status |= cpu_to_le32(CmdIntr);
1357 sp->tx_ring[entry].link =
1358 cpu_to_le32(TX_RING_ELEM_DMA(sp, sp->cur_tx % TX_RING_SIZE));
1359 sp->tx_ring[entry].tx_desc_addr =
1360 cpu_to_le32(TX_RING_ELEM_DMA(sp, entry) + TX_DESCR_BUF_OFFSET);
1361 /* The data region is always in one buffer descriptor. */
1362 sp->tx_ring[entry].count = cpu_to_le32(sp->tx_threshold);
1363 sp->tx_ring[entry].tx_buf_addr0 =
1364 cpu_to_le32(pci_map_single(sp->pdev, skb->data,
1365 skb->len, PCI_DMA_TODEVICE));
1366 sp->tx_ring[entry].tx_buf_size0 = cpu_to_le32(skb->len);
1367 /* Trigger the command unit resume. */
1368 wait_for_cmd_done(ioaddr + SCBCmd);
1369 clear_suspend(sp->last_cmd);
1370 /* We want the time window between clearing suspend flag on the previous
1371 command and resuming CU to be as small as possible.
1372 Interrupts in between are very undesired. --SAW */
1373 outb(CUResume, ioaddr + SCBCmd);
1374 sp->last_cmd = (struct descriptor *)&sp->tx_ring[entry];
1375
1376 /* Leave room for set_rx_mode(). If there is no more space than reserved
1377 for multicast filter mark the ring as full. */
1378 if ((int)(sp->cur_tx - sp->dirty_tx) >= TX_QUEUE_LIMIT) {
1379 netif_stop_queue(dev);
1380 sp->tx_full = 1;
1381 }
1382
1383 spin_unlock_irqrestore(&sp->lock, flags);
1384 }
1385
1386 dev->trans_start = jiffies;
1387
1388 return 0;
1389 }
1390
1391 static void speedo_tx_buffer_gc(struct net_device *dev)
1392 {
1393 unsigned int dirty_tx;
1394 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1395
1396 dirty_tx = sp->dirty_tx;
1397 while ((int)(sp->cur_tx - dirty_tx) > 0) {
1398 int entry = dirty_tx % TX_RING_SIZE;
1399 int status = le32_to_cpu(sp->tx_ring[entry].status);
1400
1401 if (speedo_debug > 5)
1402 printk(KERN_DEBUG " scavenge candidate %d status %4.4x.\n",
1403 entry, status);
1404 if ((status & StatusComplete) == 0)
1405 break; /* It still hasn't been processed. */
1406 if (status & TxUnderrun)
1407 if (sp->tx_threshold < 0x01e08000) {
1408 if (speedo_debug > 2)
1409 printk(KERN_DEBUG "%s: TX underrun, threshold adjusted.\n",
1410 dev->name);
1411 sp->tx_threshold += 0x00040000;
1412 }
1413 /* Free the original skb. */
1414 if (sp->tx_skbuff[entry]) {
1415 sp->stats.tx_packets++; /* Count only user packets. */
1416 sp->stats.tx_bytes += sp->tx_skbuff[entry]->len;
1417 pci_unmap_single(sp->pdev,
1418 le32_to_cpu(sp->tx_ring[entry].tx_buf_addr0),
1419 sp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1420 dev_kfree_skb_irq(sp->tx_skbuff[entry]);
1421 sp->tx_skbuff[entry] = 0;
1422 }
1423 dirty_tx++;
1424 }
1425
1426 if (speedo_debug && (int)(sp->cur_tx - dirty_tx) > TX_RING_SIZE) {
1427 printk(KERN_ERR "out-of-sync dirty pointer, %d vs. %d,"
1428 " full=%d.\n",
1429 dirty_tx, sp->cur_tx, sp->tx_full);
1430 dirty_tx += TX_RING_SIZE;
1431 }
1432
1433 while (sp->mc_setup_head != NULL
1434 && (int)(dirty_tx - sp->mc_setup_head->tx - 1) > 0) {
1435 struct speedo_mc_block *t;
1436 if (speedo_debug > 1)
1437 printk(KERN_DEBUG "%s: freeing mc frame.\n", dev->name);
1438 pci_unmap_single(sp->pdev, sp->mc_setup_head->frame_dma,
1439 sp->mc_setup_head->len, PCI_DMA_TODEVICE);
1440 t = sp->mc_setup_head->next;
1441 kfree(sp->mc_setup_head);
1442 sp->mc_setup_head = t;
1443 }
1444 if (sp->mc_setup_head == NULL)
1445 sp->mc_setup_tail = NULL;
1446
1447 sp->dirty_tx = dirty_tx;
1448 }
1449
1450 /* The interrupt handler does all of the Rx thread work and cleans up
1451 after the Tx thread. */
1452 static void speedo_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1453 {
1454 struct net_device *dev = (struct net_device *)dev_instance;
1455 struct speedo_private *sp;
1456 long ioaddr, boguscnt = max_interrupt_work;
1457 unsigned short status;
1458
1459 #ifndef final_version
1460 if (dev == NULL) {
1461 printk(KERN_ERR "speedo_interrupt(): irq %d for unknown device.\n", irq);
1462 return;
1463 }
1464 #endif
1465
1466 ioaddr = dev->base_addr;
1467 sp = (struct speedo_private *)dev->priv;
1468
1469 #ifndef final_version
1470 /* A lock to prevent simultaneous entry on SMP machines. */
1471 if (test_and_set_bit(0, (void*)&sp->in_interrupt)) {
1472 printk(KERN_ERR"%s: SMP simultaneous entry of an interrupt handler.\n",
1473 dev->name);
1474 sp->in_interrupt = 0; /* Avoid halting machine. */
1475 return;
1476 }
1477 #endif
1478
1479 do {
1480 status = inw(ioaddr + SCBStatus);
1481 /* Acknowledge all of the current interrupt sources ASAP. */
1482 /* Will change from 0xfc00 to 0xff00 when we start handling
1483 FCP and ER interrupts --Dragan */
1484 outw(status & 0xfc00, ioaddr + SCBStatus);
1485
1486 if (speedo_debug > 4)
1487 printk(KERN_DEBUG "%s: interrupt status=%#4.4x.\n",
1488 dev->name, status);
1489
1490 if ((status & 0xfc00) == 0)
1491 break;
1492
1493 /* Always check if all rx buffers are allocated. --SAW */
1494 speedo_refill_rx_buffers(dev, 0);
1495
1496 if ((status & 0x5000) || /* Packet received, or Rx error. */
1497 (sp->rx_ring_state&(RrNoMem|RrPostponed)) == RrPostponed)
1498 /* Need to gather the postponed packet. */
1499 speedo_rx(dev);
1500
1501 if (status & 0x1000) {
1502 spin_lock(&sp->lock);
1503 if ((status & 0x003c) == 0x0028) { /* No more Rx buffers. */
1504 struct RxFD *rxf;
1505 printk(KERN_WARNING "%s: card reports no RX buffers.\n",
1506 dev->name);
1507 rxf = sp->rx_ringp[sp->cur_rx % RX_RING_SIZE];
1508 if (rxf == NULL) {
1509 if (speedo_debug > 2)
1510 printk(KERN_DEBUG
1511 "%s: NULL cur_rx in speedo_interrupt().\n",
1512 dev->name);
1513 sp->rx_ring_state |= RrNoMem|RrNoResources;
1514 } else if (rxf == sp->last_rxf) {
1515 if (speedo_debug > 2)
1516 printk(KERN_DEBUG
1517 "%s: cur_rx is last in speedo_interrupt().\n",
1518 dev->name);
1519 sp->rx_ring_state |= RrNoMem|RrNoResources;
1520 } else
1521 outb(RxResumeNoResources, ioaddr + SCBCmd);
1522 } else if ((status & 0x003c) == 0x0008) { /* No resources. */
1523 struct RxFD *rxf;
1524 printk(KERN_WARNING "%s: card reports no resources.\n",
1525 dev->name);
1526 rxf = sp->rx_ringp[sp->cur_rx % RX_RING_SIZE];
1527 if (rxf == NULL) {
1528 if (speedo_debug > 2)
1529 printk(KERN_DEBUG
1530 "%s: NULL cur_rx in speedo_interrupt().\n",
1531 dev->name);
1532 sp->rx_ring_state |= RrNoMem|RrNoResources;
1533 } else if (rxf == sp->last_rxf) {
1534 if (speedo_debug > 2)
1535 printk(KERN_DEBUG
1536 "%s: cur_rx is last in speedo_interrupt().\n",
1537 dev->name);
1538 sp->rx_ring_state |= RrNoMem|RrNoResources;
1539 } else {
1540 /* Restart the receiver. */
1541 outl(sp->rx_ring_dma[sp->cur_rx % RX_RING_SIZE],
1542 ioaddr + SCBPointer);
1543 outb(RxStart, ioaddr + SCBCmd);
1544 }
1545 }
1546 sp->stats.rx_errors++;
1547 spin_unlock(&sp->lock);
1548 }
1549
1550 if ((sp->rx_ring_state&(RrNoMem|RrNoResources)) == RrNoResources) {
1551 printk(KERN_WARNING
1552 "%s: restart the receiver after a possible hang.\n",
1553 dev->name);
1554 spin_lock(&sp->lock);
1555 /* Restart the receiver.
1556 I'm not sure if it's always right to restart the receiver
1557 here but I don't know another way to prevent receiver hangs.
1558 1999/12/25 SAW */
1559 outl(sp->rx_ring_dma[sp->cur_rx % RX_RING_SIZE],
1560 ioaddr + SCBPointer);
1561 outb(RxStart, ioaddr + SCBCmd);
1562 sp->rx_ring_state &= ~RrNoResources;
1563 spin_unlock(&sp->lock);
1564 }
1565
1566 /* User interrupt, Command/Tx unit interrupt or CU not active. */
1567 if (status & 0xA400) {
1568 spin_lock(&sp->lock);
1569 speedo_tx_buffer_gc(dev);
1570 if (sp->tx_full
1571 && (int)(sp->cur_tx - sp->dirty_tx) < TX_QUEUE_UNFULL) {
1572 /* The ring is no longer full. */
1573 sp->tx_full = 0;
1574 netif_wake_queue(dev); /* Attention: under a spinlock. --SAW */
1575 }
1576 spin_unlock(&sp->lock);
1577 }
1578
1579 if (--boguscnt < 0) {
1580 printk(KERN_ERR "%s: Too much work at interrupt, status=0x%4.4x.\n",
1581 dev->name, status);
1582 /* Clear all interrupt sources. */
1583 /* Will change from 0xfc00 to 0xff00 when we start handling
1584 FCP and ER interrupts --Dragan */
1585 outw(0xfc00, ioaddr + SCBStatus);
1586 break;
1587 }
1588 } while (1);
1589
1590 if (speedo_debug > 3)
1591 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1592 dev->name, inw(ioaddr + SCBStatus));
1593
1594 clear_bit(0, (void*)&sp->in_interrupt);
1595 return;
1596 }
1597
1598 static inline struct RxFD *speedo_rx_alloc(struct net_device *dev, int entry)
1599 {
1600 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1601 struct RxFD *rxf;
1602 struct sk_buff *skb;
1603 /* Get a fresh skbuff to replace the consumed one. */
1604 skb = dev_alloc_skb(PKT_BUF_SZ + sizeof(struct RxFD));
1605 sp->rx_skbuff[entry] = skb;
1606 if (skb == NULL) {
1607 sp->rx_ringp[entry] = NULL;
1608 return NULL;
1609 }
1610 rxf = sp->rx_ringp[entry] = (struct RxFD *)skb->tail;
1611 sp->rx_ring_dma[entry] =
1612 pci_map_single(sp->pdev, rxf,
1613 PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
1614 skb->dev = dev;
1615 skb_reserve(skb, sizeof(struct RxFD));
1616 rxf->rx_buf_addr = 0xffffffff;
1617 pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
1618 sizeof(struct RxFD), PCI_DMA_TODEVICE);
1619 return rxf;
1620 }
1621
1622 static inline void speedo_rx_link(struct net_device *dev, int entry,
1623 struct RxFD *rxf, dma_addr_t rxf_dma)
1624 {
1625 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1626 rxf->status = cpu_to_le32(0xC0000001); /* '1' for driver use only. */
1627 rxf->link = 0; /* None yet. */
1628 rxf->count = cpu_to_le32(PKT_BUF_SZ << 16);
1629 sp->last_rxf->link = cpu_to_le32(rxf_dma);
1630 sp->last_rxf->status &= cpu_to_le32(~0xC0000000);
1631 pci_dma_sync_single(sp->pdev, sp->last_rxf_dma,
1632 sizeof(struct RxFD), PCI_DMA_TODEVICE);
1633 sp->last_rxf = rxf;
1634 sp->last_rxf_dma = rxf_dma;
1635 }
1636
1637 static int speedo_refill_rx_buf(struct net_device *dev, int force)
1638 {
1639 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1640 int entry;
1641 struct RxFD *rxf;
1642
1643 entry = sp->dirty_rx % RX_RING_SIZE;
1644 if (sp->rx_skbuff[entry] == NULL) {
1645 rxf = speedo_rx_alloc(dev, entry);
1646 if (rxf == NULL) {
1647 unsigned int forw;
1648 int forw_entry;
1649 if (speedo_debug > 2 || !(sp->rx_ring_state & RrOOMReported)) {
1650 printk(KERN_WARNING "%s: can't fill rx buffer (force %d)!\n",
1651 dev->name, force);
1652 speedo_show_state(dev);
1653 sp->rx_ring_state |= RrOOMReported;
1654 }
1655 if (!force)
1656 return -1; /* Better luck next time! */
1657 /* Borrow an skb from one of next entries. */
1658 for (forw = sp->dirty_rx + 1; forw != sp->cur_rx; forw++)
1659 if (sp->rx_skbuff[forw % RX_RING_SIZE] != NULL)
1660 break;
1661 if (forw == sp->cur_rx)
1662 return -1;
1663 forw_entry = forw % RX_RING_SIZE;
1664 sp->rx_skbuff[entry] = sp->rx_skbuff[forw_entry];
1665 sp->rx_skbuff[forw_entry] = NULL;
1666 rxf = sp->rx_ringp[forw_entry];
1667 sp->rx_ringp[forw_entry] = NULL;
1668 sp->rx_ringp[entry] = rxf;
1669 }
1670 } else {
1671 rxf = sp->rx_ringp[entry];
1672 }
1673 speedo_rx_link(dev, entry, rxf, sp->rx_ring_dma[entry]);
1674 sp->dirty_rx++;
1675 sp->rx_ring_state &= ~(RrNoMem|RrOOMReported); /* Mark the progress. */
1676 return 0;
1677 }
1678
1679 static void speedo_refill_rx_buffers(struct net_device *dev, int force)
1680 {
1681 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1682
1683 /* Refill the RX ring. */
1684 while ((int)(sp->cur_rx - sp->dirty_rx) > 0 &&
1685 speedo_refill_rx_buf(dev, force) != -1);
1686 }
1687
1688 static int
1689 speedo_rx(struct net_device *dev)
1690 {
1691 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1692 int entry = sp->cur_rx % RX_RING_SIZE;
1693 int rx_work_limit = sp->dirty_rx + RX_RING_SIZE - sp->cur_rx;
1694 int alloc_ok = 1;
1695
1696 if (speedo_debug > 4)
1697 printk(KERN_DEBUG " In speedo_rx().\n");
1698 /* If we own the next entry, it's a new packet. Send it up. */
1699 while (sp->rx_ringp[entry] != NULL) {
1700 int status;
1701 int pkt_len;
1702
1703 pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
1704 sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
1705 status = le32_to_cpu(sp->rx_ringp[entry]->status);
1706 pkt_len = le32_to_cpu(sp->rx_ringp[entry]->count) & 0x3fff;
1707
1708 if (!(status & RxComplete))
1709 break;
1710
1711 if (--rx_work_limit < 0)
1712 break;
1713
1714 /* Check for a rare out-of-memory case: the current buffer is
1715 the last buffer allocated in the RX ring. --SAW */
1716 if (sp->last_rxf == sp->rx_ringp[entry]) {
1717 /* Postpone the packet. It'll be reaped at an interrupt when this
1718 packet is no longer the last packet in the ring. */
1719 if (speedo_debug > 2)
1720 printk(KERN_DEBUG "%s: RX packet postponed!\n",
1721 dev->name);
1722 sp->rx_ring_state |= RrPostponed;
1723 break;
1724 }
1725
1726 if (speedo_debug > 4)
1727 printk(KERN_DEBUG " speedo_rx() status %8.8x len %d.\n", status,
1728 pkt_len);
1729 if ((status & (RxErrTooBig|RxOK|0x0f90)) != RxOK) {
1730 if (status & RxErrTooBig)
1731 printk(KERN_ERR "%s: Ethernet frame overran the Rx buffer, "
1732 "status %8.8x!\n", dev->name, status);
1733 else if (! (status & RxOK)) {
1734 /* There was a fatal error. This *should* be impossible. */
1735 sp->stats.rx_errors++;
1736 printk(KERN_ERR "%s: Anomalous event in speedo_rx(), "
1737 "status %8.8x.\n",
1738 dev->name, status);
1739 }
1740 } else {
1741 struct sk_buff *skb;
1742
1743 /* Check if the packet is long enough to just accept without
1744 copying to a properly sized skbuff. */
1745 if (pkt_len < rx_copybreak
1746 && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
1747 skb->dev = dev;
1748 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1749 /* 'skb_put()' points to the start of sk_buff data area. */
1750 pci_dma_sync_single(sp->pdev, sp->rx_ring_dma[entry],
1751 sizeof(struct RxFD) + pkt_len, PCI_DMA_FROMDEVICE);
1752
1753 #if 1 || USE_IP_CSUM
1754 /* Packet is in one chunk -- we can copy + cksum. */
1755 eth_copy_and_sum(skb, sp->rx_skbuff[entry]->tail, pkt_len, 0);
1756 skb_put(skb, pkt_len);
1757 #else
1758 memcpy(skb_put(skb, pkt_len), sp->rx_skbuff[entry]->tail,
1759 pkt_len);
1760 #endif
1761 } else {
1762 /* Pass up the already-filled skbuff. */
1763 skb = sp->rx_skbuff[entry];
1764 if (skb == NULL) {
1765 printk(KERN_ERR "%s: Inconsistent Rx descriptor chain.\n",
1766 dev->name);
1767 break;
1768 }
1769 sp->rx_skbuff[entry] = NULL;
1770 skb_put(skb, pkt_len);
1771 sp->rx_ringp[entry] = NULL;
1772 pci_unmap_single(sp->pdev, sp->rx_ring_dma[entry],
1773 PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
1774 }
1775 skb->protocol = eth_type_trans(skb, dev);
1776 netif_rx(skb);
1777 sp->stats.rx_packets++;
1778 sp->stats.rx_bytes += pkt_len;
1779 }
1780 entry = (++sp->cur_rx) % RX_RING_SIZE;
1781 sp->rx_ring_state &= ~RrPostponed;
1782 /* Refill the recently taken buffers.
1783 Do it one-by-one to handle traffic bursts better. */
1784 if (alloc_ok && speedo_refill_rx_buf(dev, 0) == -1)
1785 alloc_ok = 0;
1786 }
1787
1788 /* Try hard to refill the recently taken buffers. */
1789 speedo_refill_rx_buffers(dev, 1);
1790
1791 sp->last_rx_time = jiffies;
1792
1793 return 0;
1794 }
1795
1796 static int
1797 speedo_close(struct net_device *dev)
1798 {
1799 long ioaddr = dev->base_addr;
1800 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1801 int i;
1802
1803 netdevice_stop(dev);
1804 netif_stop_queue(dev);
1805
1806 if (speedo_debug > 1)
1807 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %4.4x.\n",
1808 dev->name, inw(ioaddr + SCBStatus));
1809
1810 /* Shut off the media monitoring timer. */
1811 del_timer_sync(&sp->timer);
1812
1813 /* Shutting down the chip nicely fails to disable flow control. So.. */
1814 outl(PortPartialReset, ioaddr + SCBPort);
1815
1816 free_irq(dev->irq, dev);
1817
1818 /* Print a few items for debugging. */
1819 if (speedo_debug > 3)
1820 speedo_show_state(dev);
1821
1822 /* Free all the skbuffs in the Rx and Tx queues. */
1823 for (i = 0; i < RX_RING_SIZE; i++) {
1824 struct sk_buff *skb = sp->rx_skbuff[i];
1825 sp->rx_skbuff[i] = 0;
1826 /* Clear the Rx descriptors. */
1827 if (skb) {
1828 pci_unmap_single(sp->pdev,
1829 sp->rx_ring_dma[i],
1830 PKT_BUF_SZ + sizeof(struct RxFD), PCI_DMA_FROMDEVICE);
1831 dev_kfree_skb(skb);
1832 }
1833 }
1834
1835 for (i = 0; i < TX_RING_SIZE; i++) {
1836 struct sk_buff *skb = sp->tx_skbuff[i];
1837 sp->tx_skbuff[i] = 0;
1838 /* Clear the Tx descriptors. */
1839 if (skb) {
1840 pci_unmap_single(sp->pdev,
1841 le32_to_cpu(sp->tx_ring[i].tx_buf_addr0),
1842 skb->len, PCI_DMA_TODEVICE);
1843 dev_kfree_skb(skb);
1844 }
1845 }
1846
1847 /* Free multicast setting blocks. */
1848 for (i = 0; sp->mc_setup_head != NULL; i++) {
1849 struct speedo_mc_block *t;
1850 t = sp->mc_setup_head->next;
1851 kfree(sp->mc_setup_head);
1852 sp->mc_setup_head = t;
1853 }
1854 sp->mc_setup_tail = NULL;
1855 if (speedo_debug > 0)
1856 printk(KERN_DEBUG "%s: %d multicast blocks dropped.\n", dev->name, i);
1857
1858 pci_set_power_state(sp->pdev, 2);
1859
1860 MOD_DEC_USE_COUNT;
1861
1862 return 0;
1863 }
1864
1865 /* The Speedo-3 has an especially awkward and unusable method of getting
1866 statistics out of the chip. It takes an unpredictable length of time
1867 for the dump-stats command to complete. To avoid a busy-wait loop we
1868 update the stats with the previous dump results, and then trigger a
1869 new dump.
1870
1871 Oh, and incoming frames are dropped while executing dump-stats!
1872 */
1873 static struct net_device_stats *
1874 speedo_get_stats(struct net_device *dev)
1875 {
1876 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1877 long ioaddr = dev->base_addr;
1878
1879 /* Update only if the previous dump finished. */
1880 if (sp->lstats->done_marker == le32_to_cpu(0xA007)) {
1881 sp->stats.tx_aborted_errors += le32_to_cpu(sp->lstats->tx_coll16_errs);
1882 sp->stats.tx_window_errors += le32_to_cpu(sp->lstats->tx_late_colls);
1883 sp->stats.tx_fifo_errors += le32_to_cpu(sp->lstats->tx_underruns);
1884 sp->stats.tx_fifo_errors += le32_to_cpu(sp->lstats->tx_lost_carrier);
1885 /*sp->stats.tx_deferred += le32_to_cpu(sp->lstats->tx_deferred);*/
1886 sp->stats.collisions += le32_to_cpu(sp->lstats->tx_total_colls);
1887 sp->stats.rx_crc_errors += le32_to_cpu(sp->lstats->rx_crc_errs);
1888 sp->stats.rx_frame_errors += le32_to_cpu(sp->lstats->rx_align_errs);
1889 sp->stats.rx_over_errors += le32_to_cpu(sp->lstats->rx_resource_errs);
1890 sp->stats.rx_fifo_errors += le32_to_cpu(sp->lstats->rx_overrun_errs);
1891 sp->stats.rx_length_errors += le32_to_cpu(sp->lstats->rx_runt_errs);
1892 sp->lstats->done_marker = 0x0000;
1893 if (netif_running(dev)) {
1894 unsigned long flags;
1895 /* Take a spinlock to make wait_for_cmd_done and sending the
1896 command atomic. --SAW */
1897 spin_lock_irqsave(&sp->lock, flags);
1898 wait_for_cmd_done(ioaddr + SCBCmd);
1899 outb(CUDumpStats, ioaddr + SCBCmd);
1900 spin_unlock_irqrestore(&sp->lock, flags);
1901 }
1902 }
1903 return &sp->stats;
1904 }
1905
1906 static int speedo_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1907 {
1908 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1909 long ioaddr = dev->base_addr;
1910 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1911 int phy = sp->phy[0] & 0x1f;
1912 int saved_acpi;
1913 int t;
1914
1915 switch(cmd) {
1916 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1917 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1918 data->phy_id = phy;
1919
1920 case SIOCGMIIREG: /* Read MII PHY register. */
1921 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1922 /* FIXME: these operations need to be serialized with MDIO
1923 access from the timeout handler.
1924 They are currently serialized only with MDIO access from the
1925 timer routine. 2000/05/09 SAW */
1926 saved_acpi = pci_set_power_state(sp->pdev, 0);
1927 t = del_timer_sync(&sp->timer);
1928 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1929 if (t)
1930 add_timer(&sp->timer); /* may be set to the past --SAW */
1931 pci_set_power_state(sp->pdev, saved_acpi);
1932 return 0;
1933
1934 case SIOCSMIIREG: /* Write MII PHY register. */
1935 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1936 if (!capable(CAP_NET_ADMIN))
1937 return -EPERM;
1938 saved_acpi = pci_set_power_state(sp->pdev, 0);
1939 t = del_timer_sync(&sp->timer);
1940 mdio_write(ioaddr, data->phy_id, data->reg_num, data->val_in);
1941 if (t)
1942 add_timer(&sp->timer); /* may be set to the past --SAW */
1943 pci_set_power_state(sp->pdev, saved_acpi);
1944 return 0;
1945 default:
1946 return -EOPNOTSUPP;
1947 }
1948 }
1949
1950 /* Set or clear the multicast filter for this adaptor.
1951 This is very ugly with Intel chips -- we usually have to execute an
1952 entire configuration command, plus process a multicast command.
1953 This is complicated. We must put a large configuration command and
1954 an arbitrarily-sized multicast command in the transmit list.
1955 To minimize the disruption -- the previous command might have already
1956 loaded the link -- we convert the current command block, normally a Tx
1957 command, into a no-op and link it to the new command.
1958 */
1959 static void set_rx_mode(struct net_device *dev)
1960 {
1961 struct speedo_private *sp = (struct speedo_private *)dev->priv;
1962 long ioaddr = dev->base_addr;
1963 struct descriptor *last_cmd;
1964 char new_rx_mode;
1965 unsigned long flags;
1966 int entry, i;
1967
1968 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1969 new_rx_mode = 3;
1970 } else if ((dev->flags & IFF_ALLMULTI) ||
1971 dev->mc_count > multicast_filter_limit) {
1972 new_rx_mode = 1;
1973 } else
1974 new_rx_mode = 0;
1975
1976 if (speedo_debug > 3)
1977 printk(KERN_DEBUG "%s: set_rx_mode %d -> %d\n", dev->name,
1978 sp->rx_mode, new_rx_mode);
1979
1980 if ((int)(sp->cur_tx - sp->dirty_tx) > TX_RING_SIZE - TX_MULTICAST_SIZE) {
1981 /* The Tx ring is full -- don't add anything! Hope the mode will be
1982 * set again later. */
1983 sp->rx_mode = -1;
1984 return;
1985 }
1986
1987 if (new_rx_mode != sp->rx_mode) {
1988 u8 *config_cmd_data;
1989
1990 spin_lock_irqsave(&sp->lock, flags);
1991 entry = sp->cur_tx++ % TX_RING_SIZE;
1992 last_cmd = sp->last_cmd;
1993 sp->last_cmd = (struct descriptor *)&sp->tx_ring[entry];
1994
1995 sp->tx_skbuff[entry] = 0; /* Redundant. */
1996 sp->tx_ring[entry].status = cpu_to_le32(CmdSuspend | CmdConfigure);
1997 sp->tx_ring[entry].link =
1998 cpu_to_le32(TX_RING_ELEM_DMA(sp, (entry + 1) % TX_RING_SIZE));
1999 config_cmd_data = (void *)&sp->tx_ring[entry].tx_desc_addr;
2000 /* Construct a full CmdConfig frame. */
2001 memcpy(config_cmd_data, i82558_config_cmd, CONFIG_DATA_SIZE);
2002 config_cmd_data[1] = (txfifo << 4) | rxfifo;
2003 config_cmd_data[4] = rxdmacount;
2004 config_cmd_data[5] = txdmacount + 0x80;
2005 config_cmd_data[15] |= (new_rx_mode & 2) ? 1 : 0;
2006 /* 0x80 doesn't disable FC 0x84 does.
2007 Disable Flow control since we are not ACK-ing any FC interrupts
2008 for now. --Dragan */
2009 config_cmd_data[19] = 0x84;
2010 config_cmd_data[19] |= sp->full_duplex ? 0x40 : 0;
2011 config_cmd_data[21] = (new_rx_mode & 1) ? 0x0D : 0x05;
2012 if (sp->phy[0] & 0x8000) { /* Use the AUI port instead. */
2013 config_cmd_data[15] |= 0x80;
2014 config_cmd_data[8] = 0;
2015 }
2016 /* Trigger the command unit resume. */
2017 wait_for_cmd_done(ioaddr + SCBCmd);
2018 clear_suspend(last_cmd);
2019 outb(CUResume, ioaddr + SCBCmd);
2020 if ((int)(sp->cur_tx - sp->dirty_tx) >= TX_QUEUE_LIMIT) {
2021 netif_stop_queue(dev);
2022 sp->tx_full = 1;
2023 }
2024 spin_unlock_irqrestore(&sp->lock, flags);
2025 }
2026
2027 if (new_rx_mode == 0 && dev->mc_count < 4) {
2028 /* The simple case of 0-3 multicast list entries occurs often, and
2029 fits within one tx_ring[] entry. */
2030 struct dev_mc_list *mclist;
2031 u16 *setup_params, *eaddrs;
2032
2033 spin_lock_irqsave(&sp->lock, flags);
2034 entry = sp->cur_tx++ % TX_RING_SIZE;
2035 last_cmd = sp->last_cmd;
2036 sp->last_cmd = (struct descriptor *)&sp->tx_ring[entry];
2037
2038 sp->tx_skbuff[entry] = 0;
2039 sp->tx_ring[entry].status = cpu_to_le32(CmdSuspend | CmdMulticastList);
2040 sp->tx_ring[entry].link =
2041 cpu_to_le32(TX_RING_ELEM_DMA(sp, (entry + 1) % TX_RING_SIZE));
2042 sp->tx_ring[entry].tx_desc_addr = 0; /* Really MC list count. */
2043 setup_params = (u16 *)&sp->tx_ring[entry].tx_desc_addr;
2044 *setup_params++ = cpu_to_le16(dev->mc_count*6);
2045 /* Fill in the multicast addresses. */
2046 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
2047 i++, mclist = mclist->next) {
2048 eaddrs = (u16 *)mclist->dmi_addr;
2049 *setup_params++ = *eaddrs++;
2050 *setup_params++ = *eaddrs++;
2051 *setup_params++ = *eaddrs++;
2052 }
2053
2054 wait_for_cmd_done(ioaddr + SCBCmd);
2055 clear_suspend(last_cmd);
2056 /* Immediately trigger the command unit resume. */
2057 outb(CUResume, ioaddr + SCBCmd);
2058
2059 if ((int)(sp->cur_tx - sp->dirty_tx) >= TX_QUEUE_LIMIT) {
2060 netif_stop_queue(dev);
2061 sp->tx_full = 1;
2062 }
2063 spin_unlock_irqrestore(&sp->lock, flags);
2064 } else if (new_rx_mode == 0) {
2065 struct dev_mc_list *mclist;
2066 u16 *setup_params, *eaddrs;
2067 struct speedo_mc_block *mc_blk;
2068 struct descriptor *mc_setup_frm;
2069 int i;
2070
2071 mc_blk = kmalloc(sizeof(*mc_blk) + 2 + multicast_filter_limit*6,
2072 GFP_ATOMIC);
2073 if (mc_blk == NULL) {
2074 printk(KERN_ERR "%s: Failed to allocate a setup frame.\n",
2075 dev->name);
2076 sp->rx_mode = -1; /* We failed, try again. */
2077 return;
2078 }
2079 mc_blk->next = NULL;
2080 mc_blk->len = 2 + multicast_filter_limit*6;
2081 mc_blk->frame_dma =
2082 pci_map_single(sp->pdev, &mc_blk->frame, mc_blk->len,
2083 PCI_DMA_TODEVICE);
2084 mc_setup_frm = &mc_blk->frame;
2085
2086 /* Fill the setup frame. */
2087 if (speedo_debug > 1)
2088 printk(KERN_DEBUG "%s: Constructing a setup frame at %p.\n",
2089 dev->name, mc_setup_frm);
2090 mc_setup_frm->cmd_status =
2091 cpu_to_le32(CmdSuspend | CmdIntr | CmdMulticastList);
2092 /* Link set below. */
2093 setup_params = (u16 *)&mc_setup_frm->params;
2094 *setup_params++ = cpu_to_le16(dev->mc_count*6);
2095 /* Fill in the multicast addresses. */
2096 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
2097 i++, mclist = mclist->next) {
2098 eaddrs = (u16 *)mclist->dmi_addr;
2099 *setup_params++ = *eaddrs++;
2100 *setup_params++ = *eaddrs++;
2101 *setup_params++ = *eaddrs++;
2102 }
2103
2104 /* Disable interrupts while playing with the Tx Cmd list. */
2105 spin_lock_irqsave(&sp->lock, flags);
2106
2107 if (sp->mc_setup_tail)
2108 sp->mc_setup_tail->next = mc_blk;
2109 else
2110 sp->mc_setup_head = mc_blk;
2111 sp->mc_setup_tail = mc_blk;
2112 mc_blk->tx = sp->cur_tx;
2113
2114 entry = sp->cur_tx++ % TX_RING_SIZE;
2115 last_cmd = sp->last_cmd;
2116 sp->last_cmd = mc_setup_frm;
2117
2118 /* Change the command to a NoOp, pointing to the CmdMulti command. */
2119 sp->tx_skbuff[entry] = 0;
2120 sp->tx_ring[entry].status = cpu_to_le32(CmdNOp);
2121 sp->tx_ring[entry].link = cpu_to_le32(mc_blk->frame_dma);
2122
2123 /* Set the link in the setup frame. */
2124 mc_setup_frm->link =
2125 cpu_to_le32(TX_RING_ELEM_DMA(sp, (entry + 1) % TX_RING_SIZE));
2126
2127 pci_dma_sync_single(sp->pdev, mc_blk->frame_dma,
2128 mc_blk->len, PCI_DMA_TODEVICE);
2129
2130 wait_for_cmd_done(ioaddr + SCBCmd);
2131 clear_suspend(last_cmd);
2132 /* Immediately trigger the command unit resume. */
2133 outb(CUResume, ioaddr + SCBCmd);
2134
2135 if ((int)(sp->cur_tx - sp->dirty_tx) >= TX_QUEUE_LIMIT) {
2136 netif_stop_queue(dev);
2137 sp->tx_full = 1;
2138 }
2139 spin_unlock_irqrestore(&sp->lock, flags);
2140
2141 if (speedo_debug > 5)
2142 printk(" CmdMCSetup frame length %d in entry %d.\n",
2143 dev->mc_count, entry);
2144 }
2145
2146 sp->rx_mode = new_rx_mode;
2147 }
2148
2149 #ifdef CONFIG_PM
2150 static int eepro100_suspend(struct pci_dev *pdev, u32 state)
2151 {
2152 struct net_device *dev = pci_get_drvdata (pdev);
2153 long ioaddr = dev->base_addr;
2154
2155 if (!netif_running(dev))
2156 return 0;
2157
2158 netif_device_detach(dev);
2159 outl(PortPartialReset, ioaddr + SCBPort);
2160
2161 /* XXX call pci_set_power_state ()? */
2162 return 0;
2163 }
2164
2165 static int eepro100_resume(struct pci_dev *pdev)
2166 {
2167 struct net_device *dev = pci_get_drvdata (pdev);
2168 struct speedo_private *sp = (struct speedo_private *)dev->priv;
2169 long ioaddr = dev->base_addr;
2170
2171 if (!netif_running(dev))
2172 return 0;
2173
2174 /* I'm absolutely uncertain if this part of code may work.
2175 The problems are:
2176 - correct hardware reinitialization;
2177 - correct driver behavior between different steps of the
2178 reinitialization;
2179 - serialization with other driver calls.
2180 2000/03/08 SAW */
2181 outw(SCBMaskAll, ioaddr + SCBCmd);
2182 speedo_resume(dev);
2183 netif_device_attach(dev);
2184 sp->rx_mode = -1;
2185 sp->flow_ctrl = sp->partner = 0;
2186 set_rx_mode(dev);
2187 return 0;
2188 }
2189 #endif /* CONFIG_PM */
2190
2191 static void __devexit eepro100_remove_one (struct pci_dev *pdev)
2192 {
2193 struct net_device *dev = pci_get_drvdata (pdev);
2194 struct speedo_private *sp = (struct speedo_private *)dev->priv;
2195
2196 unregister_netdev(dev);
2197
2198 release_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
2199 release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2200
2201 #ifndef USE_IO
2202 iounmap((char *)dev->base_addr);
2203 #endif
2204
2205 pci_free_consistent(pdev, TX_RING_SIZE * sizeof(struct TxFD)
2206 + sizeof(struct speedo_stats),
2207 sp->tx_ring, sp->tx_ring_dma);
2208 kfree(dev);
2209 }
2210
2211 static struct pci_device_id eepro100_pci_tbl[] __devinitdata = {
2212 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557,
2213 PCI_ANY_ID, PCI_ANY_ID, },
2214 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER,
2215 PCI_ANY_ID, PCI_ANY_ID, },
2216 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ID1029,
2217 PCI_ANY_ID, PCI_ANY_ID, },
2218 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ID1030,
2219 PCI_ANY_ID, PCI_ANY_ID, },
2220 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_7,
2221 PCI_ANY_ID, PCI_ANY_ID, },
2222 { 0,}
2223 };
2224 MODULE_DEVICE_TABLE(pci, eepro100_pci_tbl);
2225
2226 static struct pci_driver eepro100_driver = {
2227 name: "eepro100",
2228 id_table: eepro100_pci_tbl,
2229 probe: eepro100_init_one,
2230 remove: eepro100_remove_one,
2231 #ifdef CONFIG_PM
2232 suspend: eepro100_suspend,
2233 resume: eepro100_resume,
2234 #endif /* CONFIG_PM */
2235 };
2236
2237 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48)
2238 static int pci_module_init(struct pci_driver *pdev)
2239 {
2240 int rc;
2241
2242 rc = pci_register_driver(pdev);
2243 if (rc <= 0) {
2244 printk(KERN_INFO "%s: No cards found, driver not installed.\n",
2245 pdev->name);
2246 pci_unregister_driver(pdev);
2247 return -ENODEV;
2248 }
2249 return 0;
2250 }
2251 #endif
2252
2253 static int __init eepro100_init_module(void)
2254 {
2255 if (debug >= 0 && speedo_debug != debug)
2256 printk(KERN_INFO "eepro100.c: Debug level is %d.\n", debug);
2257 if (debug >= 0)
2258 speedo_debug = debug;
2259
2260 return pci_module_init(&eepro100_driver);
2261 }
2262
2263 static void __exit eepro100_cleanup_module(void)
2264 {
2265 pci_unregister_driver(&eepro100_driver);
2266 }
2267
2268 module_init(eepro100_init_module);
2269 module_exit(eepro100_cleanup_module);
2270
2271 /*
2272 * Local variables:
2273 * compile-command: "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -c eepro100.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`"
2274 * c-indent-level: 4
2275 * c-basic-offset: 4
2276 * tab-width: 4
2277 * End:
2278 */
2279