File: /usr/src/linux/drivers/net/epic100.c
1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22
23 ---------------------------------------------------------------------
24
25 Linux kernel-specific changes:
26
27 LK1.1.2 (jgarzik):
28 * Merge becker version 1.09 (4/08/2000)
29
30 LK1.1.3:
31 * Major bugfix to 1.09 driver (Francis Romieu)
32
33 LK1.1.4 (jgarzik):
34 * Merge becker test version 1.09 (5/29/2000)
35
36 LK1.1.5:
37 * Fix locking (jgarzik)
38 * Limit 83c175 probe to ethernet-class PCI devices (rgooch)
39
40 LK1.1.6:
41 * Merge becker version 1.11
42 * Move pci_enable_device before any PCI BAR len checks
43
44 LK1.1.7:
45 * { fill me in }
46
47 LK1.1.8:
48 * ethtool driver info support (jgarzik)
49
50 LK1.1.9:
51 * ethtool media get/set support (jgarzik)
52
53 LK1.1.10:
54 * revert MII transceiver init change (jgarzik)
55
56 */
57
58 #define DRV_NAME "epic100"
59 #define DRV_VERSION "1.11+LK1.1.10"
60 #define DRV_RELDATE "July 6, 2001"
61
62
63 /* The user-configurable values.
64 These may be modified when a driver module is loaded.*/
65
66 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
67 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
68 static int max_interrupt_work = 32;
69
70 /* Used to pass the full-duplex flag, etc. */
71 #define MAX_UNITS 8 /* More are supported, limit only on options */
72 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
73 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
74
75 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
76 Setting to > 1518 effectively disables this feature. */
77 static int rx_copybreak;
78
79 /* Operational parameters that are set at compile time. */
80
81 /* Keep the ring sizes a power of two for operational efficiency.
82 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
83 Making the Tx ring too large decreases the effectiveness of channel
84 bonding and packet priority.
85 There are no ill effects from too-large receive rings. */
86 #define TX_RING_SIZE 16
87 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
88 #define RX_RING_SIZE 32
89 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
90 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
91
92 /* Operational parameters that usually are not changed. */
93 /* Time in jiffies before concluding the transmitter is hung. */
94 #define TX_TIMEOUT (2*HZ)
95
96 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
97
98 /* Bytes transferred to chip before transmission starts. */
99 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
100 #define TX_FIFO_THRESH 256
101 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
102
103 #if !defined(__OPTIMIZE__)
104 #warning You must compile this file with the correct options!
105 #warning See the last lines of the source file.
106 #error You must compile this driver with "-O".
107 #endif
108
109 #include <linux/config.h>
110 #include <linux/module.h>
111 #include <linux/kernel.h>
112 #include <linux/string.h>
113 #include <linux/timer.h>
114 #include <linux/errno.h>
115 #include <linux/ioport.h>
116 #include <linux/slab.h>
117 #include <linux/interrupt.h>
118 #include <linux/pci.h>
119 #include <linux/delay.h>
120 #include <linux/netdevice.h>
121 #include <linux/etherdevice.h>
122 #include <linux/skbuff.h>
123 #include <linux/init.h>
124 #include <linux/spinlock.h>
125 #include <linux/ethtool.h>
126 #include <linux/mii.h>
127 #include <asm/bitops.h>
128 #include <asm/io.h>
129 #include <asm/uaccess.h>
130
131 /* These identify the driver base version and may not be removed. */
132 static char version[] __devinitdata =
133 DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
134 static char version2[] __devinitdata =
135 " http://www.scyld.com/network/epic100.html\n";
136 static char version3[] __devinitdata =
137 " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
138
139 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
140 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
141 MODULE_PARM(debug, "i");
142 MODULE_PARM(max_interrupt_work, "i");
143 MODULE_PARM(rx_copybreak, "i");
144 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
145 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
146 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
147 MODULE_PARM_DESC(max_interrupt_work, "EPIC/100 maximum events handled per interrupt");
148 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
149 MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
150 MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
151
152 /*
153 Theory of Operation
154
155 I. Board Compatibility
156
157 This device driver is designed for the SMC "EPIC/100", the SMC
158 single-chip Ethernet controllers for PCI. This chip is used on
159 the SMC EtherPower II boards.
160
161 II. Board-specific settings
162
163 PCI bus devices are configured by the system at boot time, so no jumpers
164 need to be set on the board. The system BIOS will assign the
165 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
166 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
167 interrupt lines.
168
169 III. Driver operation
170
171 IIIa. Ring buffers
172
173 IVb. References
174
175 http://www.smsc.com/main/datasheets/83c171.pdf
176 http://www.smsc.com/main/datasheets/83c175.pdf
177 http://scyld.com/expert/NWay.html
178 http://www.national.com/pf/DP/DP83840A.html
179
180 IVc. Errata
181
182 */
183
184
185 enum pci_id_flags_bits {
186 /* Set PCI command register bits before calling probe1(). */
187 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
188 /* Read and map the single following PCI BAR. */
189 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
190 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
191 };
192
193 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
194
195 #define EPIC_TOTAL_SIZE 0x100
196 #define USE_IO_OPS 1
197 #ifdef USE_IO_OPS
198 #define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_IO|PCI_ADDR0
199 #else
200 #define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_MEM|PCI_ADDR1
201 #endif
202
203 typedef enum {
204 SMSC_83C170_0,
205 SMSC_83C170,
206 SMSC_83C175,
207 } chip_t;
208
209
210 struct epic_chip_info {
211 const char *name;
212 enum pci_id_flags_bits pci_flags;
213 int io_size; /* Needed for I/O region check or ioremap(). */
214 int drv_flags; /* Driver use, intended as capability flags. */
215 };
216
217
218 /* indexed by chip_t */
219 static struct epic_chip_info pci_id_tbl[] = {
220 { "SMSC EPIC/100 83c170",
221 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },
222 { "SMSC EPIC/100 83c170",
223 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR },
224 { "SMSC EPIC/C 83c175",
225 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },
226 };
227
228
229 static struct pci_device_id epic_pci_tbl[] __devinitdata = {
230 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
231 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
232 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
233 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
234 { 0,}
235 };
236 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
237
238
239 #ifndef USE_IO_OPS
240 #undef inb
241 #undef inw
242 #undef inl
243 #undef outb
244 #undef outw
245 #undef outl
246 #define inb readb
247 #define inw readw
248 #define inl readl
249 #define outb writeb
250 #define outw writew
251 #define outl writel
252 #endif
253
254 /* Offsets to registers, using the (ugh) SMC names. */
255 enum epic_registers {
256 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
257 PCIBurstCnt=0x18,
258 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
259 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
260 LAN0=64, /* MAC address. */
261 MC0=80, /* Multicast filter table. */
262 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
263 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
264 };
265
266 /* Interrupt register bits, using my own meaningful names. */
267 enum IntrStatus {
268 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
269 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
270 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
271 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
272 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
273 };
274 enum CommandBits {
275 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
276 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
277 };
278
279 static u16 media2miictl[16] = {
280 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
281 0, 0, 0, 0, 0, 0, 0, 0 };
282
283 /* The EPIC100 Rx and Tx buffer descriptors. */
284
285 struct epic_tx_desc {
286 u32 txstatus;
287 u32 bufaddr;
288 u32 buflength;
289 u32 next;
290 };
291
292 struct epic_rx_desc {
293 u32 rxstatus;
294 u32 bufaddr;
295 u32 buflength;
296 u32 next;
297 };
298
299 enum desc_status_bits {
300 DescOwn=0x8000,
301 };
302
303 #define PRIV_ALIGN 15 /* Required alignment mask */
304 struct epic_private {
305 struct epic_rx_desc *rx_ring;
306 struct epic_tx_desc *tx_ring;
307 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
308 struct sk_buff* tx_skbuff[TX_RING_SIZE];
309 /* The addresses of receive-in-place skbuffs. */
310 struct sk_buff* rx_skbuff[RX_RING_SIZE];
311
312 dma_addr_t tx_ring_dma;
313 dma_addr_t rx_ring_dma;
314
315 /* Ring pointers. */
316 spinlock_t lock; /* Group with Tx control cache line. */
317 unsigned int cur_tx, dirty_tx;
318 struct descriptor *last_tx_desc;
319
320 unsigned int cur_rx, dirty_rx;
321 unsigned int rx_buf_sz; /* Based on MTU+slack. */
322 struct descriptor *last_rx_desc;
323 long last_rx_time; /* Last Rx, in jiffies. */
324
325 struct pci_dev *pci_dev; /* PCI bus location. */
326 int chip_id, chip_flags;
327
328 struct net_device_stats stats;
329 struct timer_list timer; /* Media selection timer. */
330 int tx_threshold;
331 unsigned char mc_filter[8];
332 signed char phys[4]; /* MII device addresses. */
333 u16 advertising; /* NWay media advertisement */
334 int mii_phy_cnt;
335 unsigned int tx_full:1; /* The Tx queue is full. */
336 unsigned int full_duplex:1; /* Current duplex setting. */
337 unsigned int duplex_lock:1; /* Duplex forced by the user. */
338 unsigned int default_port:4; /* Last dev->if_port value. */
339 unsigned int media2:4; /* Secondary monitored media port. */
340 unsigned int medialock:1; /* Don't sense media type. */
341 unsigned int mediasense:1; /* Media sensing in progress. */
342 };
343
344 static int epic_open(struct net_device *dev);
345 static int read_eeprom(long ioaddr, int location);
346 static int mdio_read(struct net_device *dev, int phy_id, int location);
347 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
348 static void epic_restart(struct net_device *dev);
349 static void epic_timer(unsigned long data);
350 static void epic_tx_timeout(struct net_device *dev);
351 static void epic_init_ring(struct net_device *dev);
352 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
353 static int epic_rx(struct net_device *dev);
354 static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
355 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
356 static int epic_close(struct net_device *dev);
357 static struct net_device_stats *epic_get_stats(struct net_device *dev);
358 static void set_rx_mode(struct net_device *dev);
359
360
361
362 static int __devinit epic_init_one (struct pci_dev *pdev,
363 const struct pci_device_id *ent)
364 {
365 static int card_idx = -1;
366 long ioaddr;
367 int chip_idx = (int) ent->driver_data;
368 int irq;
369 struct net_device *dev;
370 struct epic_private *ep;
371 int i, option = 0, duplex = 0;
372 void *ring_space;
373 dma_addr_t ring_dma;
374
375 /* when built into the kernel, we only print version if device is found */
376 #ifndef MODULE
377 static int printed_version;
378 if (!printed_version++)
379 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
380 version, version2, version3);
381 #endif
382
383 card_idx++;
384
385 i = pci_enable_device(pdev);
386 if (i)
387 return i;
388 irq = pdev->irq;
389
390 if (pci_resource_len(pdev, 0) < pci_id_tbl[chip_idx].io_size) {
391 printk (KERN_ERR "card %d: no PCI region space\n", card_idx);
392 return -ENODEV;
393 }
394
395 pci_set_master(pdev);
396
397 dev = alloc_etherdev(sizeof (*ep));
398 if (!dev) {
399 printk (KERN_ERR "card %d: no memory for eth device\n", card_idx);
400 return -ENOMEM;
401 }
402 SET_MODULE_OWNER(dev);
403
404 if (pci_request_regions(pdev, DRV_NAME))
405 goto err_out_free_netdev;
406
407 #ifdef USE_IO_OPS
408 ioaddr = pci_resource_start (pdev, 0);
409 #else
410 ioaddr = pci_resource_start (pdev, 1);
411 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
412 if (!ioaddr) {
413 printk (KERN_ERR DRV_NAME " %d: ioremap failed\n", card_idx);
414 goto err_out_free_res;
415 }
416 #endif
417
418 pci_set_drvdata(pdev, dev);
419 ep = dev->priv;
420
421 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
422 if (!ring_space)
423 goto err_out_iounmap;
424 ep->tx_ring = (struct epic_tx_desc *)ring_space;
425 ep->tx_ring_dma = ring_dma;
426
427 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
428 if (!ring_space)
429 goto err_out_unmap_tx;
430 ep->rx_ring = (struct epic_rx_desc *)ring_space;
431 ep->rx_ring_dma = ring_dma;
432
433 if (dev->mem_start) {
434 option = dev->mem_start;
435 duplex = (dev->mem_start & 16) ? 1 : 0;
436 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
437 if (options[card_idx] >= 0)
438 option = options[card_idx];
439 if (full_duplex[card_idx] >= 0)
440 duplex = full_duplex[card_idx];
441 }
442
443 dev->base_addr = ioaddr;
444 dev->irq = irq;
445
446 spin_lock_init (&ep->lock);
447
448 /* Bring the chip out of low-power mode. */
449 outl(0x4200, ioaddr + GENCTL);
450 /* Magic?! If we don't set this bit the MII interface won't work. */
451 outl(0x0008, ioaddr + TEST1);
452
453 /* Turn on the MII transceiver. */
454 outl(0x12, ioaddr + MIICfg);
455 if (chip_idx == 1)
456 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
457 outl(0x0200, ioaddr + GENCTL);
458
459 /* Note: the '175 does not have a serial EEPROM. */
460 for (i = 0; i < 3; i++)
461 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
462
463 if (debug > 2) {
464 printk(KERN_DEBUG DRV_NAME "(%s): EEPROM contents\n",
465 pdev->slot_name);
466 for (i = 0; i < 64; i++)
467 printk(" %4.4x%s", read_eeprom(ioaddr, i),
468 i % 16 == 15 ? "\n" : "");
469 }
470
471 ep->pci_dev = pdev;
472 ep->chip_id = chip_idx;
473 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
474
475 /* Find the connected MII xcvrs.
476 Doing this in open() would allow detecting external xcvrs later, but
477 takes much time and no cards have external MII. */
478 {
479 int phy, phy_idx = 0;
480 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
481 int mii_status = mdio_read(dev, phy, 1);
482 if (mii_status != 0xffff && mii_status != 0x0000) {
483 ep->phys[phy_idx++] = phy;
484 printk(KERN_INFO DRV_NAME "(%s): MII transceiver #%d control "
485 "%4.4x status %4.4x.\n",
486 pdev->slot_name, phy, mdio_read(dev, phy, 0), mii_status);
487 }
488 }
489 ep->mii_phy_cnt = phy_idx;
490 if (phy_idx != 0) {
491 phy = ep->phys[0];
492 ep->advertising = mdio_read(dev, phy, 4);
493 printk(KERN_INFO DRV_NAME "(%s): Autonegotiation advertising %4.4x link "
494 "partner %4.4x.\n",
495 pdev->slot_name, ep->advertising, mdio_read(dev, phy, 5));
496 } else if ( ! (ep->chip_flags & NO_MII)) {
497 printk(KERN_WARNING DRV_NAME "(%s): ***WARNING***: No MII transceiver found!\n",
498 pdev->slot_name);
499 /* Use the known PHY address of the EPII. */
500 ep->phys[0] = 3;
501 }
502 }
503
504 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
505 if (ep->chip_flags & MII_PWRDWN)
506 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
507 outl(0x0008, ioaddr + GENCTL);
508
509 /* The lower four bits are the media type. */
510 if (duplex) {
511 ep->duplex_lock = ep->full_duplex = 1;
512 printk(KERN_INFO DRV_NAME "(%s): Forced full duplex operation requested.\n",
513 pdev->slot_name);
514 }
515 dev->if_port = ep->default_port = option;
516 if (ep->default_port)
517 ep->medialock = 1;
518
519 /* The Epic-specific entries in the device structure. */
520 dev->open = &epic_open;
521 dev->hard_start_xmit = &epic_start_xmit;
522 dev->stop = &epic_close;
523 dev->get_stats = &epic_get_stats;
524 dev->set_multicast_list = &set_rx_mode;
525 dev->do_ioctl = &netdev_ioctl;
526 dev->watchdog_timeo = TX_TIMEOUT;
527 dev->tx_timeout = &epic_tx_timeout;
528
529 i = register_netdev(dev);
530 if (i)
531 goto err_out_unmap_tx;
532
533 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
534 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq);
535 for (i = 0; i < 5; i++)
536 printk("%2.2x:", dev->dev_addr[i]);
537 printk("%2.2x.\n", dev->dev_addr[i]);
538
539 return 0;
540
541 err_out_unmap_tx:
542 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
543 err_out_iounmap:
544 #ifndef USE_IO_OPS
545 iounmap(ioaddr);
546 err_out_free_res:
547 #endif
548 pci_release_regions(pdev);
549 err_out_free_netdev:
550 kfree(dev);
551 return -ENODEV;
552 }
553
554 /* Serial EEPROM section. */
555
556 /* EEPROM_Ctrl bits. */
557 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
558 #define EE_CS 0x02 /* EEPROM chip select. */
559 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
560 #define EE_WRITE_0 0x01
561 #define EE_WRITE_1 0x09
562 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
563 #define EE_ENB (0x0001 | EE_CS)
564
565 /* Delay between EEPROM clock transitions.
566 This serves to flush the operation to the PCI bus.
567 */
568
569 #define eeprom_delay() inl(ee_addr)
570
571 /* The EEPROM commands include the alway-set leading bit. */
572 #define EE_WRITE_CMD (5 << 6)
573 #define EE_READ64_CMD (6 << 6)
574 #define EE_READ256_CMD (6 << 8)
575 #define EE_ERASE_CMD (7 << 6)
576
577 static int read_eeprom(long ioaddr, int location)
578 {
579 int i;
580 int retval = 0;
581 long ee_addr = ioaddr + EECTL;
582 int read_cmd = location |
583 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
584
585 outl(EE_ENB & ~EE_CS, ee_addr);
586 outl(EE_ENB, ee_addr);
587
588 /* Shift the read command bits out. */
589 for (i = 12; i >= 0; i--) {
590 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
591 outl(EE_ENB | dataval, ee_addr);
592 eeprom_delay();
593 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
594 eeprom_delay();
595 }
596 outl(EE_ENB, ee_addr);
597
598 for (i = 16; i > 0; i--) {
599 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
600 eeprom_delay();
601 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
602 outl(EE_ENB, ee_addr);
603 eeprom_delay();
604 }
605
606 /* Terminate the EEPROM access. */
607 outl(EE_ENB & ~EE_CS, ee_addr);
608 return retval;
609 }
610
611 #define MII_READOP 1
612 #define MII_WRITEOP 2
613 static int mdio_read(struct net_device *dev, int phy_id, int location)
614 {
615 long ioaddr = dev->base_addr;
616 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
617 int i;
618
619 outl(read_cmd, ioaddr + MIICtrl);
620 /* Typical operation takes 25 loops. */
621 for (i = 400; i > 0; i--) {
622 barrier();
623 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
624 /* Work around read failure bug. */
625 if (phy_id == 1 && location < 6
626 && inw(ioaddr + MIIData) == 0xffff) {
627 outl(read_cmd, ioaddr + MIICtrl);
628 continue;
629 }
630 return inw(ioaddr + MIIData);
631 }
632 }
633 return 0xffff;
634 }
635
636 static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
637 {
638 long ioaddr = dev->base_addr;
639 int i;
640
641 outw(value, ioaddr + MIIData);
642 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
643 for (i = 10000; i > 0; i--) {
644 barrier();
645 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
646 break;
647 }
648 return;
649 }
650
651
652 static int epic_open(struct net_device *dev)
653 {
654 struct epic_private *ep = dev->priv;
655 long ioaddr = dev->base_addr;
656 int i;
657 int retval;
658
659 /* Soft reset the chip. */
660 outl(0x4001, ioaddr + GENCTL);
661
662 if ((retval = request_irq(dev->irq, &epic_interrupt, SA_SHIRQ, dev->name, dev)))
663 return retval;
664
665 epic_init_ring(dev);
666
667 outl(0x4000, ioaddr + GENCTL);
668 /* This magic is documented in SMSC app note 7.15 */
669 outl(0x0008, ioaddr + TEST1);
670
671 /* Pull the chip out of low-power mode, enable interrupts, and set for
672 PCI read multiple. The MIIcfg setting and strange write order are
673 required by the details of which bits are reset and the transceiver
674 wiring on the Ositech CardBus card.
675 */
676 #if 0
677 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
678 #endif
679 if (ep->chip_flags & MII_PWRDWN)
680 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
681
682 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
683 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
684 inl(ioaddr + GENCTL);
685 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
686 #else
687 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
688 inl(ioaddr + GENCTL);
689 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
690 #endif
691
692 for (i = 0; i < 3; i++)
693 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
694
695 ep->tx_threshold = TX_FIFO_THRESH;
696 outl(ep->tx_threshold, ioaddr + TxThresh);
697
698 if (media2miictl[dev->if_port & 15]) {
699 if (ep->mii_phy_cnt)
700 mdio_write(dev, ep->phys[0], 0, media2miictl[dev->if_port&15]);
701 if (dev->if_port == 1) {
702 if (debug > 1)
703 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
704 "status %4.4x.\n",
705 dev->name, mdio_read(dev, ep->phys[0], 1));
706 }
707 } else {
708 int mii_reg5 = mdio_read(dev, ep->phys[0], 5);
709 if (mii_reg5 != 0xffff) {
710 if ((mii_reg5 & 0x0100) || (mii_reg5 & 0x01C0) == 0x0040)
711 ep->full_duplex = 1;
712 else if (! (mii_reg5 & 0x4000))
713 mdio_write(dev, ep->phys[0], 0, 0x1200);
714 if (debug > 1)
715 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
716 " register read of %4.4x.\n", dev->name,
717 ep->full_duplex ? "full" : "half",
718 ep->phys[0], mii_reg5);
719 }
720 }
721
722 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
723 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
724 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
725
726 /* Start the chip's Rx process. */
727 set_rx_mode(dev);
728 outl(StartRx | RxQueued, ioaddr + COMMAND);
729
730 netif_start_queue(dev);
731
732 /* Enable interrupts by setting the interrupt mask. */
733 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
734 | CntFull | TxUnderrun | TxDone | TxEmpty
735 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
736 ioaddr + INTMASK);
737
738 if (debug > 1)
739 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
740 "%s-duplex.\n",
741 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
742 ep->full_duplex ? "full" : "half");
743
744 /* Set the timer to switch to check for link beat and perhaps switch
745 to an alternate media type. */
746 init_timer(&ep->timer);
747 ep->timer.expires = jiffies + 3*HZ;
748 ep->timer.data = (unsigned long)dev;
749 ep->timer.function = &epic_timer; /* timer handler */
750 add_timer(&ep->timer);
751
752 return 0;
753 }
754
755 /* Reset the chip to recover from a PCI transaction error.
756 This may occur at interrupt time. */
757 static void epic_pause(struct net_device *dev)
758 {
759 long ioaddr = dev->base_addr;
760 struct epic_private *ep = dev->priv;
761
762 netif_stop_queue (dev);
763
764 /* Disable interrupts by clearing the interrupt mask. */
765 outl(0x00000000, ioaddr + INTMASK);
766 /* Stop the chip's Tx and Rx DMA processes. */
767 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
768
769 /* Update the error counts. */
770 if (inw(ioaddr + COMMAND) != 0xffff) {
771 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
772 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
773 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
774 }
775
776 /* Remove the packets on the Rx queue. */
777 epic_rx(dev);
778 }
779
780 static void epic_restart(struct net_device *dev)
781 {
782 long ioaddr = dev->base_addr;
783 struct epic_private *ep = dev->priv;
784 int i;
785
786 /* Soft reset the chip. */
787 outl(0x4001, ioaddr + GENCTL);
788
789 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
790 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
791 udelay(1);
792
793 /* This magic is documented in SMSC app note 7.15 */
794 for (i = 16; i > 0; i--)
795 outl(0x0008, ioaddr + TEST1);
796
797 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
798 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
799 #else
800 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
801 #endif
802 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
803 if (ep->chip_flags & MII_PWRDWN)
804 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
805
806 for (i = 0; i < 3; i++)
807 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
808
809 ep->tx_threshold = TX_FIFO_THRESH;
810 outl(ep->tx_threshold, ioaddr + TxThresh);
811 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
812 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
813 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
814 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
815 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
816
817 /* Start the chip's Rx process. */
818 set_rx_mode(dev);
819 outl(StartRx | RxQueued, ioaddr + COMMAND);
820
821 /* Enable interrupts by setting the interrupt mask. */
822 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
823 | CntFull | TxUnderrun | TxDone | TxEmpty
824 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
825 ioaddr + INTMASK);
826 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
827 " interrupt %4.4x.\n",
828 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
829 (int)inl(ioaddr + INTSTAT));
830 return;
831 }
832
833 static void check_media(struct net_device *dev)
834 {
835 struct epic_private *ep = dev->priv;
836 long ioaddr = dev->base_addr;
837 int mii_reg5 = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], 5) : 0;
838 int negotiated = mii_reg5 & ep->advertising;
839 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
840
841 if (ep->duplex_lock)
842 return;
843 if (mii_reg5 == 0xffff) /* Bogus read */
844 return;
845 if (ep->full_duplex != duplex) {
846 ep->full_duplex = duplex;
847 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
848 " partner capability of %4.4x.\n", dev->name,
849 ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
850 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
851 }
852 }
853
854 static void epic_timer(unsigned long data)
855 {
856 struct net_device *dev = (struct net_device *)data;
857 struct epic_private *ep = dev->priv;
858 long ioaddr = dev->base_addr;
859 int next_tick = 5*HZ;
860
861 if (debug > 3) {
862 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
863 dev->name, (int)inl(ioaddr + TxSTAT));
864 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
865 "IntStatus %4.4x RxStatus %4.4x.\n",
866 dev->name, (int)inl(ioaddr + INTMASK),
867 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
868 }
869
870 check_media(dev);
871
872 ep->timer.expires = jiffies + next_tick;
873 add_timer(&ep->timer);
874 }
875
876 static void epic_tx_timeout(struct net_device *dev)
877 {
878 struct epic_private *ep = dev->priv;
879 long ioaddr = dev->base_addr;
880
881 if (debug > 0) {
882 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
883 "Tx status %4.4x.\n",
884 dev->name, (int)inw(ioaddr + TxSTAT));
885 if (debug > 1) {
886 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
887 dev->name, ep->dirty_tx, ep->cur_tx);
888 }
889 }
890 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
891 ep->stats.tx_fifo_errors++;
892 outl(RestartTx, ioaddr + COMMAND);
893 } else {
894 epic_restart(dev);
895 outl(TxQueued, dev->base_addr + COMMAND);
896 }
897
898 dev->trans_start = jiffies;
899 ep->stats.tx_errors++;
900 if (!ep->tx_full)
901 netif_wake_queue(dev);
902 }
903
904 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
905 static void epic_init_ring(struct net_device *dev)
906 {
907 struct epic_private *ep = dev->priv;
908 int i;
909
910 ep->tx_full = 0;
911 ep->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
912 ep->dirty_tx = ep->cur_tx = 0;
913 ep->cur_rx = ep->dirty_rx = 0;
914 ep->last_rx_time = jiffies;
915 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
916
917 /* Initialize all Rx descriptors. */
918 for (i = 0; i < RX_RING_SIZE; i++) {
919 ep->rx_ring[i].rxstatus = 0;
920 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
921 ep->rx_ring[i].next = ep->rx_ring_dma +
922 (i+1)*sizeof(struct epic_rx_desc);
923 ep->rx_skbuff[i] = 0;
924 }
925 /* Mark the last entry as wrapping the ring. */
926 ep->rx_ring[i-1].next = ep->rx_ring_dma;
927
928 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
929 for (i = 0; i < RX_RING_SIZE; i++) {
930 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
931 ep->rx_skbuff[i] = skb;
932 if (skb == NULL)
933 break;
934 skb->dev = dev; /* Mark as being used by this device. */
935 skb_reserve(skb, 2); /* 16 byte align the IP header. */
936 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
937 skb->tail, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
938 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
939 }
940 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
941
942 /* The Tx buffer descriptor is filled in as needed, but we
943 do need to clear the ownership bit. */
944 for (i = 0; i < TX_RING_SIZE; i++) {
945 ep->tx_skbuff[i] = 0;
946 ep->tx_ring[i].txstatus = 0x0000;
947 ep->tx_ring[i].next = ep->tx_ring_dma +
948 (i+1)*sizeof(struct epic_tx_desc);
949 }
950 ep->tx_ring[i-1].next = ep->tx_ring_dma;
951 return;
952 }
953
954 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
955 {
956 struct epic_private *ep = dev->priv;
957 int entry, free_count;
958 u32 ctrl_word;
959 long flags;
960
961 /* Caution: the write order is important here, set the field with the
962 "ownership" bit last. */
963
964 /* Calculate the next Tx descriptor entry. */
965 spin_lock_irqsave(&ep->lock, flags);
966 free_count = ep->cur_tx - ep->dirty_tx;
967 entry = ep->cur_tx % TX_RING_SIZE;
968
969 ep->tx_skbuff[entry] = skb;
970 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
971 skb->len, PCI_DMA_TODEVICE);
972 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
973 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
974 } else if (free_count == TX_QUEUE_LEN/2) {
975 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
976 } else if (free_count < TX_QUEUE_LEN - 1) {
977 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
978 } else {
979 /* Leave room for an additional entry. */
980 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
981 ep->tx_full = 1;
982 }
983 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
984 ep->tx_ring[entry].txstatus =
985 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
986 | cpu_to_le32(DescOwn);
987
988 ep->cur_tx++;
989 if (ep->tx_full)
990 netif_stop_queue(dev);
991
992 spin_unlock_irqrestore(&ep->lock, flags);
993 /* Trigger an immediate transmit demand. */
994 outl(TxQueued, dev->base_addr + COMMAND);
995
996 dev->trans_start = jiffies;
997 if (debug > 4)
998 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
999 "flag %2.2x Tx status %8.8x.\n",
1000 dev->name, (int)skb->len, entry, ctrl_word,
1001 (int)inl(dev->base_addr + TxSTAT));
1002
1003 return 0;
1004 }
1005
1006 /* The interrupt handler does all of the Rx thread work and cleans up
1007 after the Tx thread. */
1008 static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1009 {
1010 struct net_device *dev = dev_instance;
1011 struct epic_private *ep = dev->priv;
1012 long ioaddr = dev->base_addr;
1013 int status, boguscnt = max_interrupt_work;
1014
1015 do {
1016 status = inl(ioaddr + INTSTAT);
1017 /* Acknowledge all of the current interrupt sources ASAP. */
1018 outl(status & 0x00007fff, ioaddr + INTSTAT);
1019
1020 if (debug > 4)
1021 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1022 "intstat=%#8.8x.\n",
1023 dev->name, status, (int)inl(ioaddr + INTSTAT));
1024
1025 if ((status & IntrSummary) == 0)
1026 break;
1027
1028 if (status & (RxDone | RxStarted | RxEarlyWarn | RxOverflow))
1029 epic_rx(dev);
1030
1031 if (status & (TxEmpty | TxDone)) {
1032 unsigned int dirty_tx, cur_tx;
1033
1034 /* Note: if this lock becomes a problem we can narrow the locked
1035 region at the cost of occasionally grabbing the lock more
1036 times. */
1037 spin_lock(&ep->lock);
1038 cur_tx = ep->cur_tx;
1039 dirty_tx = ep->dirty_tx;
1040 for (; cur_tx - dirty_tx > 0; dirty_tx++) {
1041 struct sk_buff *skb;
1042 int entry = dirty_tx % TX_RING_SIZE;
1043 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
1044
1045 if (txstatus & DescOwn)
1046 break; /* It still hasn't been Txed */
1047
1048 if ( ! (txstatus & 0x0001)) {
1049 /* There was an major error, log it. */
1050 #ifndef final_version
1051 if (debug > 1)
1052 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1053 dev->name, txstatus);
1054 #endif
1055 ep->stats.tx_errors++;
1056 if (txstatus & 0x1050) ep->stats.tx_aborted_errors++;
1057 if (txstatus & 0x0008) ep->stats.tx_carrier_errors++;
1058 if (txstatus & 0x0040) ep->stats.tx_window_errors++;
1059 if (txstatus & 0x0010) ep->stats.tx_fifo_errors++;
1060 #ifdef ETHER_STATS
1061 if (txstatus & 0x1000) ep->stats.collisions16++;
1062 #endif
1063 } else {
1064 #ifdef ETHER_STATS
1065 if ((txstatus & 0x0002) != 0) ep->stats.tx_deferred++;
1066 #endif
1067 ep->stats.collisions += (txstatus >> 8) & 15;
1068 ep->stats.tx_packets++;
1069 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1070 }
1071
1072 /* Free the original skb. */
1073 skb = ep->tx_skbuff[entry];
1074 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1075 skb->len, PCI_DMA_TODEVICE);
1076 dev_kfree_skb_irq(skb);
1077 ep->tx_skbuff[entry] = 0;
1078 }
1079
1080 #ifndef final_version
1081 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1082 printk(KERN_WARNING "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1083 dev->name, dirty_tx, cur_tx, ep->tx_full);
1084 dirty_tx += TX_RING_SIZE;
1085 }
1086 #endif
1087 ep->dirty_tx = dirty_tx;
1088 if (ep->tx_full
1089 && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1090 /* The ring is no longer full, allow new TX entries. */
1091 ep->tx_full = 0;
1092 spin_unlock(&ep->lock);
1093 netif_wake_queue(dev);
1094 } else
1095 spin_unlock(&ep->lock);
1096 }
1097
1098 /* Check uncommon events all at once. */
1099 if (status & (CntFull | TxUnderrun | RxOverflow | RxFull |
1100 PCIBusErr170 | PCIBusErr175)) {
1101 if (status == 0xffffffff) /* Chip failed or removed (CardBus). */
1102 break;
1103 /* Always update the error counts to avoid overhead later. */
1104 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1105 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1106 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1107
1108 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1109 ep->stats.tx_fifo_errors++;
1110 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1111 /* Restart the transmit process. */
1112 outl(RestartTx, ioaddr + COMMAND);
1113 }
1114 if (status & RxOverflow) { /* Missed a Rx frame. */
1115 ep->stats.rx_errors++;
1116 }
1117 if (status & (RxOverflow | RxFull))
1118 outw(RxQueued, ioaddr + COMMAND);
1119 if (status & PCIBusErr170) {
1120 printk(KERN_ERR "%s: PCI Bus Error! EPIC status %4.4x.\n",
1121 dev->name, status);
1122 epic_pause(dev);
1123 epic_restart(dev);
1124 }
1125 /* Clear all error sources. */
1126 outl(status & 0x7f18, ioaddr + INTSTAT);
1127 }
1128 if (--boguscnt < 0) {
1129 printk(KERN_ERR "%s: Too much work at interrupt, "
1130 "IntrStatus=0x%8.8x.\n",
1131 dev->name, status);
1132 /* Clear all interrupt sources. */
1133 outl(0x0001ffff, ioaddr + INTSTAT);
1134 break;
1135 }
1136 } while (1);
1137
1138 if (debug > 3)
1139 printk(KERN_DEBUG "%s: exiting interrupt, intr_status=%#4.4x.\n",
1140 dev->name, status);
1141
1142 return;
1143 }
1144
1145 static int epic_rx(struct net_device *dev)
1146 {
1147 struct epic_private *ep = dev->priv;
1148 int entry = ep->cur_rx % RX_RING_SIZE;
1149 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1150 int work_done = 0;
1151
1152 if (debug > 4)
1153 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1154 ep->rx_ring[entry].rxstatus);
1155 /* If we own the next entry, it's a new packet. Send it up. */
1156 while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
1157 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1158
1159 if (debug > 4)
1160 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1161 if (--rx_work_limit < 0)
1162 break;
1163 if (status & 0x2006) {
1164 if (debug > 2)
1165 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1166 dev->name, status);
1167 if (status & 0x2000) {
1168 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1169 "multiple buffers, status %4.4x!\n", dev->name, status);
1170 ep->stats.rx_length_errors++;
1171 } else if (status & 0x0006)
1172 /* Rx Frame errors are counted in hardware. */
1173 ep->stats.rx_errors++;
1174 } else {
1175 /* Malloc up new buffer, compatible with net-2e. */
1176 /* Omit the four octet CRC from the length. */
1177 short pkt_len = (status >> 16) - 4;
1178 struct sk_buff *skb;
1179
1180 pci_dma_sync_single(ep->pci_dev, ep->rx_ring[entry].bufaddr,
1181 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1182 if (pkt_len > PKT_BUF_SZ - 4) {
1183 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1184 "%d bytes.\n",
1185 dev->name, status, pkt_len);
1186 pkt_len = 1514;
1187 }
1188 /* Check if the packet is long enough to accept without copying
1189 to a minimally-sized skbuff. */
1190 if (pkt_len < rx_copybreak
1191 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1192 skb->dev = dev;
1193 skb_reserve(skb, 2); /* 16 byte align the IP header */
1194 #if 1 /* HAS_IP_COPYSUM */
1195 eth_copy_and_sum(skb, ep->rx_skbuff[entry]->tail, pkt_len, 0);
1196 skb_put(skb, pkt_len);
1197 #else
1198 memcpy(skb_put(skb, pkt_len), ep->rx_skbuff[entry]->tail,
1199 pkt_len);
1200 #endif
1201 } else {
1202 pci_unmap_single(ep->pci_dev,
1203 ep->rx_ring[entry].bufaddr,
1204 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1205 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1206 ep->rx_skbuff[entry] = NULL;
1207 }
1208 skb->protocol = eth_type_trans(skb, dev);
1209 netif_rx(skb);
1210 dev->last_rx = jiffies;
1211 ep->stats.rx_packets++;
1212 ep->stats.rx_bytes += pkt_len;
1213 }
1214 work_done++;
1215 entry = (++ep->cur_rx) % RX_RING_SIZE;
1216 }
1217
1218 /* Refill the Rx ring buffers. */
1219 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1220 entry = ep->dirty_rx % RX_RING_SIZE;
1221 if (ep->rx_skbuff[entry] == NULL) {
1222 struct sk_buff *skb;
1223 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1224 if (skb == NULL)
1225 break;
1226 skb->dev = dev; /* Mark as being used by this device. */
1227 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1228 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1229 skb->tail, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1230 work_done++;
1231 }
1232 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1233 }
1234 return work_done;
1235 }
1236
1237 static int epic_close(struct net_device *dev)
1238 {
1239 long ioaddr = dev->base_addr;
1240 struct epic_private *ep = dev->priv;
1241 struct sk_buff *skb;
1242 int i;
1243
1244 netif_stop_queue(dev);
1245
1246 if (debug > 1)
1247 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1248 dev->name, (int)inl(ioaddr + INTSTAT));
1249
1250 del_timer_sync(&ep->timer);
1251 epic_pause(dev);
1252 free_irq(dev->irq, dev);
1253
1254 /* Free all the skbuffs in the Rx queue. */
1255 for (i = 0; i < RX_RING_SIZE; i++) {
1256 skb = ep->rx_skbuff[i];
1257 ep->rx_skbuff[i] = 0;
1258 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1259 ep->rx_ring[i].buflength = 0;
1260 if (skb) {
1261 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1262 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1263 dev_kfree_skb(skb);
1264 }
1265 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1266 }
1267 for (i = 0; i < TX_RING_SIZE; i++) {
1268 skb = ep->tx_skbuff[i];
1269 ep->tx_skbuff[i] = 0;
1270 if (!skb)
1271 continue;
1272 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1273 skb->len, PCI_DMA_TODEVICE);
1274 dev_kfree_skb(skb);
1275 }
1276
1277 /* Green! Leave the chip in low-power mode. */
1278 outl(0x0008, ioaddr + GENCTL);
1279
1280 return 0;
1281 }
1282
1283 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1284 {
1285 struct epic_private *ep = dev->priv;
1286 long ioaddr = dev->base_addr;
1287
1288 if (netif_running(dev)) {
1289 /* Update the error counts. */
1290 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1291 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1292 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1293 }
1294
1295 return &ep->stats;
1296 }
1297
1298 /* Set or clear the multicast filter for this adaptor.
1299 Note that we only use exclusion around actually queueing the
1300 new frame, not around filling ep->setup_frame. This is non-deterministic
1301 when re-entered but still correct. */
1302
1303 /* The little-endian AUTODIN II ethernet CRC calculation.
1304 N.B. Do not use for bulk data, use a table-based routine instead.
1305 This is common code and should be moved to net/core/crc.c */
1306 static unsigned const ethernet_polynomial_le = 0xedb88320U;
1307 static inline unsigned ether_crc_le(int length, unsigned char *data)
1308 {
1309 unsigned int crc = 0xffffffff; /* Initial value. */
1310 while(--length >= 0) {
1311 unsigned char current_octet = *data++;
1312 int bit;
1313 for (bit = 8; --bit >= 0; current_octet >>= 1) {
1314 if ((crc ^ current_octet) & 1) {
1315 crc >>= 1;
1316 crc ^= ethernet_polynomial_le;
1317 } else
1318 crc >>= 1;
1319 }
1320 }
1321 return crc;
1322 }
1323
1324 static void set_rx_mode(struct net_device *dev)
1325 {
1326 long ioaddr = dev->base_addr;
1327 struct epic_private *ep = dev->priv;
1328 unsigned char mc_filter[8]; /* Multicast hash filter */
1329 int i;
1330
1331 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1332 outl(0x002C, ioaddr + RxCtrl);
1333 /* Unconditionally log net taps. */
1334 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1335 memset(mc_filter, 0xff, sizeof(mc_filter));
1336 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1337 /* There is apparently a chip bug, so the multicast filter
1338 is never enabled. */
1339 /* Too many to filter perfectly -- accept all multicasts. */
1340 memset(mc_filter, 0xff, sizeof(mc_filter));
1341 outl(0x000C, ioaddr + RxCtrl);
1342 } else if (dev->mc_count == 0) {
1343 outl(0x0004, ioaddr + RxCtrl);
1344 return;
1345 } else { /* Never executed, for now. */
1346 struct dev_mc_list *mclist;
1347
1348 memset(mc_filter, 0, sizeof(mc_filter));
1349 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1350 i++, mclist = mclist->next)
1351 set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f,
1352 mc_filter);
1353 }
1354 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1355 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1356 for (i = 0; i < 4; i++)
1357 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1358 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1359 }
1360 return;
1361 }
1362
1363 static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
1364 {
1365 struct epic_private *np = dev->priv;
1366 u32 ethcmd;
1367
1368 if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
1369 return -EFAULT;
1370
1371 switch (ethcmd) {
1372 case ETHTOOL_GDRVINFO:
1373 {
1374 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1375 strcpy (info.driver, DRV_NAME);
1376 strcpy (info.version, DRV_VERSION);
1377 strcpy (info.bus_info, np->pci_dev->slot_name);
1378 if (copy_to_user (useraddr, &info, sizeof (info)))
1379 return -EFAULT;
1380 return 0;
1381 }
1382
1383 default:
1384 break;
1385 }
1386
1387 return -EOPNOTSUPP;
1388 }
1389
1390 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1391 {
1392 struct epic_private *ep = dev->priv;
1393 long ioaddr = dev->base_addr;
1394 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1395
1396 switch(cmd) {
1397 case SIOCETHTOOL:
1398 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
1399
1400 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1401 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1402 data->phy_id = ep->phys[0] & 0x1f;
1403 /* Fall Through */
1404
1405 case SIOCGMIIREG: /* Read MII PHY register. */
1406 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1407 if (! netif_running(dev)) {
1408 outl(0x0200, ioaddr + GENCTL);
1409 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1410 }
1411 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1412 #if 0 /* Just leave on if the ioctl() is ever used. */
1413 if (! netif_running(dev)) {
1414 outl(0x0008, ioaddr + GENCTL);
1415 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1416 }
1417 #endif
1418 return 0;
1419
1420 case SIOCSMIIREG: /* Write MII PHY register. */
1421 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1422 if (!capable(CAP_NET_ADMIN))
1423 return -EPERM;
1424 if (! netif_running(dev)) {
1425 outl(0x0200, ioaddr + GENCTL);
1426 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1427 }
1428 if (data->phy_id == ep->phys[0]) {
1429 u16 value = data->val_in;
1430 switch (data->reg_num) {
1431 case 0:
1432 /* Check for autonegotiation on or reset. */
1433 ep->duplex_lock = (value & 0x9000) ? 0 : 1;
1434 if (ep->duplex_lock)
1435 ep->full_duplex = (value & 0x0100) ? 1 : 0;
1436 break;
1437 case 4: ep->advertising = value; break;
1438 }
1439 /* Perhaps check_duplex(dev), depending on chip semantics. */
1440 }
1441 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1442 #if 0 /* Leave on if the ioctl() is used. */
1443 if (! netif_running(dev)) {
1444 outl(0x0008, ioaddr + GENCTL);
1445 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1446 }
1447 #endif
1448 return 0;
1449 default:
1450 return -EOPNOTSUPP;
1451 }
1452 }
1453
1454
1455 static void __devexit epic_remove_one (struct pci_dev *pdev)
1456 {
1457 struct net_device *dev = pci_get_drvdata(pdev);
1458 struct epic_private *ep = dev->priv;
1459
1460 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1461 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1462 unregister_netdev(dev);
1463 #ifndef USE_IO_OPS
1464 iounmap((void*) dev->base_addr);
1465 #endif
1466 pci_release_regions(pdev);
1467 kfree(dev);
1468 pci_set_drvdata(pdev, NULL);
1469 /* pci_power_off(pdev, -1); */
1470 }
1471
1472
1473 #ifdef CONFIG_PM
1474
1475 static int epic_suspend (struct pci_dev *pdev, u32 state)
1476 {
1477 struct net_device *dev = pci_get_drvdata(pdev);
1478 long ioaddr = dev->base_addr;
1479
1480 if (!netif_running(dev))
1481 return 0;
1482 epic_pause(dev);
1483 /* Put the chip into low-power mode. */
1484 outl(0x0008, ioaddr + GENCTL);
1485 /* pci_power_off(pdev, -1); */
1486 return 0;
1487 }
1488
1489
1490 static int epic_resume (struct pci_dev *pdev)
1491 {
1492 struct net_device *dev = pci_get_drvdata(pdev);
1493
1494 if (!netif_running(dev))
1495 return 0;
1496 epic_restart(dev);
1497 /* pci_power_on(pdev); */
1498 return 0;
1499 }
1500
1501 #endif /* CONFIG_PM */
1502
1503
1504 static struct pci_driver epic_driver = {
1505 name: DRV_NAME,
1506 id_table: epic_pci_tbl,
1507 probe: epic_init_one,
1508 remove: epic_remove_one,
1509 #ifdef CONFIG_PM
1510 suspend: epic_suspend,
1511 resume: epic_resume,
1512 #endif /* CONFIG_PM */
1513 };
1514
1515
1516 static int __init epic_init (void)
1517 {
1518 /* when a module, this is printed whether or not devices are found in probe */
1519 #ifdef MODULE
1520 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
1521 version, version2, version3);
1522 #endif
1523
1524 return pci_module_init (&epic_driver);
1525 }
1526
1527
1528 static void __exit epic_cleanup (void)
1529 {
1530 pci_unregister_driver (&epic_driver);
1531 }
1532
1533
1534 module_init(epic_init);
1535 module_exit(epic_cleanup);
1536