File: /usr/src/linux/drivers/net/gmac.c
1 /*
2 * Network device driver for the GMAC ethernet controller on
3 * Apple G4 Powermacs.
4 *
5 * Copyright (C) 2000 Paul Mackerras & Ben. Herrenschmidt
6 *
7 * portions based on sunhme.c by David S. Miller
8 *
9 * Changes:
10 * Arnaldo Carvalho de Melo <acme@conectiva.com.br> - 08/06/2000
11 * - check init_etherdev return in gmac_probe1
12 * BenH <benh@kernel.crashing.org> - 03/09/2000
13 * - Add support for new PHYs
14 * - Add some PowerBook sleep code
15 * BenH <benh@kernel.crashing.org> - ??/??/????
16 * - PHY updates
17 * BenH <benh@kernel.crashing.org> - 08/08/2001
18 * - Add more PHYs, fixes to sleep code
19 */
20
21 #include <linux/module.h>
22
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/types.h>
27 #include <linux/fcntl.h>
28 #include <linux/interrupt.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <asm/prom.h>
37 #include <asm/io.h>
38 #include <asm/pgtable.h>
39 #include <asm/feature.h>
40 #include <asm/keylargo.h>
41 #include <asm/pci-bridge.h>
42 #ifdef CONFIG_PMAC_PBOOK
43 #include <linux/adb.h>
44 #include <linux/pmu.h>
45 #include <asm/irq.h>
46 #endif
47
48 #include "gmac.h"
49
50 #define DEBUG_PHY
51
52 /* Driver version 1.5, kernel 2.4.x */
53 #define GMAC_VERSION "v1.5k4"
54
55 #define DUMMY_BUF_LEN RX_BUF_ALLOC_SIZE + RX_OFFSET + GMAC_BUFFER_ALIGN
56 static unsigned char *dummy_buf;
57 static struct net_device *gmacs;
58
59 /* Prototypes */
60 static int mii_read(struct gmac *gm, int phy, int r);
61 static int mii_write(struct gmac *gm, int phy, int r, int v);
62 static void mii_poll_start(struct gmac *gm);
63 static void mii_poll_stop(struct gmac *gm);
64 static void mii_interrupt(struct gmac *gm);
65 static int mii_lookup_and_reset(struct gmac *gm);
66 static void mii_setup_phy(struct gmac *gm);
67 static int mii_do_reset_phy(struct gmac *gm, int phy_addr);
68 static void mii_init_BCM5400(struct gmac *gm);
69 static void mii_init_BCM5401(struct gmac *gm);
70
71 static void gmac_set_power(struct gmac *gm, int power_up);
72 static int gmac_powerup_and_reset(struct net_device *dev);
73 static void gmac_set_gigabit_mode(struct gmac *gm, int gigabit);
74 static void gmac_set_duplex_mode(struct gmac *gm, int full_duplex);
75 static void gmac_mac_init(struct gmac *gm, unsigned char *mac_addr);
76 static void gmac_init_rings(struct gmac *gm, int from_irq);
77 static void gmac_start_dma(struct gmac *gm);
78 static void gmac_stop_dma(struct gmac *gm);
79 static void gmac_set_multicast(struct net_device *dev);
80 static int gmac_open(struct net_device *dev);
81 static int gmac_close(struct net_device *dev);
82 static void gmac_tx_timeout(struct net_device *dev);
83 static int gmac_xmit_start(struct sk_buff *skb, struct net_device *dev);
84 static void gmac_tx_cleanup(struct net_device *dev, int force_cleanup);
85 static void gmac_receive(struct net_device *dev);
86 static void gmac_interrupt(int irq, void *dev_id, struct pt_regs *regs);
87 static struct net_device_stats *gmac_stats(struct net_device *dev);
88 static int gmac_probe(void);
89 static void gmac_probe1(struct device_node *gmac);
90
91 #ifdef CONFIG_PMAC_PBOOK
92 int gmac_sleep_notify(struct pmu_sleep_notifier *self, int when);
93 static struct pmu_sleep_notifier gmac_sleep_notifier = {
94 gmac_sleep_notify, SLEEP_LEVEL_NET,
95 };
96 #endif
97
98 /*
99 * Read via the mii interface from a PHY register
100 */
101 static int
102 mii_read(struct gmac *gm, int phy, int r)
103 {
104 int timeout;
105
106 GM_OUT(GM_MIF_FRAME_CTL_DATA,
107 (0x01 << GM_MIF_FRAME_START_SHIFT) |
108 (0x02 << GM_MIF_FRAME_OPCODE_SHIFT) |
109 GM_MIF_FRAME_TURNAROUND_HI |
110 (phy << GM_MIF_FRAME_PHY_ADDR_SHIFT) |
111 (r << GM_MIF_FRAME_REG_ADDR_SHIFT));
112
113 for (timeout = 1000; timeout > 0; --timeout) {
114 udelay(20);
115 if (GM_IN(GM_MIF_FRAME_CTL_DATA) & GM_MIF_FRAME_TURNAROUND_LO)
116 return GM_IN(GM_MIF_FRAME_CTL_DATA) & GM_MIF_FRAME_DATA_MASK;
117 }
118 return -1;
119 }
120
121 /*
122 * Write on the mii interface to a PHY register
123 */
124 static int
125 mii_write(struct gmac *gm, int phy, int r, int v)
126 {
127 int timeout;
128
129 GM_OUT(GM_MIF_FRAME_CTL_DATA,
130 (0x01 << GM_MIF_FRAME_START_SHIFT) |
131 (0x01 << GM_MIF_FRAME_OPCODE_SHIFT) |
132 GM_MIF_FRAME_TURNAROUND_HI |
133 (phy << GM_MIF_FRAME_PHY_ADDR_SHIFT) |
134 (r << GM_MIF_FRAME_REG_ADDR_SHIFT) |
135 (v & GM_MIF_FRAME_DATA_MASK));
136
137 for (timeout = 1000; timeout > 0; --timeout) {
138 udelay(20);
139 if (GM_IN(GM_MIF_FRAME_CTL_DATA) & GM_MIF_FRAME_TURNAROUND_LO)
140 return 0;
141 }
142 return -1;
143 }
144
145 /*
146 * Start MIF autopolling of the PHY status register
147 */
148 static void
149 mii_poll_start(struct gmac *gm)
150 {
151 unsigned int tmp;
152
153 /* Start the MIF polling on the external transceiver. */
154 tmp = GM_IN(GM_MIF_CFG);
155 tmp &= ~(GM_MIF_CFGPR_MASK | GM_MIF_CFGPD_MASK);
156 tmp |= ((gm->phy_addr & 0x1f) << GM_MIF_CFGPD_SHIFT);
157 tmp |= (MII_SR << GM_MIF_CFGPR_SHIFT);
158 tmp |= GM_MIF_CFGPE;
159 GM_OUT(GM_MIF_CFG, tmp);
160
161 /* Let the bits set. */
162 udelay(GM_MIF_POLL_DELAY);
163
164 GM_OUT(GM_MIF_IRQ_MASK, 0xffc0);
165 }
166
167 /*
168 * Stop MIF autopolling of the PHY status register
169 */
170 static void
171 mii_poll_stop(struct gmac *gm)
172 {
173 GM_OUT(GM_MIF_IRQ_MASK, 0xffff);
174 GM_BIC(GM_MIF_CFG, GM_MIF_CFGPE);
175 udelay(GM_MIF_POLL_DELAY);
176 }
177
178 /*
179 * Called when the MIF detect a change of the PHY status
180 *
181 * handles monitoring the link and updating GMAC with the correct
182 * duplex mode.
183 *
184 * Note: Are we missing status changes ? In this case, we'll have to
185 * a timer and control the autoneg. process more closely. Also, we may
186 * want to stop rx and tx side when the link is down.
187 */
188
189 /* Link modes of the BCM5400 PHY */
190 static int phy_BCM5400_link_table[8][3] = {
191 { 0, 0, 0 }, /* No link */
192 { 0, 0, 0 }, /* 10BT Half Duplex */
193 { 1, 0, 0 }, /* 10BT Full Duplex */
194 { 0, 1, 0 }, /* 100BT Half Duplex */
195 { 0, 1, 0 }, /* 100BT Half Duplex */
196 { 1, 1, 0 }, /* 100BT Full Duplex*/
197 { 1, 0, 1 }, /* 1000BT */
198 { 1, 0, 1 }, /* 1000BT */
199 };
200
201 static void
202 mii_interrupt(struct gmac *gm)
203 {
204 int phy_status;
205 int lpar_ability;
206
207 mii_poll_stop(gm);
208
209 /* May the status change before polling is re-enabled ? */
210 mii_poll_start(gm);
211
212 /* We read the Auxilliary Status Summary register */
213 phy_status = mii_read(gm, gm->phy_addr, MII_SR);
214 if ((phy_status ^ gm->phy_status) & (MII_SR_ASSC | MII_SR_LKS)) {
215 int full_duplex = 0;
216 int link_100 = 0;
217 int gigabit = 0;
218 #ifdef DEBUG_PHY
219 printk(KERN_INFO "%s: Link state change, phy_status: 0x%04x\n",
220 gm->dev->name, phy_status);
221 #endif
222 gm->phy_status = phy_status;
223
224 /* Should we enable that in generic mode ? */
225 lpar_ability = mii_read(gm, gm->phy_addr, MII_ANLPA);
226 if (lpar_ability & MII_ANLPA_PAUS)
227 GM_BIS(GM_MAC_CTRL_CONFIG, GM_MAC_CTRL_CONF_SND_PAUSE_EN);
228 else
229 GM_BIC(GM_MAC_CTRL_CONFIG, GM_MAC_CTRL_CONF_SND_PAUSE_EN);
230
231 /* Link ? Check for speed and duplex */
232 if ((phy_status & MII_SR_LKS) && (phy_status & MII_SR_ASSC)) {
233 int restart = 0;
234 int aux_stat, link;
235 switch (gm->phy_type) {
236 case PHY_B5201:
237 case PHY_B5221:
238 aux_stat = mii_read(gm, gm->phy_addr, MII_BCM5201_AUXCTLSTATUS);
239 #ifdef DEBUG_PHY
240 printk(KERN_INFO "%s: Link up ! BCM5201/5221 aux_stat: 0x%04x\n",
241 gm->dev->name, aux_stat);
242 #endif
243 full_duplex = ((aux_stat & MII_BCM5201_AUXCTLSTATUS_DUPLEX) != 0);
244 link_100 = ((aux_stat & MII_BCM5201_AUXCTLSTATUS_SPEED) != 0);
245 break;
246 case PHY_B5400:
247 case PHY_B5401:
248 case PHY_B5411:
249 aux_stat = mii_read(gm, gm->phy_addr, MII_BCM5400_AUXSTATUS);
250 link = (aux_stat & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
251 MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT;
252 #ifdef DEBUG_PHY
253 printk(KERN_INFO "%s: Link up ! BCM54xx aux_stat: 0x%04x (link mode: %d)\n",
254 gm->dev->name, aux_stat, link);
255 #endif
256 full_duplex = phy_BCM5400_link_table[link][0];
257 link_100 = phy_BCM5400_link_table[link][1];
258 gigabit = phy_BCM5400_link_table[link][2];
259 break;
260 case PHY_LXT971:
261 aux_stat = mii_read(gm, gm->phy_addr, MII_LXT971_STATUS2);
262 #ifdef DEBUG_PHY
263 printk(KERN_INFO "%s: Link up ! LXT971 stat2: 0x%04x\n",
264 gm->dev->name, aux_stat);
265 #endif
266 full_duplex = ((aux_stat & MII_LXT971_STATUS2_FULLDUPLEX) != 0);
267 link_100 = ((aux_stat & MII_LXT971_STATUS2_SPEED) != 0);
268 break;
269 default:
270 full_duplex = (lpar_ability & MII_ANLPA_FDAM) != 0;
271 link_100 = (lpar_ability & MII_ANLPA_100M) != 0;
272 break;
273 }
274 #ifdef DEBUG_PHY
275 printk(KERN_INFO "%s: Full Duplex: %d, Speed: %s\n",
276 gm->dev->name, full_duplex,
277 gigabit ? "1000" : (link_100 ? "100" : "10"));
278 #endif
279 if (gigabit != gm->gigabit) {
280 gm->gigabit = gigabit;
281 gmac_set_gigabit_mode(gm, gm->gigabit);
282 restart = 1;
283 }
284 if (full_duplex != gm->full_duplex) {
285 gm->full_duplex = full_duplex;
286 gmac_set_duplex_mode(gm, gm->full_duplex);
287 restart = 1;
288 }
289 if (restart)
290 gmac_start_dma(gm);
291 } else if (!(phy_status & MII_SR_LKS)) {
292 #ifdef DEBUG_PHY
293 printk(KERN_INFO "%s: Link down !\n", gm->dev->name);
294 #endif
295 }
296 }
297 }
298
299 /* Power management: stop PHY chip for suspend mode
300 *
301 * TODO: This will have to be modified is WOL is to be supported.
302 */
303 static void
304 gmac_suspend(struct gmac* gm)
305 {
306 int data, timeout;
307 unsigned long flags;
308
309 gm->sleeping = 1;
310 netif_device_detach(gm->dev);
311
312
313 spin_lock_irqsave(&gm->lock, flags);
314 if (gm->opened) {
315 disable_irq(gm->dev->irq);
316 /* Stop polling PHY */
317 mii_poll_stop(gm);
318 }
319 /* Mask out all chips interrupts */
320 GM_OUT(GM_IRQ_MASK, 0xffffffff);
321 spin_unlock_irqrestore(&gm->lock, flags);
322
323 if (gm->opened) {
324 int i;
325 /* Empty Tx ring of any remaining gremlins */
326 gmac_tx_cleanup(gm->dev, 1);
327
328 /* Empty Rx ring of any remaining gremlins */
329 for (i = 0; i < NRX; ++i) {
330 if (gm->rx_buff[i] != 0) {
331 dev_kfree_skb_irq(gm->rx_buff[i]);
332 gm->rx_buff[i] = 0;
333 }
334 }
335 }
336
337 /* Clear interrupts on 5201 */
338 if (gm->phy_type == PHY_B5201 || gm->phy_type == PHY_B5221)
339 mii_write(gm, gm->phy_addr, MII_BCM5201_INTERRUPT, 0);
340
341 /* Drive MDIO high */
342 GM_OUT(GM_MIF_CFG, 0);
343
344 /* Unchanged, don't ask me why */
345 data = mii_read(gm, gm->phy_addr, MII_ANLPA);
346 mii_write(gm, gm->phy_addr, MII_ANLPA, data);
347
348 /* Stop everything */
349 GM_OUT(GM_MAC_RX_CONFIG, 0);
350 GM_OUT(GM_MAC_TX_CONFIG, 0);
351 GM_OUT(GM_MAC_XIF_CONFIG, 0);
352 GM_OUT(GM_TX_CONF, 0);
353 GM_OUT(GM_RX_CONF, 0);
354
355 /* Set MAC in reset state */
356 GM_OUT(GM_RESET, GM_RESET_TX | GM_RESET_RX);
357 for (timeout = 100; timeout > 0; --timeout) {
358 mdelay(10);
359 if ((GM_IN(GM_RESET) & (GM_RESET_TX | GM_RESET_RX)) == 0)
360 break;
361 }
362 GM_OUT(GM_MAC_TX_RESET, GM_MAC_TX_RESET_NOW);
363 GM_OUT(GM_MAC_RX_RESET, GM_MAC_RX_RESET_NOW);
364
365 /* Superisolate PHY */
366 if (gm->phy_type == PHY_B5201 || gm->phy_type == PHY_B5221)
367 mii_write(gm, gm->phy_addr, MII_BCM5201_MULTIPHY,
368 MII_BCM5201_MULTIPHY_SUPERISOLATE);
369
370 /* Put MDIO in sane electric state. According to an obscure
371 * Apple comment, not doing so may let them drive some current
372 * during sleep and possibly damage BCM PHYs.
373 */
374 GM_OUT(GM_MIF_CFG, GM_MIF_CFGBB);
375 GM_OUT(GM_MIF_BB_CLOCK, 0);
376 GM_OUT(GM_MIF_BB_DATA, 0);
377 GM_OUT(GM_MIF_BB_OUT_ENABLE, 0);
378 GM_OUT(GM_MAC_XIF_CONFIG,
379 GM_MAC_XIF_CONF_GMII_MODE|GM_MAC_XIF_CONF_MII_INT_LOOP);
380 (void)GM_IN(GM_MAC_XIF_CONFIG);
381
382 /* Unclock the GMAC chip */
383 gmac_set_power(gm, 0);
384 }
385
386 static void
387 gmac_resume(struct gmac *gm)
388 {
389 int data;
390
391 if (gmac_powerup_and_reset(gm->dev)) {
392 printk(KERN_ERR "%s: Couldn't revive gmac ethernet !\n", gm->dev->name);
393 return;
394 }
395
396 gm->sleeping = 0;
397
398 if (gm->opened) {
399 /* Create fresh rings */
400 gmac_init_rings(gm, 1);
401 /* re-initialize the MAC */
402 gmac_mac_init(gm, gm->dev->dev_addr);
403 /* re-initialize the multicast tables & promisc mode if any */
404 gmac_set_multicast(gm->dev);
405 }
406
407 /* Early enable Tx and Rx so that we are clocked */
408 GM_BIS(GM_TX_CONF, GM_TX_CONF_DMA_EN);
409 mdelay(20);
410 GM_BIS(GM_RX_CONF, GM_RX_CONF_DMA_EN);
411 mdelay(20);
412 GM_BIS(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
413 mdelay(20);
414 GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_ENABLE);
415 mdelay(20);
416 if (gm->phy_type == PHY_B5201 || gm->phy_type == PHY_B5221) {
417 data = mii_read(gm, gm->phy_addr, MII_BCM5201_MULTIPHY);
418 mii_write(gm, gm->phy_addr, MII_BCM5201_MULTIPHY,
419 data & ~MII_BCM5201_MULTIPHY_SUPERISOLATE);
420 }
421 mdelay(1);
422
423 if (gm->opened) {
424 /* restart polling PHY */
425 mii_interrupt(gm);
426 /* restart DMA operations */
427 gmac_start_dma(gm);
428 netif_device_attach(gm->dev);
429 enable_irq(gm->dev->irq);
430 } else {
431 /* Driver not opened, just leave things off. Note that
432 * we could be smart and superisolate the PHY when the
433 * driver is closed, but I won't do that unless I have
434 * a better understanding of some electrical issues with
435 * this PHY chip --BenH
436 */
437 GM_OUT(GM_MAC_RX_CONFIG, 0);
438 GM_OUT(GM_MAC_TX_CONFIG, 0);
439 GM_OUT(GM_MAC_XIF_CONFIG, 0);
440 GM_OUT(GM_TX_CONF, 0);
441 GM_OUT(GM_RX_CONF, 0);
442 }
443 }
444
445 static int
446 mii_do_reset_phy(struct gmac *gm, int phy_addr)
447 {
448 int mii_control, timeout;
449
450 mii_control = mii_read(gm, phy_addr, MII_CR);
451 mii_write(gm, phy_addr, MII_CR, mii_control | MII_CR_RST);
452 mdelay(10);
453 for (timeout = 100; timeout > 0; --timeout) {
454 mii_control = mii_read(gm, phy_addr, MII_CR);
455 if (mii_control == -1) {
456 printk(KERN_ERR "%s PHY died after reset !\n",
457 gm->dev->name);
458 return 1;
459 }
460 if ((mii_control & MII_CR_RST) == 0)
461 break;
462 mdelay(10);
463 }
464 if (mii_control & MII_CR_RST) {
465 printk(KERN_ERR "%s PHY reset timeout !\n", gm->dev->name);
466 return 1;
467 }
468 mii_write(gm, phy_addr, MII_CR, mii_control & ~MII_CR_ISOL);
469 return 0;
470 }
471
472 /* Here's a bunch of configuration routines for
473 * Broadcom PHYs used on various Mac models. Unfortunately,
474 * except for the 5201, Broadcom never sent me any documentation,
475 * so this is from my understanding of Apple's Open Firmware
476 * drivers and Darwin's implementation
477 */
478
479 static void
480 mii_init_BCM5400(struct gmac *gm)
481 {
482 int data;
483
484 /* Configure for gigabit full duplex */
485 data = mii_read(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL);
486 data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
487 mii_write(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL, data);
488
489 data = mii_read(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL);
490 data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
491 mii_write(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL, data);
492
493 mdelay(10);
494
495 /* Reset and configure cascaded 10/100 PHY */
496 mii_do_reset_phy(gm, 0x1f);
497
498 data = mii_read(gm, 0x1f, MII_BCM5201_MULTIPHY);
499 data |= MII_BCM5201_MULTIPHY_SERIALMODE;
500 mii_write(gm, 0x1f, MII_BCM5201_MULTIPHY, data);
501
502 data = mii_read(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL);
503 data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
504 mii_write(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL, data);
505 }
506
507 static void
508 mii_init_BCM5401(struct gmac *gm)
509 {
510 int data;
511 int rev;
512
513 rev = mii_read(gm, gm->phy_addr, MII_ID1) & 0x000f;
514 if (rev == 0 || rev == 3) {
515 /* Some revisions of 5401 appear to need this
516 * initialisation sequence to disable, according
517 * to OF, "tap power management"
518 *
519 * WARNING ! OF and Darwin don't agree on the
520 * register addresses. OF seem to interpret the
521 * register numbers below as decimal
522 */
523 mii_write(gm, gm->phy_addr, 0x18, 0x0c20);
524 mii_write(gm, gm->phy_addr, 0x17, 0x0012);
525 mii_write(gm, gm->phy_addr, 0x15, 0x1804);
526 mii_write(gm, gm->phy_addr, 0x17, 0x0013);
527 mii_write(gm, gm->phy_addr, 0x15, 0x1204);
528 mii_write(gm, gm->phy_addr, 0x17, 0x8006);
529 mii_write(gm, gm->phy_addr, 0x15, 0x0132);
530 mii_write(gm, gm->phy_addr, 0x17, 0x8006);
531 mii_write(gm, gm->phy_addr, 0x15, 0x0232);
532 mii_write(gm, gm->phy_addr, 0x17, 0x201f);
533 mii_write(gm, gm->phy_addr, 0x15, 0x0a20);
534 }
535
536 /* Configure for gigabit full duplex */
537 data = mii_read(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL);
538 data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
539 mii_write(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL, data);
540
541 mdelay(10);
542
543 /* Reset and configure cascaded 10/100 PHY */
544 mii_do_reset_phy(gm, 0x1f);
545
546 data = mii_read(gm, 0x1f, MII_BCM5201_MULTIPHY);
547 data |= MII_BCM5201_MULTIPHY_SERIALMODE;
548 mii_write(gm, 0x1f, MII_BCM5201_MULTIPHY, data);
549 }
550
551 static void
552 mii_init_BCM5411(struct gmac *gm)
553 {
554 int data;
555
556 /* Here's some more Apple black magic to setup
557 * some voltage stuffs.
558 */
559 mii_write(gm, gm->phy_addr, 0x1c, 0x8c23);
560 mii_write(gm, gm->phy_addr, 0x1c, 0x8ca3);
561 mii_write(gm, gm->phy_addr, 0x1c, 0x8c23);
562
563 /* Here, Apple seems to want to reset it, do
564 * it as well
565 */
566 mii_write(gm, gm->phy_addr, MII_CR, MII_CR_RST);
567
568 /* Start autoneg */
569 mii_write(gm, gm->phy_addr, MII_CR,
570 MII_CR_ASSE|MII_CR_FDM| /* Autospeed, full duplex */
571 MII_CR_RAN|
572 MII_CR_SPEEDSEL2 /* chip specific, gigabit enable ? */);
573
574 data = mii_read(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL);
575 data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
576 mii_write(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL, data);
577 }
578
579 static int
580 mii_lookup_and_reset(struct gmac *gm)
581 {
582 int i, mii_status, mii_control;
583
584 gm->phy_addr = -1;
585 gm->phy_type = PHY_UNKNOWN;
586
587 /* Hard reset the PHY */
588 feature_gmac_phy_reset(gm->of_node);
589
590 /* Find the PHY */
591 for(i=0; i<=31; i++) {
592 mii_control = mii_read(gm, i, MII_CR);
593 mii_status = mii_read(gm, i, MII_SR);
594 if (mii_control != -1 && mii_status != -1 &&
595 (mii_control != 0xffff || mii_status != 0xffff))
596 break;
597 }
598 gm->phy_addr = i;
599 if (gm->phy_addr > 31)
600 return 0;
601
602 /* Reset it */
603 if (mii_do_reset_phy(gm, gm->phy_addr))
604 goto fail;
605
606 /* Read the PHY ID */
607 gm->phy_id = (mii_read(gm, gm->phy_addr, MII_ID0) << 16) |
608 mii_read(gm, gm->phy_addr, MII_ID1);
609 #ifdef DEBUG_PHY
610 printk(KERN_INFO "%s: PHY ID: 0x%08x\n", gm->dev->name, gm->phy_id);
611 #endif
612 if ((gm->phy_id & MII_BCM5400_MASK) == MII_BCM5400_ID) {
613 gm->phy_type = PHY_B5400;
614 printk(KERN_INFO "%s: Found Broadcom BCM5400 PHY (Gigabit)\n",
615 gm->dev->name);
616 mii_init_BCM5400(gm);
617 } else if ((gm->phy_id & MII_BCM5401_MASK) == MII_BCM5401_ID) {
618 gm->phy_type = PHY_B5401;
619 printk(KERN_INFO "%s: Found Broadcom BCM5401 PHY (Gigabit)\n",
620 gm->dev->name);
621 mii_init_BCM5401(gm);
622 } else if ((gm->phy_id & MII_BCM5411_MASK) == MII_BCM5411_ID) {
623 gm->phy_type = PHY_B5411;
624 printk(KERN_INFO "%s: Found Broadcom BCM5411 PHY (Gigabit)\n",
625 gm->dev->name);
626 mii_init_BCM5411(gm);
627 } else if ((gm->phy_id & MII_BCM5201_MASK) == MII_BCM5201_ID) {
628 gm->phy_type = PHY_B5201;
629 printk(KERN_INFO "%s: Found Broadcom BCM5201 PHY\n", gm->dev->name);
630 } else if ((gm->phy_id & MII_BCM5221_MASK) == MII_BCM5221_ID) {
631 gm->phy_type = PHY_B5221;
632 printk(KERN_INFO "%s: Found Broadcom BCM5221 PHY\n", gm->dev->name);
633 } else if ((gm->phy_id & MII_LXT971_MASK) == MII_LXT971_ID) {
634 gm->phy_type = PHY_LXT971;
635 printk(KERN_INFO "%s: Found LevelOne LX971 PHY\n", gm->dev->name);
636 } else {
637 printk(KERN_WARNING "%s: Warning ! Unknown PHY ID 0x%08x, using generic mode...\n",
638 gm->dev->name, gm->phy_id);
639 }
640
641 return 1;
642
643 fail:
644 gm->phy_addr = -1;
645 return 0;
646 }
647
648 /*
649 * Setup the PHY autonegociation parameters
650 *
651 * Code to force the PHY duplex mode and speed should be
652 * added here
653 */
654 static void
655 mii_setup_phy(struct gmac *gm)
656 {
657 int data;
658
659 /* Stop auto-negociation */
660 data = mii_read(gm, gm->phy_addr, MII_CR);
661 mii_write(gm, gm->phy_addr, MII_CR, data & ~MII_CR_ASSE);
662
663 /* Set advertisement to 10/100 and Half/Full duplex
664 * (full capabilities) */
665 data = mii_read(gm, gm->phy_addr, MII_ANA);
666 data |= MII_ANA_TXAM | MII_ANA_FDAM | MII_ANA_10M;
667 mii_write(gm, gm->phy_addr, MII_ANA, data);
668
669 /* Restart auto-negociation */
670 data = mii_read(gm, gm->phy_addr, MII_CR);
671 data |= MII_CR_ASSE;
672 mii_write(gm, gm->phy_addr, MII_CR, data);
673 data |= MII_CR_RAN;
674 mii_write(gm, gm->phy_addr, MII_CR, data);
675 }
676
677 /*
678 * Turn On/Off the gmac cell inside Uni-N
679 *
680 * ToDo: Add code to support powering down of the PHY.
681 */
682 static void
683 gmac_set_power(struct gmac *gm, int power_up)
684 {
685 if (power_up) {
686 feature_set_gmac_power(gm->of_node, 1);
687 if (gm->pci_devfn != 0xff) {
688 u16 cmd;
689
690 /*
691 * Make sure PCI is correctly configured
692 *
693 * We use old pci_bios versions of the function since, by
694 * default, gmac is not powered up, and so will be absent
695 * from the kernel initial PCI lookup.
696 *
697 * Should be replaced by 2.4 new PCI mecanisms and really
698 * regiser the device.
699 */
700 pcibios_read_config_word(gm->pci_bus, gm->pci_devfn,
701 PCI_COMMAND, &cmd);
702 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
703 pcibios_write_config_word(gm->pci_bus, gm->pci_devfn,
704 PCI_COMMAND, cmd);
705 pcibios_write_config_byte(gm->pci_bus, gm->pci_devfn,
706 PCI_LATENCY_TIMER, 16);
707 pcibios_write_config_byte(gm->pci_bus, gm->pci_devfn,
708 PCI_CACHE_LINE_SIZE, 8);
709 }
710 } else {
711 feature_set_gmac_power(gm->of_node, 0);
712 }
713 }
714
715 /*
716 * Makes sure the GMAC cell is powered up, and reset it
717 */
718 static int
719 gmac_powerup_and_reset(struct net_device *dev)
720 {
721 struct gmac *gm = (struct gmac *) dev->priv;
722 int timeout;
723
724 /* turn on GB clock */
725 gmac_set_power(gm, 1);
726 /* Perform a software reset */
727 GM_OUT(GM_RESET, GM_RESET_TX | GM_RESET_RX);
728 for (timeout = 100; timeout > 0; --timeout) {
729 mdelay(10);
730 if ((GM_IN(GM_RESET) & (GM_RESET_TX | GM_RESET_RX)) == 0) {
731 /* Mask out all chips interrupts */
732 GM_OUT(GM_IRQ_MASK, 0xffffffff);
733 GM_OUT(GM_MAC_TX_RESET, GM_MAC_TX_RESET_NOW);
734 GM_OUT(GM_MAC_RX_RESET, GM_MAC_RX_RESET_NOW);
735 return 0;
736 }
737 }
738 printk(KERN_ERR "%s reset failed!\n", dev->name);
739 gmac_set_power(gm, 0);
740 gm->phy_type = 0;
741 return -1;
742 }
743
744 /*
745 * Set the MAC duplex mode.
746 *
747 * Side effect: stops Tx MAC
748 */
749 static void
750 gmac_set_duplex_mode(struct gmac *gm, int full_duplex)
751 {
752 /* Stop Tx MAC */
753 GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
754 while(GM_IN(GM_MAC_TX_CONFIG) & GM_MAC_TX_CONF_ENABLE)
755 ;
756
757 if (full_duplex) {
758 GM_BIS(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_IGNORE_CARRIER
759 | GM_MAC_TX_CONF_IGNORE_COLL);
760 GM_BIC(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_DISABLE_ECHO);
761 } else {
762 GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_IGNORE_CARRIER
763 | GM_MAC_TX_CONF_IGNORE_COLL);
764 GM_BIS(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_DISABLE_ECHO);
765 }
766 }
767
768 /* Set the MAC gigabit mode. Side effect: stops Tx MAC */
769 static void
770 gmac_set_gigabit_mode(struct gmac *gm, int gigabit)
771 {
772 /* Stop Tx MAC */
773 GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
774 while(GM_IN(GM_MAC_TX_CONFIG) & GM_MAC_TX_CONF_ENABLE)
775 ;
776
777 if (gigabit) {
778 GM_BIS(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_GMII_MODE);
779 } else {
780 GM_BIC(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_GMII_MODE);
781 }
782 }
783
784 /*
785 * Initialize a bunch of registers to put the chip into a known
786 * and hopefully happy state
787 */
788 static void
789 gmac_mac_init(struct gmac *gm, unsigned char *mac_addr)
790 {
791 int i, fifo_size;
792
793 /* Set random seed to low bits of MAC address */
794 GM_OUT(GM_MAC_RANDOM_SEED, mac_addr[5] | (mac_addr[4] << 8));
795
796 /* Configure the data path mode to MII/GII */
797 GM_OUT(GM_PCS_DATAPATH_MODE, GM_PCS_DATAPATH_MII);
798
799 /* Configure XIF to MII mode. Full duplex led is set
800 * by Apple, so...
801 */
802 GM_OUT(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_TX_MII_OUT_EN
803 | GM_MAC_XIF_CONF_FULL_DPLX_LED);
804
805 /* Mask out all MAC interrupts */
806 GM_OUT(GM_MAC_TX_MASK, 0xffff);
807 GM_OUT(GM_MAC_RX_MASK, 0xffff);
808 GM_OUT(GM_MAC_CTRLSTAT_MASK, 0xff);
809
810 /* Setup bits of MAC */
811 GM_OUT(GM_MAC_SND_PAUSE, GM_MAC_SND_PAUSE_DEFAULT);
812 GM_OUT(GM_MAC_CTRL_CONFIG, GM_MAC_CTRL_CONF_RCV_PAUSE_EN);
813
814 /* Configure GEM DMA */
815 GM_OUT(GM_GCONF, GM_GCONF_BURST_SZ |
816 (31 << GM_GCONF_TXDMA_LIMIT_SHIFT) |
817 (31 << GM_GCONF_RXDMA_LIMIT_SHIFT));
818 GM_OUT(GM_TX_CONF,
819 (GM_TX_CONF_FIFO_THR_DEFAULT << GM_TX_CONF_FIFO_THR_SHIFT) |
820 NTX_CONF);
821
822 /* 34 byte offset for checksum computation. This works because ip_input() will clear out
823 * the skb->csum and skb->ip_summed fields and recompute the csum if IP options are
824 * present in the header. 34 == (ethernet header len) + sizeof(struct iphdr)
825 */
826 GM_OUT(GM_RX_CONF,
827 (RX_OFFSET << GM_RX_CONF_FBYTE_OFF_SHIFT) |
828 (0x22 << GM_RX_CONF_CHK_START_SHIFT) |
829 (GM_RX_CONF_DMA_THR_DEFAULT << GM_RX_CONF_DMA_THR_SHIFT) |
830 NRX_CONF);
831
832 /* Configure other bits of MAC */
833 GM_OUT(GM_MAC_INTR_PKT_GAP0, GM_MAC_INTR_PKT_GAP0_DEFAULT);
834 GM_OUT(GM_MAC_INTR_PKT_GAP1, GM_MAC_INTR_PKT_GAP1_DEFAULT);
835 GM_OUT(GM_MAC_INTR_PKT_GAP2, GM_MAC_INTR_PKT_GAP2_DEFAULT);
836 GM_OUT(GM_MAC_MIN_FRAME_SIZE, GM_MAC_MIN_FRAME_SIZE_DEFAULT);
837 GM_OUT(GM_MAC_MAX_FRAME_SIZE, GM_MAC_MAX_FRAME_SIZE_DEFAULT);
838 GM_OUT(GM_MAC_PREAMBLE_LEN, GM_MAC_PREAMBLE_LEN_DEFAULT);
839 GM_OUT(GM_MAC_JAM_SIZE, GM_MAC_JAM_SIZE_DEFAULT);
840 GM_OUT(GM_MAC_ATTEMPT_LIMIT, GM_MAC_ATTEMPT_LIMIT_DEFAULT);
841 GM_OUT(GM_MAC_SLOT_TIME, GM_MAC_SLOT_TIME_DEFAULT);
842 GM_OUT(GM_MAC_CONTROL_TYPE, GM_MAC_CONTROL_TYPE_DEFAULT);
843
844 /* Setup MAC addresses, clear filters, clear hash table */
845 GM_OUT(GM_MAC_ADDR_NORMAL0, (mac_addr[4] << 8) + mac_addr[5]);
846 GM_OUT(GM_MAC_ADDR_NORMAL1, (mac_addr[2] << 8) + mac_addr[3]);
847 GM_OUT(GM_MAC_ADDR_NORMAL2, (mac_addr[0] << 8) + mac_addr[1]);
848 GM_OUT(GM_MAC_ADDR_ALT0, 0);
849 GM_OUT(GM_MAC_ADDR_ALT1, 0);
850 GM_OUT(GM_MAC_ADDR_ALT2, 0);
851 GM_OUT(GM_MAC_ADDR_CTRL0, 0x0001);
852 GM_OUT(GM_MAC_ADDR_CTRL1, 0xc200);
853 GM_OUT(GM_MAC_ADDR_CTRL2, 0x0180);
854 GM_OUT(GM_MAC_ADDR_FILTER0, 0);
855 GM_OUT(GM_MAC_ADDR_FILTER1, 0);
856 GM_OUT(GM_MAC_ADDR_FILTER2, 0);
857 GM_OUT(GM_MAC_ADDR_FILTER_MASK1_2, 0);
858 GM_OUT(GM_MAC_ADDR_FILTER_MASK0, 0);
859 for (i = 0; i < 27; ++i)
860 GM_OUT(GM_MAC_ADDR_FILTER_HASH0 + i, 0);
861
862 /* Clear stat counters */
863 GM_OUT(GM_MAC_COLLISION_CTR, 0);
864 GM_OUT(GM_MAC_FIRST_COLLISION_CTR, 0);
865 GM_OUT(GM_MAC_EXCS_COLLISION_CTR, 0);
866 GM_OUT(GM_MAC_LATE_COLLISION_CTR, 0);
867 GM_OUT(GM_MAC_DEFER_TIMER_COUNTER, 0);
868 GM_OUT(GM_MAC_PEAK_ATTEMPTS, 0);
869 GM_OUT(GM_MAC_RX_FRAME_CTR, 0);
870 GM_OUT(GM_MAC_RX_LEN_ERR_CTR, 0);
871 GM_OUT(GM_MAC_RX_ALIGN_ERR_CTR, 0);
872 GM_OUT(GM_MAC_RX_CRC_ERR_CTR, 0);
873 GM_OUT(GM_MAC_RX_CODE_VIOLATION_CTR, 0);
874
875 /* default to half duplex */
876 GM_OUT(GM_MAC_TX_CONFIG, 0);
877 GM_OUT(GM_MAC_RX_CONFIG, 0);
878 gmac_set_duplex_mode(gm, gm->full_duplex);
879
880 /* Setup pause thresholds */
881 fifo_size = GM_IN(GM_RX_FIFO_SIZE);
882 GM_OUT(GM_RX_PTH,
883 ((fifo_size - ((GM_MAC_MAX_FRAME_SIZE_ALIGN + 8) * 2 / GM_RX_PTH_UNITS))
884 << GM_RX_PTH_OFF_SHIFT) |
885 ((fifo_size - ((GM_MAC_MAX_FRAME_SIZE_ALIGN + 8) * 3 / GM_RX_PTH_UNITS))
886 << GM_RX_PTH_ON_SHIFT));
887
888 /* Setup interrupt blanking */
889 if (GM_IN(GM_BIF_CFG) & GM_BIF_CFG_M66EN)
890 GM_OUT(GM_RX_BLANK, (5 << GM_RX_BLANK_INTR_PACKETS_SHIFT)
891 | (8 << GM_RX_BLANK_INTR_TIME_SHIFT));
892 else
893 GM_OUT(GM_RX_BLANK, (5 << GM_RX_BLANK_INTR_PACKETS_SHIFT)
894 | (4 << GM_RX_BLANK_INTR_TIME_SHIFT));
895 }
896
897 /*
898 * Fill the Rx and Tx rings with good initial values, alloc
899 * fresh Rx skb's.
900 */
901 static void
902 gmac_init_rings(struct gmac *gm, int from_irq)
903 {
904 int i;
905 struct sk_buff *skb;
906 unsigned char *data;
907 struct gmac_dma_desc *ring;
908 int gfp_flags = GFP_KERNEL;
909
910 if (from_irq || in_interrupt())
911 gfp_flags = GFP_ATOMIC;
912
913 /* init rx ring */
914 ring = (struct gmac_dma_desc *) gm->rxring;
915 memset(ring, 0, NRX * sizeof(struct gmac_dma_desc));
916 for (i = 0; i < NRX; ++i, ++ring) {
917 data = dummy_buf;
918 gm->rx_buff[i] = skb = gmac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
919 if (skb != 0) {
920 skb->dev = gm->dev;
921 skb_put(skb, ETH_FRAME_LEN + RX_OFFSET);
922 skb_reserve(skb, RX_OFFSET);
923 data = skb->data - RX_OFFSET;
924 }
925 st_le32(&ring->lo_addr, virt_to_bus(data));
926 st_le32(&ring->size, RX_SZ_OWN | ((RX_BUF_ALLOC_SIZE-RX_OFFSET) << RX_SZ_SHIFT));
927 }
928
929 /* init tx ring */
930 ring = (struct gmac_dma_desc *) gm->txring;
931 memset(ring, 0, NTX * sizeof(struct gmac_dma_desc));
932
933 gm->next_rx = 0;
934 gm->next_tx = 0;
935 gm->tx_gone = 0;
936
937 /* set pointers in chip */
938 mb();
939 GM_OUT(GM_RX_DESC_HI, 0);
940 GM_OUT(GM_RX_DESC_LO, virt_to_bus(gm->rxring));
941 GM_OUT(GM_TX_DESC_HI, 0);
942 GM_OUT(GM_TX_DESC_LO, virt_to_bus(gm->txring));
943 }
944
945 /*
946 * Start the Tx and Rx DMA engines and enable interrupts
947 *
948 * Note: The various mdelay(20); come from Darwin implentation. Some
949 * tests (doc ?) are needed to replace those with something more intrusive.
950 */
951 static void
952 gmac_start_dma(struct gmac *gm)
953 {
954 /* Enable Tx and Rx */
955 GM_BIS(GM_TX_CONF, GM_TX_CONF_DMA_EN);
956 mdelay(20);
957 GM_BIS(GM_RX_CONF, GM_RX_CONF_DMA_EN);
958 mdelay(20);
959 GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_ENABLE);
960 mdelay(20);
961 GM_BIS(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
962 mdelay(20);
963 /* Kick the receiver and enable interrupts */
964 GM_OUT(GM_RX_KICK, NRX);
965 GM_BIC(GM_IRQ_MASK, GM_IRQ_TX_INT_ME |
966 GM_IRQ_TX_ALL |
967 GM_IRQ_RX_DONE |
968 GM_IRQ_RX_TAG_ERR |
969 GM_IRQ_MAC_RX |
970 GM_IRQ_MIF |
971 GM_IRQ_BUS_ERROR);
972 }
973
974 /*
975 * Stop the Tx and Rx DMA engines after disabling interrupts
976 *
977 * Note: The various mdelay(20); come from Darwin implentation. Some
978 * tests (doc ?) are needed to replace those with something more intrusive.
979 */
980 static void
981 gmac_stop_dma(struct gmac *gm)
982 {
983 /* disable interrupts */
984 GM_OUT(GM_IRQ_MASK, 0xffffffff);
985 /* Enable Tx and Rx */
986 GM_BIC(GM_TX_CONF, GM_TX_CONF_DMA_EN);
987 mdelay(20);
988 GM_BIC(GM_RX_CONF, GM_RX_CONF_DMA_EN);
989 mdelay(20);
990 GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_ENABLE);
991 mdelay(20);
992 GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
993 mdelay(20);
994 }
995
996 /*
997 * Configure promisc mode and setup multicast hash table
998 * filter
999 */
1000 #define CRC_POLY 0xedb88320
1001 static void
1002 gmac_set_multicast(struct net_device *dev)
1003 {
1004 struct gmac *gm = (struct gmac *) dev->priv;
1005 struct dev_mc_list *dmi = dev->mc_list;
1006 int i,j,k,b;
1007 unsigned long crc;
1008 int multicast_hash = 0;
1009 int multicast_all = 0;
1010 int promisc = 0;
1011
1012 if (gm->sleeping)
1013 return;
1014
1015 /* Lock out others. */
1016 netif_stop_queue(dev);
1017
1018
1019 if (dev->flags & IFF_PROMISC)
1020 promisc = 1;
1021 else if ((dev->flags & IFF_ALLMULTI) /* || (dev->mc_count > XXX) */) {
1022 multicast_all = 1;
1023 } else {
1024 u16 hash_table[16];
1025
1026 for(i = 0; i < 16; i++)
1027 hash_table[i] = 0;
1028
1029 for (i = 0; i < dev->mc_count; i++) {
1030 crc = ~0;
1031 for (j = 0; j < 6; ++j) {
1032 b = dmi->dmi_addr[j];
1033 for (k = 0; k < 8; ++k) {
1034 if ((crc ^ b) & 1)
1035 crc = (crc >> 1) ^ CRC_POLY;
1036 else
1037 crc >>= 1;
1038 b >>= 1;
1039 }
1040 }
1041 j = crc >> 24; /* bit number in multicast_filter */
1042 hash_table[j >> 4] |= 1 << (15 - (j & 0xf));
1043 dmi = dmi->next;
1044 }
1045
1046 for (i = 0; i < 16; i++)
1047 GM_OUT(GM_MAC_ADDR_FILTER_HASH0 + (i*4), hash_table[i]);
1048 GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_HASH_ENABLE);
1049 multicast_hash = 1;
1050 }
1051
1052 if (promisc)
1053 GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL);
1054 else
1055 GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL);
1056
1057 if (multicast_hash)
1058 GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_HASH_ENABLE);
1059 else
1060 GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_HASH_ENABLE);
1061
1062 if (multicast_all)
1063 GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL_MULTI);
1064 else
1065 GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL_MULTI);
1066
1067 /* Let us get going again. */
1068 netif_wake_queue(dev);
1069 }
1070
1071 /*
1072 * Open the interface
1073 */
1074 static int
1075 gmac_open(struct net_device *dev)
1076 {
1077 int ret;
1078 struct gmac *gm = (struct gmac *) dev->priv;
1079
1080 /* Power up and reset chip */
1081 if (gmac_powerup_and_reset(dev))
1082 return -EIO;
1083
1084 /* Get our interrupt */
1085 ret = request_irq(dev->irq, gmac_interrupt, 0, dev->name, dev);
1086 if (ret) {
1087 printk(KERN_ERR "%s can't get irq %d\n", dev->name, dev->irq);
1088 return ret;
1089 }
1090
1091 gm->full_duplex = 0;
1092 gm->phy_status = 0;
1093
1094 /* Find a PHY */
1095 if (!mii_lookup_and_reset(gm))
1096 printk(KERN_WARNING "%s WARNING ! Can't find PHY\n", dev->name);
1097
1098 /* Configure the PHY */
1099 mii_setup_phy(gm);
1100
1101 /* Initialize the descriptor rings */
1102 gmac_init_rings(gm, 0);
1103
1104 /* Initialize the MAC */
1105 gmac_mac_init(gm, dev->dev_addr);
1106
1107 /* Initialize the multicast tables & promisc mode if any */
1108 gmac_set_multicast(dev);
1109
1110 /*
1111 * Check out PHY status and start auto-poll
1112 *
1113 * Note: do this before enabling interrutps
1114 */
1115 mii_interrupt(gm);
1116
1117 /* Start the chip */
1118 gmac_start_dma(gm);
1119
1120 gm->opened = 1;
1121
1122 return 0;
1123 }
1124
1125 /*
1126 * Close the interface
1127 */
1128 static int
1129 gmac_close(struct net_device *dev)
1130 {
1131 struct gmac *gm = (struct gmac *) dev->priv;
1132 int i;
1133
1134 gm->opened = 0;
1135
1136 /* Stop chip and interrupts */
1137 gmac_stop_dma(gm);
1138
1139 /* Stop polling PHY */
1140 mii_poll_stop(gm);
1141
1142 /* Free interrupt */
1143 free_irq(dev->irq, dev);
1144
1145 /* Shut down chip */
1146 gmac_set_power(gm, 0);
1147 gm->phy_type = 0;
1148
1149 /* Empty rings of any remaining gremlins */
1150 for (i = 0; i < NRX; ++i) {
1151 if (gm->rx_buff[i] != 0) {
1152 dev_kfree_skb(gm->rx_buff[i]);
1153 gm->rx_buff[i] = 0;
1154 }
1155 }
1156 for (i = 0; i < NTX; ++i) {
1157 if (gm->tx_buff[i] != 0) {
1158 dev_kfree_skb(gm->tx_buff[i]);
1159 gm->tx_buff[i] = 0;
1160 }
1161 }
1162
1163 return 0;
1164 }
1165
1166 #ifdef CONFIG_PMAC_PBOOK
1167 int
1168 gmac_sleep_notify(struct pmu_sleep_notifier *self, int when)
1169 {
1170 struct gmac *gm;
1171
1172 /* XXX should handle more than one */
1173 if (gmacs == NULL)
1174 return PBOOK_SLEEP_OK;
1175
1176 gm = (struct gmac *) gmacs->priv;
1177 if (!gm->opened)
1178 return PBOOK_SLEEP_OK;
1179
1180 switch (when) {
1181 case PBOOK_SLEEP_REQUEST:
1182 break;
1183 case PBOOK_SLEEP_REJECT:
1184 break;
1185 case PBOOK_SLEEP_NOW:
1186 gmac_suspend(gm);
1187 break;
1188 case PBOOK_WAKE:
1189 gmac_resume(gm);
1190 break;
1191 }
1192 return PBOOK_SLEEP_OK;
1193 }
1194 #endif /* CONFIG_PMAC_PBOOK */
1195
1196 /*
1197 * Handle a transmit timeout
1198 */
1199 static void
1200 gmac_tx_timeout(struct net_device *dev)
1201 {
1202 struct gmac *gm = (struct gmac *) dev->priv;
1203 int i, timeout;
1204 unsigned long flags;
1205
1206 if (gm->sleeping)
1207 return;
1208
1209 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1210
1211 spin_lock_irqsave(&gm->lock, flags);
1212
1213 /* Stop chip */
1214 gmac_stop_dma(gm);
1215 /* Empty Tx ring of any remaining gremlins */
1216 gmac_tx_cleanup(dev, 1);
1217 /* Empty Rx ring of any remaining gremlins */
1218 for (i = 0; i < NRX; ++i) {
1219 if (gm->rx_buff[i] != 0) {
1220 dev_kfree_skb_irq(gm->rx_buff[i]);
1221 gm->rx_buff[i] = 0;
1222 }
1223 }
1224 /* Perform a software reset */
1225 GM_OUT(GM_RESET, GM_RESET_TX | GM_RESET_RX);
1226 for (timeout = 100; timeout > 0; --timeout) {
1227 mdelay(10);
1228 if ((GM_IN(GM_RESET) & (GM_RESET_TX | GM_RESET_RX)) == 0) {
1229 /* Mask out all chips interrupts */
1230 GM_OUT(GM_IRQ_MASK, 0xffffffff);
1231 GM_OUT(GM_MAC_TX_RESET, GM_MAC_TX_RESET_NOW);
1232 GM_OUT(GM_MAC_RX_RESET, GM_MAC_RX_RESET_NOW);
1233 break;
1234 }
1235 }
1236 if (!timeout)
1237 printk(KERN_ERR "%s reset chip failed !\n", dev->name);
1238 /* Create fresh rings */
1239 gmac_init_rings(gm, 1);
1240 /* re-initialize the MAC */
1241 gmac_mac_init(gm, dev->dev_addr);
1242 /* re-initialize the multicast tables & promisc mode if any */
1243 gmac_set_multicast(dev);
1244 /* Restart PHY auto-poll */
1245 mii_interrupt(gm);
1246 /* Restart chip */
1247 gmac_start_dma(gm);
1248
1249 spin_unlock_irqrestore(&gm->lock, flags);
1250
1251 netif_wake_queue(dev);
1252 }
1253
1254 /*
1255 * Add a packet to the transmit ring
1256 */
1257 static int
1258 gmac_xmit_start(struct sk_buff *skb, struct net_device *dev)
1259 {
1260 struct gmac *gm = (struct gmac *) dev->priv;
1261 volatile struct gmac_dma_desc *dp;
1262 unsigned long flags;
1263 int i;
1264
1265 if (gm->sleeping)
1266 return 1;
1267
1268 spin_lock_irqsave(&gm->lock, flags);
1269
1270 i = gm->next_tx;
1271 if (gm->tx_buff[i] != 0) {
1272 /*
1273 * Buffer is full, can't send this packet at the moment
1274 *
1275 * Can this ever happen in 2.4 ?
1276 */
1277 netif_stop_queue(dev);
1278 spin_unlock_irqrestore(&gm->lock, flags);
1279 return 1;
1280 }
1281 gm->next_tx = (i + 1) & (NTX - 1);
1282 gm->tx_buff[i] = skb;
1283
1284 dp = &gm->txring[i];
1285 /* FIXME: Interrupt on all packet for now, change this to every N packet,
1286 * with N to be adjusted
1287 */
1288 dp->flags = TX_FL_INTERRUPT;
1289 dp->hi_addr = 0;
1290 st_le32(&dp->lo_addr, virt_to_bus(skb->data));
1291 mb();
1292 st_le32(&dp->size, TX_SZ_SOP | TX_SZ_EOP | skb->len);
1293 mb();
1294
1295 GM_OUT(GM_TX_KICK, gm->next_tx);
1296
1297 if (gm->tx_buff[gm->next_tx] != 0)
1298 netif_stop_queue(dev);
1299
1300 spin_unlock_irqrestore(&gm->lock, flags);
1301
1302 dev->trans_start = jiffies;
1303
1304 return 0;
1305 }
1306
1307 /*
1308 * Handle servicing of the transmit ring by deallocating used
1309 * Tx packets and restoring flow control when necessary
1310 */
1311 static void
1312 gmac_tx_cleanup(struct net_device *dev, int force_cleanup)
1313 {
1314 struct gmac *gm = (struct gmac *) dev->priv;
1315 volatile struct gmac_dma_desc *dp;
1316 struct sk_buff *skb;
1317 int gone, i;
1318
1319 i = gm->tx_gone;
1320
1321 /* Note: If i==gone, we empty the entire ring. This works because
1322 * if the ring was empty, we wouldn't have received the interrupt
1323 */
1324 do {
1325 gone = GM_IN(GM_TX_COMP);
1326 skb = gm->tx_buff[i];
1327 if (skb == NULL)
1328 break;
1329 dp = &gm->txring[i];
1330 if (force_cleanup)
1331 ++gm->stats.tx_errors;
1332 else {
1333 ++gm->stats.tx_packets;
1334 gm->stats.tx_bytes += skb->len;
1335 }
1336 gm->tx_buff[i] = NULL;
1337 dev_kfree_skb_irq(skb);
1338 if (++i >= NTX)
1339 i = 0;
1340 } while (force_cleanup || i != gone);
1341 gm->tx_gone = i;
1342
1343 if (!force_cleanup && netif_queue_stopped(dev) &&
1344 (gm->tx_buff[gm->next_tx] == 0))
1345 netif_wake_queue(dev);
1346 }
1347
1348 /*
1349 * Handle servicing of receive ring
1350 */
1351 static void
1352 gmac_receive(struct net_device *dev)
1353 {
1354 struct gmac *gm = (struct gmac *) dev->priv;
1355 int i = gm->next_rx;
1356 volatile struct gmac_dma_desc *dp;
1357 struct sk_buff *skb, *new_skb;
1358 int len, flags, drop, last;
1359 unsigned char *data;
1360 u16 csum;
1361
1362 last = -1;
1363 for (;;) {
1364 dp = &gm->rxring[i];
1365 /* Buffer not yet filled, no more Rx buffers to handle */
1366 if (ld_le32(&dp->size) & RX_SZ_OWN)
1367 break;
1368 /* Get packet length, flags, etc... */
1369 len = (ld_le32(&dp->size) >> 16) & 0x7fff;
1370 flags = ld_le32(&dp->flags);
1371 skb = gm->rx_buff[i];
1372 drop = 0;
1373 new_skb = NULL;
1374 csum = ld_le32(&dp->size) & RX_SZ_CKSUM_MASK;
1375
1376 /* Handle errors */
1377 if ((len < ETH_ZLEN)||(flags & RX_FL_CRC_ERROR)||(!skb)) {
1378 ++gm->stats.rx_errors;
1379 if (len < ETH_ZLEN)
1380 ++gm->stats.rx_length_errors;
1381 if (flags & RX_FL_CRC_ERROR)
1382 ++gm->stats.rx_crc_errors;
1383 if (!skb) {
1384 ++gm->stats.rx_dropped;
1385 skb = gmac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1386 if (skb) {
1387 gm->rx_buff[i] = skb;
1388 skb->dev = dev;
1389 skb_put(skb, ETH_FRAME_LEN + RX_OFFSET);
1390 skb_reserve(skb, RX_OFFSET);
1391 }
1392 }
1393 drop = 1;
1394 } else {
1395 /* Large packet, alloc a new skb for the ring */
1396 if (len > RX_COPY_THRESHOLD) {
1397 new_skb = gmac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1398 if(!new_skb) {
1399 printk(KERN_INFO "%s: Out of SKBs in Rx, packet dropped !\n",
1400 dev->name);
1401 drop = 1;
1402 ++gm->stats.rx_dropped;
1403 goto finish;
1404 }
1405
1406 gm->rx_buff[i] = new_skb;
1407 new_skb->dev = dev;
1408 skb_put(new_skb, ETH_FRAME_LEN + RX_OFFSET);
1409 skb_reserve(new_skb, RX_OFFSET);
1410 skb_trim(skb, len);
1411 } else {
1412 /* Small packet, copy it to a new small skb */
1413 struct sk_buff *copy_skb = dev_alloc_skb(len + RX_OFFSET);
1414
1415 if(!copy_skb) {
1416 printk(KERN_INFO "%s: Out of SKBs in Rx, packet dropped !\n",
1417 dev->name);
1418 drop = 1;
1419 ++gm->stats.rx_dropped;
1420 goto finish;
1421 }
1422
1423 copy_skb->dev = dev;
1424 skb_reserve(copy_skb, RX_OFFSET);
1425 skb_put(copy_skb, len);
1426 memcpy(copy_skb->data, skb->data, len);
1427
1428 new_skb = skb;
1429 skb = copy_skb;
1430 }
1431 }
1432 finish:
1433 /* Need to drop packet ? */
1434 if (drop) {
1435 new_skb = skb;
1436 skb = NULL;
1437 }
1438
1439 /* Put back ring entry */
1440 data = new_skb ? (new_skb->data - RX_OFFSET) : dummy_buf;
1441 dp->hi_addr = 0;
1442 st_le32(&dp->lo_addr, virt_to_bus(data));
1443 mb();
1444 st_le32(&dp->size, RX_SZ_OWN | ((RX_BUF_ALLOC_SIZE-RX_OFFSET) << RX_SZ_SHIFT));
1445
1446 /* Got Rx packet ? */
1447 if (skb) {
1448 /* Yes, baby, keep that hot ;) */
1449 if(!(csum ^ 0xffff))
1450 skb->ip_summed = CHECKSUM_UNNECESSARY;
1451 else
1452 skb->ip_summed = CHECKSUM_NONE;
1453 skb->ip_summed = CHECKSUM_NONE;
1454 skb->protocol = eth_type_trans(skb, dev);
1455 gm->stats.rx_bytes += skb->len;
1456 netif_rx(skb);
1457 dev->last_rx = jiffies;
1458 ++gm->stats.rx_packets;
1459 }
1460
1461 last = i;
1462 if (++i >= NRX)
1463 i = 0;
1464 }
1465 gm->next_rx = i;
1466 if (last >= 0) {
1467 mb();
1468 GM_OUT(GM_RX_KICK, last & 0xfffffffc);
1469 }
1470 }
1471
1472 /*
1473 * Service chip interrupts
1474 */
1475 static void
1476 gmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1477 {
1478 struct net_device *dev = (struct net_device *) dev_id;
1479 struct gmac *gm = (struct gmac *) dev->priv;
1480 unsigned int status;
1481
1482 status = GM_IN(GM_IRQ_STATUS);
1483 if (status & (GM_IRQ_BUS_ERROR | GM_IRQ_MIF))
1484 GM_OUT(GM_IRQ_ACK, status & (GM_IRQ_BUS_ERROR | GM_IRQ_MIF));
1485
1486 if (status & (GM_IRQ_RX_TAG_ERR | GM_IRQ_BUS_ERROR)) {
1487 printk(KERN_ERR "%s: IRQ Error status: 0x%08x\n",
1488 dev->name, status);
1489 }
1490
1491 if (status & GM_IRQ_MIF) {
1492 spin_lock(&gm->lock);
1493 mii_interrupt(gm);
1494 spin_unlock(&gm->lock);
1495 }
1496
1497 if (status & GM_IRQ_RX_DONE) {
1498 spin_lock(&gm->lock);
1499 gmac_receive(dev);
1500 spin_unlock(&gm->lock);
1501 }
1502
1503 if (status & (GM_IRQ_TX_INT_ME | GM_IRQ_TX_ALL)) {
1504 spin_lock(&gm->lock);
1505 gmac_tx_cleanup(dev, 0);
1506 spin_unlock(&gm->lock);
1507 }
1508 }
1509
1510 /*
1511 * Retreive some error stats from chip and return them
1512 * to above layer
1513 */
1514 static struct net_device_stats *
1515 gmac_stats(struct net_device *dev)
1516 {
1517 struct gmac *gm = (struct gmac *) dev->priv;
1518 struct net_device_stats *stats = &gm->stats;
1519
1520 if (gm && gm->opened && !gm->sleeping) {
1521 stats->rx_crc_errors += GM_IN(GM_MAC_RX_CRC_ERR_CTR);
1522 GM_OUT(GM_MAC_RX_CRC_ERR_CTR, 0);
1523
1524 stats->rx_frame_errors += GM_IN(GM_MAC_RX_ALIGN_ERR_CTR);
1525 GM_OUT(GM_MAC_RX_ALIGN_ERR_CTR, 0);
1526
1527 stats->rx_length_errors += GM_IN(GM_MAC_RX_LEN_ERR_CTR);
1528 GM_OUT(GM_MAC_RX_LEN_ERR_CTR, 0);
1529
1530 stats->tx_aborted_errors += GM_IN(GM_MAC_EXCS_COLLISION_CTR);
1531
1532 stats->collisions +=
1533 (GM_IN(GM_MAC_EXCS_COLLISION_CTR) +
1534 GM_IN(GM_MAC_LATE_COLLISION_CTR));
1535 GM_OUT(GM_MAC_EXCS_COLLISION_CTR, 0);
1536 GM_OUT(GM_MAC_LATE_COLLISION_CTR, 0);
1537 }
1538
1539 return stats;
1540 }
1541
1542 static int __init
1543 gmac_probe(void)
1544 {
1545 struct device_node *gmac;
1546
1547 /* We bump use count during probe since get_free_page can sleep
1548 * which can be a race condition if module is unloaded at this
1549 * point.
1550 */
1551 MOD_INC_USE_COUNT;
1552
1553 /*
1554 * We don't use PCI scanning on pmac since the GMAC cell is disabled
1555 * by default, and thus absent from kernel original PCI probing.
1556 */
1557 for (gmac = find_compatible_devices("network", "gmac"); gmac != 0;
1558 gmac = gmac->next)
1559 gmac_probe1(gmac);
1560
1561 #ifdef CONFIG_PMAC_PBOOK
1562 if (gmacs)
1563 pmu_register_sleep_notifier(&gmac_sleep_notifier);
1564 #endif
1565
1566 MOD_DEC_USE_COUNT;
1567
1568 return gmacs? 0: -ENODEV;
1569 }
1570
1571 static void
1572 gmac_probe1(struct device_node *gmac)
1573 {
1574 struct gmac *gm;
1575 unsigned long tx_descpage, rx_descpage;
1576 unsigned char *addr;
1577 struct net_device *dev;
1578 int i;
1579
1580 if (gmac->n_addrs < 1 || gmac->n_intrs < 1) {
1581 printk(KERN_ERR "can't use GMAC %s: %d addrs and %d intrs\n",
1582 gmac->full_name, gmac->n_addrs, gmac->n_intrs);
1583 return;
1584 }
1585
1586 addr = get_property(gmac, "local-mac-address", NULL);
1587 if (addr == NULL) {
1588 printk(KERN_ERR "Can't get mac-address for GMAC %s\n",
1589 gmac->full_name);
1590 return;
1591 }
1592
1593 if (dummy_buf == NULL) {
1594 dummy_buf = kmalloc(DUMMY_BUF_LEN, GFP_KERNEL);
1595 if (dummy_buf == NULL) {
1596 printk(KERN_ERR "GMAC: failed to allocated dummy buffer\n");
1597 return;
1598 }
1599 }
1600
1601 tx_descpage = get_free_page(GFP_KERNEL);
1602 if (tx_descpage == 0) {
1603 printk(KERN_ERR "GMAC: can't get a page for tx descriptors\n");
1604 return;
1605 }
1606 rx_descpage = get_free_page(GFP_KERNEL);
1607 if (rx_descpage == 0) {
1608 printk(KERN_ERR "GMAC: can't get a page for rx descriptors\n");
1609 goto out_txdesc;
1610 }
1611
1612 dev = init_etherdev(NULL, sizeof(struct gmac));
1613 if (!dev) {
1614 printk(KERN_ERR "GMAC: init_etherdev failed, out of memory\n");
1615 goto out_rxdesc;
1616 }
1617 SET_MODULE_OWNER(dev);
1618
1619 gm = dev->priv;
1620 dev->base_addr = gmac->addrs[0].address;
1621 gm->regs = (volatile unsigned int *)
1622 ioremap(gmac->addrs[0].address, 0x10000);
1623 if (!gm->regs) {
1624 printk(KERN_ERR "GMAC: unable to map I/O registers\n");
1625 goto out_unreg;
1626 }
1627 dev->irq = gmac->intrs[0].line;
1628 gm->dev = dev;
1629 gm->of_node = gmac;
1630
1631 spin_lock_init(&gm->lock);
1632
1633 if (pci_device_from_OF_node(gmac, &gm->pci_bus, &gm->pci_devfn)) {
1634 gm->pci_bus = gm->pci_devfn = 0xff;
1635 printk(KERN_ERR "Can't locate GMAC PCI entry\n");
1636 }
1637
1638 printk(KERN_INFO "%s: GMAC at", dev->name);
1639 for (i = 0; i < 6; ++i) {
1640 dev->dev_addr[i] = addr[i];
1641 printk("%c%.2x", (i? ':': ' '), addr[i]);
1642 }
1643 printk(", driver " GMAC_VERSION "\n");
1644
1645 gm->tx_desc_page = tx_descpage;
1646 gm->rx_desc_page = rx_descpage;
1647 gm->rxring = (volatile struct gmac_dma_desc *) rx_descpage;
1648 gm->txring = (volatile struct gmac_dma_desc *) tx_descpage;
1649
1650 gm->phy_addr = 0;
1651 gm->opened = 0;
1652 gm->sleeping = 0;
1653
1654 dev->open = gmac_open;
1655 dev->stop = gmac_close;
1656 dev->hard_start_xmit = gmac_xmit_start;
1657 dev->get_stats = gmac_stats;
1658 dev->set_multicast_list = &gmac_set_multicast;
1659 dev->tx_timeout = &gmac_tx_timeout;
1660 dev->watchdog_timeo = 5*HZ;
1661
1662 ether_setup(dev);
1663
1664 gm->next_gmac = gmacs;
1665 gmacs = dev;
1666 return;
1667
1668 out_unreg:
1669 unregister_netdev(dev);
1670 kfree(dev);
1671 out_rxdesc:
1672 free_page(rx_descpage);
1673 out_txdesc:
1674 free_page(tx_descpage);
1675 }
1676
1677 MODULE_AUTHOR("Paul Mackerras/Ben Herrenschmidt");
1678 MODULE_DESCRIPTION("PowerMac GMAC driver.");
1679
1680 static void __exit gmac_cleanup_module(void)
1681 {
1682 struct gmac *gm;
1683 struct net_device *dev;
1684
1685 #ifdef CONFIG_PMAC_PBOOK
1686 if (gmacs)
1687 pmu_unregister_sleep_notifier(&gmac_sleep_notifier);
1688 #endif
1689
1690 while ((dev = gmacs) != NULL) {
1691 gm = (struct gmac *) dev->priv;
1692 unregister_netdev(dev);
1693 iounmap((void *) gm->regs);
1694 free_page(gm->tx_desc_page);
1695 free_page(gm->rx_desc_page);
1696 gmacs = gm->next_gmac;
1697 kfree(dev);
1698 }
1699 if (dummy_buf != NULL) {
1700 kfree(dummy_buf);
1701 dummy_buf = NULL;
1702 }
1703 }
1704
1705 module_init(gmac_probe);
1706 module_exit(gmac_cleanup_module);
1707