File: /usr/src/linux/drivers/net/gt96100eth.h
1 /*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * Ethernet driver definitions for the MIPS GT96100 Advanced
24 * Communication Controller.
25 *
26 */
27 #ifndef _GT96100ETH_H
28 #define _GT96100ETH_H
29
30 #include <asm/galileo-boards/gt96100.h>
31
32 /* Keep the ring sizes a power of two for efficiency. */
33 #define TX_RING_SIZE 16
34 #define RX_RING_SIZE 32
35 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
36
37 #define RX_HASH_TABLE_SIZE 16384
38 #define HASH_HOP_NUMBER 12
39
40 #define NUM_INTERFACES 2
41
42 #define GT96100ETH_TX_TIMEOUT HZ
43
44 #define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG)
45 #define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE)
46
47 #ifdef CONFIG_MIPS_EV96100
48 #define GT96100_ETHER0_IRQ 4
49 #define GT96100_ETHER1_IRQ 4
50 #else
51 #define GT96100_ETHER0_IRQ -1
52 #define GT96100_ETHER1_IRQ -1
53 #endif
54
55 #define GT96100ETH_READ(gp, offset) \
56 GT96100_READ((gp->port_offset + offset))
57
58 #define GT96100ETH_WRITE(gp, offset, data) \
59 GT96100_WRITE((gp->port_offset + offset), data)
60
61 #define GT96100ETH_SETBIT(gp, offset, bits) {\
62 u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \
63 GT96100ETH_WRITE(gp, offset, val); }
64
65 #define GT96100ETH_CLRBIT(gp, offset, bits) {\
66 u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \
67 GT96100ETH_WRITE(gp, offset, val); }
68
69
70 /* Bit definitions of the SMI Reg */
71 enum {
72 smirDataMask = 0xffff,
73 smirPhyAdMask = 0x1f << 16,
74 smirPhyAdBit = 16,
75 smirRegAdMask = 0x1f << 21,
76 smirRegAdBit = 21,
77 smirOpCode = 1 << 26,
78 smirReadValid = 1 << 27,
79 smirBusy = 1 << 28
80 };
81
82 /* Bit definitions of the Port Config Reg */
83 enum pcr_bits {
84 pcrPM = 1,
85 pcrRBM = 2,
86 pcrPBF = 4,
87 pcrEN = 1 << 7,
88 pcrLPBKMask = 0x3 << 8,
89 pcrLPBKBit = 8,
90 pcrFC = 1 << 10,
91 pcrHS = 1 << 12,
92 pcrHM = 1 << 13,
93 pcrHDM = 1 << 14,
94 pcrHD = 1 << 15,
95 pcrISLMask = 0x7 << 28,
96 pcrISLBit = 28,
97 pcrACCS = 1 << 31
98 };
99
100 /* Bit definitions of the Port Config Extend Reg */
101 enum pcxr_bits {
102 pcxrIGMP = 1,
103 pcxrSPAN = 2,
104 pcxrPAR = 4,
105 pcxrPRIOtxMask = 0x7 << 3,
106 pcxrPRIOtxBit = 3,
107 pcxrPRIOrxMask = 0x3 << 6,
108 pcxrPRIOrxBit = 6,
109 pcxrPRIOrxOverride = 1 << 8,
110 pcxrDPLXen = 1 << 9,
111 pcxrFCTLen = 1 << 10,
112 pcxrFLP = 1 << 11,
113 pcxrFCTL = 1 << 12,
114 pcxrMFLMask = 0x3 << 14,
115 pcxrMFLBit = 14,
116 pcxrMIBclrMode = 1 << 16,
117 pcxrSpeed = 1 << 18,
118 pcxrSpeeden = 1 << 19,
119 pcxrRMIIen = 1 << 20,
120 pcxrDSCPen = 1 << 21
121 };
122
123 /* Bit definitions of the Port Command Reg */
124 enum pcmr_bits {
125 pcmrFJ = 1 << 15
126 };
127
128
129 /* Bit definitions of the Port Status Reg */
130 enum psr_bits {
131 psrSpeed = 1,
132 psrDuplex = 2,
133 psrFctl = 4,
134 psrLink = 8,
135 psrPause = 1 << 4,
136 psrTxLow = 1 << 5,
137 psrTxHigh = 1 << 6,
138 psrTxInProg = 1 << 7
139 };
140
141 /* Bit definitions of the SDMA Config Reg */
142 enum sdcr_bits {
143 sdcrRCMask = 0xf << 2,
144 sdcrRCBit = 2,
145 sdcrBLMR = 1 << 6,
146 sdcrBLMT = 1 << 7,
147 sdcrPOVR = 1 << 8,
148 sdcrRIFB = 1 << 9,
149 sdcrBSZMask = 0x3 << 12,
150 sdcrBSZBit = 12
151 };
152
153 /* Bit definitions of the SDMA Command Reg */
154 enum sdcmr_bits {
155 sdcmrERD = 1 << 7,
156 sdcmrAR = 1 << 15,
157 sdcmrSTDH = 1 << 16,
158 sdcmrSTDL = 1 << 17,
159 sdcmrTXDH = 1 << 23,
160 sdcmrTXDL = 1 << 24,
161 sdcmrAT = 1 << 31
162 };
163
164 /* Bit definitions of the Interrupt Cause Reg */
165 enum icr_bits {
166 icrRxBuffer = 1,
167 icrTxBufferHigh = 1 << 2,
168 icrTxBufferLow = 1 << 3,
169 icrTxEndHigh = 1 << 6,
170 icrTxEndLow = 1 << 7,
171 icrRxError = 1 << 8,
172 icrTxErrorHigh = 1 << 10,
173 icrTxErrorLow = 1 << 11,
174 icrRxOVR = 1 << 12,
175 icrTxUdr = 1 << 13,
176 icrRxBufferQ0 = 1 << 16,
177 icrRxBufferQ1 = 1 << 17,
178 icrRxBufferQ2 = 1 << 18,
179 icrRxBufferQ3 = 1 << 19,
180 icrRxErrorQ0 = 1 << 20,
181 icrRxErrorQ1 = 1 << 21,
182 icrRxErrorQ2 = 1 << 22,
183 icrRxErrorQ3 = 1 << 23,
184 icrMIIPhySTC = 1 << 28,
185 icrSMIdone = 1 << 29,
186 icrEtherIntSum = 1 << 31
187 };
188
189
190 /* The Rx and Tx descriptor lists. */
191
192 typedef struct {
193 u32 cmdstat;
194 u32 byte_cnt;
195 u32 buff_ptr;
196 u32 next;
197 } gt96100_td_t;
198
199 #define tdByteCntBit 16
200
201 typedef struct {
202 u32 cmdstat;
203 u32 buff_cnt_sz;
204 u32 buff_ptr;
205 u32 next;
206 } gt96100_rd_t;
207
208 #define rdBuffSzBit 16
209 #define rdByteCntMask 0xffff
210
211
212 /* Values for the Tx command-status descriptor entry. */
213 enum td_cmdstat {
214 txOwn = 1 << 31,
215 txAutoMode = 1 << 30,
216 txEI = 1 << 23,
217 txGenCRC = 1 << 22,
218 txPad = 1 << 18,
219 txFirst = 1 << 17,
220 txLast = 1 << 16,
221 txErrorSummary = 1 << 15,
222 txReTxCntMask = 0x0f << 10,
223 txReTxCntBit = 10,
224 txCollision = 1 << 9,
225 txReTxLimit = 1 << 8,
226 txUnderrun = 1 << 6,
227 txLateCollision = 1 << 5
228 };
229
230 #define TxReTxCntBit 10
231
232 /* Values for the Rx command-status descriptor entry. */
233 enum rd_cmdstat {
234 rxOwn = 1 << 31,
235 rxAutoMode = 1 << 30,
236 rxEI = 1 << 23,
237 rxFirst = 1 << 17,
238 rxLast = 1 << 16,
239 rxErrorSummary = 1 << 15,
240 rxIGMP = 1 << 14,
241 rxHashExpired = 1 << 13,
242 rxMissedFrame = 1 << 12,
243 rxFrameType = 1 << 11,
244 rxShortFrame = 1 << 8,
245 rxMaxFrameLen = 1 << 7,
246 rxOverrun = 1 << 6,
247 rxCollision = 1 << 4,
248 rxCRCError = 1
249 };
250
251 /* Bit fields of a Hash Table Entry */
252 enum hash_table_entry {
253 hteValid = 1,
254 hteSkip = 2,
255 hteRD = 4
256 };
257
258 // The MIB counters
259 typedef struct {
260 u32 byteReceived;
261 u32 byteSent;
262 u32 framesReceived;
263 u32 framesSent;
264 u32 totalByteReceived;
265 u32 totalFramesReceived;
266 u32 broadcastFramesReceived;
267 u32 multicastFramesReceived;
268 u32 cRCError;
269 u32 oversizeFrames;
270 u32 fragments;
271 u32 jabber;
272 u32 collision;
273 u32 lateCollision;
274 u32 frames64;
275 u32 frames65_127;
276 u32 frames128_255;
277 u32 frames256_511;
278 u32 frames512_1023;
279 u32 frames1024_MaxSize;
280 u32 macRxError;
281 u32 droppedFrames;
282 u32 outMulticastFrames;
283 u32 outBroadcastFrames;
284 u32 undersizeFrames;
285 } mib_counters_t;
286
287
288 struct gt96100_private {
289 gt96100_rd_t *rx_ring;
290 gt96100_td_t *tx_ring;
291 // The Rx and Tx rings must be 16-byte aligned
292 dma_addr_t rx_ring_dma;
293 dma_addr_t tx_ring_dma;
294 char *hash_table;
295 // The Hash Table must be 8-byte aligned
296 dma_addr_t hash_table_dma;
297 int hash_mode;
298
299 // The Rx buffers must be 8-byte aligned
300 char *rx_buff[RX_RING_SIZE];
301 // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
302 // of payload must be 8-byte aligned
303 struct sk_buff *tx_skbuff[TX_RING_SIZE];
304 int rx_next_out; /* The next free ring entry to receive */
305 int tx_next_in; /* The next free ring entry to send */
306 int tx_next_out; /* The last ring entry the ISR processed */
307 int tx_count; /* current # of pkts waiting to be sent in Tx ring */
308
309 mib_counters_t mib;
310 struct net_device_stats stats;
311
312 int io_size;
313 int port_num; // 0 or 1
314 u32 port_offset;
315
316 int phy_addr; // PHY address
317 u32 last_psr; // last value of the port status register
318
319 int options; /* User-settable misc. driver options. */
320 int drv_flags;
321 unsigned char phys[2]; /* MII device addresses. */
322 spinlock_t lock; /* Serialise access to device */
323 };
324
325 #endif
326