File: /usr/src/linux/drivers/net/gt96100eth.c
1 /*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
24 *
25 */
26
27 #ifndef __mips__
28 #error This driver only works with MIPS architectures!
29 #endif
30
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
38 #include <linux/in.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/delay.h>
48 #include <asm/irq.h>
49 #include <asm/bitops.h>
50 #include <asm/io.h>
51
52 #include "gt96100eth.h"
53
54 #ifdef GT96100_DEBUG
55 static int gt96100_debug = GT96100_DEBUG;
56 #else
57 static int gt96100_debug = 3;
58 #endif
59
60 // prototypes
61 static void *dmaalloc(size_t size, dma_addr_t * dma_handle);
62 static void dmafree(size_t size, void *vaddr);
63 static int gt96100_add_hash_entry(struct net_device *dev,
64 unsigned char *addr);
65 static void read_mib_counters(struct gt96100_private *gp);
66 static int read_MII(struct net_device *dev, u32 reg);
67 static int write_MII(struct net_device *dev, u32 reg, u16 data);
68 static void dump_MII(struct net_device *dev);
69 static void update_stats(struct gt96100_private *gp);
70 static void abort(struct net_device *dev, u32 abort_bits);
71 static void hard_stop(struct net_device *dev);
72 static void enable_ether_irq(struct net_device *dev);
73 static void disable_ether_irq(struct net_device *dev);
74 static int __init gt96100_probe1(struct net_device *dev, long ioaddr,
75 int irq, int port_num);
76 static int gt96100_init(struct net_device *dev);
77 static int gt96100_open(struct net_device *dev);
78 static int gt96100_close(struct net_device *dev);
79 static int gt96100_tx(struct sk_buff *skb, struct net_device *dev);
80 static int gt96100_rx(struct net_device *dev, u32 status);
81 static void gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs);
82 static void gt96100_tx_timeout(struct net_device *dev);
83 static void gt96100_set_rx_mode(struct net_device *dev);
84 static struct net_device_stats *gt96100_get_stats(struct net_device *dev);
85
86 static char version[] __devinitdata =
87 "gt96100eth.c:0.1 stevel@mvista.com\n";
88
89 // FIX! Need real Ethernet addresses
90 static unsigned char gt96100_station_addr[2][6] __devinitdata =
91 { {0x01, 0x02, 0x03, 0x04, 0x05, 0x06},
92 {0x01, 0x02, 0x03, 0x04, 0x05, 0x07}
93 };
94
95 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
96
97 #define RUN_AT(x) (jiffies + (x))
98
99 // For reading/writing 32-bit words from/to DMA memory
100 #define cpu_to_dma32 cpu_to_be32
101 #define dma32_to_cpu be32_to_cpu
102
103 /*
104 * Base address and interupt of the GT96100 ethernet controllers
105 */
106 static struct {
107 unsigned int port;
108 int irq;
109 } gt96100_iflist[NUM_INTERFACES] = {
110 {
111 GT96100_ETH0_BASE, GT96100_ETHER0_IRQ}, {
112 GT96100_ETH1_BASE, GT96100_ETHER1_IRQ}
113 };
114
115 /*
116 DMA memory allocation, derived from pci_alloc_consistent.
117 */
118 static void *dmaalloc(size_t size, dma_addr_t * dma_handle)
119 {
120 void *ret;
121
122 ret =
123 (void *) __get_free_pages(GFP_ATOMIC | GFP_DMA,
124 get_order(size));
125
126 if (ret != NULL) {
127 dma_cache_inv((unsigned long) ret, size);
128 if (dma_handle != NULL)
129 *dma_handle = virt_to_phys(ret);
130
131 /* bump virtual address up to non-cached area */
132 ret = KSEG1ADDR(ret);
133 }
134
135 return ret;
136 }
137
138 static void dmafree(size_t size, void *vaddr)
139 {
140 vaddr = KSEG0ADDR(vaddr);
141 free_pages((unsigned long) vaddr, get_order(size));
142 }
143
144
145 static int read_MII(struct net_device *dev, u32 reg)
146 {
147 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
148 int timedout = 20;
149 u32 smir = smirOpCode | (gp->phy_addr << smirPhyAdBit) |
150 (reg << smirRegAdBit);
151
152 // wait for last operation to complete
153 while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
154 // snooze for 1 msec and check again
155 #if 0
156 current->state = TASK_INTERRUPTIBLE;
157 schedule_timeout(10 * HZ / 10000);
158 #else
159 mdelay(1);
160 #endif
161
162 if (--timedout == 0) {
163 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
164 dev->name);
165 return -1;
166 }
167 }
168
169 GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
170
171 timedout = 20;
172 // wait for read to complete
173 while (!(smir = GT96100_READ(GT96100_ETH_SMI_REG) & smirReadValid)) {
174 // snooze for 1 msec and check again
175 #if 0
176 current->state = TASK_INTERRUPTIBLE;
177 schedule_timeout(10 * HZ / 10000);
178 #else
179 mdelay(1);
180 #endif
181
182 if (--timedout == 0) {
183 printk(KERN_ERR "%s: read_MII timeout!!\n",
184 dev->name);
185 return -1;
186 }
187 }
188
189 return (int) (smir & smirDataMask);
190 }
191
192 static int write_MII(struct net_device *dev, u32 reg, u16 data)
193 {
194 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
195 int timedout = 20;
196 u32 smir =
197 (gp->phy_addr << smirPhyAdBit) | (reg << smirRegAdBit) | data;
198
199 // wait for last operation to complete
200 while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
201 // snooze for 1 msec and check again
202 #if 0
203 current->state = TASK_INTERRUPTIBLE;
204 schedule_timeout(10 * HZ / 10000);
205 #else
206 mdelay(1);
207 #endif
208
209 if (--timedout == 0) {
210 printk(KERN_ERR "%s: write_MII busy timeout!!\n",
211 dev->name);
212 return -1;
213 }
214 }
215
216 GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
217 return 0;
218 }
219
220
221 static void dump_MII(struct net_device *dev)
222 {
223 int i, val;
224
225 for (i = 0; i < 7; i++) {
226 if ((val = read_MII(dev, i)) >= 0)
227 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
228 }
229 for (i = 16; i < 21; i++) {
230 if ((val = read_MII(dev, i)) >= 0)
231 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
232 }
233 }
234
235
236 static int
237 gt96100_add_hash_entry(struct net_device *dev, unsigned char *addr)
238 {
239 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
240 u16 hashResult, stmp;
241 unsigned char ctmp, hash_ea[6];
242 u32 tblEntry, *tblEntryAddr;
243 int i;
244
245 for (i = 0; i < 6; i++) {
246 // nibble swap
247 ctmp = nibswap(addr[i]);
248 // invert every nibble
249 hash_ea[i] = ((ctmp & 1) << 3) | ((ctmp & 8) >> 3) |
250 ((ctmp & 2) << 1) | ((ctmp & 4) >> 1);
251 hash_ea[i] |= ((ctmp & 0x10) << 3) | ((ctmp & 0x80) >> 3) |
252 ((ctmp & 0x20) << 1) | ((ctmp & 0x40) >> 1);
253 }
254
255 if (gp->hash_mode == 0) {
256 hashResult = ((u16) hash_ea[0] & 0xfc) << 7;
257 stmp =
258 ((u16) hash_ea[0] & 0x03) | (((u16) hash_ea[1] & 0x7f)
259 << 2);
260 stmp ^=
261 (((u16) hash_ea[1] >> 7) & 0x01) | ((u16) hash_ea[2] <<
262 1);
263 stmp ^= (u16) hash_ea[3] | (((u16) hash_ea[4] & 1) << 8);
264 hashResult |= stmp;
265 } else {
266 return -1; // don't support hash mode 1
267 }
268
269 tblEntryAddr =
270 (u32 *) (&gp->hash_table[((u32) hashResult & 0x7ff) << 3]);
271
272 for (i = 0; i < HASH_HOP_NUMBER; i++) {
273 if ((*tblEntryAddr & hteValid)
274 && !(*tblEntryAddr & hteSkip)) {
275 // This entry is already occupied, go to next entry
276 tblEntryAddr += 2;
277 } else {
278 memset(tblEntryAddr, 0, 8);
279 tblEntry = hteValid | hteRD;
280 tblEntry |= (u32) addr[5] << 3;
281 tblEntry |= (u32) addr[4] << 11;
282 tblEntry |= (u32) addr[3] << 19;
283 tblEntry |= ((u32) addr[2] & 0x1f) << 27;
284 *(tblEntryAddr + 1) = cpu_to_dma32(tblEntry);
285 tblEntry = ((u32) addr[2] >> 5) & 0x07;
286 tblEntry |= (u32) addr[1] << 3;
287 tblEntry |= (u32) addr[0] << 11;
288 *tblEntryAddr = cpu_to_dma32(tblEntry);
289 break;
290 }
291 }
292
293 if (i >= HASH_HOP_NUMBER) {
294 printk(KERN_ERR "%s: gt96100_add_hash_entry expired!\n",
295 dev->name);
296 return -1; // Couldn't find an unused entry
297 }
298
299 return 0;
300 }
301
302
303 static void read_mib_counters(struct gt96100_private *gp)
304 {
305 u32 *mib_regs = (u32 *) & gp->mib;
306 int i;
307
308 for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++)
309 mib_regs[i] =
310 GT96100ETH_READ(gp,
311 GT96100_ETH_MIB_COUNT_BASE +
312 i * sizeof(u32));
313 }
314
315
316 static void update_stats(struct gt96100_private *gp)
317 {
318 mib_counters_t *mib = &gp->mib;
319 struct net_device_stats *stats = &gp->stats;
320
321 read_mib_counters(gp);
322
323 stats->rx_packets = mib->totalFramesReceived;
324 stats->tx_packets = mib->framesSent;
325 stats->rx_bytes = mib->totalByteReceived;
326 stats->tx_bytes = mib->byteSent;
327 stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
328 //the tx error counters are incremented by the ISR
329 //rx_dropped incremented by gt96100_rx
330 //tx_dropped incremented by gt96100_tx
331 stats->multicast = mib->multicastFramesReceived;
332 // Tx collisions incremented by ISR, so add in MIB Rx collisions
333 stats->collisions += mib->collision + mib->lateCollision;
334 stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
335 // The RxError condition means the Rx DMA encountered a
336 // CPU owned descriptor, which, if things are working as
337 // they should, means the Rx ring has overflowed.
338 stats->rx_over_errors = mib->macRxError;
339 stats->rx_crc_errors = mib->cRCError;
340 }
341
342 static void abort(struct net_device *dev, u32 abort_bits)
343 {
344 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
345 int timedout = 100; // wait up to 100 msec for hard stop to complete
346
347 if (gt96100_debug > 2)
348 printk(KERN_INFO "%s: abort\n", dev->name);
349
350 // Return if neither Rx or Tx abort bits are set
351 if (!(abort_bits & (sdcmrAR | sdcmrAT)))
352 return;
353
354 // make sure only the Rx/Tx abort bits are set
355 abort_bits &= (sdcmrAR | sdcmrAT);
356
357 spin_lock(&gp->lock);
358
359 // abort any Rx/Tx DMA immediately
360 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits);
361
362 if (gt96100_debug > 2)
363 printk(KERN_INFO "%s: abort: SDMA comm = %x\n",
364 dev->name, GT96100ETH_READ(gp,
365 GT96100_ETH_SDMA_COMM));
366
367 // wait for abort to complete
368 while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) {
369 // snooze for 20 msec and check again
370 #if 0
371 current->state = TASK_INTERRUPTIBLE;
372 schedule_timeout(10 * HZ / 10000);
373 #else
374 mdelay(1);
375 #endif
376
377 if (--timedout == 0) {
378 printk(KERN_ERR "%s: abort timeout!!\n",
379 dev->name);
380 break;
381 }
382 }
383
384 if (gt96100_debug > 2)
385 printk(KERN_INFO "%s: abort: timedout=%d\n", dev->name,
386 timedout);
387
388 spin_unlock(&gp->lock);
389 }
390
391
392 static void hard_stop(struct net_device *dev)
393 {
394 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
395
396 if (gt96100_debug > 2)
397 printk(KERN_INFO "%s: hard stop\n", dev->name);
398
399 disable_ether_irq(dev);
400
401 abort(dev, sdcmrAR | sdcmrAT);
402
403 // disable port
404 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0);
405 }
406
407
408 static void enable_ether_irq(struct net_device *dev)
409 {
410 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
411 u32 intMask;
412
413 // unmask interrupts
414 GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK,
415 icrRxBuffer | icrTxBufferLow | icrTxEndLow |
416 icrRxError | icrTxErrorLow | icrRxOVR |
417 icrTxUdr | icrRxBufferQ0 | icrRxErrorQ0 |
418 icrMIIPhySTC);
419
420 // now route ethernet interrupts to GT Int0 (eth0 and eth1 will be
421 // sharing it).
422 // FIX! The kernel's irq code should do this
423 intMask = GT96100_READ(GT96100_INT0_HIGH_MASK);
424 intMask |= 1 << gp->port_num;
425 GT96100_WRITE(GT96100_INT0_HIGH_MASK, intMask);
426 }
427
428 static void disable_ether_irq(struct net_device *dev)
429 {
430 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
431 u32 intMask;
432
433 // FIX! The kernel's irq code should do this
434 intMask = GT96100_READ(GT96100_INT0_HIGH_MASK);
435 intMask &= ~(1 << gp->port_num);
436 GT96100_WRITE(GT96100_INT0_HIGH_MASK, intMask);
437
438 GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0);
439 }
440
441
442 /*
443 * Probe for a GT96100 ethernet controller.
444 */
445 int __init gt96100_probe(struct net_device *dev)
446 {
447 unsigned int base_addr = dev ? dev->base_addr : 0;
448 int i;
449
450 #ifndef CONFIG_MIPS_GT96100ETH
451 return -ENODEV;
452 #endif
453
454 if (gt96100_debug > 2)
455 printk(KERN_INFO "%s: gt96100_probe\n", dev->name);
456
457 if (base_addr >= KSEG0) /* Check a single specified location. */
458 return gt96100_probe1(dev, base_addr, dev->irq, 0);
459 else if (base_addr != 0) /* Don't probe at all. */
460 return -ENXIO;
461
462 // for (i = 0; i<NUM_INTERFACES; i++) {
463 for (i = NUM_INTERFACES - 1; i >= 0; i--) {
464 int base_addr = gt96100_iflist[i].port;
465 #if 0
466 if (check_region(base_addr, GT96100_ETH_IO_SIZE)) {
467 printk(KERN_ERR
468 "%s: gt96100_probe: ioaddr 0x%lx taken?\n",
469 dev->name, base_addr);
470 continue;
471 }
472 #endif
473 if (gt96100_probe1
474 (dev, base_addr, gt96100_iflist[i].irq, i) == 0)
475 return 0;
476 }
477 return -ENODEV;
478 }
479
480
481
482 static int __init
483 gt96100_probe1(struct net_device *dev, long ioaddr, int irq, int port_num)
484 {
485 static unsigned version_printed = 0;
486 struct gt96100_private *gp = NULL;
487 int i, retval;
488 u32 cpuConfig;
489
490 // FIX! probe for GT96100 by reading a suitable register
491
492 if (gt96100_debug > 2)
493 printk(KERN_INFO "gt96100_probe1: ioaddr 0x%lx, irq %d\n",
494 ioaddr, irq);
495
496 request_region(ioaddr, GT96100_ETH_IO_SIZE, "GT96100ETH");
497
498 cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG);
499 if (cpuConfig & (1 << 12)) {
500 printk(KERN_ERR
501 "gt96100_probe1: must be in Big Endian mode!\n");
502 retval = -ENODEV;
503 goto free_region;
504 }
505
506 if (gt96100_debug > 2)
507 printk(KERN_INFO
508 "gt96100_probe1: chip in Big Endian mode - cool\n");
509
510 /* Allocate a new 'dev' if needed. */
511 if (dev == NULL)
512 dev = init_etherdev(0, sizeof(struct gt96100_private));
513
514 if (gt96100_debug && version_printed++ == 0)
515 printk(version);
516
517 if (irq < 0) {
518 printk(KERN_ERR
519 "gt96100_probe1: irq unknown - probing not supported\n");
520 retval = -ENODEV;
521 goto free_region;
522 }
523
524 printk(KERN_INFO "%s: GT-96100 ethernet found at 0x%lx, irq %d\n",
525 dev->name, ioaddr, irq);
526
527 /* private struct aligned and zeroed by init_etherdev */
528 /* Fill in the 'dev' fields. */
529 dev->base_addr = ioaddr;
530 dev->irq = irq;
531 memcpy(dev->dev_addr, gt96100_station_addr[port_num],
532 sizeof(dev->dev_addr));
533
534 printk(KERN_INFO "%s: HW Address ", dev->name);
535 for (i = 0; i < sizeof(dev->dev_addr); i++) {
536 printk("%2.2x", dev->dev_addr[i]);
537 printk(i < 5 ? ":" : "\n");
538 }
539
540 /* Initialize our private structure. */
541 if (dev->priv == NULL) {
542
543 gp =
544 (struct gt96100_private *) kmalloc(sizeof(*gp),
545 GFP_KERNEL);
546 if (gp == NULL) {
547 retval = -ENOMEM;
548 goto free_region;
549 }
550
551 dev->priv = gp;
552 }
553
554 gp = dev->priv;
555
556 memset(gp, 0, sizeof(*gp)); // clear it
557
558 gp->port_num = port_num;
559 gp->io_size = GT96100_ETH_IO_SIZE;
560 gp->port_offset = port_num * GT96100_ETH_IO_SIZE;
561 gp->phy_addr = port_num + 1;
562
563 if (gt96100_debug > 2)
564 printk(KERN_INFO "%s: gt96100_probe1, port %d\n",
565 dev->name, gp->port_num);
566
567 // Allocate Rx and Tx descriptor rings
568 if (gp->rx_ring == NULL) {
569 // All descriptors in ring must be 16-byte aligned
570 gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE
571 +
572 sizeof(gt96100_td_t) * TX_RING_SIZE,
573 &gp->rx_ring_dma);
574 if (gp->rx_ring == NULL) {
575 retval = -ENOMEM;
576 goto free_region;
577 }
578
579 gp->tx_ring =
580 (gt96100_td_t *) (gp->rx_ring + RX_RING_SIZE);
581 gp->tx_ring_dma =
582 gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE;
583 }
584
585 if (gt96100_debug > 2)
586 printk(KERN_INFO
587 "%s: gt96100_probe1, rx_ring=%p, tx_ring=%p\n",
588 dev->name, gp->rx_ring, gp->tx_ring);
589
590 // Allocate Rx Hash Table
591 if (gp->hash_table == NULL) {
592 gp->hash_table = (char *) dmaalloc(RX_HASH_TABLE_SIZE,
593 &gp->hash_table_dma);
594 if (gp->hash_table == NULL) {
595 dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
596 + sizeof(gt96100_td_t) * TX_RING_SIZE,
597 gp->rx_ring);
598 retval = -ENOMEM;
599 goto free_region;
600 }
601 }
602
603 if (gt96100_debug > 2)
604 printk(KERN_INFO "%s: gt96100_probe1, hash=%p\n",
605 dev->name, gp->hash_table);
606
607 spin_lock_init(&gp->lock);
608
609 dev->open = gt96100_open;
610 dev->hard_start_xmit = gt96100_tx;
611 dev->stop = gt96100_close;
612 dev->get_stats = gt96100_get_stats;
613 //dev->do_ioctl = gt96100_ioctl;
614 dev->set_multicast_list = gt96100_set_rx_mode;
615 dev->tx_timeout = gt96100_tx_timeout;
616 dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT;
617
618 /* Fill in the fields of the device structure with ethernet values. */
619 ether_setup(dev);
620 return 0;
621
622 free_region:
623 release_region(ioaddr, gp->io_size);
624 unregister_netdev(dev);
625 if (dev->priv != NULL)
626 kfree(dev->priv);
627 kfree(dev);
628 printk(KERN_ERR "%s: gt96100_probe1 failed. Returns %d\n",
629 dev->name, retval);
630 return retval;
631 }
632
633
634 static int gt96100_init(struct net_device *dev)
635 {
636 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
637 unsigned long flags;
638 u32 phyAD, ciu;
639 int i;
640
641 if (gt96100_debug > 2)
642 printk("%s: gt96100_init: dev=%p\n", dev->name, dev);
643
644 // Stop and disable Port
645 hard_stop(dev);
646
647 spin_lock_irqsave(&gp->lock, flags);
648
649 // First things first, set-up hash table
650 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
651 gp->hash_mode = 0;
652 // Add a single entry to hash table - our ethernet address
653 gt96100_add_hash_entry(dev, dev->dev_addr);
654 // Set-up DMA ptr to hash table
655 GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma);
656 if (gt96100_debug > 2)
657 printk("%s: gt96100_init: Hash Tbl Ptr=%x\n", dev->name,
658 GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR));
659
660 // Setup Tx descriptor ring
661 for (i = 0; i < TX_RING_SIZE; i++) {
662 gp->tx_ring[i].cmdstat = 0; // CPU owns
663 gp->tx_ring[i].byte_cnt = 0;
664 gp->tx_ring[i].buff_ptr = 0;
665 gp->tx_ring[i].next =
666 cpu_to_dma32(gp->tx_ring_dma +
667 sizeof(gt96100_td_t) * (i + 1));
668 }
669 /* Wrap the ring. */
670 gp->tx_ring[i - 1].next = cpu_to_dma32(gp->tx_ring_dma);
671
672 // setup only the lowest priority TxCDP reg
673 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0,
674 gp->tx_ring_dma);
675 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0);
676 if (gt96100_debug > 2)
677 printk("%s: gt96100_init: Curr Tx Desc Ptr0=%x\n",
678 dev->name, GT96100ETH_READ(gp,
679 GT96100_ETH_CURR_TX_DESC_PTR0));
680
681 // Setup Rx descriptor ring
682 for (i = 0; i < RX_RING_SIZE; i++) {
683 dma_addr_t rx_buff_dma;
684 gp->rx_ring[i].next =
685 cpu_to_dma32(gp->rx_ring_dma +
686 sizeof(gt96100_rd_t) * (i + 1));
687 if (gp->rx_buff[i] == NULL)
688 gp->rx_buff[i] =
689 dmaalloc(PKT_BUF_SZ, &rx_buff_dma);
690 else
691 rx_buff_dma = virt_to_phys(gp->rx_buff[i]);
692 if (gp->rx_buff[i] == NULL)
693 break;
694 gp->rx_ring[i].buff_ptr = cpu_to_dma32(rx_buff_dma);
695 gp->rx_ring[i].buff_cnt_sz =
696 cpu_to_dma32(PKT_BUF_SZ << rdBuffSzBit);
697 // Give ownership to device, enable interrupt
698 gp->rx_ring[i].cmdstat =
699 cpu_to_dma32((u32) (rxOwn | rxEI));
700 }
701
702 if (i != RX_RING_SIZE) {
703 int j;
704 for (j = 0; j < RX_RING_SIZE; j++) {
705 if (gp->rx_buff[j]) {
706 dmafree(PKT_BUF_SZ, gp->rx_buff[j]);
707 gp->rx_buff[j] = NULL;
708 }
709 }
710 printk(KERN_ERR "%s: Rx ring allocation failed.\n",
711 dev->name);
712 spin_unlock_irqrestore(&gp->lock, flags);
713 return -ENOMEM;
714 }
715
716 /* Wrap the ring. */
717 gp->rx_ring[i - 1].next = cpu_to_dma32(gp->rx_ring_dma);
718
719 // Set our MII PHY device address
720 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
721 phyAD &= ~(0x1f << (gp->port_num * 5));
722 phyAD |= gp->phy_addr << (gp->port_num * 5);
723 GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD);
724
725 if (gt96100_debug > 2)
726 printk("%s: gt96100_init: PhyAD=%x\n", dev->name,
727 GT96100_READ(GT96100_ETH_PHY_ADDR_REG));
728
729 // Clear all the RxFDP and RXCDP regs...
730 for (i = 0; i < 4; i++) {
731 GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0 + i * 4,
732 0);
733 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0 + i * 4,
734 0);
735 }
736 // and setup only the lowest priority RxFDP and RxCDP regs
737 GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0,
738 gp->rx_ring_dma);
739 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0,
740 gp->rx_ring_dma);
741 if (gt96100_debug > 2)
742 printk("%s: gt96100_init: 1st/Curr Rx Desc Ptr0=%x/%x\n",
743 dev->name, GT96100ETH_READ(gp,
744 GT96100_ETH_1ST_RX_DESC_PTR0),
745 GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0));
746
747 // init Rx/Tx indeces and pkt counters
748 gp->rx_next_out = gp->tx_next_in = gp->tx_next_out = 0;
749 gp->tx_count = 0;
750
751 // setup DMA
752
753 // FIX! this should be done by Kernel setup code
754 ciu = GT96100_READ(GT96100_CIU_ARBITER_CONFIG);
755 ciu |= (0x0c << (gp->port_num * 2)); // set Ether DMA req priority to high
756 // FIX! setting the following bit causes the EV96100 board to hang!!!
757 //ciu |= (1 << (24+gp->port_num)); // pull Ethernet port out of Reset???
758 // FIX! endian mode???
759 ciu &= ~(1 << 31); // set desc endianess to Big
760 GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, ciu);
761 if (gt96100_debug > 2)
762 printk("%s: gt96100_init: CIU Config=%x/%x\n", dev->name,
763 ciu, GT96100_READ(GT96100_CIU_ARBITER_CONFIG));
764
765 // We want the Rx/Tx DMA to write/read data to/from memory in
766 // Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
767 // FIX! endian mode???
768 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
769 //sdcrBLMR | sdcrBLMT |
770 (0xf << sdcrRCBit) | sdcrRIFB | (3 << sdcrBSZBit));
771 if (gt96100_debug > 2)
772 printk("%s: gt96100_init: SDMA Config=%x\n", dev->name,
773 GT96100ETH_READ(gp, GT96100_ETH_SDMA_CONFIG));
774
775 // start Rx DMA
776 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
777 if (gt96100_debug > 2)
778 printk("%s: gt96100_init: SDMA Comm=%x\n", dev->name,
779 GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
780
781 // enable interrupts
782 enable_ether_irq(dev);
783
784 /*
785 * Disable all Type-of-Service queueing. All Rx packets will be
786 * treated normally and will be sent to the lowest priority
787 * queue.
788 *
789 * Disable flow-control for now. FIX! support flow control?
790 */
791 // clear all the MIB ctr regs
792 // Enable reg clear on read. FIX! desc of this bit is inconsistent
793 // in the GT-96100A datasheet.
794 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
795 pcxrFCTL | pcxrFCTLen | pcxrFLP);
796 read_mib_counters(gp);
797 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
798 pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrMIBclrMode);
799
800 if (gt96100_debug > 2)
801 printk("%s: gt96100_init: Port Config Ext=%x\n", dev->name,
802 GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG_EXT));
803
804 // enable this port (set hash size to 1/2K)
805 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, pcrEN | pcrHS);
806 if (gt96100_debug > 2)
807 printk("%s: gt96100_init: Port Config=%x\n", dev->name,
808 GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG));
809
810 // we should now be receiving frames
811 if (gt96100_debug > 2)
812 dump_MII(dev);
813
814 spin_unlock_irqrestore(&gp->lock, flags);
815 return 0;
816 }
817
818
819 static int gt96100_open(struct net_device *dev)
820 {
821 int retval;
822
823 MOD_INC_USE_COUNT;
824
825 if (gt96100_debug > 2)
826 printk("%s: gt96100_open: dev=%p\n", dev->name, dev);
827
828 if ((retval = request_irq(dev->irq, >96100_interrupt,
829 SA_SHIRQ, dev->name, dev))) {
830 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
831 dev->irq);
832 MOD_DEC_USE_COUNT;
833 return retval;
834 }
835 // Initialize and startup the GT-96100 ethernet port
836 if ((retval = gt96100_init(dev))) {
837 printk(KERN_ERR "%s: error in gt96100_init\n", dev->name);
838 free_irq(dev->irq, dev);
839 MOD_DEC_USE_COUNT;
840 return retval;
841 }
842
843 netif_start_queue(dev);
844
845 if (gt96100_debug > 2)
846 printk("%s: gt96100_open: Initialization done.\n",
847 dev->name);
848
849 return 0;
850 }
851
852 static int gt96100_close(struct net_device *dev)
853 {
854 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
855 int i;
856
857 if (gt96100_debug > 2)
858 printk("%s: gt96100_close: dev=%p\n", dev->name, dev);
859
860 // stop the device
861 if (netif_device_present(dev)) {
862 netif_stop_queue(dev);
863 hard_stop(dev);
864 }
865 // free the Rx DMA buffers
866 for (i = 0; i < RX_RING_SIZE; i++) {
867 if (gp->rx_buff[i]) {
868 dmafree(PKT_BUF_SZ, gp->rx_buff[i]);
869 gp->rx_buff[i] = NULL;
870 }
871 }
872
873 free_irq(dev->irq, dev);
874
875 MOD_DEC_USE_COUNT;
876 return 0;
877 }
878
879
880 static int gt96100_tx(struct sk_buff *skb, struct net_device *dev)
881 {
882 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
883 unsigned long flags;
884 int nextIn;
885
886 if (gt96100_debug > 2)
887 printk("%s: gt96100_tx: skb->len=%d, skb->data=%p\n",
888 dev->name, skb->len, skb->data);
889
890 spin_lock_irqsave(&gp->lock, flags);
891
892 if (gp->tx_count >= TX_RING_SIZE) {
893 printk(KERN_WARNING
894 "%s: Tx Ring full, refusing to send buffer.\n",
895 dev->name);
896 gp->stats.tx_dropped++;
897 spin_unlock_irqrestore(&gp->lock, flags);
898 return 1;
899 }
900 // Prepare the Descriptor at tx_next_in
901 nextIn = gp->tx_next_in;
902
903 if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) {
904 printk(KERN_ERR "%s: gt96100_tx: TxOwn bit wrong!!\n",
905 dev->name);
906 }
907
908 gp->tx_skbuff[nextIn] = skb;
909 gp->tx_ring[nextIn].byte_cnt =
910 cpu_to_dma32(skb->len << tdByteCntBit);
911 gp->tx_ring[nextIn].buff_ptr =
912 cpu_to_dma32(virt_to_phys(skb->data));
913 // Give ownership to device, set first and last desc, enable interrupt
914 // Setting of ownership bit must be *last*!
915 gp->tx_ring[nextIn].cmdstat =
916 cpu_to_dma32((u32) (txOwn | txEI | txFirst | txLast));
917
918 // increment tx_next_in with wrap
919 gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
920 // If count is zero, DMA should be stopped, so restart
921 if (gp->tx_count == 0) {
922 if (GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) &
923 psrTxLow) printk(KERN_WARNING
924 "%s: Tx count zero but Tx queue running!\n",
925 dev->name);
926 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
927 sdcmrERD | sdcmrTXDL);
928 }
929 // increment count and stop queue if full
930 if (++gp->tx_count == TX_RING_SIZE)
931 netif_stop_queue(dev);
932
933 dev->trans_start = jiffies;
934 spin_unlock_irqrestore(&gp->lock, flags);
935
936 return 0;
937 }
938
939
940 static int gt96100_rx(struct net_device *dev, u32 status)
941 {
942 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
943 struct sk_buff *skb;
944 int pkt_len, nextOut;
945 gt96100_rd_t *rd;
946 u32 cmdstat;
947
948 if (gt96100_debug > 2)
949 printk("%s: gt96100_rx: dev=%p, status = %x\n",
950 dev->name, dev, status);
951
952 // Continue until we reach the current descriptor pointer
953 for (nextOut = gp->rx_next_out;
954 nextOut !=
955 (GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0) -
956 gp->rx_ring_dma) / sizeof(gt96100_rd_t);
957 nextOut = (nextOut + 1) % RX_RING_SIZE) {
958
959 rd = &gp->rx_ring[nextOut];
960 cmdstat = dma32_to_cpu(rd->cmdstat);
961
962 if (cmdstat & (u32) rxOwn) {
963 cmdstat &= ~((u32) rxOwn);
964 rd->cmdstat = cpu_to_dma32(cmdstat);
965 printk(KERN_ERR
966 "%s: gt96100_rx: ownership bit wrong!\n",
967 dev->name);
968 }
969 // must be first and last (ie only) buffer of packet
970 if (!(cmdstat & (u32) rxFirst)
971 || !(cmdstat & (u32) rxLast)) {
972 printk(KERN_ERR
973 "%s: gt96100_rx: desc not first and last!\n",
974 dev->name);
975 continue;
976 }
977 // drop this received pkt if there were any errors
978 if ((cmdstat & (u32) rxErrorSummary)
979 || (status & icrRxErrorQ0)) {
980 // update the detailed rx error counters that are not covered
981 // by the MIB counters.
982 if (cmdstat & (u32) rxOverrun)
983 gp->stats.rx_fifo_errors++;
984 continue;
985 }
986
987 pkt_len = dma32_to_cpu(rd->buff_cnt_sz) & rdByteCntMask;
988
989 /* Create new skb. */
990 skb = dev_alloc_skb(pkt_len + 2);
991 if (skb == NULL) {
992 printk(KERN_ERR
993 "%s: Memory squeeze, dropping packet.\n",
994 dev->name);
995 gp->stats.rx_dropped++;
996 continue;
997 }
998 skb->dev = dev;
999 skb_reserve(skb, 2); /* 16 byte IP header align */
1000 skb_put(skb, pkt_len); /* Make room */
1001 eth_copy_and_sum(skb, gp->rx_buff[nextOut], pkt_len, 0);
1002 skb->protocol = eth_type_trans(skb, dev);
1003 netif_rx(skb); /* pass the packet to upper layers */
1004
1005 // now we can release ownership of this desc back to device
1006 cmdstat |= (u32) rxOwn;
1007 rd->cmdstat = cpu_to_dma32(cmdstat);
1008
1009 dev->last_rx = jiffies;
1010 }
1011
1012 gp->rx_next_out = nextOut;
1013 return 0;
1014 }
1015
1016
1017 static void gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1018 {
1019 struct net_device *dev = (struct net_device *) dev_id;
1020 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
1021 u32 status;
1022
1023 if (dev == NULL) {
1024 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
1025 return;
1026 }
1027
1028 status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE);
1029 // ACK interrupts
1030 #if 0
1031 GT96100ETH_CLRBIT(gp, GT96100_ETH_INT_CAUSE,
1032 icrEtherIntSum | icrRxBufferQ1 | icrRxBufferQ2 |
1033 icrRxBufferQ3 | icrRxBufferQ0 | icrTxBufferHigh |
1034 icrTxEndHigh | icrTxBufferLow | icrTxEndLow |
1035 icrTxErrorHigh | icrTxErrorLow | icrTxUdr);
1036 #else
1037 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0);
1038 #endif
1039
1040 if ((status & icrEtherIntSum) == 0) {
1041 // not our interrupt
1042 //printk("%s: isr: no ints? icr=%x,cp0_cause=%x\n",
1043 // dev->name, status, read_32bit_cp0_register(CP0_CAUSE));
1044 return;
1045 }
1046
1047 if (gt96100_debug > 3)
1048 printk("%s: isr: entry, icr=%x\n", dev->name, status);
1049
1050 if (status & (icrRxBufferQ1 | icrRxBufferQ2 | icrRxBufferQ3)) {
1051 printk(KERN_ERR "%s: isr: Rx intr in unused queues!?\n",
1052 dev->name);
1053 }
1054
1055 if (status & icrRxBufferQ0) {
1056 gt96100_rx(dev, status);
1057 }
1058
1059 if (status & (icrTxBufferHigh | icrTxEndHigh)) {
1060 printk(KERN_ERR "%s: isr: Tx intr in unused queue!?\n",
1061 dev->name);
1062 }
1063
1064 if (status & icrMIIPhySTC) {
1065 u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS);
1066 printk("%s: port status:\n", dev->name);
1067 printk
1068 ("%s: %s MBit/s, %s-duplex, flow-control %s, link is %s,\n",
1069 dev->name, psr & psrSpeed ? "100" : "10",
1070 psr & psrDuplex ? "full" : "half",
1071 psr & psrFctl ? "disabled" : "enabled",
1072 psr & psrLink ? "up" : "down");
1073 printk
1074 ("%s: TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n",
1075 dev->name, psr & psrTxLow ? "running" : "stopped",
1076 psr & psrTxHigh ? "running" : "stopped",
1077 psr & psrTxInProg ? "on" : "off");
1078 gp->last_psr = psr;
1079 }
1080
1081 if (status & (icrTxBufferLow | icrTxEndLow)) {
1082 int nextOut;
1083 gt96100_td_t *td;
1084 u32 cmdstat;
1085
1086 // Continue until we reach the current descriptor pointer
1087 for (nextOut = gp->tx_next_out;
1088 nextOut !=
1089 (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0) -
1090 gp->tx_ring_dma) / sizeof(gt96100_td_t);
1091 nextOut = (nextOut + 1) % TX_RING_SIZE) {
1092
1093 td = &gp->tx_ring[nextOut];
1094 cmdstat = dma32_to_cpu(td->cmdstat);
1095
1096 if (gt96100_debug > 2)
1097 printk("%s: isr: Tx desc cmdstat=%x\n",
1098 dev->name, cmdstat);
1099
1100 if (cmdstat & (u32) txOwn) {
1101 cmdstat &= ~((u32) txOwn);
1102 td->cmdstat = cpu_to_dma32(cmdstat);
1103 printk(KERN_ERR
1104 "%s: isr: Tx ownership bit wrong!\n",
1105 dev->name);
1106 }
1107 // increment Tx error stats
1108 if (cmdstat & (u32) txErrorSummary) {
1109 if (gt96100_debug > 2)
1110 printk
1111 ("%s: gt96100_interrupt: Tx error, cmdstat = %x\n",
1112 dev->name, cmdstat);
1113 gp->stats.tx_errors++;
1114 if (cmdstat & (u32) txReTxLimit)
1115 gp->stats.collisions++;
1116 if (cmdstat & (u32) txUnderrun)
1117 gp->stats.tx_fifo_errors++;
1118 if (cmdstat & (u32) txLateCollision)
1119 gp->stats.tx_window_errors++;
1120 }
1121 // Wake the queue if the ring was full
1122 if (gp->tx_count == TX_RING_SIZE)
1123 netif_wake_queue(dev);
1124
1125 // decrement tx ring buffer count
1126 if (gp->tx_count)
1127 gp->tx_count--;
1128
1129 // free the skb
1130 if (gp->tx_skbuff[nextOut]) {
1131 if (gt96100_debug > 2)
1132 printk
1133 ("%s: isr: good Tx, skb=%p\n",
1134 dev->name,
1135 gp->tx_skbuff[nextOut]);
1136 dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
1137 gp->tx_skbuff[nextOut] = NULL;
1138 } else {
1139 printk(KERN_ERR "%s: isr: no skb!\n",
1140 dev->name);
1141 }
1142 }
1143
1144 if (gp->tx_count == 0 && nextOut != gp->tx_next_in) {
1145 // FIX! this should probably be a panic
1146 printk(KERN_ERR
1147 "%s: isr: warning! Tx queue inconsistent\n",
1148 dev->name);
1149 }
1150
1151 gp->tx_next_out = nextOut;
1152
1153 if ((status & icrTxEndLow) && gp->tx_count != 0) {
1154 // we must restart the DMA
1155 if (gt96100_debug > 2)
1156 printk("%s: isr: Restarting Tx DMA\n",
1157 dev->name);
1158 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1159 sdcmrERD | sdcmrTXDL);
1160 }
1161 }
1162 // Now check TX errors (RX errors were handled in gt96100_rx)
1163
1164 if (status & icrTxErrorHigh) {
1165 printk(KERN_ERR
1166 "%s: isr: Tx resource error in unused queue!?\n",
1167 dev->name);
1168 }
1169
1170 if (status & icrTxErrorLow) {
1171 printk(KERN_ERR "%s: isr: Tx resource error\n", dev->name);
1172 }
1173
1174 if (status & icrTxUdr) {
1175 printk(KERN_ERR "%s: isr: Tx underrun error\n", dev->name);
1176 }
1177
1178 if (gt96100_debug > 3)
1179 printk("%s: isr: exit, icr=%x\n",
1180 dev->name, GT96100ETH_READ(gp,
1181 GT96100_ETH_INT_CAUSE));
1182 }
1183
1184
1185 /*
1186 * The Tx ring has been full longer than the watchdog timeout
1187 * value, meaning that the interrupt routine has not been freeing
1188 * up space in the Tx ring buffer.
1189 */
1190 static void gt96100_tx_timeout(struct net_device *dev)
1191 {
1192 // struct gt96100_private *gp = (struct gt96100_private *)dev->priv;
1193
1194 printk(KERN_ERR "%s: gt96100_tx_timeout: dev=%p\n", dev->name,
1195 dev);
1196
1197 // FIX! do something, like reset the device
1198 }
1199
1200
1201 static void gt96100_set_rx_mode(struct net_device *dev)
1202 {
1203 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
1204 unsigned long flags;
1205 struct dev_mc_list *mcptr;
1206
1207 if (gt96100_debug > 2)
1208 printk("%s: gt96100_set_rx_mode: dev=%p, flags=%x\n",
1209 dev->name, dev, dev->flags);
1210
1211 // stop the Receiver DMA
1212 abort(dev, sdcmrAR);
1213
1214 spin_lock_irqsave(&gp->lock, flags);
1215
1216 if (dev->flags & IFF_PROMISC)
1217 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG,
1218 pcrEN | pcrHS | pcrPM);
1219
1220 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear hash table
1221 // Add our ethernet address
1222 gt96100_add_hash_entry(dev, dev->dev_addr);
1223
1224 if (dev->mc_count) {
1225 for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
1226 gt96100_add_hash_entry(dev, mcptr->dmi_addr);
1227 }
1228 }
1229 // restart Rx DMA
1230 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
1231
1232 spin_unlock_irqrestore(&gp->lock, flags);
1233 }
1234
1235 static struct net_device_stats *gt96100_get_stats(struct net_device *dev)
1236 {
1237 struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
1238 unsigned long flags;
1239
1240 if (gt96100_debug > 2)
1241 printk("%s: gt96100_get_stats: dev=%p\n", dev->name, dev);
1242
1243 if (netif_device_present(dev)) {
1244 spin_lock_irqsave(&gp->lock, flags);
1245 update_stats(gp);
1246 spin_unlock_irqrestore(&gp->lock, flags);
1247 }
1248
1249 return &gp->stats;
1250 }
1251
1252 module_init(gt96100_probe);
1253