File: /usr/src/linux/drivers/net/hamradio/soundmodem/sm_wss.c
1 /*****************************************************************************/
2
3 /*
4 * sm_wss.c -- soundcard radio modem driver, WSS (half duplex) driver
5 *
6 * Copyright (C) 1996 Thomas Sailer (sailer@ife.ee.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Please note that the GPL allows you to use the driver, NOT the radio.
23 * In order to use the radio, you need a license from the communications
24 * authority of your country.
25 *
26 */
27
28 #include <linux/ptrace.h>
29 #include <linux/sched.h>
30 #include <linux/interrupt.h>
31 #include <asm/io.h>
32 #include <asm/dma.h>
33 #include <linux/ioport.h>
34 #include <linux/soundmodem.h>
35 #include "sm.h"
36 #include "smdma.h"
37
38 /* --------------------------------------------------------------------- */
39
40 /*
41 * currently this module is supposed to support both module styles, i.e.
42 * the old one present up to about 2.1.9, and the new one functioning
43 * starting with 2.1.21. The reason is I have a kit allowing to compile
44 * this module also under 2.0.x which was requested by several people.
45 * This will go in 2.2
46 */
47 #include <linux/version.h>
48
49 #if LINUX_VERSION_CODE >= 0x20100
50 #include <asm/uaccess.h>
51 #else
52 #include <asm/segment.h>
53 #include <linux/mm.h>
54
55 #undef put_user
56 #undef get_user
57
58 #define put_user(x,ptr) ({ __put_user((unsigned long)(x),(ptr),sizeof(*(ptr))); 0; })
59 #define get_user(x,ptr) ({ x = ((__typeof__(*(ptr)))__get_user((ptr),sizeof(*(ptr)))); 0; })
60
61 extern inline int copy_from_user(void *to, const void *from, unsigned long n)
62 {
63 int i = verify_area(VERIFY_READ, from, n);
64 if (i)
65 return i;
66 memcpy_fromfs(to, from, n);
67 return 0;
68 }
69
70 extern inline int copy_to_user(void *to, const void *from, unsigned long n)
71 {
72 int i = verify_area(VERIFY_WRITE, to, n);
73 if (i)
74 return i;
75 memcpy_tofs(to, from, n);
76 return 0;
77 }
78 #endif
79
80 /* --------------------------------------------------------------------- */
81
82 struct sc_state_wss {
83 unsigned char revwss, revid, revv, revcid;
84 unsigned char fmt[2];
85 unsigned char crystal;
86 };
87
88 #define SCSTATE ((struct sc_state_wss *)(&sm->hw))
89
90 /* --------------------------------------------------------------------- */
91
92 #define WSS_CONFIG(iobase) (iobase+0)
93 #define WSS_STATUS(iobase) (iobase+3)
94 #define WSS_CODEC_IA(iobase) (iobase+4)
95 #define WSS_CODEC_ID(iobase) (iobase+5)
96 #define WSS_CODEC_STATUS(iobase) (iobase+6)
97 #define WSS_CODEC_DATA(iobase) (iobase+7)
98
99 #define WSS_EXTENT 8
100
101 #define CS423X_HOTFIX
102
103 /* --------------------------------------------------------------------- */
104
105 static void write_codec(struct net_device *dev, unsigned char idx,
106 unsigned char data)
107 {
108 int timeout = 900000;
109
110 /* wait until codec ready */
111 while (timeout > 0 && inb(WSS_CODEC_IA(dev->base_addr)) & 0x80)
112 timeout--;
113 outb(idx, WSS_CODEC_IA(dev->base_addr));
114 outb(data, WSS_CODEC_ID(dev->base_addr));
115 }
116
117
118 /* --------------------------------------------------------------------- */
119
120 static unsigned char read_codec(struct net_device *dev, unsigned char idx)
121 {
122 int timeout = 900000;
123
124 /* wait until codec ready */
125 while (timeout > 0 && inb(WSS_CODEC_IA(dev->base_addr)) & 0x80)
126 timeout--;
127 outb(idx & 0x1f, WSS_CODEC_IA(dev->base_addr));
128 return inb(WSS_CODEC_ID(dev->base_addr));
129 }
130
131 /* --------------------------------------------------------------------- */
132
133 extern void inline wss_ack_int(struct net_device *dev)
134 {
135 outb(0, WSS_CODEC_STATUS(dev->base_addr));
136 }
137
138 /* --------------------------------------------------------------------- */
139
140 static int wss_srate_tab[16] = {
141 8000, 5510, 16000, 11025, 27420, 18900, 32000, 22050,
142 -1, 37800, -1, 44100, 48000, 33075, 9600, 6620
143 };
144
145 static int wss_srate_index(int srate)
146 {
147 int i;
148
149 for (i = 0; i < (sizeof(wss_srate_tab)/sizeof(wss_srate_tab[0])); i++)
150 if (srate == wss_srate_tab[i] && wss_srate_tab[i] > 0)
151 return i;
152 return -1;
153 }
154
155 /* --------------------------------------------------------------------- */
156
157 static int wss_set_codec_fmt(struct net_device *dev, struct sm_state *sm, unsigned char fmt,
158 unsigned char fmt2, char fdx, char fullcalib)
159 {
160 unsigned long time;
161 unsigned long flags;
162
163 save_flags(flags);
164 cli();
165 /* Clock and data format register */
166 write_codec(dev, 0x48, fmt);
167 if (SCSTATE->crystal) {
168 write_codec(dev, 0x5c, fmt2 & 0xf0);
169 /* MCE and interface config reg */
170 write_codec(dev, 0x49, (fdx ? 0 : 0x4) | (fullcalib ? 0x18 : 0));
171 } else
172 /* MCE and interface config reg */
173 write_codec(dev, 0x49, fdx ? 0x8 : 0xc);
174 outb(0xb, WSS_CODEC_IA(dev->base_addr)); /* leave MCE */
175 if (SCSTATE->crystal && !fullcalib) {
176 restore_flags(flags);
177 return 0;
178 }
179 /*
180 * wait for ACI start
181 */
182 time = 1000;
183 while (!(read_codec(dev, 0x0b) & 0x20))
184 if (!(--time)) {
185 printk(KERN_WARNING "%s: ad1848 auto calibration timed out (1)\n",
186 sm_drvname);
187 restore_flags(flags);
188 return -1;
189 }
190 /*
191 * wait for ACI end
192 */
193 sti();
194 time = jiffies + HZ/4;
195 while ((read_codec(dev, 0x0b) & 0x20) && ((signed)(jiffies - time) < 0));
196 restore_flags(flags);
197 if ((signed)(jiffies - time) >= 0) {
198 printk(KERN_WARNING "%s: ad1848 auto calibration timed out (2)\n",
199 sm_drvname);
200 return -1;
201 }
202 return 0;
203 }
204
205 /* --------------------------------------------------------------------- */
206
207 static int wss_init_codec(struct net_device *dev, struct sm_state *sm, char fdx,
208 unsigned char src_l, unsigned char src_r,
209 int igain_l, int igain_r,
210 int ogain_l, int ogain_r)
211 {
212 unsigned char tmp, reg0, reg1, reg6, reg7;
213 static const signed char irqtab[16] =
214 { -1, -1, 0x10, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20, -1, -1,
215 -1, -1 };
216 static const signed char dmatab[4] = { 1, 2, -1, 3 };
217
218 tmp = inb(WSS_STATUS(dev->base_addr));
219 if ((tmp & 0x3f) != 0x04 && (tmp & 0x3f) != 0x00 &&
220 (tmp & 0x3f) != 0x0f) {
221 printk(KERN_WARNING "sm: WSS card id register not found, "
222 "address 0x%lx, ID register 0x%02x\n",
223 dev->base_addr, (int)tmp);
224 /* return -1; */
225 SCSTATE->revwss = 0;
226 } else {
227 if ((tmp & 0x80) && ((dev->dma == 0) ||
228 ((dev->irq >= 8) && (dev->irq != 9)))) {
229 printk(KERN_ERR "%s: WSS: DMA0 and/or IRQ8..IRQ15 "
230 "(except IRQ9) cannot be used on an 8bit "
231 "card\n", sm_drvname);
232 return -1;
233 }
234 if (dev->irq > 15 || irqtab[dev->irq] == -1) {
235 printk(KERN_ERR "%s: WSS: invalid interrupt %d\n",
236 sm_drvname, (int)dev->irq);
237 return -1;
238 }
239 if (dev->dma > 3 || dmatab[dev->dma] == -1) {
240 printk(KERN_ERR "%s: WSS: invalid dma channel %d\n",
241 sm_drvname, (int)dev->dma);
242 return -1;
243 }
244 tmp = irqtab[dev->irq] | dmatab[dev->dma];
245 /* irq probe */
246 outb((tmp & 0x38) | 0x40, WSS_CONFIG(dev->base_addr));
247 if (!(inb(WSS_STATUS(dev->base_addr)) & 0x40)) {
248 outb(0, WSS_CONFIG(dev->base_addr));
249 printk(KERN_ERR "%s: WSS: IRQ%d is not free!\n",
250 sm_drvname, dev->irq);
251 }
252 outb(tmp, WSS_CONFIG(dev->base_addr));
253 SCSTATE->revwss = inb(WSS_STATUS(dev->base_addr)) & 0x3f;
254 }
255 /*
256 * initialize the codec
257 */
258 if (igain_l < 0)
259 igain_l = 0;
260 if (igain_r < 0)
261 igain_r = 0;
262 if (ogain_l > 0)
263 ogain_l = 0;
264 if (ogain_r > 0)
265 ogain_r = 0;
266 reg0 = (src_l << 6) & 0xc0;
267 reg1 = (src_r << 6) & 0xc0;
268 if (reg0 == 0x80 && igain_l >= 20) {
269 reg0 |= 0x20;
270 igain_l -= 20;
271 }
272 if (reg1 == 0x80 && igain_r >= 20) {
273 reg1 |= 0x20;
274 igain_r -= 20;
275 }
276 if (igain_l > 23)
277 igain_l = 23;
278 if (igain_r > 23)
279 igain_r = 23;
280 reg0 |= igain_l * 2 / 3;
281 reg1 |= igain_r * 2 / 3;
282 reg6 = (ogain_l < -95) ? 0x80 : (ogain_l * (-2) / 3);
283 reg7 = (ogain_r < -95) ? 0x80 : (ogain_r * (-2) / 3);
284 write_codec(dev, 9, 0);
285 write_codec(dev, 0, 0x45);
286 if (read_codec(dev, 0) != 0x45)
287 goto codec_err;
288 write_codec(dev, 0, 0xaa);
289 if (read_codec(dev, 0) != 0xaa)
290 goto codec_err;
291 write_codec(dev, 12, 0x40); /* enable MODE2 */
292 write_codec(dev, 16, 0);
293 write_codec(dev, 0, 0x45);
294 SCSTATE->crystal = (read_codec(dev, 16) != 0x45);
295 write_codec(dev, 0, 0xaa);
296 SCSTATE->crystal &= (read_codec(dev, 16) != 0xaa);
297 if (SCSTATE->crystal) {
298 SCSTATE->revcid = read_codec(dev, 0x19);
299 SCSTATE->revv = (SCSTATE->revcid >> 5) & 7;
300 SCSTATE->revcid &= 7;
301 write_codec(dev, 0x10, 0x80); /* maximum output level */
302 write_codec(dev, 0x11, 0x02); /* xtal enable and no HPF */
303 write_codec(dev, 0x12, 0x80); /* left line input control */
304 write_codec(dev, 0x13, 0x80); /* right line input control */
305 write_codec(dev, 0x16, 0); /* disable alternative freq sel */
306 write_codec(dev, 0x1a, 0xe0); /* mono IO disable */
307 write_codec(dev, 0x1b, 0x00); /* left out no att */
308 write_codec(dev, 0x1d, 0x00); /* right out no att */
309 }
310
311 if (wss_set_codec_fmt(dev, sm, SCSTATE->fmt[0], SCSTATE->fmt[0], fdx, 1))
312 goto codec_err;
313
314 write_codec(dev, 0, reg0); /* left input control */
315 write_codec(dev, 1, reg1); /* right input control */
316 write_codec(dev, 2, 0x80); /* left aux#1 input control */
317 write_codec(dev, 3, 0x80); /* right aux#1 input control */
318 write_codec(dev, 4, 0x80); /* left aux#2 input control */
319 write_codec(dev, 5, 0x80); /* right aux#2 input control */
320 write_codec(dev, 6, reg6); /* left dac control */
321 write_codec(dev, 7, reg7); /* right dac control */
322 write_codec(dev, 0xa, 0x2); /* pin control register */
323 write_codec(dev, 0xd, 0x0); /* digital mix control */
324 SCSTATE->revid = read_codec(dev, 0xc) & 0xf;
325 /*
326 * print revisions
327 */
328 if (SCSTATE->crystal)
329 printk(KERN_INFO "%s: Crystal CODEC ID %d, Chip revision %d, "
330 " Chip ID %d\n", sm_drvname, (int)SCSTATE->revid,
331 (int)SCSTATE->revv, (int)SCSTATE->revcid);
332 else
333 printk(KERN_INFO "%s: WSS revision %d, CODEC revision %d\n",
334 sm_drvname, (int)SCSTATE->revwss,
335 (int)SCSTATE->revid);
336 return 0;
337 codec_err:
338 outb(0, WSS_CONFIG(dev->base_addr));
339 printk(KERN_ERR "%s: no WSS soundcard found at address 0x%lx\n",
340 sm_drvname, dev->base_addr);
341 return -1;
342 }
343
344 /* --------------------------------------------------------------------- */
345
346 static void setup_dma_wss(struct net_device *dev, struct sm_state *sm, int send)
347 {
348 unsigned long flags;
349 static const unsigned char codecmode[2] = { 0x0e, 0x0d };
350 unsigned char oldcodecmode;
351 long abrt;
352 unsigned char fmt;
353 unsigned int numsamps;
354
355 send = !!send;
356 fmt = SCSTATE->fmt[send];
357 save_flags(flags);
358 cli();
359 /*
360 * perform the final DMA sequence to disable the codec request
361 */
362 oldcodecmode = read_codec(dev, 9);
363 write_codec(dev, 9, 0xc); /* disable codec */
364 wss_ack_int(dev);
365 if (read_codec(dev, 11) & 0x10) {
366 dma_setup(sm, oldcodecmode & 1, dev->dma);
367 abrt = 0;
368 while ((read_codec(dev, 11) & 0x10) || ((++abrt) >= 0x10000));
369 }
370 #ifdef CS423X_HOTFIX
371 if (read_codec(dev, 0x8) != fmt || SCSTATE->crystal)
372 wss_set_codec_fmt(dev, sm, fmt, fmt, 0, 0);
373 #else /* CS423X_HOTFIX */
374 if (read_codec(dev, 0x8) != fmt)
375 wss_set_codec_fmt(dev, sm, fmt, fmt, 0, 0);
376 #endif /* CS423X_HOTFIX */
377 numsamps = dma_setup(sm, send, dev->dma) - 1;
378 write_codec(dev, 15, numsamps & 0xff);
379 write_codec(dev, 14, numsamps >> 8);
380 write_codec(dev, 9, codecmode[send]);
381 restore_flags(flags);
382 }
383
384 /* --------------------------------------------------------------------- */
385
386 static void wss_interrupt(int irq, void *dev_id, struct pt_regs *regs)
387 {
388 struct net_device *dev = (struct net_device *)dev_id;
389 struct sm_state *sm = (struct sm_state *)dev->priv;
390 unsigned int curfrag;
391 unsigned int nums;
392
393 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx ||
394 sm->hdrv.magic != HDLCDRV_MAGIC)
395 return;
396 cli();
397 wss_ack_int(dev);
398 disable_dma(dev->dma);
399 clear_dma_ff(dev->dma);
400 nums = dma_ptr(sm, sm->dma.ptt_cnt > 0, dev->dma, &curfrag) - 1;
401 write_codec(dev, 15, nums & 0xff);
402 write_codec(dev, 14, nums >> 8);
403 enable_dma(dev->dma);
404 sm_int_freq(sm);
405 sti();
406 if (sm->dma.ptt_cnt <= 0) {
407 dma_receive(sm, curfrag);
408 hdlcdrv_arbitrate(dev, &sm->hdrv);
409 if (hdlcdrv_ptt(&sm->hdrv)) {
410 /* starting to transmit */
411 disable_dma(dev->dma);
412 hdlcdrv_transmitter(dev, &sm->hdrv); /* prefill HDLC buffer */
413 dma_start_transmit(sm);
414 setup_dma_wss(dev, sm, 1);
415 dma_transmit(sm);
416 }
417 } else if (dma_end_transmit(sm, curfrag)) {
418 /* stopping transmission */
419 disable_dma(dev->dma);
420 dma_init_receive(sm);
421 setup_dma_wss(dev, sm, 0);
422 } else
423 dma_transmit(sm);
424 sm_output_status(sm);
425 hdlcdrv_transmitter(dev, &sm->hdrv);
426 hdlcdrv_receiver(dev, &sm->hdrv);
427 }
428
429 /* --------------------------------------------------------------------- */
430
431 static int wss_open(struct net_device *dev, struct sm_state *sm)
432 {
433 unsigned int dmasz, u;
434
435 if (sizeof(sm->m) < sizeof(struct sc_state_wss)) {
436 printk(KERN_ERR "sm wss: wss state too big: %d > %d\n",
437 sizeof(struct sc_state_wss), sizeof(sm->m));
438 return -ENODEV;
439 }
440 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx)
441 return -ENXIO;
442 if (dev->base_addr <= 0 || dev->base_addr > 0x1000-WSS_EXTENT ||
443 dev->irq < 2 || dev->irq > 15 || dev->dma > 3)
444 return -ENXIO;
445 if (check_region(dev->base_addr, WSS_EXTENT))
446 return -EACCES;
447 /*
448 * check if a card is available
449 */
450 if (wss_init_codec(dev, sm, 0, 1, 1, 0, 0, -45, -45))
451 return -ENODEV;
452 /*
453 * initialize some variables
454 */
455 dma_init_receive(sm);
456 dmasz = (NUM_FRAGMENTS + 1) * sm->dma.ifragsz;
457 u = NUM_FRAGMENTS * sm->dma.ofragsz;
458 if (u > dmasz)
459 dmasz = u;
460 if (!(sm->dma.ibuf = sm->dma.obuf = kmalloc(dmasz, GFP_KERNEL | GFP_DMA)))
461 return -ENOMEM;
462 dma_init_transmit(sm);
463 dma_init_receive(sm);
464
465 memset(&sm->m, 0, sizeof(sm->m));
466 memset(&sm->d, 0, sizeof(sm->d));
467 if (sm->mode_tx->init)
468 sm->mode_tx->init(sm);
469 if (sm->mode_rx->init)
470 sm->mode_rx->init(sm);
471
472 if (request_dma(dev->dma, sm->hwdrv->hw_name)) {
473 kfree(sm->dma.obuf);
474 return -EBUSY;
475 }
476 if (request_irq(dev->irq, wss_interrupt, SA_INTERRUPT,
477 sm->hwdrv->hw_name, dev)) {
478 free_dma(dev->dma);
479 kfree(sm->dma.obuf);
480 return -EBUSY;
481 }
482 request_region(dev->base_addr, WSS_EXTENT, sm->hwdrv->hw_name);
483 setup_dma_wss(dev, sm, 0);
484 return 0;
485 }
486
487 /* --------------------------------------------------------------------- */
488
489 static int wss_close(struct net_device *dev, struct sm_state *sm)
490 {
491 if (!dev || !sm)
492 return -EINVAL;
493 /*
494 * disable interrupts
495 */
496 disable_dma(dev->dma);
497 write_codec(dev, 9, 0xc); /* disable codec */
498 free_irq(dev->irq, dev);
499 free_dma(dev->dma);
500 release_region(dev->base_addr, WSS_EXTENT);
501 kfree(sm->dma.obuf);
502 return 0;
503 }
504
505 /* --------------------------------------------------------------------- */
506
507 static int wss_sethw(struct net_device *dev, struct sm_state *sm, char *mode)
508 {
509 char *cp = strchr(mode, '.');
510 const struct modem_tx_info **mtp = sm_modem_tx_table;
511 const struct modem_rx_info **mrp;
512 int i, j;
513
514 if (!strcmp(mode, "off")) {
515 sm->mode_tx = NULL;
516 sm->mode_rx = NULL;
517 return 0;
518 }
519 if (cp)
520 *cp++ = '\0';
521 else
522 cp = mode;
523 for (; *mtp; mtp++) {
524 if ((*mtp)->loc_storage > sizeof(sm->m)) {
525 printk(KERN_ERR "%s: insufficient storage for modulator %s (%d)\n",
526 sm_drvname, (*mtp)->name, (*mtp)->loc_storage);
527 continue;
528 }
529 if (!(*mtp)->name || strcmp((*mtp)->name, mode))
530 continue;
531 if ((i = wss_srate_index((*mtp)->srate)) < 0)
532 continue;
533 for (mrp = sm_modem_rx_table; *mrp; mrp++) {
534 if ((*mrp)->loc_storage > sizeof(sm->d)) {
535 printk(KERN_ERR "%s: insufficient storage for demodulator %s (%d)\n",
536 sm_drvname, (*mrp)->name, (*mrp)->loc_storage);
537 continue;
538 }
539 if ((*mrp)->name && !strcmp((*mrp)->name, cp) &&
540 ((j = wss_srate_index((*mrp)->srate)) >= 0)) {
541 sm->mode_tx = *mtp;
542 sm->mode_rx = *mrp;
543 SCSTATE->fmt[0] = j;
544 SCSTATE->fmt[1] = i;
545 sm->dma.ifragsz = (sm->mode_rx->srate + 50)/100;
546 sm->dma.ofragsz = (sm->mode_tx->srate + 50)/100;
547 if (sm->dma.ifragsz < sm->mode_rx->overlap)
548 sm->dma.ifragsz = sm->mode_rx->overlap;
549 /* prefer same data format if possible to minimize switching times */
550 sm->dma.i16bit = sm->dma.o16bit = 2;
551 if (sm->mode_rx->srate == sm->mode_tx->srate) {
552 if (sm->mode_rx->demodulator_s16 && sm->mode_tx->modulator_s16)
553 sm->dma.i16bit = sm->dma.o16bit = 1;
554 else if (sm->mode_rx->demodulator_u8 && sm->mode_tx->modulator_u8)
555 sm->dma.i16bit = sm->dma.o16bit = 0;
556 }
557 if (sm->dma.i16bit == 2) {
558 if (sm->mode_rx->demodulator_s16)
559 sm->dma.i16bit = 1;
560 else if (sm->mode_rx->demodulator_u8)
561 sm->dma.i16bit = 0;
562 }
563 if (sm->dma.o16bit == 2) {
564 if (sm->mode_tx->modulator_s16)
565 sm->dma.o16bit = 1;
566 else if (sm->mode_tx->modulator_u8)
567 sm->dma.o16bit = 0;
568 }
569 if (sm->dma.i16bit == 2 || sm->dma.o16bit == 2) {
570 printk(KERN_INFO "%s: mode %s or %s unusable\n", sm_drvname,
571 sm->mode_rx->name, sm->mode_tx->name);
572 sm->mode_tx = NULL;
573 sm->mode_rx = NULL;
574 return -EINVAL;
575 }
576 #ifdef __BIG_ENDIAN
577 /* big endian 16bit only works on crystal cards... */
578 if (sm->dma.i16bit) {
579 SCSTATE->fmt[0] |= 0xc0;
580 sm->dma.ifragsz <<= 1;
581 }
582 if (sm->dma.o16bit) {
583 SCSTATE->fmt[1] |= 0xc0;
584 sm->dma.ofragsz <<= 1;
585 }
586 #else /* __BIG_ENDIAN */
587 if (sm->dma.i16bit) {
588 SCSTATE->fmt[0] |= 0x40;
589 sm->dma.ifragsz <<= 1;
590 }
591 if (sm->dma.o16bit) {
592 SCSTATE->fmt[1] |= 0x40;
593 sm->dma.ofragsz <<= 1;
594 }
595 #endif /* __BIG_ENDIAN */
596 return 0;
597 }
598 }
599 }
600 return -EINVAL;
601 }
602
603 /* --------------------------------------------------------------------- */
604
605 static int wss_ioctl(struct net_device *dev, struct sm_state *sm, struct ifreq *ifr,
606 struct hdlcdrv_ioctl *hi, int cmd)
607 {
608 struct sm_ioctl bi;
609 int i;
610
611 if (cmd != SIOCDEVPRIVATE)
612 return -ENOIOCTLCMD;
613
614 if (hi->cmd == HDLCDRVCTL_MODEMPARMASK)
615 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ |
616 HDLCDRV_PARMASK_DMA | HDLCDRV_PARMASK_SERIOBASE |
617 HDLCDRV_PARMASK_PARIOBASE | HDLCDRV_PARMASK_MIDIIOBASE;
618
619 if (copy_from_user(&bi, ifr->ifr_data, sizeof(bi)))
620 return -EFAULT;
621
622 switch (bi.cmd) {
623 default:
624 return -ENOIOCTLCMD;
625
626 case SMCTL_GETMIXER:
627 i = 0;
628 bi.data.mix.sample_rate = sm->mode_rx->srate;
629 bi.data.mix.bit_rate = sm->hdrv.par.bitrate;
630 bi.data.mix.mixer_type = SCSTATE->crystal ?
631 SM_MIXER_CRYSTAL : SM_MIXER_AD1848;
632 if (((SCSTATE->crystal ? 0x2c0c20fflu: 0x20fflu)
633 >> bi.data.mix.reg) & 1) {
634 bi.data.mix.data = read_codec(dev, bi.data.mix.reg);
635 i = 1;
636 }
637 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
638 return -EFAULT;
639 return i;
640
641 case SMCTL_SETMIXER:
642 if (!capable(CAP_SYS_RAWIO))
643 return -EACCES;
644 if ((bi.data.mix.mixer_type != SM_MIXER_CRYSTAL ||
645 !SCSTATE->crystal) &&
646 (bi.data.mix.mixer_type != SM_MIXER_AD1848 ||
647 bi.data.mix.reg >= 0x10))
648 return -EINVAL;
649 if (!((0x2c0c20fflu >> bi.data.mix.reg) & 1))
650 return -EACCES;
651 write_codec(dev, bi.data.mix.reg, bi.data.mix.data);
652 return 0;
653
654 }
655 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
656 return -EFAULT;
657 return 0;
658
659 }
660
661 /* --------------------------------------------------------------------- */
662
663 const struct hardware_info sm_hw_wss = {
664 "wss", sizeof(struct sc_state_wss),
665 wss_open, wss_close, wss_ioctl, wss_sethw
666 };
667
668 /* --------------------------------------------------------------------- */
669
670 static void setup_fdx_dma_wss(struct net_device *dev, struct sm_state *sm)
671 {
672 unsigned long flags;
673 unsigned char oldcodecmode, codecdma;
674 long abrt;
675 unsigned int osamps, isamps;
676
677 save_flags(flags);
678 cli();
679 /*
680 * perform the final DMA sequence to disable the codec request
681 */
682 oldcodecmode = read_codec(dev, 9);
683 write_codec(dev, 9, 0); /* disable codec DMA */
684 wss_ack_int(dev);
685 if ((codecdma = read_codec(dev, 11)) & 0x10) {
686 dma_setup(sm, 1, dev->dma);
687 dma_setup(sm, 0, sm->hdrv.ptt_out.dma2);
688 abrt = 0;
689 while (((codecdma = read_codec(dev, 11)) & 0x10) || ((++abrt) >= 0x10000));
690 }
691 wss_set_codec_fmt(dev, sm, SCSTATE->fmt[1], SCSTATE->fmt[0], 1, 1);
692 osamps = dma_setup(sm, 1, dev->dma) - 1;
693 isamps = dma_setup(sm, 0, sm->hdrv.ptt_out.dma2) - 1;
694 write_codec(dev, 15, osamps & 0xff);
695 write_codec(dev, 14, osamps >> 8);
696 if (SCSTATE->crystal) {
697 write_codec(dev, 31, isamps & 0xff);
698 write_codec(dev, 30, isamps >> 8);
699 }
700 write_codec(dev, 9, 3);
701 restore_flags(flags);
702 }
703
704 /* --------------------------------------------------------------------- */
705
706 static void wssfdx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
707 {
708 struct net_device *dev = (struct net_device *)dev_id;
709 struct sm_state *sm = (struct sm_state *)dev->priv;
710 unsigned long flags;
711 unsigned char cry_int_src;
712 unsigned icfrag, ocfrag, isamps, osamps;
713
714 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx ||
715 sm->hdrv.magic != HDLCDRV_MAGIC)
716 return;
717 save_flags(flags);
718 cli();
719 if (SCSTATE->crystal) {
720 /* Crystal has an essentially different interrupt handler! */
721 cry_int_src = read_codec(dev, 0x18);
722 wss_ack_int(dev);
723 if (cry_int_src & 0x10) { /* playback interrupt */
724 disable_dma(dev->dma);
725 clear_dma_ff(dev->dma);
726 osamps = dma_ptr(sm, 1, dev->dma, &ocfrag)-1;
727 write_codec(dev, 15, osamps & 0xff);
728 write_codec(dev, 14, osamps >> 8);
729 enable_dma(dev->dma);
730 }
731 if (cry_int_src & 0x20) { /* capture interrupt */
732 disable_dma(sm->hdrv.ptt_out.dma2);
733 clear_dma_ff(sm->hdrv.ptt_out.dma2);
734 isamps = dma_ptr(sm, 0, sm->hdrv.ptt_out.dma2, &icfrag)-1;
735 write_codec(dev, 31, isamps & 0xff);
736 write_codec(dev, 30, isamps >> 8);
737 enable_dma(sm->hdrv.ptt_out.dma2);
738 }
739 restore_flags(flags);
740 sm_int_freq(sm);
741 sti();
742 if (cry_int_src & 0x10) {
743 if (dma_end_transmit(sm, ocfrag))
744 dma_clear_transmit(sm);
745 dma_transmit(sm);
746 }
747 if (cry_int_src & 0x20) {
748 dma_receive(sm, icfrag);
749 hdlcdrv_arbitrate(dev, &sm->hdrv);
750 }
751 sm_output_status(sm);
752 hdlcdrv_transmitter(dev, &sm->hdrv);
753 hdlcdrv_receiver(dev, &sm->hdrv);
754 return;
755 }
756 wss_ack_int(dev);
757 disable_dma(dev->dma);
758 disable_dma(sm->hdrv.ptt_out.dma2);
759 clear_dma_ff(dev->dma);
760 clear_dma_ff(sm->hdrv.ptt_out.dma2);
761 osamps = dma_ptr(sm, 1, dev->dma, &ocfrag)-1;
762 isamps = dma_ptr(sm, 0, sm->hdrv.ptt_out.dma2, &icfrag)-1;
763 write_codec(dev, 15, osamps & 0xff);
764 write_codec(dev, 14, osamps >> 8);
765 if (SCSTATE->crystal) {
766 write_codec(dev, 31, isamps & 0xff);
767 write_codec(dev, 30, isamps >> 8);
768 }
769 enable_dma(dev->dma);
770 enable_dma(sm->hdrv.ptt_out.dma2);
771 restore_flags(flags);
772 sm_int_freq(sm);
773 sti();
774 if (dma_end_transmit(sm, ocfrag))
775 dma_clear_transmit(sm);
776 dma_transmit(sm);
777 dma_receive(sm, icfrag);
778 hdlcdrv_arbitrate(dev, &sm->hdrv);
779 sm_output_status(sm);
780 hdlcdrv_transmitter(dev, &sm->hdrv);
781 hdlcdrv_receiver(dev, &sm->hdrv);
782 }
783
784 /* --------------------------------------------------------------------- */
785
786 static int wssfdx_open(struct net_device *dev, struct sm_state *sm)
787 {
788 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx)
789 return -ENXIO;
790 if (dev->base_addr <= 0 || dev->base_addr > 0x1000-WSS_EXTENT ||
791 dev->irq < 2 || dev->irq > 15 || dev->dma > 3)
792 return -ENXIO;
793 if (check_region(dev->base_addr, WSS_EXTENT))
794 return -EACCES;
795 /*
796 * check if a card is available
797 */
798 if (wss_init_codec(dev, sm, 1, 1, 1, 0, 0, -45, -45))
799 return -ENODEV;
800 /*
801 * initialize some variables
802 */
803 if (!(sm->dma.ibuf = kmalloc(sm->dma.ifragsz * (NUM_FRAGMENTS+1), GFP_KERNEL | GFP_DMA)))
804 return -ENOMEM;
805 if (!(sm->dma.obuf = kmalloc(sm->dma.ofragsz * NUM_FRAGMENTS, GFP_KERNEL | GFP_DMA))) {
806 kfree(sm->dma.ibuf);
807 return -ENOMEM;
808 }
809 dma_init_transmit(sm);
810 dma_init_receive(sm);
811
812 memset(&sm->m, 0, sizeof(sm->m));
813 memset(&sm->d, 0, sizeof(sm->d));
814 if (sm->mode_tx->init)
815 sm->mode_tx->init(sm);
816 if (sm->mode_rx->init)
817 sm->mode_rx->init(sm);
818
819 if (request_dma(dev->dma, sm->hwdrv->hw_name)) {
820 kfree(sm->dma.ibuf);
821 kfree(sm->dma.obuf);
822 return -EBUSY;
823 }
824 if (request_dma(sm->hdrv.ptt_out.dma2, sm->hwdrv->hw_name)) {
825 kfree(sm->dma.ibuf);
826 kfree(sm->dma.obuf);
827 free_dma(dev->dma);
828 return -EBUSY;
829 }
830 if (request_irq(dev->irq, wssfdx_interrupt, SA_INTERRUPT,
831 sm->hwdrv->hw_name, dev)) {
832 kfree(sm->dma.ibuf);
833 kfree(sm->dma.obuf);
834 free_dma(dev->dma);
835 free_dma(sm->hdrv.ptt_out.dma2);
836 return -EBUSY;
837 }
838 request_region(dev->base_addr, WSS_EXTENT, sm->hwdrv->hw_name);
839 setup_fdx_dma_wss(dev, sm);
840 return 0;
841 }
842
843 /* --------------------------------------------------------------------- */
844
845 static int wssfdx_close(struct net_device *dev, struct sm_state *sm)
846 {
847 if (!dev || !sm)
848 return -EINVAL;
849 /*
850 * disable interrupts
851 */
852 disable_dma(dev->dma);
853 disable_dma(sm->hdrv.ptt_out.dma2);
854 write_codec(dev, 9, 0xc); /* disable codec */
855 free_irq(dev->irq, dev);
856 free_dma(dev->dma);
857 free_dma(sm->hdrv.ptt_out.dma2);
858 release_region(dev->base_addr, WSS_EXTENT);
859 kfree(sm->dma.ibuf);
860 kfree(sm->dma.obuf);
861 return 0;
862 }
863
864 /* --------------------------------------------------------------------- */
865
866 static int wssfdx_sethw(struct net_device *dev, struct sm_state *sm, char *mode)
867 {
868 char *cp = strchr(mode, '.');
869 const struct modem_tx_info **mtp = sm_modem_tx_table;
870 const struct modem_rx_info **mrp;
871 int i;
872
873 if (!strcmp(mode, "off")) {
874 sm->mode_tx = NULL;
875 sm->mode_rx = NULL;
876 return 0;
877 }
878 if (cp)
879 *cp++ = '\0';
880 else
881 cp = mode;
882 for (; *mtp; mtp++) {
883 if ((*mtp)->loc_storage > sizeof(sm->m)) {
884 printk(KERN_ERR "%s: insufficient storage for modulator %s (%d)\n",
885 sm_drvname, (*mtp)->name, (*mtp)->loc_storage);
886 continue;
887 }
888 if (!(*mtp)->name || strcmp((*mtp)->name, mode))
889 continue;
890 if ((i = wss_srate_index((*mtp)->srate)) < 0)
891 continue;
892 for (mrp = sm_modem_rx_table; *mrp; mrp++) {
893 if ((*mrp)->loc_storage > sizeof(sm->d)) {
894 printk(KERN_ERR "%s: insufficient storage for demodulator %s (%d)\n",
895 sm_drvname, (*mrp)->name, (*mrp)->loc_storage);
896 continue;
897 }
898 if ((*mrp)->name && !strcmp((*mrp)->name, cp) &&
899 (*mtp)->srate == (*mrp)->srate) {
900 sm->mode_tx = *mtp;
901 sm->mode_rx = *mrp;
902 SCSTATE->fmt[0] = SCSTATE->fmt[1] = i;
903 sm->dma.ifragsz = sm->dma.ofragsz = (sm->mode_rx->srate + 50)/100;
904 if (sm->dma.ifragsz < sm->mode_rx->overlap)
905 sm->dma.ifragsz = sm->mode_rx->overlap;
906 sm->dma.i16bit = sm->dma.o16bit = 2;
907 if (sm->mode_rx->demodulator_s16) {
908 sm->dma.i16bit = 1;
909 sm->dma.ifragsz <<= 1;
910 #ifdef __BIG_ENDIAN /* big endian 16bit only works on crystal cards... */
911 SCSTATE->fmt[0] |= 0xc0;
912 #else /* __BIG_ENDIAN */
913 SCSTATE->fmt[0] |= 0x40;
914 #endif /* __BIG_ENDIAN */
915 } else if (sm->mode_rx->demodulator_u8)
916 sm->dma.i16bit = 0;
917 if (sm->mode_tx->modulator_s16) {
918 sm->dma.o16bit = 1;
919 sm->dma.ofragsz <<= 1;
920 #ifdef __BIG_ENDIAN /* big endian 16bit only works on crystal cards... */
921 SCSTATE->fmt[1] |= 0xc0;
922 #else /* __BIG_ENDIAN */
923 SCSTATE->fmt[1] |= 0x40;
924 #endif /* __BIG_ENDIAN */
925 } else if (sm->mode_tx->modulator_u8)
926 sm->dma.o16bit = 0;
927 if (sm->dma.i16bit == 2 || sm->dma.o16bit == 2) {
928 printk(KERN_INFO "%s: mode %s or %s unusable\n", sm_drvname,
929 sm->mode_rx->name, sm->mode_tx->name);
930 sm->mode_tx = NULL;
931 sm->mode_rx = NULL;
932 return -EINVAL;
933 }
934 return 0;
935 }
936 }
937 }
938 return -EINVAL;
939 }
940
941 /* --------------------------------------------------------------------- */
942
943 static int wssfdx_ioctl(struct net_device *dev, struct sm_state *sm, struct ifreq *ifr,
944 struct hdlcdrv_ioctl *hi, int cmd)
945 {
946 if (cmd != SIOCDEVPRIVATE)
947 return -ENOIOCTLCMD;
948
949 if (hi->cmd == HDLCDRVCTL_MODEMPARMASK)
950 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ |
951 HDLCDRV_PARMASK_DMA | HDLCDRV_PARMASK_DMA2 |
952 HDLCDRV_PARMASK_SERIOBASE | HDLCDRV_PARMASK_PARIOBASE |
953 HDLCDRV_PARMASK_MIDIIOBASE;
954
955 return wss_ioctl(dev, sm, ifr, hi, cmd);
956 }
957
958 /* --------------------------------------------------------------------- */
959
960 const struct hardware_info sm_hw_wssfdx = {
961 "wssfdx", sizeof(struct sc_state_wss),
962 wssfdx_open, wssfdx_close, wssfdx_ioctl, wssfdx_sethw
963 };
964
965 /* --------------------------------------------------------------------- */
966
967 #undef SCSTATE
968