File: /usr/src/linux/drivers/net/mace.c
1 /*
2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/version.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <asm/prom.h>
19 #include <asm/dbdma.h>
20 #include <asm/io.h>
21 #include <asm/pgtable.h>
22 #include "mace.h"
23
24 static struct net_device *mace_devs;
25 static int port_aaui = -1;
26
27 MODULE_PARM(port_aaui, "i");
28 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
29
30 #define N_RX_RING 8
31 #define N_TX_RING 6
32 #define MAX_TX_ACTIVE 1
33 #define NCMDS_TX 1 /* dma commands per element in tx ring */
34 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
35 #define TX_TIMEOUT HZ /* 1 second */
36
37 /* Bits in transmit DMA status */
38 #define TX_DMA_ERR 0x80
39
40 struct mace_data {
41 volatile struct mace *mace;
42 volatile struct dbdma_regs *tx_dma;
43 int tx_dma_intr;
44 volatile struct dbdma_regs *rx_dma;
45 int rx_dma_intr;
46 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
47 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
48 struct sk_buff *rx_bufs[N_RX_RING];
49 int rx_fill;
50 int rx_empty;
51 struct sk_buff *tx_bufs[N_TX_RING];
52 int tx_fill;
53 int tx_empty;
54 unsigned char maccc;
55 unsigned char tx_fullup;
56 unsigned char tx_active;
57 unsigned char tx_bad_runt;
58 struct net_device_stats stats;
59 struct timer_list tx_timeout;
60 int timeout_active;
61 int port_aaui;
62 struct net_device *next_mace;
63 };
64
65 /*
66 * Number of bytes of private data per MACE: allow enough for
67 * the rx and tx dma commands plus a branch dma command each,
68 * and another 16 bytes to allow us to align the dma command
69 * buffers on a 16 byte boundary.
70 */
71 #define PRIV_BYTES (sizeof(struct mace_data) \
72 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
73
74 static int bitrev(int);
75 static int mace_probe(void);
76 static void mace_probe1(struct device_node *mace);
77 static int mace_open(struct net_device *dev);
78 static int mace_close(struct net_device *dev);
79 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
80 static struct net_device_stats *mace_stats(struct net_device *dev);
81 static void mace_set_multicast(struct net_device *dev);
82 static void mace_reset(struct net_device *dev);
83 static int mace_set_address(struct net_device *dev, void *addr);
84 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
85 static void mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);
86 static void mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs);
87 static void mace_set_timeout(struct net_device *dev);
88 static void mace_tx_timeout(unsigned long data);
89 static inline void dbdma_reset(volatile struct dbdma_regs *dma);
90 static inline void mace_clean_rings(struct mace_data *mp);
91 static void __mace_set_address(struct net_device *dev, void *addr);
92
93 /*
94 * If we can't get a skbuff when we need it, we use this area for DMA.
95 */
96 static unsigned char *dummy_buf;
97
98 /* Bit-reverse one byte of an ethernet hardware address. */
99 static inline int
100 bitrev(int b)
101 {
102 int d = 0, i;
103
104 for (i = 0; i < 8; ++i, b >>= 1)
105 d = (d << 1) | (b & 1);
106 return d;
107 }
108
109 static int __init mace_probe(void)
110 {
111 struct device_node *mace;
112
113 for (mace = find_devices("mace"); mace != NULL; mace = mace->next)
114 mace_probe1(mace);
115 return mace_devs? 0: -ENODEV;
116 }
117
118 static void __init mace_probe1(struct device_node *mace)
119 {
120 int j, rev;
121 struct net_device *dev;
122 struct mace_data *mp;
123 unsigned char *addr;
124
125 if (mace->n_addrs != 3 || mace->n_intrs != 3) {
126 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
127 mace->full_name);
128 return;
129 }
130
131 addr = get_property(mace, "mac-address", NULL);
132 if (addr == NULL) {
133 addr = get_property(mace, "local-mac-address", NULL);
134 if (addr == NULL) {
135 printk(KERN_ERR "Can't get mac-address for MACE %s\n",
136 mace->full_name);
137 return;
138 }
139 }
140
141 if (dummy_buf == NULL) {
142 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
143 if (dummy_buf == NULL) {
144 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
145 return;
146 }
147 }
148
149 dev = init_etherdev(0, PRIV_BYTES);
150 if (!dev)
151 return;
152 SET_MODULE_OWNER(dev);
153
154 mp = dev->priv;
155 dev->base_addr = mace->addrs[0].address;
156 mp->mace = (volatile struct mace *)
157 ioremap(mace->addrs[0].address, 0x1000);
158 dev->irq = mace->intrs[0].line;
159
160 printk(KERN_INFO "%s: MACE at", dev->name);
161 rev = addr[0] == 0 && addr[1] == 0xA0;
162 for (j = 0; j < 6; ++j) {
163 dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
164 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
165 }
166 printk(", chip revision %d.%d\n",
167 in_8(&mp->mace->chipid_hi), in_8(&mp->mace->chipid_lo));
168
169 mp = (struct mace_data *) dev->priv;
170 mp->maccc = ENXMT | ENRCV;
171 mp->tx_dma = (volatile struct dbdma_regs *)
172 ioremap(mace->addrs[1].address, 0x1000);
173 mp->tx_dma_intr = mace->intrs[1].line;
174 mp->rx_dma = (volatile struct dbdma_regs *)
175 ioremap(mace->addrs[2].address, 0x1000);
176 mp->rx_dma_intr = mace->intrs[2].line;
177
178 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
179 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
180
181 memset(&mp->stats, 0, sizeof(mp->stats));
182 memset((char *) mp->tx_cmds, 0,
183 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
184 init_timer(&mp->tx_timeout);
185 mp->timeout_active = 0;
186
187 if (port_aaui >= 0)
188 mp->port_aaui = port_aaui;
189 else {
190 /* Apple Network Server uses the AAUI port */
191 if (machine_is_compatible("AAPL,ShinerESB"))
192 mp->port_aaui = 1;
193 else {
194 #ifdef CONFIG_MACE_AAUI_PORT
195 mp->port_aaui = 1;
196 #else
197 mp->port_aaui = 0;
198 #endif
199 }
200 }
201
202 dev->open = mace_open;
203 dev->stop = mace_close;
204 dev->hard_start_xmit = mace_xmit_start;
205 dev->get_stats = mace_stats;
206 dev->set_multicast_list = mace_set_multicast;
207 dev->set_mac_address = mace_set_address;
208
209 ether_setup(dev);
210
211 mace_reset(dev);
212
213 if (request_irq(dev->irq, mace_interrupt, 0, "MACE", dev))
214 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
215 if (request_irq(mace->intrs[1].line, mace_txdma_intr, 0, "MACE-txdma",
216 dev))
217 printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[1].line);
218 if (request_irq(mace->intrs[2].line, mace_rxdma_intr, 0, "MACE-rxdma",
219 dev))
220 printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[2].line);
221
222 mp->next_mace = mace_devs;
223 mace_devs = dev;
224 }
225
226 static void dbdma_reset(volatile struct dbdma_regs *dma)
227 {
228 int i;
229
230 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
231
232 /*
233 * Yes this looks peculiar, but apparently it needs to be this
234 * way on some machines.
235 */
236 for (i = 200; i > 0; --i)
237 if (ld_le32(&dma->control) & RUN)
238 udelay(1);
239 }
240
241 static void mace_reset(struct net_device *dev)
242 {
243 struct mace_data *mp = (struct mace_data *) dev->priv;
244 volatile struct mace *mb = mp->mace;
245 int i;
246
247 /* soft-reset the chip */
248 i = 200;
249 while (--i) {
250 out_8(&mb->biucc, SWRST);
251 if (in_8(&mb->biucc) & SWRST) {
252 udelay(10);
253 continue;
254 }
255 break;
256 }
257 if (!i) {
258 printk(KERN_ERR "mace: cannot reset chip!\n");
259 return;
260 }
261
262 out_8(&mb->imr, 0xff); /* disable all intrs for now */
263 i = in_8(&mb->ir);
264 out_8(&mb->maccc, 0); /* turn off tx, rx */
265
266 out_8(&mb->biucc, XMTSP_64);
267 out_8(&mb->utr, RTRD);
268 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
269 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
270 out_8(&mb->rcvfc, 0);
271
272 /* load up the hardware address */
273 __mace_set_address(dev, dev->dev_addr);
274
275 /* clear the multicast filter */
276 out_8(&mb->iac, ADDRCHG | LOGADDR);
277 while ((in_8(&mb->iac) & ADDRCHG) != 0)
278 ;
279 for (i = 0; i < 8; ++i) {
280 out_8(&mb->ladrf, 0);
281 }
282 /* done changing address */
283 out_8(&mb->iac, 0);
284
285 if (mp->port_aaui)
286 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
287 else
288 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
289 }
290
291 static void __mace_set_address(struct net_device *dev, void *addr)
292 {
293 volatile struct mace *mb = ((struct mace_data *) dev->priv)->mace;
294 unsigned char *p = addr;
295 int i;
296
297 /* load up the hardware address */
298 out_8(&mb->iac, ADDRCHG | PHYADDR);
299 while ((in_8(&mb->iac) & ADDRCHG) != 0)
300 ;
301 for (i = 0; i < 6; ++i)
302 out_8(&mb->padr, dev->dev_addr[i] = p[i]);
303 }
304
305 static int mace_set_address(struct net_device *dev, void *addr)
306 {
307 struct mace_data *mp = (struct mace_data *) dev->priv;
308 volatile struct mace *mb = mp->mace;
309 unsigned long flags;
310
311 save_flags(flags); cli();
312
313 __mace_set_address(dev, addr);
314
315 out_8(&mb->iac, 0);
316 /* note: setting ADDRCHG clears ENRCV */
317 out_8(&mb->maccc, mp->maccc);
318
319 restore_flags(flags);
320 return 0;
321 }
322
323 static int mace_open(struct net_device *dev)
324 {
325 struct mace_data *mp = (struct mace_data *) dev->priv;
326 volatile struct mace *mb = mp->mace;
327 volatile struct dbdma_regs *rd = mp->rx_dma;
328 volatile struct dbdma_regs *td = mp->tx_dma;
329 volatile struct dbdma_cmd *cp;
330 int i;
331 struct sk_buff *skb;
332 unsigned char *data;
333
334 /* reset the chip */
335 mace_reset(dev);
336
337 /* initialize list of sk_buffs for receiving and set up recv dma */
338 mace_clean_rings(mp);
339 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
340 cp = mp->rx_cmds;
341 for (i = 0; i < N_RX_RING - 1; ++i) {
342 skb = dev_alloc_skb(RX_BUFLEN + 2);
343 if (skb == 0) {
344 data = dummy_buf;
345 } else {
346 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
347 data = skb->data;
348 }
349 mp->rx_bufs[i] = skb;
350 st_le16(&cp->req_count, RX_BUFLEN);
351 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
352 st_le32(&cp->phy_addr, virt_to_bus(data));
353 cp->xfer_status = 0;
354 ++cp;
355 }
356 mp->rx_bufs[i] = 0;
357 st_le16(&cp->command, DBDMA_STOP);
358 mp->rx_fill = i;
359 mp->rx_empty = 0;
360
361 /* Put a branch back to the beginning of the receive command list */
362 ++cp;
363 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
364 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
365
366 /* start rx dma */
367 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
368 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
369 out_le32(&rd->control, (RUN << 16) | RUN);
370
371 /* put a branch at the end of the tx command list */
372 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
373 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
374 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
375
376 /* reset tx dma */
377 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
378 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
379 mp->tx_fill = 0;
380 mp->tx_empty = 0;
381 mp->tx_fullup = 0;
382 mp->tx_active = 0;
383 mp->tx_bad_runt = 0;
384
385 /* turn it on! */
386 out_8(&mb->maccc, mp->maccc);
387 /* enable all interrupts except receive interrupts */
388 out_8(&mb->imr, RCVINT);
389
390 return 0;
391 }
392
393 static inline void mace_clean_rings(struct mace_data *mp)
394 {
395 int i;
396
397 /* free some skb's */
398 for (i = 0; i < N_RX_RING; ++i) {
399 if (mp->rx_bufs[i] != 0) {
400 dev_kfree_skb(mp->rx_bufs[i]);
401 mp->rx_bufs[i] = 0;
402 }
403 }
404 for (i = mp->tx_empty; i != mp->tx_fill; ) {
405 dev_kfree_skb(mp->tx_bufs[i]);
406 if (++i >= N_TX_RING)
407 i = 0;
408 }
409 }
410
411 static int mace_close(struct net_device *dev)
412 {
413 struct mace_data *mp = (struct mace_data *) dev->priv;
414 volatile struct mace *mb = mp->mace;
415 volatile struct dbdma_regs *rd = mp->rx_dma;
416 volatile struct dbdma_regs *td = mp->tx_dma;
417
418 /* disable rx and tx */
419 out_8(&mb->maccc, 0);
420 out_8(&mb->imr, 0xff); /* disable all intrs */
421
422 /* disable rx and tx dma */
423 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
424 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
425
426 mace_clean_rings(mp);
427
428 return 0;
429 }
430
431 static inline void mace_set_timeout(struct net_device *dev)
432 {
433 struct mace_data *mp = (struct mace_data *) dev->priv;
434 unsigned long flags;
435
436 save_flags(flags);
437 cli();
438 if (mp->timeout_active)
439 del_timer(&mp->tx_timeout);
440 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
441 mp->tx_timeout.function = mace_tx_timeout;
442 mp->tx_timeout.data = (unsigned long) dev;
443 add_timer(&mp->tx_timeout);
444 mp->timeout_active = 1;
445 restore_flags(flags);
446 }
447
448 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
449 {
450 struct mace_data *mp = (struct mace_data *) dev->priv;
451 volatile struct dbdma_regs *td = mp->tx_dma;
452 volatile struct dbdma_cmd *cp, *np;
453 unsigned long flags;
454 int fill, next, len;
455
456 /* see if there's a free slot in the tx ring */
457 save_flags(flags); cli();
458 fill = mp->tx_fill;
459 next = fill + 1;
460 if (next >= N_TX_RING)
461 next = 0;
462 if (next == mp->tx_empty) {
463 netif_stop_queue(dev);
464 mp->tx_fullup = 1;
465 restore_flags(flags);
466 return 1; /* can't take it at the moment */
467 }
468 restore_flags(flags);
469
470 /* partially fill in the dma command block */
471 len = skb->len;
472 if (len > ETH_FRAME_LEN) {
473 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
474 len = ETH_FRAME_LEN;
475 }
476 mp->tx_bufs[fill] = skb;
477 cp = mp->tx_cmds + NCMDS_TX * fill;
478 st_le16(&cp->req_count, len);
479 st_le32(&cp->phy_addr, virt_to_bus(skb->data));
480
481 np = mp->tx_cmds + NCMDS_TX * next;
482 out_le16(&np->command, DBDMA_STOP);
483
484 /* poke the tx dma channel */
485 save_flags(flags);
486 cli();
487 mp->tx_fill = next;
488 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
489 out_le16(&cp->xfer_status, 0);
490 out_le16(&cp->command, OUTPUT_LAST);
491 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
492 ++mp->tx_active;
493 mace_set_timeout(dev);
494 }
495 if (++next >= N_TX_RING)
496 next = 0;
497 if (next == mp->tx_empty)
498 netif_stop_queue(dev);
499 restore_flags(flags);
500
501 return 0;
502 }
503
504 static struct net_device_stats *mace_stats(struct net_device *dev)
505 {
506 struct mace_data *p = (struct mace_data *) dev->priv;
507
508 return &p->stats;
509 }
510
511 /*
512 * CRC polynomial - used in working out multicast filter bits.
513 */
514 #define CRC_POLY 0xedb88320
515
516 static void mace_set_multicast(struct net_device *dev)
517 {
518 struct mace_data *mp = (struct mace_data *) dev->priv;
519 volatile struct mace *mb = mp->mace;
520 int i, j, k, b;
521 unsigned long crc;
522
523 mp->maccc &= ~PROM;
524 if (dev->flags & IFF_PROMISC) {
525 mp->maccc |= PROM;
526 } else {
527 unsigned char multicast_filter[8];
528 struct dev_mc_list *dmi = dev->mc_list;
529
530 if (dev->flags & IFF_ALLMULTI) {
531 for (i = 0; i < 8; i++)
532 multicast_filter[i] = 0xff;
533 } else {
534 for (i = 0; i < 8; i++)
535 multicast_filter[i] = 0;
536 for (i = 0; i < dev->mc_count; i++) {
537 crc = ~0;
538 for (j = 0; j < 6; ++j) {
539 b = dmi->dmi_addr[j];
540 for (k = 0; k < 8; ++k) {
541 if ((crc ^ b) & 1)
542 crc = (crc >> 1) ^ CRC_POLY;
543 else
544 crc >>= 1;
545 b >>= 1;
546 }
547 }
548 j = crc >> 26; /* bit number in multicast_filter */
549 multicast_filter[j >> 3] |= 1 << (j & 7);
550 dmi = dmi->next;
551 }
552 }
553 #if 0
554 printk("Multicast filter :");
555 for (i = 0; i < 8; i++)
556 printk("%02x ", multicast_filter[i]);
557 printk("\n");
558 #endif
559
560 out_8(&mb->iac, ADDRCHG | LOGADDR);
561 while ((in_8(&mb->iac) & ADDRCHG) != 0)
562 ;
563 for (i = 0; i < 8; ++i) {
564 out_8(&mb->ladrf, multicast_filter[i]);
565 }
566 }
567 /* reset maccc */
568 out_8(&mb->maccc, mp->maccc);
569 }
570
571 static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
572 {
573 volatile struct mace *mb = mp->mace;
574 static int mace_babbles, mace_jabbers;
575
576 if (intr & MPCO)
577 mp->stats.rx_missed_errors += 256;
578 mp->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
579 if (intr & RNTPCO)
580 mp->stats.rx_length_errors += 256;
581 mp->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
582 if (intr & CERR)
583 ++mp->stats.tx_heartbeat_errors;
584 if (intr & BABBLE)
585 if (mace_babbles++ < 4)
586 printk(KERN_DEBUG "mace: babbling transmitter\n");
587 if (intr & JABBER)
588 if (mace_jabbers++ < 4)
589 printk(KERN_DEBUG "mace: jabbering transceiver\n");
590 }
591
592 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
593 {
594 struct net_device *dev = (struct net_device *) dev_id;
595 struct mace_data *mp = (struct mace_data *) dev->priv;
596 volatile struct mace *mb = mp->mace;
597 volatile struct dbdma_regs *td = mp->tx_dma;
598 volatile struct dbdma_cmd *cp;
599 int intr, fs, i, stat, x;
600 int xcount, dstat;
601 /* static int mace_last_fs, mace_last_xcount; */
602
603 intr = in_8(&mb->ir); /* read interrupt register */
604 in_8(&mb->xmtrc); /* get retries */
605 mace_handle_misc_intrs(mp, intr);
606
607 i = mp->tx_empty;
608 while (in_8(&mb->pr) & XMTSV) {
609 del_timer(&mp->tx_timeout);
610 mp->timeout_active = 0;
611 /*
612 * Clear any interrupt indication associated with this status
613 * word. This appears to unlatch any error indication from
614 * the DMA controller.
615 */
616 intr = in_8(&mb->ir);
617 if (intr != 0)
618 mace_handle_misc_intrs(mp, intr);
619 if (mp->tx_bad_runt) {
620 fs = in_8(&mb->xmtfs);
621 mp->tx_bad_runt = 0;
622 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
623 continue;
624 }
625 dstat = ld_le32(&td->status);
626 /* stop DMA controller */
627 out_le32(&td->control, RUN << 16);
628 /*
629 * xcount is the number of complete frames which have been
630 * written to the fifo but for which status has not been read.
631 */
632 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
633 if (xcount == 0 || (dstat & DEAD)) {
634 /*
635 * If a packet was aborted before the DMA controller has
636 * finished transferring it, it seems that there are 2 bytes
637 * which are stuck in some buffer somewhere. These will get
638 * transmitted as soon as we read the frame status (which
639 * reenables the transmit data transfer request). Turning
640 * off the DMA controller and/or resetting the MACE doesn't
641 * help. So we disable auto-padding and FCS transmission
642 * so the two bytes will only be a runt packet which should
643 * be ignored by other stations.
644 */
645 out_8(&mb->xmtfc, DXMTFCS);
646 }
647 fs = in_8(&mb->xmtfs);
648 if ((fs & XMTSV) == 0) {
649 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
650 fs, xcount, dstat);
651 mace_reset(dev);
652 /*
653 * XXX mace likes to hang the machine after a xmtfs error.
654 * This is hard to reproduce, reseting *may* help
655 */
656 }
657 cp = mp->tx_cmds + NCMDS_TX * i;
658 stat = ld_le16(&cp->xfer_status);
659 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
660 /*
661 * Check whether there were in fact 2 bytes written to
662 * the transmit FIFO.
663 */
664 udelay(1);
665 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
666 if (x != 0) {
667 /* there were two bytes with an end-of-packet indication */
668 mp->tx_bad_runt = 1;
669 mace_set_timeout(dev);
670 } else {
671 /*
672 * Either there weren't the two bytes buffered up, or they
673 * didn't have an end-of-packet indication.
674 * We flush the transmit FIFO just in case (by setting the
675 * XMTFWU bit with the transmitter disabled).
676 */
677 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
678 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
679 udelay(1);
680 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
681 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
682 }
683 }
684 /* dma should have finished */
685 if (i == mp->tx_fill) {
686 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
687 fs, xcount, dstat);
688 continue;
689 }
690 /* Update stats */
691 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
692 ++mp->stats.tx_errors;
693 if (fs & LCAR)
694 ++mp->stats.tx_carrier_errors;
695 if (fs & (UFLO|LCOL|RTRY))
696 ++mp->stats.tx_aborted_errors;
697 } else {
698 mp->stats.tx_bytes += mp->tx_bufs[i]->len;
699 ++mp->stats.tx_packets;
700 }
701 dev_kfree_skb_irq(mp->tx_bufs[i]);
702 --mp->tx_active;
703 if (++i >= N_TX_RING)
704 i = 0;
705 #if 0
706 mace_last_fs = fs;
707 mace_last_xcount = xcount;
708 #endif
709 }
710
711 if (i != mp->tx_empty) {
712 mp->tx_fullup = 0;
713 netif_wake_queue(dev);
714 }
715 mp->tx_empty = i;
716 i += mp->tx_active;
717 if (i >= N_TX_RING)
718 i -= N_TX_RING;
719 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
720 do {
721 /* set up the next one */
722 cp = mp->tx_cmds + NCMDS_TX * i;
723 out_le16(&cp->xfer_status, 0);
724 out_le16(&cp->command, OUTPUT_LAST);
725 ++mp->tx_active;
726 if (++i >= N_TX_RING)
727 i = 0;
728 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
729 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
730 mace_set_timeout(dev);
731 }
732 }
733
734 static void mace_tx_timeout(unsigned long data)
735 {
736 struct net_device *dev = (struct net_device *) data;
737 struct mace_data *mp = (struct mace_data *) dev->priv;
738 volatile struct mace *mb = mp->mace;
739 volatile struct dbdma_regs *td = mp->tx_dma;
740 volatile struct dbdma_regs *rd = mp->rx_dma;
741 volatile struct dbdma_cmd *cp;
742 unsigned long flags;
743 int i;
744
745 save_flags(flags);
746 cli();
747 mp->timeout_active = 0;
748 if (mp->tx_active == 0 && !mp->tx_bad_runt)
749 goto out;
750
751 /* update various counters */
752 mace_handle_misc_intrs(mp, in_8(&mb->ir));
753
754 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
755
756 /* turn off both tx and rx and reset the chip */
757 out_8(&mb->maccc, 0);
758 printk(KERN_ERR "mace: transmit timeout - resetting\n");
759 dbdma_reset(td);
760 mace_reset(dev);
761
762 /* restart rx dma */
763 cp = bus_to_virt(ld_le32(&rd->cmdptr));
764 dbdma_reset(rd);
765 out_le16(&cp->xfer_status, 0);
766 out_le32(&rd->cmdptr, virt_to_bus(cp));
767 out_le32(&rd->control, (RUN << 16) | RUN);
768
769 /* fix up the transmit side */
770 i = mp->tx_empty;
771 mp->tx_active = 0;
772 ++mp->stats.tx_errors;
773 if (mp->tx_bad_runt) {
774 mp->tx_bad_runt = 0;
775 } else if (i != mp->tx_fill) {
776 dev_kfree_skb(mp->tx_bufs[i]);
777 if (++i >= N_TX_RING)
778 i = 0;
779 mp->tx_empty = i;
780 }
781 mp->tx_fullup = 0;
782 netif_wake_queue(dev);
783 if (i != mp->tx_fill) {
784 cp = mp->tx_cmds + NCMDS_TX * i;
785 out_le16(&cp->xfer_status, 0);
786 out_le16(&cp->command, OUTPUT_LAST);
787 out_le32(&td->cmdptr, virt_to_bus(cp));
788 out_le32(&td->control, (RUN << 16) | RUN);
789 ++mp->tx_active;
790 mace_set_timeout(dev);
791 }
792
793 /* turn it back on */
794 out_8(&mb->imr, RCVINT);
795 out_8(&mb->maccc, mp->maccc);
796
797 out:
798 restore_flags(flags);
799 }
800
801 static void mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs)
802 {
803 }
804
805 static void mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs)
806 {
807 struct net_device *dev = (struct net_device *) dev_id;
808 struct mace_data *mp = (struct mace_data *) dev->priv;
809 volatile struct dbdma_regs *rd = mp->rx_dma;
810 volatile struct dbdma_cmd *cp, *np;
811 int i, nb, stat, next;
812 struct sk_buff *skb;
813 unsigned frame_status;
814 static int mace_lost_status;
815 unsigned char *data;
816
817 for (i = mp->rx_empty; i != mp->rx_fill; ) {
818 cp = mp->rx_cmds + i;
819 stat = ld_le16(&cp->xfer_status);
820 if ((stat & ACTIVE) == 0) {
821 next = i + 1;
822 if (next >= N_RX_RING)
823 next = 0;
824 np = mp->rx_cmds + next;
825 if (next != mp->rx_fill
826 && (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
827 printk(KERN_DEBUG "mace: lost a status word\n");
828 ++mace_lost_status;
829 } else
830 break;
831 }
832 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
833 out_le16(&cp->command, DBDMA_STOP);
834 /* got a packet, have a look at it */
835 skb = mp->rx_bufs[i];
836 if (skb == 0) {
837 ++mp->stats.rx_dropped;
838 } else if (nb > 8) {
839 data = skb->data;
840 frame_status = (data[nb-3] << 8) + data[nb-4];
841 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
842 ++mp->stats.rx_errors;
843 if (frame_status & RS_OFLO)
844 ++mp->stats.rx_over_errors;
845 if (frame_status & RS_FRAMERR)
846 ++mp->stats.rx_frame_errors;
847 if (frame_status & RS_FCSERR)
848 ++mp->stats.rx_crc_errors;
849 } else {
850 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
851 * FCS on frames with 802.3 headers. This means that Ethernet
852 * frames have 8 extra octets at the end, while 802.3 frames
853 * have only 4. We need to correctly account for this. */
854 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
855 nb -= 4;
856 else /* Ethernet header; mace includes FCS */
857 nb -= 8;
858 skb_put(skb, nb);
859 skb->dev = dev;
860 skb->protocol = eth_type_trans(skb, dev);
861 mp->stats.rx_bytes += skb->len;
862 netif_rx(skb);
863 dev->last_rx = jiffies;
864 mp->rx_bufs[i] = 0;
865 ++mp->stats.rx_packets;
866 }
867 } else {
868 ++mp->stats.rx_errors;
869 ++mp->stats.rx_length_errors;
870 }
871
872 /* advance to next */
873 if (++i >= N_RX_RING)
874 i = 0;
875 }
876 mp->rx_empty = i;
877
878 i = mp->rx_fill;
879 for (;;) {
880 next = i + 1;
881 if (next >= N_RX_RING)
882 next = 0;
883 if (next == mp->rx_empty)
884 break;
885 cp = mp->rx_cmds + i;
886 skb = mp->rx_bufs[i];
887 if (skb == 0) {
888 skb = dev_alloc_skb(RX_BUFLEN + 2);
889 if (skb != 0) {
890 skb_reserve(skb, 2);
891 mp->rx_bufs[i] = skb;
892 }
893 }
894 st_le16(&cp->req_count, RX_BUFLEN);
895 data = skb? skb->data: dummy_buf;
896 st_le32(&cp->phy_addr, virt_to_bus(data));
897 out_le16(&cp->xfer_status, 0);
898 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
899 #if 0
900 if ((ld_le32(&rd->status) & ACTIVE) != 0) {
901 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
902 while ((in_le32(&rd->status) & ACTIVE) != 0)
903 ;
904 }
905 #endif
906 i = next;
907 }
908 if (i != mp->rx_fill) {
909 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
910 mp->rx_fill = i;
911 }
912 }
913
914 MODULE_AUTHOR("Paul Mackerras");
915 MODULE_DESCRIPTION("PowerMac MACE driver.");
916
917 static void __exit mace_cleanup (void)
918 {
919 struct net_device *dev;
920 struct mace_data *mp;
921
922 while ((dev = mace_devs) != 0) {
923 mp = (struct mace_data *) mace_devs->priv;
924 mace_devs = mp->next_mace;
925
926 free_irq(dev->irq, dev);
927 free_irq(mp->tx_dma_intr, dev);
928 free_irq(mp->rx_dma_intr, dev);
929
930 unregister_netdev(dev);
931 kfree(dev);
932 }
933 if (dummy_buf != NULL) {
934 kfree(dummy_buf);
935 dummy_buf = NULL;
936 }
937 }
938
939 module_init(mace_probe);
940 module_exit(mace_cleanup);
941