File: /usr/src/linux/drivers/net/natsemi.c
1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2 /*
3 Written/copyright 1999-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL. License for under other terms may be
11 available. Contact the original author for details.
12
13 The original author may be reached as becker@scyld.com, or at
14 Scyld Computing Corporation
15 410 Severn Ave., Suite 210
16 Annapolis MD 21403
17
18 Support information and updates available at
19 http://www.scyld.com/network/netsemi.html
20
21
22 Linux kernel modifications:
23
24 Version 1.0.1:
25 - Spinlock fixes
26 - Bug fixes and better intr performance (Tjeerd)
27 Version 1.0.2:
28 - Now reads correct MAC address from eeprom
29 Version 1.0.3:
30 - Eliminate redundant priv->tx_full flag
31 - Call netif_start_queue from dev->tx_timeout
32 - wmb() in start_tx() to flush data
33 - Update Tx locking
34 - Clean up PCI enable (davej)
35 Version 1.0.4:
36 - Merge Donald Becker's natsemi.c version 1.07
37 Version 1.0.5:
38 - { fill me in }
39 Version 1.0.6:
40 * ethtool support (jgarzik)
41 * Proper initialization of the card (which sometimes
42 fails to occur and leaves the card in a non-functional
43 state). (uzi)
44
45 * Some documented register settings to optimize some
46 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
47
48 * Polling of the PHY intr for stuff like link state
49 change and auto- negotiation to finally work properly. (uzi)
50
51 * One-liner removal of a duplicate declaration of
52 netdev_error(). (uzi)
53
54 Version 1.0.7: (Manfred Spraul)
55 * pci dma
56 * SMP locking update
57 * full reset added into tx_timeout
58 * correct multicast hash generation (both big and little endian)
59 [copied from a natsemi driver version
60 from Myrio Corporation, Greg Smith]
61 * suspend/resume
62
63 version 1.0.8 (Tim Hockin <thockin@sun.com>)
64 * ETHTOOL_* support
65 * Wake on lan support (Erik Gilling)
66 * MXDMA fixes for serverworks
67 * EEPROM reload
68 TODO:
69 * big endian support with CFG:BEM instead of cpu_to_le32
70 * support for an external PHY
71 * flow control
72 */
73
74 #define DRV_NAME "natsemi"
75 #define DRV_VERSION "1.07+LK1.0.8"
76 #define DRV_RELDATE "Aug 07, 2001"
77
78
79 /* Updated to recommendations in pci-skeleton v2.03. */
80
81 /* Automatically extracted configuration info:
82 probe-func: natsemi_probe
83 config-in: tristate 'National Semiconductor DP8381x series PCI Ethernet support' CONFIG_NATSEMI
84
85 c-help-name: National Semiconductor DP8381x series PCI Ethernet support
86 c-help-symbol: CONFIG_NATSEMI
87 c-help: This driver is for the National Semiconductor DP8381x series,
88 c-help: including the 83815 chip.
89 c-help: More specific information and updates are available from
90 c-help: http://www.scyld.com/network/natsemi.html
91 */
92
93 /* The user-configurable values.
94 These may be modified when a driver module is loaded.*/
95
96 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
97 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
98 static int max_interrupt_work = 20;
99 static int mtu;
100 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
101 This chip uses a 512 element hash table based on the Ethernet CRC. */
102 static int multicast_filter_limit = 100;
103
104 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
105 Setting to > 1518 effectively disables this feature. */
106 static int rx_copybreak;
107
108 /* Used to pass the media type, etc.
109 Both 'options[]' and 'full_duplex[]' should exist for driver
110 interoperability.
111 The media type is usually passed in 'options[]'.
112 */
113 #define MAX_UNITS 8 /* More are supported, limit only on options */
114 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
115 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
116
117 /* Operational parameters that are set at compile time. */
118
119 /* Keep the ring sizes a power of two for compile efficiency.
120 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
121 Making the Tx ring too large decreases the effectiveness of channel
122 bonding and packet priority.
123 There are no ill effects from too-large receive rings. */
124 #define TX_RING_SIZE 16
125 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
126 #define RX_RING_SIZE 32
127
128 /* Operational parameters that usually are not changed. */
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (2*HZ)
131
132 #define NATSEMI_HW_TIMEOUT 400
133
134 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
135
136 #if !defined(__OPTIMIZE__)
137 #warning You must compile this file with the correct options!
138 #warning See the last lines of the source file.
139 #error You must compile this driver with "-O".
140 #endif
141
142 #include <linux/config.h>
143 #include <linux/module.h>
144 #include <linux/kernel.h>
145 #include <linux/string.h>
146 #include <linux/timer.h>
147 #include <linux/errno.h>
148 #include <linux/ioport.h>
149 #include <linux/slab.h>
150 #include <linux/interrupt.h>
151 #include <linux/pci.h>
152 #include <linux/netdevice.h>
153 #include <linux/etherdevice.h>
154 #include <linux/skbuff.h>
155 #include <linux/init.h>
156 #include <linux/spinlock.h>
157 #include <linux/ethtool.h>
158 #include <linux/delay.h>
159 #include <linux/rtnetlink.h>
160 #include <linux/mii.h>
161 #include <asm/processor.h> /* Processor type for cache alignment. */
162 #include <asm/bitops.h>
163 #include <asm/io.h>
164 #include <asm/uaccess.h>
165
166 /* These identify the driver base version and may not be removed. */
167 static char version[] __devinitdata =
168 KERN_INFO DRV_NAME ".c:v1.07 1/9/2001 Written by Donald Becker <becker@scyld.com>\n"
169 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
170 KERN_INFO " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE " Jeff Garzik, Tjeerd Mulder)\n";
171
172 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
173 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
174 MODULE_PARM(max_interrupt_work, "i");
175 MODULE_PARM(mtu, "i");
176 MODULE_PARM(debug, "i");
177 MODULE_PARM(rx_copybreak, "i");
178 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
179 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
180 MODULE_PARM_DESC(max_interrupt_work, "DP8381x maximum events handled per interrupt");
181 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
182 MODULE_PARM_DESC(debug, "DP8381x debug level (0-5)");
183 MODULE_PARM_DESC(rx_copybreak, "DP8381x copy breakpoint for copy-only-tiny-frames");
184 MODULE_PARM_DESC(options, "DP8381x: Bits 0-3: media type, bit 17: full duplex");
185 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
186
187 /*
188 Theory of Operation
189
190 I. Board Compatibility
191
192 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
193 It also works with other chips in in the DP83810 series.
194
195 II. Board-specific settings
196
197 This driver requires the PCI interrupt line to be valid.
198 It honors the EEPROM-set values.
199
200 III. Driver operation
201
202 IIIa. Ring buffers
203
204 This driver uses two statically allocated fixed-size descriptor lists
205 formed into rings by a branch from the final descriptor to the beginning of
206 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
207 The NatSemi design uses a 'next descriptor' pointer that the driver forms
208 into a list.
209
210 IIIb/c. Transmit/Receive Structure
211
212 This driver uses a zero-copy receive and transmit scheme.
213 The driver allocates full frame size skbuffs for the Rx ring buffers at
214 open() time and passes the skb->data field to the chip as receive data
215 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
216 a fresh skbuff is allocated and the frame is copied to the new skbuff.
217 When the incoming frame is larger, the skbuff is passed directly up the
218 protocol stack. Buffers consumed this way are replaced by newly allocated
219 skbuffs in a later phase of receives.
220
221 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
222 using a full-sized skbuff for small frames vs. the copying costs of larger
223 frames. New boards are typically used in generously configured machines
224 and the underfilled buffers have negligible impact compared to the benefit of
225 a single allocation size, so the default value of zero results in never
226 copying packets. When copying is done, the cost is usually mitigated by using
227 a combined copy/checksum routine. Copying also preloads the cache, which is
228 most useful with small frames.
229
230 A subtle aspect of the operation is that unaligned buffers are not permitted
231 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
232 longword aligned for further processing. On copies frames are put into the
233 skbuff at an offset of "+2", 16-byte aligning the IP header.
234
235 IIId. Synchronization
236
237 The driver runs as two independent, single-threaded flows of control. One
238 is the send-packet routine, which enforces single-threaded use by the
239 dev->tbusy flag. The other thread is the interrupt handler, which is single
240 threaded by the hardware and interrupt handling software.
241
242 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
243 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
244 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
245 the 'lp->tx_full' flag.
246
247 The interrupt handler has exclusive control over the Rx ring and records stats
248 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
249 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
250 clears both the tx_full and tbusy flags.
251
252 IV. Notes
253
254 NatSemi PCI network controllers are very uncommon.
255
256 IVb. References
257
258 http://www.scyld.com/expert/100mbps.html
259 http://www.scyld.com/expert/NWay.html
260 Datasheet is available from:
261 http://www.national.com/pf/DP/DP83815.html
262
263 IVc. Errata
264
265 None characterised.
266 */
267
268
269
270 enum pcistuff {
271 PCI_USES_IO = 0x01,
272 PCI_USES_MEM = 0x02,
273 PCI_USES_MASTER = 0x04,
274 PCI_ADDR0 = 0x08,
275 PCI_ADDR1 = 0x10,
276 };
277
278 /* MMIO operations required */
279 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
280
281
282 /* array of board data directly indexed by pci_tbl[x].driver_data */
283 static struct {
284 const char *name;
285 unsigned long flags;
286 } natsemi_pci_info[] __devinitdata = {
287 { "NatSemi DP83815", PCI_IOTYPE },
288 };
289
290 static struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
291 { 0x100B, 0x0020, PCI_ANY_ID, PCI_ANY_ID, },
292 { 0, },
293 };
294 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
295
296 /* Offsets to the device registers.
297 Unlike software-only systems, device drivers interact with complex hardware.
298 It's not useful to define symbolic names for every register bit in the
299 device.
300 */
301 enum register_offsets {
302 ChipCmd=0x00, ChipConfig=0x04, EECtrl=0x08, PCIBusCfg=0x0C,
303 IntrStatus=0x10, IntrMask=0x14, IntrEnable=0x18,
304 TxRingPtr=0x20, TxConfig=0x24,
305 RxRingPtr=0x30, RxConfig=0x34, ClkRun=0x3C,
306 WOLCmd=0x40, PauseCmd=0x44, RxFilterAddr=0x48, RxFilterData=0x4C,
307 BootRomAddr=0x50, BootRomData=0x54, SiliconRev=0x58, StatsCtrl=0x5C,
308 StatsData=0x60, RxPktErrs=0x60, RxMissed=0x68, RxCRCErrs=0x64,
309 BasicControl=0x80, BasicStatus=0x84,
310 AnegAdv=0x90, AnegPeer = 0x94, PhyStatus=0xC0, MIntrCtrl=0xC4,
311 MIntrStatus=0xC8, PhyCtrl=0xE4,
312
313 /* These are from the spec, around page 78... on a separate table.
314 * The meaning of these registers depend on the value of PGSEL. */
315 PGSEL=0xCC, PMDCSR=0xE4, TSTDAT=0xFC, DSPCFG=0xF4, SDCFG=0x8C
316 };
317
318 /* misc PCI space registers */
319 enum PCISpaceRegs {
320 PCIPM=0x44,
321 };
322
323 /* Bit in ChipCmd. */
324 enum ChipCmdBits {
325 ChipReset=0x100, RxReset=0x20, TxReset=0x10, RxOff=0x08, RxOn=0x04,
326 TxOff=0x02, TxOn=0x01,
327 };
328
329 enum PCIBusCfgBits {
330 EepromReload=0x4,
331 };
332
333 /* Bits in the interrupt status/mask registers. */
334 enum intr_status_bits {
335 IntrRxDone=0x0001, IntrRxIntr=0x0002, IntrRxErr=0x0004, IntrRxEarly=0x0008,
336 IntrRxIdle=0x0010, IntrRxOverrun=0x0020,
337 IntrTxDone=0x0040, IntrTxIntr=0x0080, IntrTxErr=0x0100,
338 IntrTxIdle=0x0200, IntrTxUnderrun=0x0400,
339 StatsMax=0x0800, LinkChange=0x4000,
340 WOLPkt=0x2000,
341 RxResetDone=0x1000000, TxResetDone=0x2000000,
342 IntrPCIErr=0x00f00000,
343 IntrNormalSummary=0x025f, IntrAbnormalSummary=0xCD20,
344 };
345
346 /* Bits in the RxMode register. */
347 enum rx_mode_bits {
348 AcceptErr=0x20, AcceptRunt=0x10,
349 AcceptBroadcast=0xC0000000,
350 AcceptMulticast=0x00200000, AcceptAllMulticast=0x20000000,
351 AcceptAllPhys=0x10000000, AcceptMyPhys=0x08000000,
352 };
353
354 /* Bits in WOLCmd register. */
355 enum wol_bits {
356 WakePhy=0x1, WakeUnicast=0x2, WakeMulticast=0x4, WakeBroadcast=0x8,
357 WakeArp=0x10, WakePMatch0=0x20, WakePMatch1=0x40, WakePMatch2=0x80,
358 WakePMatch3=0x100, WakeMagic=0x200, WakeMagicSecure=0x400,
359 SecureHack=0x100000, WokePhy=0x400000, WokeUnicast=0x800000,
360 WokeMulticast=0x1000000, WokeBroadcast=0x2000000, WokeArp=0x4000000,
361 WokePMatch0=0x8000000, WokePMatch1=0x10000000, WokePMatch2=0x20000000,
362 WokePMatch3=0x40000000, WokeMagic=0x80000000, WakeOptsSummary=0x7ff
363 };
364
365 enum aneg_bits {
366 Aneg10BaseT=0x20, Aneg10BaseTFull=0x40,
367 Aneg100BaseT=0x80, Aneg100BaseTFull=0x100,
368 };
369
370 enum config_bits {
371 CfgPhyDis=0x200, CfgPhyRst=0x400, CfgAnegEnable=0x2000,
372 CfgAneg100=0x4000, CfgAnegFull=0x8000, CfgAnegDone=0x8000000,
373 CfgFullDuplex=0x20000000,
374 CfgSpeed100=0x40000000, CfgLink=0x80000000,
375 };
376
377 enum bmcr_bits {
378 BMCRDuplex=0x100, BMCRAnegRestart=0x200, BMCRAnegEnable=0x1000,
379 BMCRSpeed=0x2000, BMCRPhyReset=0x8000,
380 };
381
382 /* The Rx and Tx buffer descriptors. */
383 /* Note that using only 32 bit fields simplifies conversion to big-endian
384 architectures. */
385 struct netdev_desc {
386 u32 next_desc;
387 s32 cmd_status;
388 u32 addr;
389 u32 software_use;
390 };
391
392 /* Bits in network_desc.status */
393 enum desc_status_bits {
394 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
395 DescNoCRC=0x10000000,
396 DescPktOK=0x08000000, RxTooLong=0x00400000,
397 };
398
399 struct netdev_private {
400 /* Descriptor rings first for alignment. */
401 dma_addr_t ring_dma;
402 struct netdev_desc* rx_ring;
403 struct netdev_desc* tx_ring;
404 /* The addresses of receive-in-place skbuffs. */
405 struct sk_buff* rx_skbuff[RX_RING_SIZE];
406 dma_addr_t rx_dma[RX_RING_SIZE];
407 /* The saved address of a sent-in-place packet/buffer, for later free(). */
408 struct sk_buff* tx_skbuff[TX_RING_SIZE];
409 dma_addr_t tx_dma[TX_RING_SIZE];
410 struct net_device_stats stats;
411 struct timer_list timer; /* Media monitoring timer. */
412 /* Frequently used values: keep some adjacent for cache effect. */
413 struct pci_dev *pci_dev;
414 struct netdev_desc *rx_head_desc;
415 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
416 unsigned int cur_tx, dirty_tx;
417 unsigned int rx_buf_sz; /* Based on MTU+slack. */
418 /* These values are keep track of the transceiver/media in use. */
419 unsigned int full_duplex;
420 /* Rx filter. */
421 u32 cur_rx_mode;
422 u32 rx_filter[16];
423 /* FIFO and PCI burst thresholds. */
424 u32 tx_config, rx_config;
425 /* original contents of ClkRun register */
426 u32 SavedClkRun;
427 /* MII transceiver section. */
428 u16 advertising; /* NWay media advertisement */
429 unsigned int iosize;
430 spinlock_t lock;
431 };
432
433 static int eeprom_read(long ioaddr, int location);
434 static int mdio_read(struct net_device *dev, int phy_id, int location);
435 static void natsemi_reset(struct net_device *dev);
436 static int netdev_open(struct net_device *dev);
437 static void check_link(struct net_device *dev);
438 static void netdev_timer(unsigned long data);
439 static void tx_timeout(struct net_device *dev);
440 static int alloc_ring(struct net_device *dev);
441 static void init_ring(struct net_device *dev);
442 static void drain_ring(struct net_device *dev);
443 static void free_ring(struct net_device *dev);
444 static void init_registers(struct net_device *dev);
445 static int start_tx(struct sk_buff *skb, struct net_device *dev);
446 static void intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
447 static void netdev_error(struct net_device *dev, int intr_status);
448 static void netdev_rx(struct net_device *dev);
449 static void netdev_tx_done(struct net_device *dev);
450 static void __set_rx_mode(struct net_device *dev);
451 static void set_rx_mode(struct net_device *dev);
452 static void __get_stats(struct net_device *dev);
453 static struct net_device_stats *get_stats(struct net_device *dev);
454 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
455 static int netdev_set_wol(struct net_device *dev, u32 newval);
456 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
457 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
458 static int netdev_get_sopass(struct net_device *dev, u8 *data);
459 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
460 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
461 static int netdev_close(struct net_device *dev);
462
463
464 static int __devinit natsemi_probe1 (struct pci_dev *pdev,
465 const struct pci_device_id *ent)
466 {
467 struct net_device *dev;
468 struct netdev_private *np;
469 int i, option, irq, chip_idx = ent->driver_data;
470 static int find_cnt = -1;
471 unsigned long ioaddr, iosize;
472 const int pcibar = 1; /* PCI base address register */
473 int prev_eedata;
474 u32 tmp;
475
476 /* when built into the kernel, we only print version if device is found */
477 #ifndef MODULE
478 static int printed_version;
479 if (!printed_version++)
480 printk(version);
481 #endif
482
483 i = pci_enable_device(pdev);
484 if (i) return i;
485
486 /* natsemi has a non-standard PM control register
487 * in PCI config space. Some boards apparently need
488 * to be brought to D0 in this manner.
489 */
490 pci_read_config_dword(pdev, PCIPM, &tmp);
491 if (tmp & (0x03|0x100)) {
492 /* D0 state, disable PME assertion */
493 u32 newtmp = tmp & ~(0x03|0x100);
494 pci_write_config_dword(pdev, PCIPM, newtmp);
495 }
496
497 find_cnt++;
498 ioaddr = pci_resource_start(pdev, pcibar);
499 iosize = pci_resource_len(pdev, pcibar);
500 irq = pdev->irq;
501
502 if (natsemi_pci_info[chip_idx].flags & PCI_USES_MASTER)
503 pci_set_master(pdev);
504
505 dev = alloc_etherdev(sizeof (struct netdev_private));
506 if (!dev)
507 return -ENOMEM;
508 SET_MODULE_OWNER(dev);
509
510 i = pci_request_regions(pdev, dev->name);
511 if (i) {
512 kfree(dev);
513 return i;
514 }
515
516 {
517 void *mmio = ioremap (ioaddr, iosize);
518 if (!mmio) {
519 pci_release_regions(pdev);
520 kfree(dev);
521 return -ENOMEM;
522 }
523 ioaddr = (unsigned long) mmio;
524 }
525
526 /* Work around the dropped serial bit. */
527 prev_eedata = eeprom_read(ioaddr, 6);
528 for (i = 0; i < 3; i++) {
529 int eedata = eeprom_read(ioaddr, i + 7);
530 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
531 dev->dev_addr[i*2+1] = eedata >> 7;
532 prev_eedata = eedata;
533 }
534
535 dev->base_addr = ioaddr;
536 dev->irq = irq;
537
538 np = dev->priv;
539
540 np->pci_dev = pdev;
541 pci_set_drvdata(pdev, dev);
542 np->iosize = iosize;
543 spin_lock_init(&np->lock);
544
545 /* Reset the chip to erase previous misconfiguration. */
546 natsemi_reset(dev);
547 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
548 if (dev->mem_start)
549 option = dev->mem_start;
550
551 /* The lower four bits are the media type. */
552 if (option > 0) {
553 if (option & 0x200)
554 np->full_duplex = 1;
555 if (option & 15)
556 printk(KERN_INFO "%s: ignoring user supplied media type %d",
557 dev->name, option & 15);
558 }
559 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
560 np->full_duplex = 1;
561
562 /* The chip-specific entries in the device structure. */
563 dev->open = &netdev_open;
564 dev->hard_start_xmit = &start_tx;
565 dev->stop = &netdev_close;
566 dev->get_stats = &get_stats;
567 dev->set_multicast_list = &set_rx_mode;
568 dev->do_ioctl = &netdev_ioctl;
569 dev->tx_timeout = &tx_timeout;
570 dev->watchdog_timeo = TX_TIMEOUT;
571
572 if (mtu)
573 dev->mtu = mtu;
574
575 i = register_netdev(dev);
576 if (i) {
577 pci_release_regions(pdev);
578 unregister_netdev(dev);
579 kfree(dev);
580 pci_set_drvdata(pdev, NULL);
581 return i;
582 }
583 netif_carrier_off(dev);
584
585 printk(KERN_INFO "%s: %s at 0x%lx, ",
586 dev->name, natsemi_pci_info[chip_idx].name, ioaddr);
587 for (i = 0; i < ETH_ALEN-1; i++)
588 printk("%2.2x:", dev->dev_addr[i]);
589 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
590
591 np->advertising = mdio_read(dev, 1, 4);
592 if ((readl(ioaddr + ChipConfig) & 0xe000) != 0xe000) {
593 u32 chip_config = readl(ioaddr + ChipConfig);
594 printk(KERN_INFO "%s: Transceiver default autonegotiation %s "
595 "10%s %s duplex.\n",
596 dev->name,
597 chip_config & 0x2000 ? "enabled, advertise" : "disabled, force",
598 chip_config & 0x4000 ? "0" : "",
599 chip_config & 0x8000 ? "full" : "half");
600 }
601 printk(KERN_INFO "%s: Transceiver status 0x%4.4x advertising %4.4x.\n",
602 dev->name, (int)readl(ioaddr + BasicStatus),
603 np->advertising);
604
605 return 0;
606 }
607
608
609 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
610 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
611
612 /* Delay between EEPROM clock transitions.
613 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
614 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
615 made udelay() unreliable.
616 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
617 depricated.
618 */
619 #define eeprom_delay(ee_addr) readl(ee_addr)
620
621 enum EEPROM_Ctrl_Bits {
622 EE_ShiftClk=0x04, EE_DataIn=0x01, EE_ChipSelect=0x08, EE_DataOut=0x02,
623 };
624 #define EE_Write0 (EE_ChipSelect)
625 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
626
627 /* The EEPROM commands include the alway-set leading bit. */
628 enum EEPROM_Cmds {
629 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
630 };
631
632 static int eeprom_read(long addr, int location)
633 {
634 int i;
635 int retval = 0;
636 int ee_addr = addr + EECtrl;
637 int read_cmd = location | EE_ReadCmd;
638 writel(EE_Write0, ee_addr);
639
640 /* Shift the read command bits out. */
641 for (i = 10; i >= 0; i--) {
642 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
643 writel(dataval, ee_addr);
644 eeprom_delay(ee_addr);
645 writel(dataval | EE_ShiftClk, ee_addr);
646 eeprom_delay(ee_addr);
647 }
648 writel(EE_ChipSelect, ee_addr);
649 eeprom_delay(ee_addr);
650
651 for (i = 0; i < 16; i++) {
652 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
653 eeprom_delay(ee_addr);
654 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
655 writel(EE_ChipSelect, ee_addr);
656 eeprom_delay(ee_addr);
657 }
658
659 /* Terminate the EEPROM access. */
660 writel(EE_Write0, ee_addr);
661 writel(0, ee_addr);
662 return retval;
663 }
664
665 /* MII transceiver control section.
666 The 83815 series has an internal transceiver, and we present the
667 management registers as if they were MII connected. */
668
669 static int mdio_read(struct net_device *dev, int phy_id, int location)
670 {
671 if (phy_id == 1 && location < 32)
672 return readl(dev->base_addr+BasicControl+(location<<2))&0xffff;
673 else
674 return 0xffff;
675 }
676
677 static void natsemi_reset(struct net_device *dev)
678 {
679 int i;
680
681 writel(ChipReset, dev->base_addr + ChipCmd);
682 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
683 if (!(readl(dev->base_addr + ChipCmd) & ChipReset))
684 break;
685 udelay(5);
686 }
687 if (i==NATSEMI_HW_TIMEOUT && debug) {
688 printk(KERN_INFO "%s: reset did not complete in %d usec.\n",
689 dev->name, i*5);
690 } else if (debug > 2) {
691 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
692 dev->name, i*5);
693 }
694
695 writel(EepromReload, dev->base_addr + PCIBusCfg);
696 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
697 if (!(readl(dev->base_addr + PCIBusCfg) & EepromReload))
698 break;
699 udelay(5);
700 }
701 if (i==NATSEMI_HW_TIMEOUT && debug) {
702 printk(KERN_INFO "%s: EEPROM did not reload in %d usec.\n",
703 dev->name, i*5);
704 } else if (debug > 2) {
705 printk(KERN_DEBUG "%s: EEPROM reloaded in %d usec.\n",
706 dev->name, i*5);
707 }
708 }
709
710
711 static int netdev_open(struct net_device *dev)
712 {
713 struct netdev_private *np = dev->priv;
714 long ioaddr = dev->base_addr;
715 int i;
716
717 /* Reset the chip, just in case. */
718 natsemi_reset(dev);
719
720 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
721 if (i) return i;
722
723 if (debug > 1)
724 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
725 dev->name, dev->irq);
726 i = alloc_ring(dev);
727 if (i < 0) {
728 free_irq(dev->irq, dev);
729 return i;
730 }
731 init_ring(dev);
732 init_registers(dev);
733
734 netif_start_queue(dev);
735
736 if (debug > 2)
737 printk(KERN_DEBUG "%s: Done netdev_open(), status: %x.\n",
738 dev->name, (int)readl(ioaddr + ChipCmd));
739
740 /* Set the timer to check for link beat. */
741 init_timer(&np->timer);
742 np->timer.expires = jiffies + 3*HZ;
743 np->timer.data = (unsigned long)dev;
744 np->timer.function = &netdev_timer; /* timer handler */
745 add_timer(&np->timer);
746
747 return 0;
748 }
749
750 static void check_link(struct net_device *dev)
751 {
752 struct netdev_private *np = dev->priv;
753 long ioaddr = dev->base_addr;
754 int duplex;
755 int chipcfg = readl(ioaddr + ChipConfig);
756
757 if(!(chipcfg & 0x80000000)) {
758 if (netif_carrier_ok(dev)) {
759 if (debug)
760 printk(KERN_INFO "%s: no link. Disabling watchdog.\n",
761 dev->name);
762 netif_carrier_off(dev);
763 }
764 return;
765 }
766 if (!netif_carrier_ok(dev)) {
767 if (debug)
768 printk(KERN_INFO "%s: link is back. Enabling watchdog.\n",
769 dev->name);
770 netif_carrier_on(dev);
771 }
772
773 duplex = np->full_duplex || (chipcfg & 0x20000000 ? 1 : 0);
774
775 /* if duplex is set then bit 28 must be set, too */
776 if (duplex ^ !!(np->rx_config & 0x10000000)) {
777 if (debug)
778 printk(KERN_INFO "%s: Setting %s-duplex based on negotiated link"
779 " capability.\n", dev->name,
780 duplex ? "full" : "half");
781 if (duplex) {
782 np->rx_config |= 0x10000000;
783 np->tx_config |= 0xC0000000;
784 } else {
785 np->rx_config &= ~0x10000000;
786 np->tx_config &= ~0xC0000000;
787 }
788 writel(np->tx_config, ioaddr + TxConfig);
789 writel(np->rx_config, ioaddr + RxConfig);
790 }
791 }
792
793 static void init_registers(struct net_device *dev)
794 {
795 struct netdev_private *np = dev->priv;
796 long ioaddr = dev->base_addr;
797 int i;
798
799 if (debug > 4)
800 printk(KERN_DEBUG "%s: found silicon revision %xh.\n",
801 dev->name, readl(ioaddr + SiliconRev));
802
803 /* On page 78 of the spec, they recommend some settings for "optimum
804 performance" to be done in sequence. These settings optimize some
805 of the 100Mbit autodetection circuitry. They say we only want to
806 do this for rev C of the chip, but engineers at NSC (Bradley
807 Kennedy) recommends always setting them. If you don't, you get
808 errors on some autonegotiations that make the device unusable.
809 */
810 writew(0x0001, ioaddr + PGSEL);
811 writew(0x189C, ioaddr + PMDCSR);
812 writew(0x0000, ioaddr + TSTDAT);
813 writew(0x5040, ioaddr + DSPCFG);
814 writew(0x008C, ioaddr + SDCFG);
815 writew(0x0000, ioaddr + PGSEL);
816
817 /* Enable PHY Specific event based interrupts. Link state change
818 and Auto-Negotiation Completion are among the affected.
819 */
820 writew(0x0002, ioaddr + MIntrCtrl);
821
822 writel(np->ring_dma, ioaddr + RxRingPtr);
823 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc), ioaddr + TxRingPtr);
824
825 for (i = 0; i < ETH_ALEN; i += 2) {
826 writel(i, ioaddr + RxFilterAddr);
827 writew(dev->dev_addr[i] + (dev->dev_addr[i+1] << 8),
828 ioaddr + RxFilterData);
829 }
830
831 /* Initialize other registers.
832 * Configure the PCI bus bursts and FIFO thresholds.
833 * Configure for standard, in-spec Ethernet.
834 * Start with half-duplex. check_link will update
835 * to the correct settings.
836 */
837
838 /* DRTH: 2: start tx if 64 bytes are in the fifo
839 * FLTH: 0x10: refill with next packet if 512 bytes are free
840 * MXDMA: 0: up to 256 byte bursts.
841 * MXDMA must be <= FLTH
842 * ECRETRY=1
843 * ATP=1
844 */
845 np->tx_config = 0x10f01002;
846 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
847 * MXDMA 0: up to 256 byte bursts
848 */
849 np->rx_config = 0x700020;
850 writel(np->tx_config, ioaddr + TxConfig);
851 writel(np->rx_config, ioaddr + RxConfig);
852
853 /* Disable PME:
854 * The PME bit is initialized from the EEPROM contents.
855 * PCI cards probably have PME disabled, but motherboard
856 * implementations may have PME set to enable WakeOnLan.
857 * With PME set the chip will scan incoming packets but
858 * nothing will be written to memory. */
859 np->SavedClkRun = readl(ioaddr + ClkRun);
860 writel(np->SavedClkRun & ~0x100, ioaddr + ClkRun);
861
862 check_link(dev);
863 __set_rx_mode(dev);
864
865 /* Enable interrupts by setting the interrupt mask. */
866 writel(IntrNormalSummary | IntrAbnormalSummary, ioaddr + IntrMask);
867 writel(1, ioaddr + IntrEnable);
868
869 writel(RxOn | TxOn, ioaddr + ChipCmd);
870 writel(4, ioaddr + StatsCtrl); /* Clear Stats */
871 }
872
873 static void netdev_timer(unsigned long data)
874 {
875 struct net_device *dev = (struct net_device *)data;
876 struct netdev_private *np = dev->priv;
877 int next_tick = 60*HZ;
878
879 if (debug > 3) {
880 /* DO NOT read the IntrStatus register,
881 * a read clears any pending interrupts.
882 */
883 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
884 dev->name);
885 }
886 spin_lock_irq(&np->lock);
887 check_link(dev);
888 spin_unlock_irq(&np->lock);
889 np->timer.expires = jiffies + next_tick;
890 add_timer(&np->timer);
891 }
892
893 static void tx_timeout(struct net_device *dev)
894 {
895 struct netdev_private *np = dev->priv;
896 long ioaddr = dev->base_addr;
897
898 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
899 " resetting...\n", dev->name, (int)readl(ioaddr + TxRingPtr));
900
901 {
902 int i;
903 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
904 for (i = 0; i < RX_RING_SIZE; i++)
905 printk(" %8.8x", (unsigned int)np->rx_ring[i].cmd_status);
906 printk("\n"KERN_DEBUG" Tx ring %p: ", np->tx_ring);
907 for (i = 0; i < TX_RING_SIZE; i++)
908 printk(" %4.4x", np->tx_ring[i].cmd_status);
909 printk("\n");
910 }
911 spin_lock_irq(&np->lock);
912 natsemi_reset(dev);
913 drain_ring(dev);
914 init_ring(dev);
915 init_registers(dev);
916 spin_unlock_irq(&np->lock);
917
918 dev->trans_start = jiffies;
919 np->stats.tx_errors++;
920 netif_wake_queue(dev);
921 }
922
923 static int alloc_ring(struct net_device *dev)
924 {
925 struct netdev_private *np = dev->priv;
926 np->rx_ring = pci_alloc_consistent(np->pci_dev,
927 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
928 &np->ring_dma);
929 if (!np->rx_ring)
930 return -ENOMEM;
931 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
932 return 0;
933 }
934
935 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
936 static void init_ring(struct net_device *dev)
937 {
938 struct netdev_private *np = dev->priv;
939 int i;
940
941 np->cur_rx = np->cur_tx = 0;
942 np->dirty_rx = np->dirty_tx = 0;
943
944 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
945 np->rx_head_desc = &np->rx_ring[0];
946
947 /* Initialize all Rx descriptors. */
948 for (i = 0; i < RX_RING_SIZE; i++) {
949 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma+sizeof(struct netdev_desc)*(i+1));
950 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
951 np->rx_skbuff[i] = NULL;
952 }
953 /* Mark the last entry as wrapping the ring. */
954 np->rx_ring[i-1].next_desc = cpu_to_le32(np->ring_dma);
955
956 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
957 for (i = 0; i < RX_RING_SIZE; i++) {
958 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
959 np->rx_skbuff[i] = skb;
960 if (skb == NULL)
961 break;
962 skb->dev = dev; /* Mark as being used by this device. */
963 np->rx_dma[i] = pci_map_single(np->pci_dev,
964 skb->data, skb->len, PCI_DMA_FROMDEVICE);
965 np->rx_ring[i].addr = cpu_to_le32(np->rx_dma[i]);
966 np->rx_ring[i].cmd_status = cpu_to_le32(DescIntr | np->rx_buf_sz);
967 }
968 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
969
970 for (i = 0; i < TX_RING_SIZE; i++) {
971 np->tx_skbuff[i] = NULL;
972 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
973 +sizeof(struct netdev_desc)*(i+1+RX_RING_SIZE));
974 np->tx_ring[i].cmd_status = 0;
975 }
976 np->tx_ring[i-1].next_desc = cpu_to_le32(np->ring_dma
977 +sizeof(struct netdev_desc)*(RX_RING_SIZE));
978 }
979
980 static void drain_ring(struct net_device *dev)
981 {
982 struct netdev_private *np = dev->priv;
983 int i;
984
985 /* Free all the skbuffs in the Rx queue. */
986 for (i = 0; i < RX_RING_SIZE; i++) {
987 np->rx_ring[i].cmd_status = 0;
988 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
989 if (np->rx_skbuff[i]) {
990 pci_unmap_single(np->pci_dev,
991 np->rx_dma[i],
992 np->rx_skbuff[i]->len,
993 PCI_DMA_FROMDEVICE);
994 dev_kfree_skb(np->rx_skbuff[i]);
995 }
996 np->rx_skbuff[i] = NULL;
997 }
998 for (i = 0; i < TX_RING_SIZE; i++) {
999 if (np->tx_skbuff[i]) {
1000 pci_unmap_single(np->pci_dev,
1001 np->rx_dma[i],
1002 np->rx_skbuff[i]->len,
1003 PCI_DMA_TODEVICE);
1004 dev_kfree_skb(np->tx_skbuff[i]);
1005 }
1006 np->tx_skbuff[i] = NULL;
1007 }
1008 }
1009
1010 static void free_ring(struct net_device *dev)
1011 {
1012 struct netdev_private *np = dev->priv;
1013 pci_free_consistent(np->pci_dev,
1014 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1015 np->rx_ring, np->ring_dma);
1016 }
1017
1018 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1019 {
1020 struct netdev_private *np = dev->priv;
1021 unsigned entry;
1022
1023 /* Note: Ordering is important here, set the field with the
1024 "ownership" bit last, and only then increment cur_tx. */
1025
1026 /* Calculate the next Tx descriptor entry. */
1027 entry = np->cur_tx % TX_RING_SIZE;
1028
1029 np->tx_skbuff[entry] = skb;
1030 np->tx_dma[entry] = pci_map_single(np->pci_dev,
1031 skb->data,skb->len, PCI_DMA_TODEVICE);
1032
1033 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
1034
1035 spin_lock_irq(&np->lock);
1036
1037 #if 0
1038 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | DescIntr | skb->len);
1039 #else
1040 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
1041 #endif
1042 /* StrongARM: Explicitly cache flush np->tx_ring and skb->data,skb->len. */
1043 wmb();
1044 np->cur_tx++;
1045 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
1046 netdev_tx_done(dev);
1047 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
1048 netif_stop_queue(dev);
1049 }
1050 spin_unlock_irq(&np->lock);
1051
1052 /* Wake the potentially-idle transmit channel. */
1053 writel(TxOn, dev->base_addr + ChipCmd);
1054
1055 dev->trans_start = jiffies;
1056
1057 if (debug > 4) {
1058 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1059 dev->name, np->cur_tx, entry);
1060 }
1061 return 0;
1062 }
1063
1064 static void netdev_tx_done(struct net_device *dev)
1065 {
1066 struct netdev_private *np = dev->priv;
1067
1068 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1069 int entry = np->dirty_tx % TX_RING_SIZE;
1070 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn)) {
1071 if (debug > 4)
1072 printk(KERN_DEBUG "%s: tx frame #%d is busy.\n",
1073 dev->name, np->dirty_tx);
1074 break;
1075 }
1076 if (debug > 4)
1077 printk(KERN_DEBUG "%s: tx frame #%d finished with status %8.8xh.\n",
1078 dev->name, np->dirty_tx,
1079 le32_to_cpu(np->tx_ring[entry].cmd_status));
1080 if (np->tx_ring[entry].cmd_status & cpu_to_le32(0x08000000)) {
1081 np->stats.tx_packets++;
1082 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1083 } else { /* Various Tx errors */
1084 int tx_status = le32_to_cpu(np->tx_ring[entry].cmd_status);
1085 if (tx_status & 0x04010000) np->stats.tx_aborted_errors++;
1086 if (tx_status & 0x02000000) np->stats.tx_fifo_errors++;
1087 if (tx_status & 0x01000000) np->stats.tx_carrier_errors++;
1088 if (tx_status & 0x00200000) np->stats.tx_window_errors++;
1089 np->stats.tx_errors++;
1090 }
1091 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
1092 np->tx_skbuff[entry]->len,
1093 PCI_DMA_TODEVICE);
1094 /* Free the original skb. */
1095 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1096 np->tx_skbuff[entry] = NULL;
1097 }
1098 if (netif_queue_stopped(dev)
1099 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1100 /* The ring is no longer full, wake queue. */
1101 netif_wake_queue(dev);
1102 }
1103 }
1104
1105 /* The interrupt handler does all of the Rx thread work and cleans up
1106 after the Tx thread. */
1107 static void intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1108 {
1109 struct net_device *dev = dev_instance;
1110 struct netdev_private *np;
1111 long ioaddr;
1112 int boguscnt = max_interrupt_work;
1113
1114 ioaddr = dev->base_addr;
1115 np = dev->priv;
1116
1117 do {
1118 /* Reading automatically acknowledges all int sources. */
1119 u32 intr_status = readl(ioaddr + IntrStatus);
1120
1121 if (debug > 4)
1122 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1123 dev->name, intr_status);
1124
1125 if (intr_status == 0)
1126 break;
1127
1128 if (intr_status & (IntrRxDone | IntrRxIntr))
1129 netdev_rx(dev);
1130
1131 if (intr_status & (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr) ) {
1132 spin_lock(&np->lock);
1133 netdev_tx_done(dev);
1134 spin_unlock(&np->lock);
1135 }
1136
1137 /* Abnormal error summary/uncommon events handlers. */
1138 if (intr_status & IntrAbnormalSummary)
1139 netdev_error(dev, intr_status);
1140
1141 if (--boguscnt < 0) {
1142 printk(KERN_WARNING "%s: Too much work at interrupt, "
1143 "status=0x%4.4x.\n",
1144 dev->name, intr_status);
1145 break;
1146 }
1147 } while (1);
1148
1149 if (debug > 3)
1150 printk(KERN_DEBUG "%s: exiting interrupt.\n",
1151 dev->name);
1152 }
1153
1154 /* This routine is logically part of the interrupt handler, but separated
1155 for clarity and better register allocation. */
1156 static void netdev_rx(struct net_device *dev)
1157 {
1158 struct netdev_private *np = dev->priv;
1159 int entry = np->cur_rx % RX_RING_SIZE;
1160 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1161 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
1162
1163 /* If the driver owns the next entry it's a new packet. Send it up. */
1164 while (desc_status < 0) { /* e.g. & DescOwn */
1165 if (debug > 4)
1166 printk(KERN_DEBUG " In netdev_rx() entry %d status was %8.8x.\n",
1167 entry, desc_status);
1168 if (--boguscnt < 0)
1169 break;
1170 if ((desc_status & (DescMore|DescPktOK|RxTooLong)) != DescPktOK) {
1171 if (desc_status & DescMore) {
1172 printk(KERN_WARNING "%s: Oversized(?) Ethernet frame spanned "
1173 "multiple buffers, entry %#x status %x.\n",
1174 dev->name, np->cur_rx, desc_status);
1175 np->stats.rx_length_errors++;
1176 } else {
1177 /* There was a error. */
1178 if (debug > 2)
1179 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1180 desc_status);
1181 np->stats.rx_errors++;
1182 if (desc_status & 0x06000000) np->stats.rx_over_errors++;
1183 if (desc_status & 0x00600000) np->stats.rx_length_errors++;
1184 if (desc_status & 0x00140000) np->stats.rx_frame_errors++;
1185 if (desc_status & 0x00080000) np->stats.rx_crc_errors++;
1186 }
1187 } else {
1188 struct sk_buff *skb;
1189 int pkt_len = (desc_status & 0x0fff) - 4; /* Omit CRC size. */
1190 /* Check if the packet is long enough to accept without copying
1191 to a minimally-sized skbuff. */
1192 if (pkt_len < rx_copybreak
1193 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1194 skb->dev = dev;
1195 skb_reserve(skb, 2); /* 16 byte align the IP header */
1196 pci_dma_sync_single(np->pci_dev, np->rx_dma[entry],
1197 np->rx_skbuff[entry]->len,
1198 PCI_DMA_FROMDEVICE);
1199 #if HAS_IP_COPYSUM
1200 eth_copy_and_sum(skb, np->rx_skbuff[entry]->tail, pkt_len, 0);
1201 skb_put(skb, pkt_len);
1202 #else
1203 memcpy(skb_put(skb, pkt_len), np->rx_skbuff[entry]->tail,
1204 pkt_len);
1205 #endif
1206 } else {
1207 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
1208 np->rx_skbuff[entry]->len,
1209 PCI_DMA_FROMDEVICE);
1210 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1211 np->rx_skbuff[entry] = NULL;
1212 }
1213 skb->protocol = eth_type_trans(skb, dev);
1214 /* W/ hardware checksum: skb->ip_summed = CHECKSUM_UNNECESSARY; */
1215 netif_rx(skb);
1216 dev->last_rx = jiffies;
1217 np->stats.rx_packets++;
1218 np->stats.rx_bytes += pkt_len;
1219 }
1220 entry = (++np->cur_rx) % RX_RING_SIZE;
1221 np->rx_head_desc = &np->rx_ring[entry];
1222 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
1223 }
1224
1225 /* Refill the Rx ring buffers. */
1226 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1227 struct sk_buff *skb;
1228 entry = np->dirty_rx % RX_RING_SIZE;
1229 if (np->rx_skbuff[entry] == NULL) {
1230 skb = dev_alloc_skb(np->rx_buf_sz);
1231 np->rx_skbuff[entry] = skb;
1232 if (skb == NULL)
1233 break; /* Better luck next round. */
1234 skb->dev = dev; /* Mark as being used by this device. */
1235 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1236 skb->data, skb->len, PCI_DMA_FROMDEVICE);
1237 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1238 }
1239 np->rx_ring[entry].cmd_status =
1240 cpu_to_le32(DescIntr | np->rx_buf_sz);
1241 }
1242
1243 /* Restart Rx engine if stopped. */
1244 writel(RxOn, dev->base_addr + ChipCmd);
1245 }
1246
1247 static void netdev_error(struct net_device *dev, int intr_status)
1248 {
1249 struct netdev_private *np = dev->priv;
1250 long ioaddr = dev->base_addr;
1251
1252 spin_lock(&np->lock);
1253 if (intr_status & LinkChange) {
1254 printk(KERN_NOTICE "%s: Link changed: Autonegotiation advertising"
1255 " %4.4x partner %4.4x.\n", dev->name,
1256 (int)readl(ioaddr + AnegAdv),
1257 (int)readl(ioaddr + AnegPeer));
1258 /* read MII int status to clear the flag */
1259 readw(ioaddr + MIntrStatus);
1260 check_link(dev);
1261 }
1262 if (intr_status & StatsMax) {
1263 __get_stats(dev);
1264 }
1265 if (intr_status & IntrTxUnderrun) {
1266 if ((np->tx_config & 0x3f) < 62)
1267 np->tx_config += 2;
1268 if (debug > 2)
1269 printk(KERN_NOTICE "%s: increasing Tx theshold, new tx cfg %8.8xh.\n",
1270 dev->name, np->tx_config);
1271 writel(np->tx_config, ioaddr + TxConfig);
1272 }
1273 if (intr_status & WOLPkt) {
1274 int wol_status = readl(ioaddr + WOLCmd);
1275 printk(KERN_NOTICE "%s: Link wake-up event %8.8x\n",
1276 dev->name, wol_status);
1277 }
1278 if ((intr_status & ~(LinkChange|StatsMax|RxResetDone|TxResetDone|0xA7ff))
1279 && debug)
1280 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1281 dev->name, intr_status);
1282 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1283 if (intr_status & IntrPCIErr) {
1284 np->stats.tx_fifo_errors++;
1285 np->stats.rx_fifo_errors++;
1286 }
1287 spin_unlock(&np->lock);
1288 }
1289
1290 static void __get_stats(struct net_device *dev)
1291 {
1292 long ioaddr = dev->base_addr;
1293 struct netdev_private *np = dev->priv;
1294
1295 /* The chip only need report frame silently dropped. */
1296 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
1297 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
1298 }
1299
1300 static struct net_device_stats *get_stats(struct net_device *dev)
1301 {
1302 struct netdev_private *np = dev->priv;
1303
1304 /* The chip only need report frame silently dropped. */
1305 spin_lock_irq(&np->lock);
1306 __get_stats(dev);
1307 spin_unlock_irq(&np->lock);
1308
1309 return &np->stats;
1310 }
1311 /* The little-endian AUTODIN II ethernet CRC calculations.
1312 A big-endian version is also available.
1313 This is slow but compact code. Do not use this routine for bulk data,
1314 use a table-based routine instead.
1315 This is common code and should be moved to net/core/crc.c.
1316 Chips may use the upper or lower CRC bits, and may reverse and/or invert
1317 them. Select the endian-ness that results in minimal calculations.
1318 */
1319 #if 0
1320 static unsigned const ethernet_polynomial_le = 0xedb88320U;
1321 static inline unsigned ether_crc_le(int length, unsigned char *data)
1322 {
1323 unsigned int crc = 0xffffffff; /* Initial value. */
1324 while(--length >= 0) {
1325 unsigned char current_octet = *data++;
1326 int bit;
1327 for (bit = 8; --bit >= 0; current_octet >>= 1) {
1328 if ((crc ^ current_octet) & 1) {
1329 crc >>= 1;
1330 crc ^= ethernet_polynomial_le;
1331 } else
1332 crc >>= 1;
1333 }
1334 }
1335 return crc;
1336 }
1337 #else
1338 #define DP_POLYNOMIAL 0x04C11DB7
1339 /* dp83815_crc - computer CRC for hash table entries */
1340 static unsigned ether_crc_le(int length, unsigned char *data)
1341 {
1342 u32 crc;
1343 u8 cur_byte;
1344 u8 msb;
1345 u8 byte, bit;
1346
1347 crc = ~0;
1348 for (byte=0; byte<length; byte++) {
1349 cur_byte = *data++;
1350 for (bit=0; bit<8; bit++) {
1351 msb = crc >> 31;
1352 crc <<= 1;
1353 if (msb ^ (cur_byte & 1)) {
1354 crc ^= DP_POLYNOMIAL;
1355 crc |= 1;
1356 }
1357 cur_byte >>= 1;
1358 }
1359 }
1360 crc >>= 23;
1361
1362 return (crc);
1363 }
1364 #endif
1365
1366 void set_bit_le(int offset, unsigned char * data)
1367 {
1368 data[offset >> 3] |= (1 << (offset & 0x07));
1369 }
1370 #define HASH_TABLE 0x200
1371 static void __set_rx_mode(struct net_device *dev)
1372 {
1373 long ioaddr = dev->base_addr;
1374 struct netdev_private *np = dev->priv;
1375 u8 mc_filter[64]; /* Multicast hash filter */
1376 u32 rx_mode;
1377
1378 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1379 /* Unconditionally log net taps. */
1380 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1381 rx_mode = AcceptBroadcast | AcceptAllMulticast | AcceptAllPhys
1382 | AcceptMyPhys;
1383 } else if ((dev->mc_count > multicast_filter_limit)
1384 || (dev->flags & IFF_ALLMULTI)) {
1385 rx_mode = AcceptBroadcast | AcceptAllMulticast | AcceptMyPhys;
1386 } else {
1387 struct dev_mc_list *mclist;
1388 int i;
1389 memset(mc_filter, 0, sizeof(mc_filter));
1390 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1391 i++, mclist = mclist->next) {
1392 set_bit_le(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff,
1393 mc_filter);
1394 }
1395 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1396 for (i = 0; i < 64; i += 2) {
1397 writew(HASH_TABLE + i, ioaddr + RxFilterAddr);
1398 writew((mc_filter[i+1]<<8) + mc_filter[i], ioaddr + RxFilterData);
1399 }
1400 }
1401 writel(rx_mode, ioaddr + RxFilterAddr);
1402 np->cur_rx_mode = rx_mode;
1403 }
1404
1405 static void set_rx_mode(struct net_device *dev)
1406 {
1407 struct netdev_private *np = dev->priv;
1408 spin_lock_irq(&np->lock);
1409 __set_rx_mode(dev);
1410 spin_unlock_irq(&np->lock);
1411 }
1412
1413 static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
1414 {
1415 struct netdev_private *np = dev->priv;
1416 struct ethtool_cmd ecmd;
1417
1418 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1419 return -EFAULT;
1420
1421 switch (ecmd.cmd) {
1422 case ETHTOOL_GDRVINFO: {
1423 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
1424 strcpy(info.driver, DRV_NAME);
1425 strcpy(info.version, DRV_VERSION);
1426 strcpy(info.bus_info, np->pci_dev->slot_name);
1427 if (copy_to_user(useraddr, &info, sizeof(info)))
1428 return -EFAULT;
1429 return 0;
1430 }
1431 case ETHTOOL_GSET: {
1432 spin_lock_irq(&np->lock);
1433 netdev_get_ecmd(dev, &ecmd);
1434 spin_unlock_irq(&np->lock);
1435 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1436 return -EFAULT;
1437 return 0;
1438 }
1439 case ETHTOOL_SSET: {
1440 int r;
1441 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1442 return -EFAULT;
1443 spin_lock_irq(&np->lock);
1444 r = netdev_set_ecmd(dev, &ecmd);
1445 spin_unlock_irq(&np->lock);
1446 return r;
1447 }
1448 case ETHTOOL_GWOL: {
1449 struct ethtool_wolinfo wol = {ETHTOOL_GWOL};
1450 spin_lock_irq(&np->lock);
1451 netdev_get_wol(dev, &wol.supported, &wol.wolopts);
1452 netdev_get_sopass(dev, wol.sopass);
1453 spin_unlock_irq(&np->lock);
1454 if (copy_to_user(useraddr, &wol, sizeof(wol)))
1455 return -EFAULT;
1456 return 0;
1457 }
1458 case ETHTOOL_SWOL: {
1459 struct ethtool_wolinfo wol;
1460 int r;
1461 if (copy_from_user(&wol, useraddr, sizeof(wol)))
1462 return -EFAULT;
1463 spin_lock_irq(&np->lock);
1464 netdev_set_wol(dev, wol.wolopts);
1465 r = netdev_set_sopass(dev, wol.sopass);
1466 spin_unlock_irq(&np->lock);
1467 return r;
1468 }
1469
1470 }
1471
1472 return -EOPNOTSUPP;
1473 }
1474
1475 static int netdev_set_wol(struct net_device *dev, u32 newval)
1476 {
1477 u32 data = readl(dev->base_addr + WOLCmd) & ~WakeOptsSummary;
1478
1479 /* translate to bitmasks this chip understands */
1480 if (newval & WAKE_PHY)
1481 data |= WakePhy;
1482 if (newval & WAKE_UCAST)
1483 data |= WakeUnicast;
1484 if (newval & WAKE_MCAST)
1485 data |= WakeMulticast;
1486 if (newval & WAKE_BCAST)
1487 data |= WakeBroadcast;
1488 if (newval & WAKE_ARP)
1489 data |= WakeArp;
1490 if (newval & WAKE_MAGIC)
1491 data |= WakeMagic;
1492 if (newval & WAKE_MAGICSECURE)
1493 data |= WakeMagicSecure;
1494
1495 writel(data, dev->base_addr + WOLCmd);
1496
1497 /* should we burn these into the EEPROM? */
1498
1499 return 0;
1500 }
1501
1502 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
1503 {
1504 u32 regval = readl(dev->base_addr + WOLCmd);
1505
1506 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
1507 | WAKE_ARP | WAKE_MAGIC | WAKE_MAGICSECURE);
1508 *cur = 0;
1509 /* translate from chip bitmasks */
1510 if (regval & 0x1)
1511 *cur |= WAKE_PHY;
1512 if (regval & 0x2)
1513 *cur |= WAKE_UCAST;
1514 if (regval & 0x4)
1515 *cur |= WAKE_MCAST;
1516 if (regval & 0x8)
1517 *cur |= WAKE_BCAST;
1518 if (regval & 0x10)
1519 *cur |= WAKE_ARP;
1520 if (regval & 0x200)
1521 *cur |= WAKE_MAGIC;
1522 if (regval & 0x400)
1523 *cur |= WAKE_MAGICSECURE;
1524
1525 return 0;
1526 }
1527
1528 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
1529 {
1530 u16 *sval = (u16 *)newval;
1531 u32 addr = readl(dev->base_addr + RxFilterAddr) & ~0x3ff;
1532
1533 /* enable writing to these registers by disabling the RX filter */
1534 addr &= ~0x80000000;
1535 writel(addr, dev->base_addr + RxFilterAddr);
1536
1537 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
1538 writel(addr | 0xa, dev->base_addr + RxFilterAddr);
1539 writew(sval[0], dev->base_addr + RxFilterData);
1540
1541 writel(addr | 0xc, dev->base_addr + RxFilterAddr);
1542 writew(sval[1], dev->base_addr + RxFilterData);
1543
1544 writel(addr | 0xe, dev->base_addr + RxFilterAddr);
1545 writew(sval[2], dev->base_addr + RxFilterData);
1546
1547 /* re-enable the RX filter */
1548 writel(addr | 0x80000000, dev->base_addr + RxFilterAddr);
1549
1550 /* should we burn this into the EEPROM? */
1551
1552 return 0;
1553 }
1554
1555 static int netdev_get_sopass(struct net_device *dev, u8 *data)
1556 {
1557 u16 *sval = (u16 *)data;
1558 u32 addr = readl(dev->base_addr + RxFilterAddr) & ~0x3ff;
1559
1560 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
1561 writel(addr | 0xa, dev->base_addr + RxFilterAddr);
1562 sval[0] = readw(dev->base_addr + RxFilterData);
1563
1564 writel(addr | 0xc, dev->base_addr + RxFilterAddr);
1565 sval[1] = readw(dev->base_addr + RxFilterData);
1566
1567 writel(addr | 0xe, dev->base_addr + RxFilterAddr);
1568 sval[2] = readw(dev->base_addr + RxFilterData);
1569
1570 return 0;
1571 }
1572
1573 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
1574 {
1575 u32 tmp;
1576
1577 ecmd->supported =
1578 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1579 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1580 SUPPORTED_Autoneg | SUPPORTED_TP);
1581
1582 /* only supports twisted-pair */
1583 ecmd->port = PORT_TP;
1584
1585 /* only supports internal transceiver */
1586 ecmd->transceiver = XCVR_INTERNAL;
1587
1588 /* this isn't fully supported at higher layers */
1589 ecmd->phy_address = readw(dev->base_addr + PhyCtrl) & 0xf;
1590
1591 tmp = readl(dev->base_addr + AnegAdv);
1592 ecmd->advertising = ADVERTISED_TP;
1593 if (tmp & Aneg10BaseT)
1594 ecmd->advertising |= ADVERTISED_10baseT_Half;
1595 if (tmp & Aneg10BaseTFull)
1596 ecmd->advertising |= ADVERTISED_10baseT_Full;
1597 if (tmp & Aneg100BaseT)
1598 ecmd->advertising |= ADVERTISED_100baseT_Half;
1599 if (tmp & Aneg100BaseTFull)
1600 ecmd->advertising |= ADVERTISED_100baseT_Full;
1601
1602 tmp = readl(dev->base_addr + ChipConfig);
1603 if (tmp & CfgAnegEnable) {
1604 ecmd->advertising |= ADVERTISED_Autoneg;
1605 ecmd->autoneg = AUTONEG_ENABLE;
1606 } else {
1607 ecmd->autoneg = AUTONEG_DISABLE;
1608 }
1609
1610 if (tmp & CfgSpeed100) {
1611 ecmd->speed = SPEED_100;
1612 } else {
1613 ecmd->speed = SPEED_10;
1614 }
1615
1616 if (tmp & CfgFullDuplex) {
1617 ecmd->duplex = DUPLEX_FULL;
1618 } else {
1619 ecmd->duplex = DUPLEX_HALF;
1620 }
1621
1622 /* ignore maxtxpkt, maxrxpkt for now */
1623
1624 return 0;
1625 }
1626
1627 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
1628 {
1629 struct netdev_private *np = dev->priv;
1630 u32 tmp;
1631
1632 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1633 return -EINVAL;
1634 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1635 return -EINVAL;
1636 if (ecmd->port != PORT_TP)
1637 return -EINVAL;
1638 if (ecmd->transceiver != XCVR_INTERNAL)
1639 return -EINVAL;
1640 if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
1641 return -EINVAL;
1642 /* ignore phy_address, maxtxpkt, maxrxpkt for now */
1643
1644 /* WHEW! now lets bang some bits */
1645
1646 if (ecmd->autoneg == AUTONEG_ENABLE) {
1647 /* advertise only what has been requested */
1648 tmp = readl(dev->base_addr + ChipConfig);
1649 tmp &= ~(CfgAneg100 | CfgAnegFull);
1650 tmp |= CfgAnegEnable;
1651 if (ecmd->advertising & ADVERTISED_100baseT_Half
1652 || ecmd->advertising & ADVERTISED_100baseT_Full) {
1653 tmp |= CfgAneg100;
1654 }
1655 if (ecmd->advertising & ADVERTISED_10baseT_Full
1656 || ecmd->advertising & ADVERTISED_100baseT_Full) {
1657 tmp |= CfgAnegFull;
1658 }
1659 writel(tmp, dev->base_addr + ChipConfig);
1660 /* turn on autonegotiation, and force a renegotiate */
1661 tmp = readl(dev->base_addr + BasicControl);
1662 tmp |= BMCRAnegEnable | BMCRAnegRestart;
1663 writel(tmp, dev->base_addr + BasicControl);
1664 np->advertising = mdio_read(dev, 1, 4);
1665 } else {
1666 /* turn off auto negotiation, set speed and duplexity */
1667 tmp = readl(dev->base_addr + BasicControl);
1668 tmp &= ~(BMCRAnegEnable | BMCRSpeed | BMCRDuplex);
1669 if (ecmd->speed == SPEED_100) {
1670 tmp |= BMCRSpeed;
1671 }
1672 if (ecmd->duplex == DUPLEX_FULL) {
1673 tmp |= BMCRDuplex;
1674 } else {
1675 np->full_duplex = 0;
1676 }
1677 writel(tmp, dev->base_addr + BasicControl);
1678 }
1679 return 0;
1680 }
1681
1682 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1683 {
1684 struct netdev_private *np = dev->priv;
1685 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1686
1687 switch(cmd) {
1688 case SIOCETHTOOL:
1689 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
1690 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1691 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1692 data->phy_id = 1;
1693 /* Fall Through */
1694
1695 case SIOCGMIIREG: /* Read MII PHY register. */
1696 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1697 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1698 return 0;
1699
1700 case SIOCSMIIREG: /* Write MII PHY register. */
1701 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1702 if (!capable(CAP_NET_ADMIN))
1703 return -EPERM;
1704 if (data->phy_id == 1) {
1705 u16 miireg = data->reg_num & 0x1f;
1706 u16 value = data->val_in;
1707 writew(value, dev->base_addr + BasicControl
1708 + (miireg << 2));
1709 switch (miireg) {
1710 case 4: np->advertising = value; break;
1711 }
1712 }
1713 return 0;
1714 default:
1715 return -EOPNOTSUPP;
1716 }
1717 }
1718
1719 static int netdev_close(struct net_device *dev)
1720 {
1721 long ioaddr = dev->base_addr;
1722 struct netdev_private *np = dev->priv;
1723 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
1724 u32 clkrun;
1725
1726 netif_stop_queue(dev);
1727 netif_carrier_off(dev);
1728
1729 if (debug > 1) {
1730 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %4.4x.",
1731 dev->name, (int)readl(ioaddr + ChipCmd));
1732 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1733 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1734 }
1735
1736 /* Only shut down chip if wake on lan is not set */
1737 if (!wol) {
1738 /* Disable interrupts using the mask. */
1739 writel(0, ioaddr + IntrMask);
1740 writel(0, ioaddr + IntrEnable);
1741 writel(2, ioaddr + StatsCtrl); /* Freeze Stats */
1742
1743 /* Stop the chip's Tx and Rx processes. */
1744 writel(RxOff | TxOff, ioaddr + ChipCmd);
1745 } else if (debug > 1) {
1746 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
1747 dev->name);
1748 /* spec says write 0 here */
1749 writel(0, ioaddr + RxRingPtr);
1750 /* allow wake-event interrupts now */
1751 writel(readl(ioaddr + IntrMask) | WOLPkt, ioaddr + IntrMask);
1752 }
1753 del_timer_sync(&np->timer);
1754
1755 #ifdef __i386__
1756 if (debug > 2) {
1757 int i;
1758 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1759 (int)np->tx_ring);
1760 for (i = 0; i < TX_RING_SIZE; i++)
1761 printk(" #%d desc. %8.8x %8.8x.\n",
1762 i, np->tx_ring[i].cmd_status, np->tx_ring[i].addr);
1763 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1764 (int)np->rx_ring);
1765 for (i = 0; i < RX_RING_SIZE; i++) {
1766 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x\n",
1767 i, np->rx_ring[i].cmd_status, np->rx_ring[i].addr);
1768 }
1769 }
1770 #endif /* __i386__ debugging only */
1771
1772 free_irq(dev->irq, dev);
1773 drain_ring(dev);
1774 free_ring(dev);
1775
1776 clkrun = np->SavedClkRun;
1777 if (wol) {
1778 /* make sure to enable PME */
1779 clkrun |= 0x100;
1780 }
1781
1782 /* Restore PME enable bit */
1783 writel(np->SavedClkRun, ioaddr + ClkRun);
1784
1785 #if 0
1786 writel(0x0200, ioaddr + ChipConfig); /* Power down Xcvr. */
1787 #endif
1788
1789 return 0;
1790 }
1791
1792
1793 static void __devexit natsemi_remove1 (struct pci_dev *pdev)
1794 {
1795 struct net_device *dev = pci_get_drvdata(pdev);
1796
1797 unregister_netdev (dev);
1798 pci_release_regions (pdev);
1799 iounmap ((char *) dev->base_addr);
1800 kfree (dev);
1801 pci_set_drvdata(pdev, NULL);
1802 }
1803
1804 #ifdef CONFIG_PM
1805
1806 static int natsemi_suspend (struct pci_dev *pdev, u32 state)
1807 {
1808 struct net_device *dev = pci_get_drvdata (pdev);
1809 struct netdev_private *np = dev->priv;
1810 long ioaddr = dev->base_addr;
1811
1812 netif_device_detach(dev);
1813 /* no more calls to tx_timeout, hard_start_xmit, set_rx_mode */
1814 rtnl_lock();
1815 rtnl_unlock();
1816 /* noone within ->open */
1817 if (netif_running (dev)) {
1818 int i;
1819 del_timer_sync(&np->timer);
1820 /* no more link beat timer calls */
1821 spin_lock_irq(&np->lock);
1822 writel(RxOff | TxOff, ioaddr + ChipCmd);
1823 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1824 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1825 break;
1826 udelay(5);
1827 }
1828 if (i==NATSEMI_HW_TIMEOUT && debug) {
1829 printk(KERN_INFO "%s: Tx/Rx process did not stop in %d usec.\n",
1830 dev->name, i*5);
1831 } else if (debug > 2) {
1832 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1833 dev->name, i*5);
1834 }
1835 /* Tx and Rx processes stopped */
1836
1837 writel(0, ioaddr + IntrEnable);
1838 /* all irq events disabled. */
1839 spin_unlock_irq(&np->lock);
1840
1841 synchronize_irq();
1842
1843 /* Update the error counts. */
1844 __get_stats(dev);
1845
1846 /* pci_power_off(pdev, -1); */
1847 drain_ring(dev);
1848 }
1849 return 0;
1850 }
1851
1852
1853 static int natsemi_resume (struct pci_dev *pdev)
1854 {
1855 struct net_device *dev = pci_get_drvdata (pdev);
1856 struct netdev_private *np = dev->priv;
1857
1858 if (netif_running (dev)) {
1859 pci_enable_device(pdev);
1860 /* pci_power_on(pdev); */
1861
1862 natsemi_reset(dev);
1863 init_ring(dev);
1864 init_registers(dev);
1865
1866 np->timer.expires = jiffies + 1*HZ;
1867 add_timer(&np->timer);
1868 }
1869 netif_device_attach(dev);
1870 return 0;
1871 }
1872
1873 #endif /* CONFIG_PM */
1874
1875 static struct pci_driver natsemi_driver = {
1876 name: DRV_NAME,
1877 id_table: natsemi_pci_tbl,
1878 probe: natsemi_probe1,
1879 remove: natsemi_remove1,
1880 #ifdef CONFIG_PM
1881 suspend: natsemi_suspend,
1882 resume: natsemi_resume,
1883 #endif
1884 };
1885
1886 static int __init natsemi_init_mod (void)
1887 {
1888 /* when a module, this is printed whether or not devices are found in probe */
1889 #ifdef MODULE
1890 printk(version);
1891 #endif
1892
1893 return pci_module_init (&natsemi_driver);
1894 }
1895
1896 static void __exit natsemi_exit_mod (void)
1897 {
1898 pci_unregister_driver (&natsemi_driver);
1899 }
1900
1901 module_init(natsemi_init_mod);
1902 module_exit(natsemi_exit_mod);
1903
1904