File: /usr/src/linux/drivers/net/pci-skeleton.c
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@mandrakesoft.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/config.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ioport.h>
94 #include <linux/netdevice.h>
95 #include <linux/etherdevice.h>
96 #include <linux/delay.h>
97 #include <linux/ethtool.h>
98 #include <linux/mii.h>
99 #include <asm/io.h>
100
101 #define NETDRV_VERSION "1.0.0"
102 #define MODNAME "netdrv"
103 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
104 #define PFX MODNAME ": "
105
106 static char version[] __devinitdata =
107 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
108 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
109
110 /* define to 1 to enable PIO instead of MMIO */
111 #undef USE_IO_OPS
112
113 /* define to 1 to enable copious debugging info */
114 #undef NETDRV_DEBUG
115
116 /* define to 1 to disable lightweight runtime debugging checks */
117 #undef NETDRV_NDEBUG
118
119
120 #ifdef NETDRV_DEBUG
121 /* note: prints function name for you */
122 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
123 #else
124 # define DPRINTK(fmt, args...)
125 #endif
126
127 #ifdef NETDRV_NDEBUG
128 # define assert(expr) do {} while (0)
129 #else
130 # define assert(expr) \
131 if(!(expr)) { \
132 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
133 #expr,__FILE__,__FUNCTION__,__LINE__); \
134 }
135 #endif
136
137
138 /* A few user-configurable values. */
139 /* media options */
140 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
141
142 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
143 static int max_interrupt_work = 20;
144
145 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
146 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
147 static int multicast_filter_limit = 32;
148
149 /* Size of the in-memory receive ring. */
150 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
151 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
152 #define RX_BUF_PAD 16
153 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
154 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
155
156 /* Number of Tx descriptor registers. */
157 #define NUM_TX_DESC 4
158
159 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
160 #define MAX_ETH_FRAME_SIZE 1536
161
162 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
163 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
164 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
165
166 /* PCI Tuning Parameters
167 Threshold is bytes transferred to chip before transmission starts. */
168 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
169
170 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
171 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
172 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
173 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174
175
176 /* Operational parameters that usually are not changed. */
177 /* Time in jiffies before concluding the transmitter is hung. */
178 #define TX_TIMEOUT (6*HZ)
179
180
181 enum {
182 HAS_CHIP_XCVR = 0x020000,
183 HAS_LNK_CHNG = 0x040000,
184 };
185
186 #define NETDRV_MIN_IO_SIZE 0x80
187 #define RTL8139B_IO_SIZE 256
188
189 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
190
191 typedef enum {
192 RTL8139 = 0,
193 NETDRV_CB,
194 SMC1211TX,
195 /*MPX5030,*/
196 DELTA8139,
197 ADDTRON8139,
198 } board_t;
199
200
201 /* indexed by board_t, above */
202 static struct {
203 const char *name;
204 } board_info[] __devinitdata = {
205 { "RealTek RTL8139 Fast Ethernet" },
206 { "RealTek RTL8139B PCI/CardBus" },
207 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
208 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
209 { "Delta Electronics 8139 10/100BaseTX" },
210 { "Addtron Technolgy 8139 10/100BaseTX" },
211 };
212
213
214 static struct pci_device_id netdrv_pci_tbl[] __devinitdata = {
215 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
216 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
217 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
218 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
219 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
220 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
221 {0,}
222 };
223 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
224
225
226 /* The rest of these values should never change. */
227
228 /* Symbolic offsets to registers. */
229 enum NETDRV_registers {
230 MAC0 = 0, /* Ethernet hardware address. */
231 MAR0 = 8, /* Multicast filter. */
232 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
233 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
234 RxBuf = 0x30,
235 RxEarlyCnt = 0x34,
236 RxEarlyStatus = 0x36,
237 ChipCmd = 0x37,
238 RxBufPtr = 0x38,
239 RxBufAddr = 0x3A,
240 IntrMask = 0x3C,
241 IntrStatus = 0x3E,
242 TxConfig = 0x40,
243 ChipVersion = 0x43,
244 RxConfig = 0x44,
245 Timer = 0x48, /* A general-purpose counter. */
246 RxMissed = 0x4C, /* 24 bits valid, write clears. */
247 Cfg9346 = 0x50,
248 Config0 = 0x51,
249 Config1 = 0x52,
250 FlashReg = 0x54,
251 MediaStatus = 0x58,
252 Config3 = 0x59,
253 Config4 = 0x5A, /* absent on RTL-8139A */
254 HltClk = 0x5B,
255 MultiIntr = 0x5C,
256 TxSummary = 0x60,
257 BasicModeCtrl = 0x62,
258 BasicModeStatus = 0x64,
259 NWayAdvert = 0x66,
260 NWayLPAR = 0x68,
261 NWayExpansion = 0x6A,
262 /* Undocumented registers, but required for proper operation. */
263 FIFOTMS = 0x70, /* FIFO Control and test. */
264 CSCR = 0x74, /* Chip Status and Configuration Register. */
265 PARA78 = 0x78,
266 PARA7c = 0x7c, /* Magic transceiver parameter register. */
267 Config5 = 0xD8, /* absent on RTL-8139A */
268 };
269
270 enum ClearBitMasks {
271 MultiIntrClear = 0xF000,
272 ChipCmdClear = 0xE2,
273 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
274 };
275
276 enum ChipCmdBits {
277 CmdReset = 0x10,
278 CmdRxEnb = 0x08,
279 CmdTxEnb = 0x04,
280 RxBufEmpty = 0x01,
281 };
282
283 /* Interrupt register bits, using my own meaningful names. */
284 enum IntrStatusBits {
285 PCIErr = 0x8000,
286 PCSTimeout = 0x4000,
287 RxFIFOOver = 0x40,
288 RxUnderrun = 0x20,
289 RxOverflow = 0x10,
290 TxErr = 0x08,
291 TxOK = 0x04,
292 RxErr = 0x02,
293 RxOK = 0x01,
294 };
295 enum TxStatusBits {
296 TxHostOwns = 0x2000,
297 TxUnderrun = 0x4000,
298 TxStatOK = 0x8000,
299 TxOutOfWindow = 0x20000000,
300 TxAborted = 0x40000000,
301 TxCarrierLost = 0x80000000,
302 };
303 enum RxStatusBits {
304 RxMulticast = 0x8000,
305 RxPhysical = 0x4000,
306 RxBroadcast = 0x2000,
307 RxBadSymbol = 0x0020,
308 RxRunt = 0x0010,
309 RxTooLong = 0x0008,
310 RxCRCErr = 0x0004,
311 RxBadAlign = 0x0002,
312 RxStatusOK = 0x0001,
313 };
314
315 /* Bits in RxConfig. */
316 enum rx_mode_bits {
317 AcceptErr = 0x20,
318 AcceptRunt = 0x10,
319 AcceptBroadcast = 0x08,
320 AcceptMulticast = 0x04,
321 AcceptMyPhys = 0x02,
322 AcceptAllPhys = 0x01,
323 };
324
325 /* Bits in TxConfig. */
326 enum tx_config_bits {
327 TxIFG1 = (1 << 25), /* Interframe Gap Time */
328 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
329 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
330 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
331 TxClearAbt = (1 << 0), /* Clear abort (WO) */
332 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
333
334 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
335 };
336
337 /* Bits in Config1 */
338 enum Config1Bits {
339 Cfg1_PM_Enable = 0x01,
340 Cfg1_VPD_Enable = 0x02,
341 Cfg1_PIO = 0x04,
342 Cfg1_MMIO = 0x08,
343 Cfg1_LWAKE = 0x10,
344 Cfg1_Driver_Load = 0x20,
345 Cfg1_LED0 = 0x40,
346 Cfg1_LED1 = 0x80,
347 };
348
349 enum RxConfigBits {
350 /* Early Rx threshold, none or X/16 */
351 RxCfgEarlyRxNone = 0,
352 RxCfgEarlyRxShift = 24,
353
354 /* rx fifo threshold */
355 RxCfgFIFOShift = 13,
356 RxCfgFIFONone = (7 << RxCfgFIFOShift),
357
358 /* Max DMA burst */
359 RxCfgDMAShift = 8,
360 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
361
362 /* rx ring buffer length */
363 RxCfgRcv8K = 0,
364 RxCfgRcv16K = (1 << 11),
365 RxCfgRcv32K = (1 << 12),
366 RxCfgRcv64K = (1 << 11) | (1 << 12),
367
368 /* Disable packet wrap at end of Rx buffer */
369 RxNoWrap = (1 << 7),
370 };
371
372
373 /* Twister tuning parameters from RealTek.
374 Completely undocumented, but required to tune bad links. */
375 enum CSCRBits {
376 CSCR_LinkOKBit = 0x0400,
377 CSCR_LinkChangeBit = 0x0800,
378 CSCR_LinkStatusBits = 0x0f000,
379 CSCR_LinkDownOffCmd = 0x003c0,
380 CSCR_LinkDownCmd = 0x0f3c0,
381 };
382
383
384 enum Cfg9346Bits {
385 Cfg9346_Lock = 0x00,
386 Cfg9346_Unlock = 0xC0,
387 };
388
389
390 #define PARA78_default 0x78fa8388
391 #define PARA7c_default 0xcb38de43 /* param[0][3] */
392 #define PARA7c_xxx 0xcb38de43
393 static const unsigned long param[4][4] = {
394 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
395 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
398 };
399
400 struct ring_info {
401 struct sk_buff *skb;
402 dma_addr_t mapping;
403 };
404
405
406 typedef enum {
407 CH_8139 = 0,
408 CH_8139_K,
409 CH_8139A,
410 CH_8139B,
411 CH_8130,
412 CH_8139C,
413 } chip_t;
414
415
416 /* directly indexed by chip_t, above */
417 const static struct {
418 const char *name;
419 u8 version; /* from RTL8139C docs */
420 u32 RxConfigMask; /* should clear the bits supported by this chip */
421 } rtl_chip_info[] = {
422 { "RTL-8139",
423 0x40,
424 0xf0fe0040, /* XXX copied from RTL8139A, verify */
425 },
426
427 { "RTL-8139 rev K",
428 0x60,
429 0xf0fe0040,
430 },
431
432 { "RTL-8139A",
433 0x70,
434 0xf0fe0040,
435 },
436
437 { "RTL-8139B",
438 0x78,
439 0xf0fc0040
440 },
441
442 { "RTL-8130",
443 0x7C,
444 0xf0fe0040, /* XXX copied from RTL8139A, verify */
445 },
446
447 { "RTL-8139C",
448 0x74,
449 0xf0fc0040, /* XXX copied from RTL8139B, verify */
450 },
451
452 };
453
454
455 struct netdrv_private {
456 board_t board;
457 void *mmio_addr;
458 int drv_flags;
459 struct pci_dev *pci_dev;
460 struct net_device_stats stats;
461 struct timer_list timer; /* Media selection timer. */
462 unsigned char *rx_ring;
463 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
464 unsigned int tx_flag;
465 atomic_t cur_tx;
466 atomic_t dirty_tx;
467 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
468 struct ring_info tx_info[NUM_TX_DESC];
469 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
470 unsigned char *tx_bufs; /* Tx bounce buffer region. */
471 dma_addr_t rx_ring_dma;
472 dma_addr_t tx_bufs_dma;
473 char phys[4]; /* MII device addresses. */
474 char twistie, twist_row, twist_col; /* Twister tune state. */
475 unsigned int full_duplex:1; /* Full-duplex operation requested. */
476 unsigned int duplex_lock:1;
477 unsigned int default_port:4; /* Last dev->if_port value. */
478 unsigned int media2:4; /* Secondary monitored media port. */
479 unsigned int medialock:1; /* Don't sense media type. */
480 unsigned int mediasense:1; /* Media sensing in progress. */
481 spinlock_t lock;
482 chip_t chipset;
483 };
484
485 MODULE_AUTHOR ("Jeff Garzik <jgarzik@mandrakesoft.com>");
486 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
487 MODULE_PARM (multicast_filter_limit, "i");
488 MODULE_PARM (max_interrupt_work, "i");
489 MODULE_PARM (debug, "i");
490 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
491 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
492 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
493 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
494 MODULE_PARM_DESC (debug, "(unused)");
495
496 static int read_eeprom (void *ioaddr, int location, int addr_len);
497 static int netdrv_open (struct net_device *dev);
498 static int mdio_read (struct net_device *dev, int phy_id, int location);
499 static void mdio_write (struct net_device *dev, int phy_id, int location,
500 int val);
501 static void netdrv_timer (unsigned long data);
502 static void netdrv_tx_timeout (struct net_device *dev);
503 static void netdrv_init_ring (struct net_device *dev);
504 static int netdrv_start_xmit (struct sk_buff *skb,
505 struct net_device *dev);
506 static void netdrv_interrupt (int irq, void *dev_instance,
507 struct pt_regs *regs);
508 static int netdrv_close (struct net_device *dev);
509 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
510 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
511 static inline u32 ether_crc (int length, unsigned char *data);
512 static void netdrv_set_rx_mode (struct net_device *dev);
513 static void netdrv_hw_start (struct net_device *dev);
514
515
516 #ifdef USE_IO_OPS
517
518 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
519 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
520 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
521 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
522 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
523 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
524 #define NETDRV_W8_F NETDRV_W8
525 #define NETDRV_W16_F NETDRV_W16
526 #define NETDRV_W32_F NETDRV_W32
527 #undef readb
528 #undef readw
529 #undef readl
530 #undef writeb
531 #undef writew
532 #undef writel
533 #define readb(addr) inb((unsigned long)(addr))
534 #define readw(addr) inw((unsigned long)(addr))
535 #define readl(addr) inl((unsigned long)(addr))
536 #define writeb(val,addr) outb((val),(unsigned long)(addr))
537 #define writew(val,addr) outw((val),(unsigned long)(addr))
538 #define writel(val,addr) outl((val),(unsigned long)(addr))
539
540 #else
541
542 /* write MMIO register, with flush */
543 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
544 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
545 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
546 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
547
548
549 #if MMIO_FLUSH_AUDIT_COMPLETE
550
551 /* write MMIO register */
552 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
553 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
554 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
555
556 #else
557
558 /* write MMIO register, then flush */
559 #define NETDRV_W8 NETDRV_W8_F
560 #define NETDRV_W16 NETDRV_W16_F
561 #define NETDRV_W32 NETDRV_W32_F
562
563 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
564
565 /* read MMIO register */
566 #define NETDRV_R8(reg) readb (ioaddr + (reg))
567 #define NETDRV_R16(reg) readw (ioaddr + (reg))
568 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
569
570 #endif /* USE_IO_OPS */
571
572
573 static const u16 netdrv_intr_mask =
574 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
575 TxErr | TxOK | RxErr | RxOK;
576
577 static const unsigned int netdrv_rx_config =
578 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
579 (RX_FIFO_THRESH << RxCfgFIFOShift) |
580 (RX_DMA_BURST << RxCfgDMAShift);
581
582
583 static int __devinit netdrv_init_board (struct pci_dev *pdev,
584 struct net_device **dev_out,
585 void **ioaddr_out)
586 {
587 void *ioaddr = NULL;
588 struct net_device *dev;
589 struct netdrv_private *tp;
590 u8 tmp8;
591 int rc, i;
592 u32 pio_start, pio_end, pio_flags, pio_len;
593 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
594 u32 tmp;
595
596 DPRINTK ("ENTER\n");
597
598 assert (pdev != NULL);
599 assert (ioaddr_out != NULL);
600
601 *ioaddr_out = NULL;
602 *dev_out = NULL;
603
604 /* dev zeroed in init_etherdev */
605 dev = alloc_etherdev (sizeof (*tp));
606 if (dev == NULL) {
607 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
608 DPRINTK ("EXIT, returning -ENOMEM\n");
609 return -ENOMEM;
610 }
611 SET_MODULE_OWNER(dev);
612 tp = dev->priv;
613
614 /* enable device (incl. PCI PM wakeup), and bus-mastering */
615 rc = pci_enable_device (pdev);
616 if (rc)
617 goto err_out;
618
619 pio_start = pci_resource_start (pdev, 0);
620 pio_end = pci_resource_end (pdev, 0);
621 pio_flags = pci_resource_flags (pdev, 0);
622 pio_len = pci_resource_len (pdev, 0);
623
624 mmio_start = pci_resource_start (pdev, 1);
625 mmio_end = pci_resource_end (pdev, 1);
626 mmio_flags = pci_resource_flags (pdev, 1);
627 mmio_len = pci_resource_len (pdev, 1);
628
629 /* set this immediately, we need to know before
630 * we talk to the chip directly */
631 DPRINTK("PIO region size == 0x%02X\n", pio_len);
632 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
633
634 /* make sure PCI base addr 0 is PIO */
635 if (!(pio_flags & IORESOURCE_IO)) {
636 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
637 rc = -ENODEV;
638 goto err_out;
639 }
640
641 /* make sure PCI base addr 1 is MMIO */
642 if (!(mmio_flags & IORESOURCE_MEM)) {
643 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
644 rc = -ENODEV;
645 goto err_out;
646 }
647
648 /* check for weird/broken PCI region reporting */
649 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
650 (mmio_len < NETDRV_MIN_IO_SIZE)) {
651 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
652 rc = -ENODEV;
653 goto err_out;
654 }
655
656 rc = pci_request_regions (pdev, "pci-skeleton");
657 if (rc)
658 goto err_out;
659
660 pci_set_master (pdev);
661
662 #ifdef USE_IO_OPS
663 ioaddr = (void *) pio_start;
664 #else
665 /* ioremap MMIO region */
666 ioaddr = ioremap (mmio_start, mmio_len);
667 if (ioaddr == NULL) {
668 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
669 rc = -EIO;
670 goto err_out_free_res;
671 }
672 #endif /* USE_IO_OPS */
673
674 /* Soft reset the chip. */
675 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
676
677 /* Check that the chip has finished the reset. */
678 for (i = 1000; i > 0; i--)
679 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
680 break;
681 else
682 udelay (10);
683
684 /* Bring the chip out of low-power mode. */
685 /* <insert device-specific code here> */
686
687 #ifndef USE_IO_OPS
688 /* sanity checks -- ensure PIO and MMIO registers agree */
689 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
690 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
691 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
692 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
693 #endif /* !USE_IO_OPS */
694
695 /* identify chip attached to board */
696 tmp = NETDRV_R8 (ChipVersion);
697 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
698 if (tmp == rtl_chip_info[i].version) {
699 tp->chipset = i;
700 goto match;
701 }
702
703 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
704 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
705 pdev->slot_name);
706 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pdev->slot_name, NETDRV_R32 (TxConfig));
707 tp->chipset = 0;
708
709 match:
710 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
711 tmp,
712 tp->chipset,
713 rtl_chip_info[tp->chipset].name);
714
715 i = register_netdev (dev);
716 if (i)
717 goto err_out_unmap;
718
719 DPRINTK ("EXIT, returning 0\n");
720 *ioaddr_out = ioaddr;
721 *dev_out = dev;
722 return 0;
723
724 err_out_unmap:
725 #ifndef USE_IO_OPS
726 iounmap(ioaddr);
727 err_out_free_res:
728 #endif
729 pci_release_regions (pdev);
730 err_out:
731 kfree (dev);
732 DPRINTK ("EXIT, returning %d\n", rc);
733 return rc;
734 }
735
736
737 static int __devinit netdrv_init_one (struct pci_dev *pdev,
738 const struct pci_device_id *ent)
739 {
740 struct net_device *dev = NULL;
741 struct netdrv_private *tp;
742 int i, addr_len, option;
743 void *ioaddr = NULL;
744 static int board_idx = -1;
745 u8 tmp;
746
747 /* when built into the kernel, we only print version if device is found */
748 #ifndef MODULE
749 static int printed_version;
750 if (!printed_version++)
751 printk(version);
752 #endif
753
754 DPRINTK ("ENTER\n");
755
756 assert (pdev != NULL);
757 assert (ent != NULL);
758
759 board_idx++;
760
761 i = netdrv_init_board (pdev, &dev, &ioaddr);
762 if (i < 0) {
763 DPRINTK ("EXIT, returning %d\n", i);
764 return i;
765 }
766
767 tp = dev->priv;
768
769 assert (ioaddr != NULL);
770 assert (dev != NULL);
771 assert (tp != NULL);
772
773 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
774 for (i = 0; i < 3; i++)
775 ((u16 *) (dev->dev_addr))[i] =
776 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
777
778 /* The Rtl8139-specific entries in the device structure. */
779 dev->open = netdrv_open;
780 dev->hard_start_xmit = netdrv_start_xmit;
781 dev->stop = netdrv_close;
782 dev->get_stats = netdrv_get_stats;
783 dev->set_multicast_list = netdrv_set_rx_mode;
784 dev->do_ioctl = netdrv_ioctl;
785 dev->tx_timeout = netdrv_tx_timeout;
786 dev->watchdog_timeo = TX_TIMEOUT;
787
788 dev->irq = pdev->irq;
789 dev->base_addr = (unsigned long) ioaddr;
790
791 /* dev->priv/tp zeroed and aligned in init_etherdev */
792 tp = dev->priv;
793
794 /* note: tp->chipset set in netdrv_init_board */
795 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
796 PCI_COMMAND_MASTER | NETDRV_CAPS;
797 tp->pci_dev = pdev;
798 tp->board = ent->driver_data;
799 tp->mmio_addr = ioaddr;
800 tp->lock = SPIN_LOCK_UNLOCKED;
801
802 pci_set_drvdata(pdev, dev);
803
804 tp->phys[0] = 32;
805
806 printk (KERN_INFO "%s: %s at 0x%lx, "
807 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
808 "IRQ %d\n",
809 dev->name,
810 board_info[ent->driver_data].name,
811 dev->base_addr,
812 dev->dev_addr[0], dev->dev_addr[1],
813 dev->dev_addr[2], dev->dev_addr[3],
814 dev->dev_addr[4], dev->dev_addr[5],
815 dev->irq);
816
817 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
818 dev->name, rtl_chip_info[tp->chipset].name);
819
820 /* Put the chip into low-power mode. */
821 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
822
823 /* The lower four bits are the media type. */
824 option = (board_idx > 7) ? 0 : media[board_idx];
825 if (option > 0) {
826 tp->full_duplex = (option & 0x200) ? 1 : 0;
827 tp->default_port = option & 15;
828 if (tp->default_port)
829 tp->medialock = 1;
830 }
831
832 if (tp->full_duplex) {
833 printk (KERN_INFO
834 "%s: Media type forced to Full Duplex.\n",
835 dev->name);
836 mdio_write (dev, tp->phys[0], 4, 0x141);
837 tp->duplex_lock = 1;
838 }
839
840 DPRINTK ("EXIT - returning 0\n");
841 return 0;
842 }
843
844
845 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
846 {
847 struct net_device *dev = pci_get_drvdata (pdev);
848 struct netdrv_private *np;
849
850 DPRINTK ("ENTER\n");
851
852 assert (dev != NULL);
853
854 np = dev->priv;
855 assert (np != NULL);
856
857 unregister_netdev (dev);
858
859 #ifndef USE_IO_OPS
860 iounmap (np->mmio_addr);
861 #endif /* !USE_IO_OPS */
862
863 pci_release_regions (pdev);
864
865 #ifndef NETDRV_NDEBUG
866 /* poison memory before freeing */
867 memset (dev, 0xBC,
868 sizeof (struct net_device) +
869 sizeof (struct netdrv_private));
870 #endif /* NETDRV_NDEBUG */
871
872 kfree (dev);
873
874 pci_set_drvdata (pdev, NULL);
875
876 pci_power_off (pdev, -1);
877
878 DPRINTK ("EXIT\n");
879 }
880
881
882 /* Serial EEPROM section. */
883
884 /* EEPROM_Ctrl bits. */
885 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
886 #define EE_CS 0x08 /* EEPROM chip select. */
887 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
888 #define EE_WRITE_0 0x00
889 #define EE_WRITE_1 0x02
890 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
891 #define EE_ENB (0x80 | EE_CS)
892
893 /* Delay between EEPROM clock transitions.
894 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
895 */
896
897 #define eeprom_delay() readl(ee_addr)
898
899 /* The EEPROM commands include the alway-set leading bit. */
900 #define EE_WRITE_CMD (5)
901 #define EE_READ_CMD (6)
902 #define EE_ERASE_CMD (7)
903
904 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
905 {
906 int i;
907 unsigned retval = 0;
908 void *ee_addr = ioaddr + Cfg9346;
909 int read_cmd = location | (EE_READ_CMD << addr_len);
910
911 DPRINTK ("ENTER\n");
912
913 writeb (EE_ENB & ~EE_CS, ee_addr);
914 writeb (EE_ENB, ee_addr);
915 eeprom_delay ();
916
917 /* Shift the read command bits out. */
918 for (i = 4 + addr_len; i >= 0; i--) {
919 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
920 writeb (EE_ENB | dataval, ee_addr);
921 eeprom_delay ();
922 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
923 eeprom_delay ();
924 }
925 writeb (EE_ENB, ee_addr);
926 eeprom_delay ();
927
928 for (i = 16; i > 0; i--) {
929 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
930 eeprom_delay ();
931 retval =
932 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
933 0);
934 writeb (EE_ENB, ee_addr);
935 eeprom_delay ();
936 }
937
938 /* Terminate the EEPROM access. */
939 writeb (~EE_CS, ee_addr);
940 eeprom_delay ();
941
942 DPRINTK ("EXIT - returning %d\n", retval);
943 return retval;
944 }
945
946 /* MII serial management: mostly bogus for now. */
947 /* Read and write the MII management registers using software-generated
948 serial MDIO protocol.
949 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
950 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
951 "overclocking" issues. */
952 #define MDIO_DIR 0x80
953 #define MDIO_DATA_OUT 0x04
954 #define MDIO_DATA_IN 0x02
955 #define MDIO_CLK 0x01
956 #define MDIO_WRITE0 (MDIO_DIR)
957 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
958
959 #define mdio_delay() readb(mdio_addr)
960
961
962 static char mii_2_8139_map[8] = {
963 BasicModeCtrl,
964 BasicModeStatus,
965 0,
966 0,
967 NWayAdvert,
968 NWayLPAR,
969 NWayExpansion,
970 0
971 };
972
973
974 /* Syncronize the MII management interface by shifting 32 one bits out. */
975 static void mdio_sync (void *mdio_addr)
976 {
977 int i;
978
979 DPRINTK ("ENTER\n");
980
981 for (i = 32; i >= 0; i--) {
982 writeb (MDIO_WRITE1, mdio_addr);
983 mdio_delay ();
984 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
985 mdio_delay ();
986 }
987
988 DPRINTK ("EXIT\n");
989 }
990
991
992 static int mdio_read (struct net_device *dev, int phy_id, int location)
993 {
994 struct netdrv_private *tp = dev->priv;
995 void *mdio_addr = tp->mmio_addr + Config4;
996 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
997 int retval = 0;
998 int i;
999
1000 DPRINTK ("ENTER\n");
1001
1002 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1003 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1004 return location < 8 && mii_2_8139_map[location] ?
1005 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1006 }
1007 mdio_sync (mdio_addr);
1008 /* Shift the read command bits out. */
1009 for (i = 15; i >= 0; i--) {
1010 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1011
1012 writeb (MDIO_DIR | dataval, mdio_addr);
1013 mdio_delay ();
1014 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1015 mdio_delay ();
1016 }
1017
1018 /* Read the two transition, 16 data, and wire-idle bits. */
1019 for (i = 19; i > 0; i--) {
1020 writeb (0, mdio_addr);
1021 mdio_delay ();
1022 retval =
1023 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1024 : 0);
1025 writeb (MDIO_CLK, mdio_addr);
1026 mdio_delay ();
1027 }
1028
1029 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1030 return (retval >> 1) & 0xffff;
1031 }
1032
1033
1034 static void mdio_write (struct net_device *dev, int phy_id, int location,
1035 int value)
1036 {
1037 struct netdrv_private *tp = dev->priv;
1038 void *mdio_addr = tp->mmio_addr + Config4;
1039 int mii_cmd =
1040 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1041 int i;
1042
1043 DPRINTK ("ENTER\n");
1044
1045 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1046 if (location < 8 && mii_2_8139_map[location]) {
1047 writew (value,
1048 tp->mmio_addr + mii_2_8139_map[location]);
1049 readw (tp->mmio_addr + mii_2_8139_map[location]);
1050 }
1051 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1052 return;
1053 }
1054 mdio_sync (mdio_addr);
1055
1056 /* Shift the command bits out. */
1057 for (i = 31; i >= 0; i--) {
1058 int dataval =
1059 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1060 writeb (dataval, mdio_addr);
1061 mdio_delay ();
1062 writeb (dataval | MDIO_CLK, mdio_addr);
1063 mdio_delay ();
1064 }
1065
1066 /* Clear out extra bits. */
1067 for (i = 2; i > 0; i--) {
1068 writeb (0, mdio_addr);
1069 mdio_delay ();
1070 writeb (MDIO_CLK, mdio_addr);
1071 mdio_delay ();
1072 }
1073
1074 DPRINTK ("EXIT\n");
1075 }
1076
1077
1078 static int netdrv_open (struct net_device *dev)
1079 {
1080 struct netdrv_private *tp = dev->priv;
1081 int retval;
1082 #ifdef NETDRV_DEBUG
1083 void *ioaddr = tp->mmio_addr;
1084 #endif
1085
1086 DPRINTK ("ENTER\n");
1087
1088 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1089 if (retval) {
1090 DPRINTK ("EXIT, returning %d\n", retval);
1091 return retval;
1092 }
1093
1094 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1095 &tp->tx_bufs_dma);
1096 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1097 &tp->rx_ring_dma);
1098 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1099 free_irq(dev->irq, dev);
1100
1101 if (tp->tx_bufs)
1102 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1103 tp->tx_bufs, tp->tx_bufs_dma);
1104 if (tp->rx_ring)
1105 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1106 tp->rx_ring, tp->rx_ring_dma);
1107
1108 DPRINTK ("EXIT, returning -ENOMEM\n");
1109 return -ENOMEM;
1110
1111 }
1112
1113 tp->full_duplex = tp->duplex_lock;
1114 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1115
1116 netdrv_init_ring (dev);
1117 netdrv_hw_start (dev);
1118
1119 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1120 " GP Pins %2.2x %s-duplex.\n",
1121 dev->name, pci_resource_start (tp->pci_dev, 1),
1122 dev->irq, NETDRV_R8 (MediaStatus),
1123 tp->full_duplex ? "full" : "half");
1124
1125 /* Set the timer to switch to check for link beat and perhaps switch
1126 to an alternate media type. */
1127 init_timer (&tp->timer);
1128 tp->timer.expires = jiffies + 3 * HZ;
1129 tp->timer.data = (unsigned long) dev;
1130 tp->timer.function = &netdrv_timer;
1131 add_timer (&tp->timer);
1132
1133 DPRINTK ("EXIT, returning 0\n");
1134 return 0;
1135 }
1136
1137
1138 /* Start the hardware at open or resume. */
1139 static void netdrv_hw_start (struct net_device *dev)
1140 {
1141 struct netdrv_private *tp = dev->priv;
1142 void *ioaddr = tp->mmio_addr;
1143 u32 i;
1144 u8 tmp;
1145
1146 DPRINTK ("ENTER\n");
1147
1148 /* Soft reset the chip. */
1149 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1150 udelay (100);
1151
1152 /* Check that the chip has finished the reset. */
1153 for (i = 1000; i > 0; i--)
1154 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1155 break;
1156
1157 /* Restore our idea of the MAC address. */
1158 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1159 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1160
1161 /* Must enable Tx/Rx before setting transfer thresholds! */
1162 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1163 CmdRxEnb | CmdTxEnb);
1164
1165 i = netdrv_rx_config |
1166 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1167 NETDRV_W32_F (RxConfig, i);
1168
1169 /* Check this value: the documentation for IFG contradicts ifself. */
1170 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1171
1172 /* unlock Config[01234] and BMCR register writes */
1173 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1174 udelay (10);
1175
1176 tp->cur_rx = 0;
1177
1178 /* Lock Config[01234] and BMCR register writes */
1179 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1180 udelay (10);
1181
1182 /* init Rx ring buffer DMA address */
1183 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1184
1185 /* init Tx buffer DMA addresses */
1186 for (i = 0; i < NUM_TX_DESC; i++)
1187 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1188
1189 NETDRV_W32_F (RxMissed, 0);
1190
1191 netdrv_set_rx_mode (dev);
1192
1193 /* no early-rx interrupts */
1194 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1195
1196 /* make sure RxTx has started */
1197 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1198 CmdRxEnb | CmdTxEnb);
1199
1200 /* Enable all known interrupts by setting the interrupt mask. */
1201 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1202
1203 netif_start_queue (dev);
1204
1205 DPRINTK ("EXIT\n");
1206 }
1207
1208
1209 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1210 static void netdrv_init_ring (struct net_device *dev)
1211 {
1212 struct netdrv_private *tp = dev->priv;
1213 int i;
1214
1215 DPRINTK ("ENTER\n");
1216
1217 tp->cur_rx = 0;
1218 atomic_set (&tp->cur_tx, 0);
1219 atomic_set (&tp->dirty_tx, 0);
1220
1221 for (i = 0; i < NUM_TX_DESC; i++) {
1222 tp->tx_info[i].skb = NULL;
1223 tp->tx_info[i].mapping = 0;
1224 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1225 }
1226
1227 DPRINTK ("EXIT\n");
1228 }
1229
1230
1231 static void netdrv_timer (unsigned long data)
1232 {
1233 struct net_device *dev = (struct net_device *) data;
1234 struct netdrv_private *tp = dev->priv;
1235 void *ioaddr = tp->mmio_addr;
1236 int next_tick = 60 * HZ;
1237 int mii_reg5;
1238
1239 mii_reg5 = mdio_read (dev, tp->phys[0], 5);
1240
1241 if (!tp->duplex_lock && mii_reg5 != 0xffff) {
1242 int duplex = (mii_reg5 & 0x0100)
1243 || (mii_reg5 & 0x01C0) == 0x0040;
1244 if (tp->full_duplex != duplex) {
1245 tp->full_duplex = duplex;
1246 printk (KERN_INFO
1247 "%s: Setting %s-duplex based on MII #%d link"
1248 " partner ability of %4.4x.\n", dev->name,
1249 tp->full_duplex ? "full" : "half",
1250 tp->phys[0], mii_reg5);
1251 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1252 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1253 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1254 }
1255 }
1256
1257 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1258 dev->name, NETDRV_R16 (NWayLPAR));
1259 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1260 " RxStatus %4.4x.\n", dev->name,
1261 NETDRV_R16 (IntrMask),
1262 NETDRV_R16 (IntrStatus),
1263 NETDRV_R32 (RxEarlyStatus));
1264 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1265 dev->name, NETDRV_R8 (Config0),
1266 NETDRV_R8 (Config1));
1267
1268 tp->timer.expires = jiffies + next_tick;
1269 add_timer (&tp->timer);
1270 }
1271
1272
1273 static void netdrv_tx_clear (struct netdrv_private *tp)
1274 {
1275 int i;
1276
1277 atomic_set (&tp->cur_tx, 0);
1278 atomic_set (&tp->dirty_tx, 0);
1279
1280 /* Dump the unsent Tx packets. */
1281 for (i = 0; i < NUM_TX_DESC; i++) {
1282 struct ring_info *rp = &tp->tx_info[i];
1283 if (rp->mapping != 0) {
1284 pci_unmap_single (tp->pci_dev, rp->mapping,
1285 rp->skb->len, PCI_DMA_TODEVICE);
1286 rp->mapping = 0;
1287 }
1288 if (rp->skb) {
1289 dev_kfree_skb (rp->skb);
1290 rp->skb = NULL;
1291 tp->stats.tx_dropped++;
1292 }
1293 }
1294 }
1295
1296
1297 static void netdrv_tx_timeout (struct net_device *dev)
1298 {
1299 struct netdrv_private *tp = dev->priv;
1300 void *ioaddr = tp->mmio_addr;
1301 int i;
1302 u8 tmp8;
1303 unsigned long flags;
1304
1305 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1306 "media %2.2x.\n", dev->name,
1307 NETDRV_R8 (ChipCmd),
1308 NETDRV_R16 (IntrStatus),
1309 NETDRV_R8 (MediaStatus));
1310
1311 /* disable Tx ASAP, if not already */
1312 tmp8 = NETDRV_R8 (ChipCmd);
1313 if (tmp8 & CmdTxEnb)
1314 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1315
1316 /* Disable interrupts by clearing the interrupt mask. */
1317 NETDRV_W16 (IntrMask, 0x0000);
1318
1319 /* Emit info to figure out what went wrong. */
1320 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1321 dev->name, atomic_read (&tp->cur_tx),
1322 atomic_read (&tp->dirty_tx));
1323 for (i = 0; i < NUM_TX_DESC; i++)
1324 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1325 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1326 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1327 " (queue head)" : "");
1328
1329 /* Stop a shared interrupt from scavenging while we are. */
1330 spin_lock_irqsave (&tp->lock, flags);
1331
1332 netdrv_tx_clear (tp);
1333
1334 spin_unlock_irqrestore (&tp->lock, flags);
1335
1336 /* ...and finally, reset everything */
1337 netdrv_hw_start (dev);
1338
1339 netif_wake_queue (dev);
1340 }
1341
1342
1343
1344 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1345 {
1346 struct netdrv_private *tp = dev->priv;
1347 void *ioaddr = tp->mmio_addr;
1348 int entry;
1349
1350 /* Calculate the next Tx descriptor entry. */
1351 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1352
1353 assert (tp->tx_info[entry].skb == NULL);
1354 assert (tp->tx_info[entry].mapping == 0);
1355
1356 tp->tx_info[entry].skb = skb;
1357 /* tp->tx_info[entry].mapping = 0; */
1358 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1359
1360 /* Note: the chip doesn't have auto-pad! */
1361 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1362 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1363
1364 dev->trans_start = jiffies;
1365 atomic_inc (&tp->cur_tx);
1366 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1367 netif_stop_queue (dev);
1368
1369 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1370 dev->name, skb->data, skb->len, entry);
1371
1372 return 0;
1373 }
1374
1375
1376 static void netdrv_tx_interrupt (struct net_device *dev,
1377 struct netdrv_private *tp,
1378 void *ioaddr)
1379 {
1380 int cur_tx, dirty_tx, tx_left;
1381
1382 assert (dev != NULL);
1383 assert (tp != NULL);
1384 assert (ioaddr != NULL);
1385
1386 dirty_tx = atomic_read (&tp->dirty_tx);
1387
1388 cur_tx = atomic_read (&tp->cur_tx);
1389 tx_left = cur_tx - dirty_tx;
1390 while (tx_left > 0) {
1391 int entry = dirty_tx % NUM_TX_DESC;
1392 int txstatus;
1393
1394 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1395
1396 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1397 break; /* It still hasn't been Txed */
1398
1399 /* Note: TxCarrierLost is always asserted at 100mbps. */
1400 if (txstatus & (TxOutOfWindow | TxAborted)) {
1401 /* There was an major error, log it. */
1402 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1403 dev->name, txstatus);
1404 tp->stats.tx_errors++;
1405 if (txstatus & TxAborted) {
1406 tp->stats.tx_aborted_errors++;
1407 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1408 }
1409 if (txstatus & TxCarrierLost)
1410 tp->stats.tx_carrier_errors++;
1411 if (txstatus & TxOutOfWindow)
1412 tp->stats.tx_window_errors++;
1413 #ifdef ETHER_STATS
1414 if ((txstatus & 0x0f000000) == 0x0f000000)
1415 tp->stats.collisions16++;
1416 #endif
1417 } else {
1418 if (txstatus & TxUnderrun) {
1419 /* Add 64 to the Tx FIFO threshold. */
1420 if (tp->tx_flag < 0x00300000)
1421 tp->tx_flag += 0x00020000;
1422 tp->stats.tx_fifo_errors++;
1423 }
1424 tp->stats.collisions += (txstatus >> 24) & 15;
1425 tp->stats.tx_bytes += txstatus & 0x7ff;
1426 tp->stats.tx_packets++;
1427 }
1428
1429 /* Free the original skb. */
1430 if (tp->tx_info[entry].mapping != 0) {
1431 pci_unmap_single(tp->pci_dev,
1432 tp->tx_info[entry].mapping,
1433 tp->tx_info[entry].skb->len,
1434 PCI_DMA_TODEVICE);
1435 tp->tx_info[entry].mapping = 0;
1436 }
1437 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1438 tp->tx_info[entry].skb = NULL;
1439 dirty_tx++;
1440 if (dirty_tx < 0) { /* handle signed int overflow */
1441 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1442 dirty_tx = cur_tx - tx_left + 1;
1443 }
1444 if (netif_queue_stopped (dev))
1445 netif_wake_queue (dev);
1446
1447 cur_tx = atomic_read (&tp->cur_tx);
1448 tx_left = cur_tx - dirty_tx;
1449
1450 }
1451
1452 #ifndef NETDRV_NDEBUG
1453 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1454 printk (KERN_ERR
1455 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1456 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1457 dirty_tx += NUM_TX_DESC;
1458 }
1459 #endif /* NETDRV_NDEBUG */
1460
1461 atomic_set (&tp->dirty_tx, dirty_tx);
1462 }
1463
1464
1465 /* TODO: clean this up! Rx reset need not be this intensive */
1466 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1467 struct netdrv_private *tp, void *ioaddr)
1468 {
1469 u8 tmp8;
1470 int tmp_work = 1000;
1471
1472 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1473 dev->name, rx_status);
1474 if (rx_status & RxTooLong) {
1475 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1476 dev->name, rx_status);
1477 /* A.C.: The chip hangs here. */
1478 }
1479 tp->stats.rx_errors++;
1480 if (rx_status & (RxBadSymbol | RxBadAlign))
1481 tp->stats.rx_frame_errors++;
1482 if (rx_status & (RxRunt | RxTooLong))
1483 tp->stats.rx_length_errors++;
1484 if (rx_status & RxCRCErr)
1485 tp->stats.rx_crc_errors++;
1486 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1487 tp->cur_rx = 0;
1488
1489 /* disable receive */
1490 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1491 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1492
1493 /* A.C.: Reset the multicast list. */
1494 netdrv_set_rx_mode (dev);
1495
1496 /* XXX potentially temporary hack to
1497 * restart hung receiver */
1498 while (--tmp_work > 0) {
1499 tmp8 = NETDRV_R8 (ChipCmd);
1500 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1501 break;
1502 NETDRV_W8_F (ChipCmd,
1503 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1504 }
1505
1506 /* G.S.: Re-enable receiver */
1507 /* XXX temporary hack to work around receiver hang */
1508 netdrv_set_rx_mode (dev);
1509
1510 if (tmp_work <= 0)
1511 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1512 }
1513
1514
1515 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1516 field alignments and semantics. */
1517 static void netdrv_rx_interrupt (struct net_device *dev,
1518 struct netdrv_private *tp, void *ioaddr)
1519 {
1520 unsigned char *rx_ring;
1521 u16 cur_rx;
1522
1523 assert (dev != NULL);
1524 assert (tp != NULL);
1525 assert (ioaddr != NULL);
1526
1527 rx_ring = tp->rx_ring;
1528 cur_rx = tp->cur_rx;
1529
1530 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1531 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1532 NETDRV_R16 (RxBufAddr),
1533 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1534
1535 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1536 int ring_offset = cur_rx % RX_BUF_LEN;
1537 u32 rx_status;
1538 unsigned int rx_size;
1539 unsigned int pkt_size;
1540 struct sk_buff *skb;
1541
1542 /* read size+status of next frame from DMA ring buffer */
1543 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1544 rx_size = rx_status >> 16;
1545 pkt_size = rx_size - 4;
1546
1547 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1548 " cur %4.4x.\n", dev->name, rx_status,
1549 rx_size, cur_rx);
1550 #if NETDRV_DEBUG > 2
1551 {
1552 int i;
1553 DPRINTK ("%s: Frame contents ", dev->name);
1554 for (i = 0; i < 70; i++)
1555 printk (" %2.2x",
1556 rx_ring[ring_offset + i]);
1557 printk (".\n");
1558 }
1559 #endif
1560
1561 /* If Rx err or invalid rx_size/rx_status received
1562 * (which happens if we get lost in the ring),
1563 * Rx process gets reset, so we abort any further
1564 * Rx processing.
1565 */
1566 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1567 (!(rx_status & RxStatusOK))) {
1568 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1569 return;
1570 }
1571
1572 /* Malloc up new buffer, compatible with net-2e. */
1573 /* Omit the four octet CRC from the length. */
1574
1575 /* TODO: consider allocating skb's outside of
1576 * interrupt context, both to speed interrupt processing,
1577 * and also to reduce the chances of having to
1578 * drop packets here under memory pressure.
1579 */
1580
1581 skb = dev_alloc_skb (pkt_size + 2);
1582 if (skb) {
1583 skb->dev = dev;
1584 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1585
1586 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1587 skb_put (skb, pkt_size);
1588
1589 skb->protocol = eth_type_trans (skb, dev);
1590 netif_rx (skb);
1591 dev->last_rx = jiffies;
1592 tp->stats.rx_bytes += pkt_size;
1593 tp->stats.rx_packets++;
1594 } else {
1595 printk (KERN_WARNING
1596 "%s: Memory squeeze, dropping packet.\n",
1597 dev->name);
1598 tp->stats.rx_dropped++;
1599 }
1600
1601 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1602 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1603 }
1604
1605 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1606 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1607 NETDRV_R16 (RxBufAddr),
1608 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1609
1610 tp->cur_rx = cur_rx;
1611 }
1612
1613
1614 static void netdrv_weird_interrupt (struct net_device *dev,
1615 struct netdrv_private *tp,
1616 void *ioaddr,
1617 int status, int link_changed)
1618 {
1619 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1620 dev->name, status);
1621
1622 assert (dev != NULL);
1623 assert (tp != NULL);
1624 assert (ioaddr != NULL);
1625
1626 /* Update the error count. */
1627 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1628 NETDRV_W32 (RxMissed, 0);
1629
1630 if ((status & RxUnderrun) && link_changed &&
1631 (tp->drv_flags & HAS_LNK_CHNG)) {
1632 /* Really link-change on new chips. */
1633 int lpar = NETDRV_R16 (NWayLPAR);
1634 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1635 || tp->duplex_lock;
1636 if (tp->full_duplex != duplex) {
1637 tp->full_duplex = duplex;
1638 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1639 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1640 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1641 }
1642 status &= ~RxUnderrun;
1643 }
1644
1645 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1646 if (status &
1647 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1648 tp->stats.rx_errors++;
1649
1650 if (status & (PCSTimeout))
1651 tp->stats.rx_length_errors++;
1652 if (status & (RxUnderrun | RxFIFOOver))
1653 tp->stats.rx_fifo_errors++;
1654 if (status & RxOverflow) {
1655 tp->stats.rx_over_errors++;
1656 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1657 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1658 }
1659 if (status & PCIErr) {
1660 u16 pci_cmd_status;
1661 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1662
1663 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1664 dev->name, pci_cmd_status);
1665 }
1666 }
1667
1668
1669 /* The interrupt handler does all of the Rx thread work and cleans up
1670 after the Tx thread. */
1671 static void netdrv_interrupt (int irq, void *dev_instance,
1672 struct pt_regs *regs)
1673 {
1674 struct net_device *dev = (struct net_device *) dev_instance;
1675 struct netdrv_private *tp = dev->priv;
1676 int boguscnt = max_interrupt_work;
1677 void *ioaddr = tp->mmio_addr;
1678 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1679
1680 spin_lock (&tp->lock);
1681
1682 do {
1683 status = NETDRV_R16 (IntrStatus);
1684
1685 /* h/w no longer present (hotplug?) or major error, bail */
1686 if (status == 0xFFFF)
1687 break;
1688
1689 /* Acknowledge all of the current interrupt sources ASAP */
1690 NETDRV_W16_F (IntrStatus, status);
1691
1692 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1693 dev->name, status,
1694 NETDRV_R16 (IntrStatus));
1695
1696 if ((status &
1697 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1698 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1699 break;
1700
1701 /* Check uncommon events with one test. */
1702 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1703 RxFIFOOver | TxErr | RxErr))
1704 netdrv_weird_interrupt (dev, tp, ioaddr,
1705 status, link_changed);
1706
1707 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1708 netdrv_rx_interrupt (dev, tp, ioaddr);
1709
1710 if (status & (TxOK | TxErr))
1711 netdrv_tx_interrupt (dev, tp, ioaddr);
1712
1713 boguscnt--;
1714 } while (boguscnt > 0);
1715
1716 if (boguscnt <= 0) {
1717 printk (KERN_WARNING
1718 "%s: Too much work at interrupt, "
1719 "IntrStatus=0x%4.4x.\n", dev->name,
1720 status);
1721
1722 /* Clear all interrupt sources. */
1723 NETDRV_W16 (IntrStatus, 0xffff);
1724 }
1725
1726 spin_unlock (&tp->lock);
1727
1728 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1729 dev->name, NETDRV_R16 (IntrStatus));
1730 }
1731
1732
1733 static int netdrv_close (struct net_device *dev)
1734 {
1735 struct netdrv_private *tp = dev->priv;
1736 void *ioaddr = tp->mmio_addr;
1737 unsigned long flags;
1738
1739 DPRINTK ("ENTER\n");
1740
1741 netif_stop_queue (dev);
1742
1743 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1744 dev->name, NETDRV_R16 (IntrStatus));
1745
1746 del_timer_sync (&tp->timer);
1747
1748 spin_lock_irqsave (&tp->lock, flags);
1749
1750 /* Stop the chip's Tx and Rx DMA processes. */
1751 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1752
1753 /* Disable interrupts by clearing the interrupt mask. */
1754 NETDRV_W16 (IntrMask, 0x0000);
1755
1756 /* Update the error counts. */
1757 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1758 NETDRV_W32 (RxMissed, 0);
1759
1760 spin_unlock_irqrestore (&tp->lock, flags);
1761
1762 synchronize_irq ();
1763 free_irq (dev->irq, dev);
1764
1765 netdrv_tx_clear (tp);
1766
1767 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1768 tp->rx_ring, tp->rx_ring_dma);
1769 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1770 tp->tx_bufs, tp->tx_bufs_dma);
1771 tp->rx_ring = NULL;
1772 tp->tx_bufs = NULL;
1773
1774 /* Green! Put the chip in low-power mode. */
1775 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1776 NETDRV_W8 (Config1, 0x03);
1777 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1778
1779 DPRINTK ("EXIT\n");
1780 return 0;
1781 }
1782
1783
1784 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1785 {
1786 struct netdrv_private *tp = dev->priv;
1787 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
1788 unsigned long flags;
1789 int rc = 0;
1790
1791 DPRINTK ("ENTER\n");
1792
1793 switch (cmd) {
1794 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1795 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1796 data->phy_id = tp->phys[0] & 0x3f;
1797 /* Fall Through */
1798
1799 case SIOCGMIIREG: /* Read MII PHY register. */
1800 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1801 spin_lock_irqsave (&tp->lock, flags);
1802 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1803 spin_unlock_irqrestore (&tp->lock, flags);
1804 break;
1805
1806 case SIOCSMIIREG: /* Write MII PHY register. */
1807 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1808 if (!capable (CAP_NET_ADMIN)) {
1809 rc = -EPERM;
1810 break;
1811 }
1812
1813 spin_lock_irqsave (&tp->lock, flags);
1814 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1815 spin_unlock_irqrestore (&tp->lock, flags);
1816 break;
1817
1818 default:
1819 rc = -EOPNOTSUPP;
1820 break;
1821 }
1822
1823 DPRINTK ("EXIT, returning %d\n", rc);
1824 return rc;
1825 }
1826
1827
1828 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1829 {
1830 struct netdrv_private *tp = dev->priv;
1831 void *ioaddr = tp->mmio_addr;
1832
1833 DPRINTK ("ENTER\n");
1834
1835 assert (tp != NULL);
1836
1837 if (netif_running(dev)) {
1838 unsigned long flags;
1839
1840 spin_lock_irqsave (&tp->lock, flags);
1841
1842 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1843 NETDRV_W32 (RxMissed, 0);
1844
1845 spin_unlock_irqrestore (&tp->lock, flags);
1846 }
1847
1848 DPRINTK ("EXIT\n");
1849 return &tp->stats;
1850 }
1851
1852 /* Set or clear the multicast filter for this adaptor.
1853 This routine is not state sensitive and need not be SMP locked. */
1854
1855 static unsigned const ethernet_polynomial = 0x04c11db7U;
1856 static inline u32 ether_crc (int length, unsigned char *data)
1857 {
1858 int crc = -1;
1859
1860 DPRINTK ("ENTER\n");
1861
1862 while (--length >= 0) {
1863 unsigned char current_octet = *data++;
1864 int bit;
1865 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
1866 crc = (crc << 1) ^
1867 ((crc < 0) ^ (current_octet & 1) ?
1868 ethernet_polynomial : 0);
1869 }
1870
1871 DPRINTK ("EXIT\n");
1872 return crc;
1873 }
1874
1875
1876 static void netdrv_set_rx_mode (struct net_device *dev)
1877 {
1878 struct netdrv_private *tp = dev->priv;
1879 void *ioaddr = tp->mmio_addr;
1880 u32 mc_filter[2]; /* Multicast hash filter */
1881 int i, rx_mode;
1882 u32 tmp;
1883
1884 DPRINTK ("ENTER\n");
1885
1886 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1887 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1888
1889 /* Note: do not reorder, GCC is clever about common statements. */
1890 if (dev->flags & IFF_PROMISC) {
1891 /* Unconditionally log net taps. */
1892 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1893 dev->name);
1894 rx_mode =
1895 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1896 AcceptAllPhys;
1897 mc_filter[1] = mc_filter[0] = 0xffffffff;
1898 } else if ((dev->mc_count > multicast_filter_limit)
1899 || (dev->flags & IFF_ALLMULTI)) {
1900 /* Too many to filter perfectly -- accept all multicasts. */
1901 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1902 mc_filter[1] = mc_filter[0] = 0xffffffff;
1903 } else {
1904 struct dev_mc_list *mclist;
1905 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1906 mc_filter[1] = mc_filter[0] = 0;
1907 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1908 i++, mclist = mclist->next)
1909 set_bit (ether_crc (ETH_ALEN, mclist->dmi_addr) >> 26,
1910 mc_filter);
1911 }
1912
1913 /* if called from irq handler, lock already acquired */
1914 if (!in_irq ())
1915 spin_lock_irq (&tp->lock);
1916
1917 /* We can safely update without stopping the chip. */
1918 tmp = netdrv_rx_config | rx_mode |
1919 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1920 NETDRV_W32_F (RxConfig, tmp);
1921 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1922 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1923
1924 if (!in_irq ())
1925 spin_unlock_irq (&tp->lock);
1926
1927 DPRINTK ("EXIT\n");
1928 }
1929
1930
1931 #ifdef CONFIG_PM
1932
1933 static int netdrv_suspend (struct pci_dev *pdev, u32 state)
1934 {
1935 struct net_device *dev = pci_get_drvdata (pdev);
1936 struct netdrv_private *tp = dev->priv;
1937 void *ioaddr = tp->mmio_addr;
1938 unsigned long flags;
1939
1940 if (!netif_running(dev))
1941 return;
1942 netif_device_detach (dev);
1943
1944 spin_lock_irqsave (&tp->lock, flags);
1945
1946 /* Disable interrupts, stop Tx and Rx. */
1947 NETDRV_W16 (IntrMask, 0x0000);
1948 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1949
1950 /* Update the error counts. */
1951 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1952 NETDRV_W32 (RxMissed, 0);
1953
1954 spin_unlock_irqrestore (&tp->lock, flags);
1955
1956 pci_power_off (pdev, -1);
1957
1958 return 0;
1959 }
1960
1961
1962 static int netdrv_resume (struct pci_dev *pdev)
1963 {
1964 struct net_device *dev = pci_get_drvdata (pdev);
1965
1966 if (!netif_running(dev))
1967 return;
1968 pci_power_on (pdev);
1969 netif_device_attach (dev);
1970 netdrv_hw_start (dev);
1971
1972 return 0;
1973 }
1974
1975 #endif /* CONFIG_PM */
1976
1977
1978 static struct pci_driver netdrv_pci_driver = {
1979 name: MODNAME,
1980 id_table: netdrv_pci_tbl,
1981 probe: netdrv_init_one,
1982 remove: netdrv_remove_one,
1983 #ifdef CONFIG_PM
1984 suspend: netdrv_suspend,
1985 resume: netdrv_resume,
1986 #endif /* CONFIG_PM */
1987 };
1988
1989
1990 static int __init netdrv_init_module (void)
1991 {
1992 /* when a module, this is printed whether or not devices are found in probe */
1993 #ifdef MODULE
1994 printk(version);
1995 #endif
1996 return pci_module_init (&netdrv_pci_driver);
1997 }
1998
1999
2000 static void __exit netdrv_cleanup_module (void)
2001 {
2002 pci_unregister_driver (&netdrv_pci_driver);
2003 }
2004
2005
2006 module_init(netdrv_init_module);
2007 module_exit(netdrv_cleanup_module);
2008