File: /usr/src/linux/drivers/net/pcmcia/nmclan_cs.c
1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License.
14
15 Ported to Linux 1.3.* network driver environment by
16 Matti Aarnio <mea@utu.fi>
17
18 References
19
20 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
21 Am79C940 (MACE) Data Sheet, 1994
22 Am79C90 (C-LANCE) Data Sheet, 1994
23 Linux PCMCIA Programmer's Guide v1.17
24 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
25
26 Eric Mears, New Media Corporation
27 Tom Pollard, New Media Corporation
28 Dean Siasoyco, New Media Corporation
29 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
30 Donald Becker <becker@scyld.com>
31 David Hinds <dahinds@users.sourceforge.net>
32
33 The Linux client driver is based on the 3c589_cs.c client driver by
34 David Hinds.
35
36 The Linux network driver outline is based on the 3c589_cs.c driver,
37 the 8390.c driver, and the example skeleton.c kernel code, which are
38 by Donald Becker.
39
40 The Am2150 network driver hardware interface code is based on the
41 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
42
43 Special thanks for testing and help in debugging this driver goes
44 to Ken Lesniak.
45
46 -------------------------------------------------------------------------------
47 Driver Notes and Issues
48 -------------------------------------------------------------------------------
49
50 1. Developed on a Dell 320SLi
51 PCMCIA Card Services 2.6.2
52 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
53
54 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
55 'insmod pcmcia_core.o io_speed=300'.
56 This will avoid problems with fast systems which causes rx_framecnt
57 to return random values.
58
59 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
60 before extraction.
61
62 4. There is a bad slow-down problem in this driver.
63
64 5. Future: Multicast processing. In the meantime, do _not_ compile your
65 kernel with multicast ip enabled.
66
67 -------------------------------------------------------------------------------
68 History
69 -------------------------------------------------------------------------------
70 Log: nmclan_cs.c,v
71 * Revision 0.16 1995/07/01 06:42:17 rpao
72 * Bug fix: nmclan_reset() called CardServices incorrectly.
73 *
74 * Revision 0.15 1995/05/24 08:09:47 rpao
75 * Re-implement MULTI_TX dev->tbusy handling.
76 *
77 * Revision 0.14 1995/05/23 03:19:30 rpao
78 * Added, in nmclan_config(), "tuple.Attributes = 0;".
79 * Modified MACE ID check to ignore chip revision level.
80 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
81 *
82 * Revision 0.13 1995/05/18 05:56:34 rpao
83 * Statistics changes.
84 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
85 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
86 *
87 * Revision 0.12 1995/05/14 00:12:23 rpao
88 * Statistics overhaul.
89 *
90
91 95/05/13 rpao V0.10a
92 Bug fix: MACE statistics counters used wrong I/O ports.
93 Bug fix: mace_interrupt() needed to allow statistics to be
94 processed without RX or TX interrupts pending.
95 95/05/11 rpao V0.10
96 Multiple transmit request processing.
97 Modified statistics to use MACE counters where possible.
98 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
99 *Released
100 95/05/10 rpao V0.08
101 Bug fix: Make all non-exported functions private by using
102 static keyword.
103 Bug fix: Test IntrCnt _before_ reading MACE_IR.
104 95/05/10 rpao V0.07 Statistics.
105 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
106
107 ---------------------------------------------------------------------------- */
108
109 /* ----------------------------------------------------------------------------
110 Conditional Compilation Options
111 ---------------------------------------------------------------------------- */
112
113 #define MULTI_TX 0
114 #define RESET_ON_TIMEOUT 1
115 #define TX_INTERRUPTABLE 1
116 #define RESET_XILINX 0
117
118 /* ----------------------------------------------------------------------------
119 Include Files
120 ---------------------------------------------------------------------------- */
121
122 #include <linux/module.h>
123 #include <linux/kernel.h>
124 #include <linux/init.h>
125 #include <linux/sched.h>
126 #include <linux/ptrace.h>
127 #include <linux/slab.h>
128 #include <linux/string.h>
129 #include <linux/timer.h>
130 #include <linux/interrupt.h>
131 #include <linux/in.h>
132 #include <linux/delay.h>
133 #include <asm/io.h>
134 #include <asm/system.h>
135 #include <asm/bitops.h>
136
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/skbuff.h>
140 #include <linux/if_arp.h>
141 #include <linux/ioport.h>
142
143 #include <pcmcia/version.h>
144 #include <pcmcia/cs_types.h>
145 #include <pcmcia/cs.h>
146 #include <pcmcia/cisreg.h>
147 #include <pcmcia/cistpl.h>
148 #include <pcmcia/ds.h>
149
150 /* ----------------------------------------------------------------------------
151 Defines
152 ---------------------------------------------------------------------------- */
153
154 #define ETHER_ADDR_LEN ETH_ALEN
155 /* 6 bytes in an Ethernet Address */
156 #define MACE_LADRF_LEN 8
157 /* 8 bytes in Logical Address Filter */
158
159 /* Loop Control Defines */
160 #define MACE_MAX_IR_ITERATIONS 10
161 #define MACE_MAX_RX_ITERATIONS 12
162 /*
163 TBD: Dean brought this up, and I assumed the hardware would
164 handle it:
165
166 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
167 non-zero when the isr exits. We may not get another interrupt
168 to process the remaining packets for some time.
169 */
170
171 /*
172 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
173 which manages the interface between the MACE and the PCMCIA bus. It
174 also includes buffer management for the 32K x 8 SRAM to control up to
175 four transmit and 12 receive frames at a time.
176 */
177 #define AM2150_MAX_TX_FRAMES 4
178 #define AM2150_MAX_RX_FRAMES 12
179
180 /* Am2150 Ethernet Card I/O Mapping */
181 #define AM2150_RCV 0x00
182 #define AM2150_XMT 0x04
183 #define AM2150_XMT_SKIP 0x09
184 #define AM2150_RCV_NEXT 0x0A
185 #define AM2150_RCV_FRAME_COUNT 0x0B
186 #define AM2150_MACE_BANK 0x0C
187 #define AM2150_MACE_BASE 0x10
188
189 /* MACE Registers */
190 #define MACE_RCVFIFO 0
191 #define MACE_XMTFIFO 1
192 #define MACE_XMTFC 2
193 #define MACE_XMTFS 3
194 #define MACE_XMTRC 4
195 #define MACE_RCVFC 5
196 #define MACE_RCVFS 6
197 #define MACE_FIFOFC 7
198 #define MACE_IR 8
199 #define MACE_IMR 9
200 #define MACE_PR 10
201 #define MACE_BIUCC 11
202 #define MACE_FIFOCC 12
203 #define MACE_MACCC 13
204 #define MACE_PLSCC 14
205 #define MACE_PHYCC 15
206 #define MACE_CHIPIDL 16
207 #define MACE_CHIPIDH 17
208 #define MACE_IAC 18
209 /* Reserved */
210 #define MACE_LADRF 20
211 #define MACE_PADR 21
212 /* Reserved */
213 /* Reserved */
214 #define MACE_MPC 24
215 /* Reserved */
216 #define MACE_RNTPC 26
217 #define MACE_RCVCC 27
218 /* Reserved */
219 #define MACE_UTR 29
220 #define MACE_RTR1 30
221 #define MACE_RTR2 31
222
223 /* MACE Bit Masks */
224 #define MACE_XMTRC_EXDEF 0x80
225 #define MACE_XMTRC_XMTRC 0x0F
226
227 #define MACE_XMTFS_XMTSV 0x80
228 #define MACE_XMTFS_UFLO 0x40
229 #define MACE_XMTFS_LCOL 0x20
230 #define MACE_XMTFS_MORE 0x10
231 #define MACE_XMTFS_ONE 0x08
232 #define MACE_XMTFS_DEFER 0x04
233 #define MACE_XMTFS_LCAR 0x02
234 #define MACE_XMTFS_RTRY 0x01
235
236 #define MACE_RCVFS_RCVSTS 0xF000
237 #define MACE_RCVFS_OFLO 0x8000
238 #define MACE_RCVFS_CLSN 0x4000
239 #define MACE_RCVFS_FRAM 0x2000
240 #define MACE_RCVFS_FCS 0x1000
241
242 #define MACE_FIFOFC_RCVFC 0xF0
243 #define MACE_FIFOFC_XMTFC 0x0F
244
245 #define MACE_IR_JAB 0x80
246 #define MACE_IR_BABL 0x40
247 #define MACE_IR_CERR 0x20
248 #define MACE_IR_RCVCCO 0x10
249 #define MACE_IR_RNTPCO 0x08
250 #define MACE_IR_MPCO 0x04
251 #define MACE_IR_RCVINT 0x02
252 #define MACE_IR_XMTINT 0x01
253
254 #define MACE_MACCC_PROM 0x80
255 #define MACE_MACCC_DXMT2PD 0x40
256 #define MACE_MACCC_EMBA 0x20
257 #define MACE_MACCC_RESERVED 0x10
258 #define MACE_MACCC_DRCVPA 0x08
259 #define MACE_MACCC_DRCVBC 0x04
260 #define MACE_MACCC_ENXMT 0x02
261 #define MACE_MACCC_ENRCV 0x01
262
263 #define MACE_PHYCC_LNKFL 0x80
264 #define MACE_PHYCC_DLNKTST 0x40
265 #define MACE_PHYCC_REVPOL 0x20
266 #define MACE_PHYCC_DAPC 0x10
267 #define MACE_PHYCC_LRT 0x08
268 #define MACE_PHYCC_ASEL 0x04
269 #define MACE_PHYCC_RWAKE 0x02
270 #define MACE_PHYCC_AWAKE 0x01
271
272 #define MACE_IAC_ADDRCHG 0x80
273 #define MACE_IAC_PHYADDR 0x04
274 #define MACE_IAC_LOGADDR 0x02
275
276 #define MACE_UTR_RTRE 0x80
277 #define MACE_UTR_RTRD 0x40
278 #define MACE_UTR_RPA 0x20
279 #define MACE_UTR_FCOLL 0x10
280 #define MACE_UTR_RCVFCSE 0x08
281 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
282 #define MACE_UTR_LOOP_NO_MENDEC 0x04
283 #define MACE_UTR_LOOP_EXTERNAL 0x02
284 #define MACE_UTR_LOOP_NONE 0x00
285 #define MACE_UTR_RESERVED 0x01
286
287 /* Switch MACE register bank (only 0 and 1 are valid) */
288 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
289
290 #define MACE_IMR_DEFAULT \
291 (0xFF - \
292 ( \
293 MACE_IR_CERR | \
294 MACE_IR_RCVCCO | \
295 MACE_IR_RNTPCO | \
296 MACE_IR_MPCO | \
297 MACE_IR_RCVINT | \
298 MACE_IR_XMTINT \
299 ) \
300 )
301 #undef MACE_IMR_DEFAULT
302 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
303
304 #define TX_TIMEOUT ((400*HZ)/1000)
305
306 /* ----------------------------------------------------------------------------
307 Type Definitions
308 ---------------------------------------------------------------------------- */
309
310 typedef struct _mace_statistics {
311 /* MACE_XMTFS */
312 int xmtsv;
313 int uflo;
314 int lcol;
315 int more;
316 int one;
317 int defer;
318 int lcar;
319 int rtry;
320
321 /* MACE_XMTRC */
322 int exdef;
323 int xmtrc;
324
325 /* RFS1--Receive Status (RCVSTS) */
326 int oflo;
327 int clsn;
328 int fram;
329 int fcs;
330
331 /* RFS2--Runt Packet Count (RNTPC) */
332 int rfs_rntpc;
333
334 /* RFS3--Receive Collision Count (RCVCC) */
335 int rfs_rcvcc;
336
337 /* MACE_IR */
338 int jab;
339 int babl;
340 int cerr;
341 int rcvcco;
342 int rntpco;
343 int mpco;
344
345 /* MACE_MPC */
346 int mpc;
347
348 /* MACE_RNTPC */
349 int rntpc;
350
351 /* MACE_RCVCC */
352 int rcvcc;
353 } mace_statistics;
354
355 typedef struct _mace_private {
356 dev_link_t link;
357 struct net_device dev;
358 dev_node_t node;
359 struct net_device_stats linux_stats; /* Linux statistics counters */
360 mace_statistics mace_stats; /* MACE chip statistics counters */
361
362 /* restore_multicast_list() state variables */
363 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
364 int multicast_num_addrs;
365
366 char tx_free_frames; /* Number of free transmit frame buffers */
367 char tx_irq_disabled; /* MACE TX interrupt disabled */
368 } mace_private;
369
370 /* ----------------------------------------------------------------------------
371 Private Global Variables
372 ---------------------------------------------------------------------------- */
373
374 #ifdef PCMCIA_DEBUG
375 static char rcsid[] =
376 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
377 static char *version =
378 "nmclan_cs 0.16 (Roger C. Pao)";
379 #endif
380
381 static dev_info_t dev_info="nmclan_cs";
382 static dev_link_t *dev_list;
383
384 static char *if_names[]={
385 "Auto", "10baseT", "BNC",
386 };
387
388 #ifdef PCMCIA_DEBUG
389 static int pc_debug = PCMCIA_DEBUG;
390 MODULE_PARM(pc_debug, "i");
391 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
392 #else
393 #define DEBUG(n, args...)
394 #endif
395
396 /* ----------------------------------------------------------------------------
397 Parameters
398 These are the parameters that can be set during loading with
399 'insmod'.
400 ---------------------------------------------------------------------------- */
401
402 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
403 static int if_port;
404
405 /* Bit map of interrupts to choose from */
406 static u_int irq_mask = 0xdeb8;
407 static int irq_list[4] = { -1 };
408
409 MODULE_PARM(if_port, "i");
410 MODULE_PARM(irq_mask, "i");
411 MODULE_PARM(irq_list, "1-4i");
412
413 /* ----------------------------------------------------------------------------
414 Function Prototypes
415 ---------------------------------------------------------------------------- */
416
417 static void nmclan_config(dev_link_t *link);
418 static void nmclan_release(u_long arg);
419 static int nmclan_event(event_t event, int priority,
420 event_callback_args_t *args);
421
422 static void nmclan_reset(struct net_device *dev);
423 static int mace_config(struct net_device *dev, struct ifmap *map);
424 static int mace_open(struct net_device *dev);
425 static int mace_close(struct net_device *dev);
426 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
427 static void mace_tx_timeout(struct net_device *dev);
428 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
429 static struct net_device_stats *mace_get_stats(struct net_device *dev);
430 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
431 static void restore_multicast_list(struct net_device *dev);
432
433 static void set_multicast_list(struct net_device *dev);
434
435 static dev_link_t *nmclan_attach(void);
436 static void nmclan_detach(dev_link_t *);
437
438 /* ----------------------------------------------------------------------------
439 flush_stale_links
440 Clean up stale device structures
441 ---------------------------------------------------------------------------- */
442
443 static void flush_stale_links(void)
444 {
445 dev_link_t *link, *next;
446 for (link = dev_list; link; link = next) {
447 next = link->next;
448 if (link->state & DEV_STALE_LINK)
449 nmclan_detach(link);
450 }
451 }
452
453 /* ----------------------------------------------------------------------------
454 cs_error
455 Report a Card Services related error.
456 ---------------------------------------------------------------------------- */
457
458 static void cs_error(client_handle_t handle, int func, int ret)
459 {
460 error_info_t err = { func, ret };
461 CardServices(ReportError, handle, &err);
462 }
463
464 /* ----------------------------------------------------------------------------
465 nmclan_attach
466 Creates an "instance" of the driver, allocating local data
467 structures for one device. The device is registered with Card
468 Services.
469 ---------------------------------------------------------------------------- */
470
471 static dev_link_t *nmclan_attach(void)
472 {
473 mace_private *lp;
474 dev_link_t *link;
475 struct net_device *dev;
476 client_reg_t client_reg;
477 int i, ret;
478
479 DEBUG(0, "nmclan_attach()\n");
480 DEBUG(1, "%s\n", rcsid);
481 flush_stale_links();
482
483 /* Create new ethernet device */
484 lp = kmalloc(sizeof(*lp), GFP_KERNEL);
485 if (!lp) return NULL;
486 memset(lp, 0, sizeof(*lp));
487 link = &lp->link; dev = &lp->dev;
488 link->priv = dev->priv = link->irq.Instance = lp;
489
490 link->release.function = &nmclan_release;
491 link->release.data = (u_long)link;
492 link->io.NumPorts1 = 32;
493 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
494 link->io.IOAddrLines = 5;
495 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
496 link->irq.IRQInfo1 = IRQ_INFO2_VALID|IRQ_LEVEL_ID;
497 if (irq_list[0] == -1)
498 link->irq.IRQInfo2 = irq_mask;
499 else
500 for (i = 0; i < 4; i++)
501 link->irq.IRQInfo2 |= 1 << irq_list[i];
502 link->irq.Handler = &mace_interrupt;
503 link->conf.Attributes = CONF_ENABLE_IRQ;
504 link->conf.Vcc = 50;
505 link->conf.IntType = INT_MEMORY_AND_IO;
506 link->conf.ConfigIndex = 1;
507 link->conf.Present = PRESENT_OPTION;
508
509 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
510
511 dev->hard_start_xmit = &mace_start_xmit;
512 dev->set_config = &mace_config;
513 dev->get_stats = &mace_get_stats;
514 dev->set_multicast_list = &set_multicast_list;
515 ether_setup(dev);
516 dev->open = &mace_open;
517 dev->stop = &mace_close;
518 #ifdef HAVE_TX_TIMEOUT
519 dev->tx_timeout = mace_tx_timeout;
520 dev->watchdog_timeo = TX_TIMEOUT;
521 #endif
522
523 /* Register with Card Services */
524 link->next = dev_list;
525 dev_list = link;
526 client_reg.dev_info = &dev_info;
527 client_reg.Attributes = INFO_IO_CLIENT | INFO_CARD_SHARE;
528 client_reg.EventMask =
529 CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
530 CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
531 CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
532 client_reg.event_handler = &nmclan_event;
533 client_reg.Version = 0x0210;
534 client_reg.event_callback_args.client_data = link;
535 ret = CardServices(RegisterClient, &link->handle, &client_reg);
536 if (ret != 0) {
537 cs_error(link->handle, RegisterClient, ret);
538 nmclan_detach(link);
539 return NULL;
540 }
541
542 return link;
543 } /* nmclan_attach */
544
545 /* ----------------------------------------------------------------------------
546 nmclan_detach
547 This deletes a driver "instance". The device is de-registered
548 with Card Services. If it has been released, all local data
549 structures are freed. Otherwise, the structures will be freed
550 when the device is released.
551 ---------------------------------------------------------------------------- */
552
553 static void nmclan_detach(dev_link_t *link)
554 {
555 mace_private *lp = link->priv;
556 dev_link_t **linkp;
557
558 DEBUG(0, "nmclan_detach(0x%p)\n", link);
559
560 /* Locate device structure */
561 for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
562 if (*linkp == link) break;
563 if (*linkp == NULL)
564 return;
565
566 del_timer(&link->release);
567 if (link->state & DEV_CONFIG) {
568 nmclan_release((u_long)link);
569 if (link->state & DEV_STALE_CONFIG) {
570 link->state |= DEV_STALE_LINK;
571 return;
572 }
573 }
574
575 if (link->handle)
576 CardServices(DeregisterClient, link->handle);
577
578 /* Unlink device structure, free bits */
579 *linkp = link->next;
580 if (link->dev)
581 unregister_netdev(&lp->dev);
582 kfree(lp);
583
584 } /* nmclan_detach */
585
586 /* ----------------------------------------------------------------------------
587 mace_read
588 Reads a MACE register. This is bank independent; however, the
589 caller must ensure that this call is not interruptable. We are
590 assuming that during normal operation, the MACE is always in
591 bank 0.
592 ---------------------------------------------------------------------------- */
593 static int mace_read(ioaddr_t ioaddr, int reg)
594 {
595 int data = 0xFF;
596 unsigned long flags;
597
598 switch (reg >> 4) {
599 case 0: /* register 0-15 */
600 data = inb(ioaddr + AM2150_MACE_BASE + reg);
601 break;
602 case 1: /* register 16-31 */
603 save_flags(flags);
604 cli();
605 MACEBANK(1);
606 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
607 MACEBANK(0);
608 restore_flags(flags);
609 break;
610 }
611 return (data & 0xFF);
612 } /* mace_read */
613
614 /* ----------------------------------------------------------------------------
615 mace_write
616 Writes to a MACE register. This is bank independent; however,
617 the caller must ensure that this call is not interruptable. We
618 are assuming that during normal operation, the MACE is always in
619 bank 0.
620 ---------------------------------------------------------------------------- */
621 static void mace_write(ioaddr_t ioaddr, int reg, int data)
622 {
623 unsigned long flags;
624
625 switch (reg >> 4) {
626 case 0: /* register 0-15 */
627 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
628 break;
629 case 1: /* register 16-31 */
630 save_flags(flags);
631 cli();
632 MACEBANK(1);
633 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
634 MACEBANK(0);
635 restore_flags(flags);
636 break;
637 }
638 } /* mace_write */
639
640 /* ----------------------------------------------------------------------------
641 mace_init
642 Resets the MACE chip.
643 ---------------------------------------------------------------------------- */
644 static void mace_init(ioaddr_t ioaddr, char *enet_addr)
645 {
646 int i;
647
648 /* MACE Software reset */
649 mace_write(ioaddr, MACE_BIUCC, 1);
650 while (mace_read(ioaddr, MACE_BIUCC) & 0x01) {
651 /* Wait for reset bit to be cleared automatically after <= 200ns */;
652 }
653 mace_write(ioaddr, MACE_BIUCC, 0);
654
655 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
656 mace_write(ioaddr, MACE_FIFOCC, 0x0F);
657
658 mace_write(ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
659 mace_write(ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
660
661 /*
662 * Bit 2-1 PORTSEL[1-0] Port Select.
663 * 00 AUI/10Base-2
664 * 01 10Base-T
665 * 10 DAI Port (reserved in Am2150)
666 * 11 GPSI
667 * For this card, only the first two are valid.
668 * So, PLSCC should be set to
669 * 0x00 for 10Base-2
670 * 0x02 for 10Base-T
671 * Or just set ASEL in PHYCC below!
672 */
673 switch (if_port) {
674 case 1:
675 mace_write(ioaddr, MACE_PLSCC, 0x02);
676 break;
677 case 2:
678 mace_write(ioaddr, MACE_PLSCC, 0x00);
679 break;
680 default:
681 mace_write(ioaddr, MACE_PHYCC, /* ASEL */ 4);
682 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
683 and the MACE device will automatically select the operating media
684 interface port. */
685 break;
686 }
687
688 mace_write(ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
689 /* Poll ADDRCHG bit */
690 while (mace_read(ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
691 ;
692 /* Set PADR register */
693 for (i = 0; i < ETHER_ADDR_LEN; i++)
694 mace_write(ioaddr, MACE_PADR, enet_addr[i]);
695
696 /* MAC Configuration Control Register should be written last */
697 /* Let set_multicast_list set this. */
698 /* mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
699 mace_write(ioaddr, MACE_MACCC, 0x00);
700 } /* mace_init */
701
702 /* ----------------------------------------------------------------------------
703 nmclan_config
704 This routine is scheduled to run after a CARD_INSERTION event
705 is received, to configure the PCMCIA socket, and to make the
706 ethernet device available to the system.
707 ---------------------------------------------------------------------------- */
708
709 #define CS_CHECK(fn, args...) \
710 while ((last_ret=CardServices(last_fn=(fn), args))!=0) goto cs_failed
711
712 static void nmclan_config(dev_link_t *link)
713 {
714 client_handle_t handle = link->handle;
715 mace_private *lp = link->priv;
716 struct net_device *dev = &lp->dev;
717 tuple_t tuple;
718 cisparse_t parse;
719 u_char buf[64];
720 int i, last_ret, last_fn;
721 ioaddr_t ioaddr;
722
723 DEBUG(0, "nmclan_config(0x%p)\n", link);
724
725 tuple.Attributes = 0;
726 tuple.TupleData = buf;
727 tuple.TupleDataMax = 64;
728 tuple.TupleOffset = 0;
729 tuple.DesiredTuple = CISTPL_CONFIG;
730 CS_CHECK(GetFirstTuple, handle, &tuple);
731 CS_CHECK(GetTupleData, handle, &tuple);
732 CS_CHECK(ParseTuple, handle, &tuple, &parse);
733 link->conf.ConfigBase = parse.config.base;
734
735 /* Configure card */
736 link->state |= DEV_CONFIG;
737
738 CS_CHECK(RequestIO, handle, &link->io);
739 CS_CHECK(RequestIRQ, handle, &link->irq);
740 CS_CHECK(RequestConfiguration, handle, &link->conf);
741 dev->irq = link->irq.AssignedIRQ;
742 dev->base_addr = link->io.BasePort1;
743 i = register_netdev(dev);
744 if (i != 0) {
745 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
746 goto failed;
747 }
748
749 ioaddr = dev->base_addr;
750
751 /* Read the ethernet address from the CIS. */
752 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
753 tuple.TupleData = buf;
754 tuple.TupleDataMax = 64;
755 tuple.TupleOffset = 0;
756 CS_CHECK(GetFirstTuple, handle, &tuple);
757 CS_CHECK(GetTupleData, handle, &tuple);
758 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
759
760 /* Verify configuration by reading the MACE ID. */
761 {
762 char sig[2];
763
764 sig[0] = mace_read(ioaddr, MACE_CHIPIDL);
765 sig[1] = mace_read(ioaddr, MACE_CHIPIDH);
766 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
767 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
768 sig[0], sig[1]);
769 } else {
770 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
771 " be 0x40 0x?9\n", sig[0], sig[1]);
772 link->state &= ~DEV_CONFIG_PENDING;
773 return;
774 }
775 }
776
777 mace_init(ioaddr, dev->dev_addr);
778
779 /* The if_port symbol can be set when the module is loaded */
780 if (if_port <= 2)
781 dev->if_port = if_port;
782 else
783 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
784
785 strcpy(lp->node.dev_name, dev->name);
786 link->dev = &lp->node;
787 link->state &= ~DEV_CONFIG_PENDING;
788
789 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
790 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
791 for (i = 0; i < 6; i++)
792 printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
793 return;
794
795 cs_failed:
796 cs_error(link->handle, last_fn, last_ret);
797 failed:
798 nmclan_release((u_long)link);
799 return;
800
801 } /* nmclan_config */
802
803 /* ----------------------------------------------------------------------------
804 nmclan_release
805 After a card is removed, nmclan_release() will unregister the
806 net device, and release the PCMCIA configuration. If the device
807 is still open, this will be postponed until it is closed.
808 ---------------------------------------------------------------------------- */
809 static void nmclan_release(u_long arg)
810 {
811 dev_link_t *link = (dev_link_t *)arg;
812
813 DEBUG(0, "nmclan_release(0x%p)\n", link);
814
815 if (link->open) {
816 DEBUG(1, "nmclan_cs: release postponed, '%s' "
817 "still open\n", link->dev->dev_name);
818 link->state |= DEV_STALE_CONFIG;
819 return;
820 }
821
822 CardServices(ReleaseConfiguration, link->handle);
823 CardServices(ReleaseIO, link->handle, &link->io);
824 CardServices(ReleaseIRQ, link->handle, &link->irq);
825
826 link->state &= ~DEV_CONFIG;
827
828 } /* nmclan_release */
829
830 /* ----------------------------------------------------------------------------
831 nmclan_event
832 The card status event handler. Mostly, this schedules other
833 stuff to run after an event is received. A CARD_REMOVAL event
834 also sets some flags to discourage the net drivers from trying
835 to talk to the card any more.
836 ---------------------------------------------------------------------------- */
837 static int nmclan_event(event_t event, int priority,
838 event_callback_args_t *args)
839 {
840 dev_link_t *link = args->client_data;
841 mace_private *lp = link->priv;
842 struct net_device *dev = &lp->dev;
843
844 DEBUG(1, "nmclan_event(0x%06x)\n", event);
845
846 switch (event) {
847 case CS_EVENT_CARD_REMOVAL:
848 link->state &= ~DEV_PRESENT;
849 if (link->state & DEV_CONFIG) {
850 netif_device_detach(dev);
851 mod_timer(&link->release, jiffies + HZ/20);
852 }
853 break;
854 case CS_EVENT_CARD_INSERTION:
855 link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
856 nmclan_config(link);
857 break;
858 case CS_EVENT_PM_SUSPEND:
859 link->state |= DEV_SUSPEND;
860 /* Fall through... */
861 case CS_EVENT_RESET_PHYSICAL:
862 if (link->state & DEV_CONFIG) {
863 if (link->open)
864 netif_device_detach(dev);
865 CardServices(ReleaseConfiguration, link->handle);
866 }
867 break;
868 case CS_EVENT_PM_RESUME:
869 link->state &= ~DEV_SUSPEND;
870 /* Fall through... */
871 case CS_EVENT_CARD_RESET:
872 if (link->state & DEV_CONFIG) {
873 CardServices(RequestConfiguration, link->handle, &link->conf);
874 if (link->open) {
875 nmclan_reset(dev);
876 netif_device_attach(dev);
877 }
878 }
879 break;
880 case CS_EVENT_RESET_REQUEST:
881 return 1;
882 break;
883 }
884 return 0;
885 } /* nmclan_event */
886
887 /* ----------------------------------------------------------------------------
888 nmclan_reset
889 Reset and restore all of the Xilinx and MACE registers.
890 ---------------------------------------------------------------------------- */
891 static void nmclan_reset(struct net_device *dev)
892 {
893 mace_private *lp = dev->priv;
894
895 #if RESET_XILINX
896 dev_link_t *link = &lp->link;
897 conf_reg_t reg;
898 u_long OrigCorValue;
899
900 /* Save original COR value */
901 reg.Function = 0;
902 reg.Action = CS_READ;
903 reg.Offset = CISREG_COR;
904 reg.Value = 0;
905 CardServices(AccessConfigurationRegister, link->handle, ®);
906 OrigCorValue = reg.Value;
907
908 /* Reset Xilinx */
909 reg.Action = CS_WRITE;
910 reg.Offset = CISREG_COR;
911 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
912 OrigCorValue);
913 reg.Value = COR_SOFT_RESET;
914 CardServices(AccessConfigurationRegister, link->handle, ®);
915 /* Need to wait for 20 ms for PCMCIA to finish reset. */
916
917 /* Restore original COR configuration index */
918 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
919 CardServices(AccessConfigurationRegister, link->handle, ®);
920 /* Xilinx is now completely reset along with the MACE chip. */
921 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
922
923 #endif /* #if RESET_XILINX */
924
925 /* Xilinx is now completely reset along with the MACE chip. */
926 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
927
928 /* Reinitialize the MACE chip for operation. */
929 mace_init(dev->base_addr, dev->dev_addr);
930 mace_write(dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
931
932 /* Restore the multicast list and enable TX and RX. */
933 restore_multicast_list(dev);
934 } /* nmclan_reset */
935
936 /* ----------------------------------------------------------------------------
937 mace_config
938 [Someone tell me what this is supposed to do? Is if_port a defined
939 standard? If so, there should be defines to indicate 1=10Base-T,
940 2=10Base-2, etc. including limited automatic detection.]
941 ---------------------------------------------------------------------------- */
942 static int mace_config(struct net_device *dev, struct ifmap *map)
943 {
944 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
945 if (map->port <= 2) {
946 dev->if_port = map->port;
947 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
948 if_names[dev->if_port]);
949 } else
950 return -EINVAL;
951 }
952 return 0;
953 } /* mace_config */
954
955 /* ----------------------------------------------------------------------------
956 mace_open
957 Open device driver.
958 ---------------------------------------------------------------------------- */
959 static int mace_open(struct net_device *dev)
960 {
961 ioaddr_t ioaddr = dev->base_addr;
962 mace_private *lp = dev->priv;
963 dev_link_t *link = &lp->link;
964
965 if (!DEV_OK(link))
966 return -ENODEV;
967
968 link->open++;
969 MOD_INC_USE_COUNT;
970
971 MACEBANK(0);
972
973 netif_start_queue(dev);
974 nmclan_reset(dev);
975
976 return 0; /* Always succeed */
977 } /* mace_open */
978
979 /* ----------------------------------------------------------------------------
980 mace_close
981 Closes device driver.
982 ---------------------------------------------------------------------------- */
983 static int mace_close(struct net_device *dev)
984 {
985 ioaddr_t ioaddr = dev->base_addr;
986 mace_private *lp = dev->priv;
987 dev_link_t *link = &lp->link;
988
989 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
990
991 /* Mask off all interrupts from the MACE chip. */
992 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
993
994 link->open--;
995 netif_stop_queue(dev);
996 if (link->state & DEV_STALE_CONFIG)
997 mod_timer(&link->release, jiffies + HZ/20);
998
999 MOD_DEC_USE_COUNT;
1000
1001 return 0;
1002 } /* mace_close */
1003
1004 /* ----------------------------------------------------------------------------
1005 mace_start_xmit
1006 This routine begins the packet transmit function. When completed,
1007 it will generate a transmit interrupt.
1008
1009 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
1010 returns 0, the "packet is now solely the responsibility of the
1011 driver." If _start_xmit returns non-zero, the "transmission
1012 failed, put skb back into a list."
1013 ---------------------------------------------------------------------------- */
1014
1015 static void mace_tx_timeout(struct net_device *dev)
1016 {
1017 mace_private *lp = (mace_private *)dev->priv;
1018 dev_link_t *link = &lp->link;
1019
1020 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
1021 #if RESET_ON_TIMEOUT
1022 printk("resetting card\n");
1023 CardServices(ResetCard, link->handle);
1024 #else /* #if RESET_ON_TIMEOUT */
1025 printk("NOT resetting card\n");
1026 #endif /* #if RESET_ON_TIMEOUT */
1027 dev->trans_start = jiffies;
1028 netif_wake_queue(dev);
1029 }
1030
1031 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
1032 {
1033 mace_private *lp = (mace_private *)dev->priv;
1034 ioaddr_t ioaddr = dev->base_addr;
1035
1036 netif_stop_queue(dev);
1037
1038 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
1039 dev->name, (long)skb->len);
1040
1041 #if (!TX_INTERRUPTABLE)
1042 /* Disable MACE TX interrupts. */
1043 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
1044 ioaddr + AM2150_MACE_BASE + MACE_IMR);
1045 lp->tx_irq_disabled=1;
1046 #endif /* #if (!TX_INTERRUPTABLE) */
1047
1048 {
1049 /* This block must not be interrupted by another transmit request!
1050 mace_tx_timeout will take care of timer-based retransmissions from
1051 the upper layers. The interrupt handler is guaranteed never to
1052 service a transmit interrupt while we are in here.
1053 */
1054
1055 lp->linux_stats.tx_bytes += skb->len;
1056 lp->tx_free_frames--;
1057
1058 /* WARNING: Write the _exact_ number of bytes written in the header! */
1059 /* Put out the word header [must be an outw()] . . . */
1060 outw(skb->len, ioaddr + AM2150_XMT);
1061 /* . . . and the packet [may be any combination of outw() and outb()] */
1062 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1063 if (skb->len & 1) {
1064 /* Odd byte transfer */
1065 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1066 }
1067
1068 dev->trans_start = jiffies;
1069
1070 #if MULTI_TX
1071 if (lp->tx_free_frames > 0)
1072 netif_start_queue(dev);
1073 #endif /* #if MULTI_TX */
1074 }
1075
1076 #if (!TX_INTERRUPTABLE)
1077 /* Re-enable MACE TX interrupts. */
1078 lp->tx_irq_disabled=0;
1079 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1080 #endif /* #if (!TX_INTERRUPTABLE) */
1081
1082 dev_kfree_skb(skb);
1083
1084 return 0;
1085 } /* mace_start_xmit */
1086
1087 /* ----------------------------------------------------------------------------
1088 mace_interrupt
1089 The interrupt handler.
1090 ---------------------------------------------------------------------------- */
1091 static void mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1092 {
1093 mace_private *lp = (mace_private *)dev_id;
1094 struct net_device *dev = &lp->dev;
1095 ioaddr_t ioaddr = dev->base_addr;
1096 int status;
1097 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1098
1099 if (dev == NULL) {
1100 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1101 irq);
1102 return;
1103 }
1104
1105 if (lp->tx_irq_disabled) {
1106 printk(
1107 (lp->tx_irq_disabled?
1108 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1109 "[isr=%02X, imr=%02X]\n":
1110 KERN_NOTICE "%s: Re-entering the interrupt handler "
1111 "[isr=%02X, imr=%02X]\n"),
1112 dev->name,
1113 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1114 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1115 );
1116 /* WARNING: MACE_IR has been read! */
1117 return;
1118 }
1119
1120 if (!netif_device_present(dev)) {
1121 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1122 goto exception;
1123 }
1124
1125 do {
1126 /* WARNING: MACE_IR is a READ/CLEAR port! */
1127 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1128
1129 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1130
1131 if (status & MACE_IR_RCVINT) {
1132 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1133 }
1134
1135 if (status & MACE_IR_XMTINT) {
1136 unsigned char fifofc;
1137 unsigned char xmtrc;
1138 unsigned char xmtfs;
1139
1140 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1141 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1142 lp->linux_stats.tx_errors++;
1143 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1144 }
1145
1146 /* Transmit Retry Count (XMTRC, reg 4) */
1147 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1148 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1149 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1150
1151 if (
1152 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1153 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1154 ) {
1155 lp->mace_stats.xmtsv++;
1156
1157 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1158 if (xmtfs & MACE_XMTFS_UFLO) {
1159 /* Underflow. Indicates that the Transmit FIFO emptied before
1160 the end of frame was reached. */
1161 lp->mace_stats.uflo++;
1162 }
1163 if (xmtfs & MACE_XMTFS_LCOL) {
1164 /* Late Collision */
1165 lp->mace_stats.lcol++;
1166 }
1167 if (xmtfs & MACE_XMTFS_MORE) {
1168 /* MORE than one retry was needed */
1169 lp->mace_stats.more++;
1170 }
1171 if (xmtfs & MACE_XMTFS_ONE) {
1172 /* Exactly ONE retry occurred */
1173 lp->mace_stats.one++;
1174 }
1175 if (xmtfs & MACE_XMTFS_DEFER) {
1176 /* Transmission was defered */
1177 lp->mace_stats.defer++;
1178 }
1179 if (xmtfs & MACE_XMTFS_LCAR) {
1180 /* Loss of carrier */
1181 lp->mace_stats.lcar++;
1182 }
1183 if (xmtfs & MACE_XMTFS_RTRY) {
1184 /* Retry error: transmit aborted after 16 attempts */
1185 lp->mace_stats.rtry++;
1186 }
1187 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1188
1189 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1190
1191 lp->linux_stats.tx_packets++;
1192 lp->tx_free_frames++;
1193 netif_wake_queue(dev);
1194 } /* if (status & MACE_IR_XMTINT) */
1195
1196 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1197 if (status & MACE_IR_JAB) {
1198 /* Jabber Error. Excessive transmit duration (20-150ms). */
1199 lp->mace_stats.jab++;
1200 }
1201 if (status & MACE_IR_BABL) {
1202 /* Babble Error. >1518 bytes transmitted. */
1203 lp->mace_stats.babl++;
1204 }
1205 if (status & MACE_IR_CERR) {
1206 /* Collision Error. CERR indicates the absence of the
1207 Signal Quality Error Test message after a packet
1208 transmission. */
1209 lp->mace_stats.cerr++;
1210 }
1211 if (status & MACE_IR_RCVCCO) {
1212 /* Receive Collision Count Overflow; */
1213 lp->mace_stats.rcvcco++;
1214 }
1215 if (status & MACE_IR_RNTPCO) {
1216 /* Runt Packet Count Overflow */
1217 lp->mace_stats.rntpco++;
1218 }
1219 if (status & MACE_IR_MPCO) {
1220 /* Missed Packet Count Overflow */
1221 lp->mace_stats.mpco++;
1222 }
1223 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1224
1225 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1226
1227 exception:
1228 return;
1229 } /* mace_interrupt */
1230
1231 /* ----------------------------------------------------------------------------
1232 mace_rx
1233 Receives packets.
1234 ---------------------------------------------------------------------------- */
1235 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1236 {
1237 mace_private *lp = (mace_private *)dev->priv;
1238 ioaddr_t ioaddr = dev->base_addr;
1239 unsigned char rx_framecnt;
1240 unsigned short rx_status;
1241
1242 while (
1243 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1244 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1245 (RxCnt--)
1246 ) {
1247 rx_status = inw(ioaddr + AM2150_RCV);
1248
1249 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1250 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1251
1252 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1253 lp->linux_stats.rx_errors++;
1254 if (rx_status & MACE_RCVFS_OFLO) {
1255 lp->mace_stats.oflo++;
1256 }
1257 if (rx_status & MACE_RCVFS_CLSN) {
1258 lp->mace_stats.clsn++;
1259 }
1260 if (rx_status & MACE_RCVFS_FRAM) {
1261 lp->mace_stats.fram++;
1262 }
1263 if (rx_status & MACE_RCVFS_FCS) {
1264 lp->mace_stats.fcs++;
1265 }
1266 } else {
1267 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1268 /* Auto Strip is off, always subtract 4 */
1269 struct sk_buff *skb;
1270
1271 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1272 /* runt packet count */
1273 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1274 /* rcv collision count */
1275
1276 DEBUG(3, " receiving packet size 0x%X rx_status"
1277 " 0x%X.\n", pkt_len, rx_status);
1278
1279 skb = dev_alloc_skb(pkt_len+2);
1280
1281 if (skb != NULL) {
1282 skb->dev = dev;
1283
1284 skb_reserve(skb, 2);
1285 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1286 if (pkt_len & 1)
1287 *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1288 skb->protocol = eth_type_trans(skb, dev);
1289
1290 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1291 dev->last_rx = jiffies;
1292 lp->linux_stats.rx_packets++;
1293 lp->linux_stats.rx_bytes += pkt_len;
1294 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1295 continue;
1296 } else {
1297 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1298 " %d.\n", dev->name, pkt_len);
1299 lp->linux_stats.rx_dropped++;
1300 }
1301 }
1302 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1303 } /* while */
1304
1305 return 0;
1306 } /* mace_rx */
1307
1308 /* ----------------------------------------------------------------------------
1309 pr_linux_stats
1310 ---------------------------------------------------------------------------- */
1311 static void pr_linux_stats(struct net_device_stats *pstats)
1312 {
1313 DEBUG(2, "pr_linux_stats\n");
1314 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1315 (long)pstats->rx_packets, (long)pstats->tx_packets);
1316 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1317 (long)pstats->rx_errors, (long)pstats->tx_errors);
1318 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1319 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1320 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1321 (long)pstats->multicast, (long)pstats->collisions);
1322
1323 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1324 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1325 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1326 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1327 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1328 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1329
1330 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1331 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1332 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1333 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1334 DEBUG(2, " tx_window_errors=%ld\n",
1335 (long)pstats->tx_window_errors);
1336 } /* pr_linux_stats */
1337
1338 /* ----------------------------------------------------------------------------
1339 pr_mace_stats
1340 ---------------------------------------------------------------------------- */
1341 static void pr_mace_stats(mace_statistics *pstats)
1342 {
1343 DEBUG(2, "pr_mace_stats\n");
1344
1345 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1346 pstats->xmtsv, pstats->uflo);
1347 DEBUG(2, " lcol=%-7d more=%d\n",
1348 pstats->lcol, pstats->more);
1349 DEBUG(2, " one=%-7d defer=%d\n",
1350 pstats->one, pstats->defer);
1351 DEBUG(2, " lcar=%-7d rtry=%d\n",
1352 pstats->lcar, pstats->rtry);
1353
1354 /* MACE_XMTRC */
1355 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1356 pstats->exdef, pstats->xmtrc);
1357
1358 /* RFS1--Receive Status (RCVSTS) */
1359 DEBUG(2, " oflo=%-7d clsn=%d\n",
1360 pstats->oflo, pstats->clsn);
1361 DEBUG(2, " fram=%-7d fcs=%d\n",
1362 pstats->fram, pstats->fcs);
1363
1364 /* RFS2--Runt Packet Count (RNTPC) */
1365 /* RFS3--Receive Collision Count (RCVCC) */
1366 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1367 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1368
1369 /* MACE_IR */
1370 DEBUG(2, " jab=%-7d babl=%d\n",
1371 pstats->jab, pstats->babl);
1372 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1373 pstats->cerr, pstats->rcvcco);
1374 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1375 pstats->rntpco, pstats->mpco);
1376
1377 /* MACE_MPC */
1378 DEBUG(2, " mpc=%d\n", pstats->mpc);
1379
1380 /* MACE_RNTPC */
1381 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1382
1383 /* MACE_RCVCC */
1384 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1385
1386 } /* pr_mace_stats */
1387
1388 /* ----------------------------------------------------------------------------
1389 update_stats
1390 Update statistics. We change to register window 1, so this
1391 should be run single-threaded if the device is active. This is
1392 expected to be a rare operation, and it's simpler for the rest
1393 of the driver to assume that window 0 is always valid rather
1394 than use a special window-state variable.
1395
1396 oflo & uflo should _never_ occur since it would mean the Xilinx
1397 was not able to transfer data between the MACE FIFO and the
1398 card's SRAM fast enough. If this happens, something is
1399 seriously wrong with the hardware.
1400 ---------------------------------------------------------------------------- */
1401 static void update_stats(ioaddr_t ioaddr, struct net_device *dev)
1402 {
1403 mace_private *lp = (mace_private *)dev->priv;
1404
1405 lp->mace_stats.rcvcc += mace_read(ioaddr, MACE_RCVCC);
1406 lp->mace_stats.rntpc += mace_read(ioaddr, MACE_RNTPC);
1407 lp->mace_stats.mpc += mace_read(ioaddr, MACE_MPC);
1408 /* At this point, mace_stats is fully updated for this call.
1409 We may now update the linux_stats. */
1410
1411 /* The MACE has no equivalent for linux_stats field which are commented
1412 out. */
1413
1414 /* lp->linux_stats.multicast; */
1415 lp->linux_stats.collisions =
1416 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1417 /* Collision: The MACE may retry sending a packet 15 times
1418 before giving up. The retry count is in XMTRC.
1419 Does each retry constitute a collision?
1420 If so, why doesn't the RCVCC record these collisions? */
1421
1422 /* detailed rx_errors: */
1423 lp->linux_stats.rx_length_errors =
1424 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1425 /* lp->linux_stats.rx_over_errors */
1426 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1427 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1428 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1429 lp->linux_stats.rx_missed_errors =
1430 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1431
1432 /* detailed tx_errors */
1433 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1434 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1435 /* LCAR usually results from bad cabling. */
1436 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1437 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1438 /* lp->linux_stats.tx_window_errors; */
1439
1440 return;
1441 } /* update_stats */
1442
1443 /* ----------------------------------------------------------------------------
1444 mace_get_stats
1445 Gathers ethernet statistics from the MACE chip.
1446 ---------------------------------------------------------------------------- */
1447 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1448 {
1449 mace_private *lp = (mace_private *)dev->priv;
1450
1451 update_stats(dev->base_addr, dev);
1452
1453 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1454 pr_linux_stats(&lp->linux_stats);
1455 pr_mace_stats(&lp->mace_stats);
1456
1457 return &lp->linux_stats;
1458 } /* net_device_stats */
1459
1460 /* ----------------------------------------------------------------------------
1461 updateCRC
1462 Modified from Am79C90 data sheet.
1463 ---------------------------------------------------------------------------- */
1464
1465 #if BROKEN_MULTICAST
1466
1467 static void updateCRC(int *CRC, int bit)
1468 {
1469 int poly[]={
1470 1,1,1,0, 1,1,0,1,
1471 1,0,1,1, 1,0,0,0,
1472 1,0,0,0, 0,0,1,1,
1473 0,0,1,0, 0,0,0,0
1474 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1475 CRC generator polynomial. */
1476
1477 int j;
1478
1479 /* shift CRC and control bit (CRC[32]) */
1480 for (j = 32; j > 0; j--)
1481 CRC[j] = CRC[j-1];
1482 CRC[0] = 0;
1483
1484 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1485 if (bit ^ CRC[32])
1486 for (j = 0; j < 32; j++)
1487 CRC[j] ^= poly[j];
1488 } /* updateCRC */
1489
1490 /* ----------------------------------------------------------------------------
1491 BuildLAF
1492 Build logical address filter.
1493 Modified from Am79C90 data sheet.
1494
1495 Input
1496 ladrf: logical address filter (contents initialized to 0)
1497 adr: ethernet address
1498 ---------------------------------------------------------------------------- */
1499 static void BuildLAF(int *ladrf, int *adr)
1500 {
1501 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1502
1503 int i, byte; /* temporary array indices */
1504 int hashcode; /* the output object */
1505
1506 CRC[32]=0;
1507
1508 for (byte = 0; byte < 6; byte++)
1509 for (i = 0; i < 8; i++)
1510 updateCRC(CRC, (adr[byte] >> i) & 1);
1511
1512 hashcode = 0;
1513 for (i = 0; i < 6; i++)
1514 hashcode = (hashcode << 1) + CRC[i];
1515
1516 byte = hashcode >> 3;
1517 ladrf[byte] |= (1 << (hashcode & 7));
1518
1519 #ifdef PCMCIA_DEBUG
1520 if (pc_debug > 2) {
1521 printk(KERN_DEBUG " adr =");
1522 for (i = 0; i < 6; i++)
1523 printk(" %02X", adr[i]);
1524 printk("\n" KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63]"
1525 " =", hashcode);
1526 for (i = 0; i < 8; i++)
1527 printk(" %02X", ladrf[i]);
1528 printk("\n");
1529 }
1530 #endif
1531 } /* BuildLAF */
1532
1533 /* ----------------------------------------------------------------------------
1534 restore_multicast_list
1535 Restores the multicast filter for MACE chip to the last
1536 set_multicast_list() call.
1537
1538 Input
1539 multicast_num_addrs
1540 multicast_ladrf[]
1541 ---------------------------------------------------------------------------- */
1542 static void restore_multicast_list(struct net_device *dev)
1543 {
1544 mace_private *lp = (mace_private *)dev->priv;
1545 int num_addrs = lp->multicast_num_addrs;
1546 int *ladrf = lp->multicast_ladrf;
1547 ioaddr_t ioaddr = dev->base_addr;
1548 int i;
1549
1550 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1551 dev->name, num_addrs);
1552
1553 if (num_addrs > 0) {
1554
1555 DEBUG(1, "Attempt to restore multicast list detected.\n");
1556
1557 mace_write(ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1558 /* Poll ADDRCHG bit */
1559 while (mace_read(ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1560 ;
1561 /* Set LADRF register */
1562 for (i = 0; i < MACE_LADRF_LEN; i++)
1563 mace_write(ioaddr, MACE_LADRF, ladrf[i]);
1564
1565 mace_write(ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1566 mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1567
1568 } else if (num_addrs < 0) {
1569
1570 /* Promiscuous mode: receive all packets */
1571 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1572 mace_write(ioaddr, MACE_MACCC,
1573 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1574 );
1575
1576 } else {
1577
1578 /* Normal mode */
1579 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1580 mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1581
1582 }
1583 } /* restore_multicast_list */
1584
1585 /* ----------------------------------------------------------------------------
1586 set_multicast_list
1587 Set or clear the multicast filter for this adaptor.
1588
1589 Input
1590 num_addrs == -1 Promiscuous mode, receive all packets
1591 num_addrs == 0 Normal mode, clear multicast list
1592 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1593 best-effort filtering.
1594 Output
1595 multicast_num_addrs
1596 multicast_ladrf[]
1597 ---------------------------------------------------------------------------- */
1598
1599 static void set_multicast_list(struct net_device *dev)
1600 {
1601 mace_private *lp = (mace_private *)dev->priv;
1602 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1603 int i;
1604 struct dev_mc_list *dmi = dev->mc_list;
1605
1606 #ifdef PCMCIA_DEBUG
1607 if (pc_debug > 1) {
1608 static int old;
1609 if (dev->mc_count != old) {
1610 old = dev->mc_count;
1611 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1612 dev->name, old);
1613 }
1614 }
1615 #endif
1616
1617 /* Set multicast_num_addrs. */
1618 lp->multicast_num_addrs = dev->mc_count;
1619
1620 /* Set multicast_ladrf. */
1621 if (num_addrs > 0) {
1622 /* Calculate multicast logical address filter */
1623 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1624 for (i = 0; i < dev->mc_count; i++) {
1625 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1626 dmi = dmi->next;
1627 BuildLAF(lp->multicast_ladrf, adr);
1628 }
1629 }
1630
1631 restore_multicast_list(dev);
1632
1633 } /* set_multicast_list */
1634
1635 #endif /* BROKEN_MULTICAST */
1636
1637 static void restore_multicast_list(struct net_device *dev)
1638 {
1639 ioaddr_t ioaddr = dev->base_addr;
1640
1641 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1642 ((mace_private *)(dev->priv))->multicast_num_addrs);
1643
1644 if (dev->flags & IFF_PROMISC) {
1645 /* Promiscuous mode: receive all packets */
1646 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1647 mace_write(ioaddr, MACE_MACCC,
1648 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1649 );
1650 } else {
1651 /* Normal mode */
1652 mace_write(ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1653 mace_write(ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1654 }
1655 } /* restore_multicast_list */
1656
1657 static void set_multicast_list(struct net_device *dev)
1658 {
1659 mace_private *lp = (mace_private *)dev->priv;
1660
1661 #ifdef PCMCIA_DEBUG
1662 if (pc_debug > 1) {
1663 static int old;
1664 if (dev->mc_count != old) {
1665 old = dev->mc_count;
1666 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1667 dev->name, old);
1668 }
1669 }
1670 #endif
1671
1672 lp->multicast_num_addrs = dev->mc_count;
1673 restore_multicast_list(dev);
1674
1675 } /* set_multicast_list */
1676
1677 /* ----------------------------------------------------------------------------
1678 init_nmclan_cs
1679 ---------------------------------------------------------------------------- */
1680
1681 static int __init init_nmclan_cs(void)
1682 {
1683 servinfo_t serv;
1684 DEBUG(0, "%s\n", version);
1685 CardServices(GetCardServicesInfo, &serv);
1686 if (serv.Revision != CS_RELEASE_CODE) {
1687 printk(KERN_NOTICE "nmclan_cs: Card Services release does not match!\n");
1688 return -1;
1689 }
1690 register_pccard_driver(&dev_info, &nmclan_attach, &nmclan_detach);
1691 return 0;
1692 }
1693
1694 /* ----------------------------------------------------------------------------
1695 exit_nmclan_cs
1696 ---------------------------------------------------------------------------- */
1697
1698 static void __exit exit_nmclan_cs(void)
1699 {
1700 DEBUG(0, "nmclan_cs: unloading\n");
1701 unregister_pccard_driver(&dev_info);
1702 while (dev_list != NULL)
1703 nmclan_detach(dev_list);
1704 }
1705
1706 module_init(init_nmclan_cs);
1707 module_exit(exit_nmclan_cs);
1708