File: /usr/src/linux/drivers/net/pcmcia/wavelan.h
1 /*
2 * Wavelan Pcmcia driver
3 *
4 * Jean II - HPLB '96
5 *
6 * Reorganization and extension of the driver.
7 * Original copyright follow. See wavelan_cs.h for details.
8 *
9 * This file contain the declarations of the Wavelan hardware. Note that
10 * the Pcmcia Wavelan include a i82593 controller (see definitions in
11 * file i82593.h).
12 *
13 * The main difference between the pcmcia hardware and the ISA one is
14 * the Ethernet Controller (i82593 instead of i82586). The i82593 allow
15 * only one send buffer. The PSA (Parameter Storage Area : EEprom for
16 * permanent storage of various info) is memory mapped, but not the
17 * MMI (Modem Management Interface).
18 */
19
20 /*
21 * Definitions for the AT&T GIS (formerly NCR) WaveLAN PCMCIA card:
22 * An Ethernet-like radio transceiver controlled by an Intel 82593
23 * coprocessor.
24 *
25 *
26 ****************************************************************************
27 * Copyright 1995
28 * Anthony D. Joseph
29 * Massachusetts Institute of Technology
30 *
31 * Permission to use, copy, modify, and distribute this program
32 * for any purpose and without fee is hereby granted, provided
33 * that this copyright and permission notice appear on all copies
34 * and supporting documentation, the name of M.I.T. not be used
35 * in advertising or publicity pertaining to distribution of the
36 * program without specific prior permission, and notice be given
37 * in supporting documentation that copying and distribution is
38 * by permission of M.I.T. M.I.T. makes no representations about
39 * the suitability of this software for any purpose. It is pro-
40 * vided "as is" without express or implied warranty.
41 ****************************************************************************
42 *
43 *
44 * Credits:
45 * Special thanks to Jan Hoogendoorn of AT&T GIS Utrecht for
46 * providing extremely useful information about WaveLAN PCMCIA hardware
47 *
48 * This driver is based upon several other drivers, in particular:
49 * David Hinds' Linux driver for the PCMCIA 3c589 ethernet adapter
50 * Bruce Janson's Linux driver for the AT-bus WaveLAN adapter
51 * Anders Klemets' PCMCIA WaveLAN adapter driver
52 * Robert Morris' BSDI driver for the PCMCIA WaveLAN adapter
53 */
54
55 #ifndef _WAVELAN_H
56 #define _WAVELAN_H
57
58 /************************** MAGIC NUMBERS ***************************/
59
60 /* The detection of the wavelan card is made by reading the MAC address
61 * from the card and checking it. If you have a non AT&T product (OEM,
62 * like DEC RoamAbout, or Digital Ocean, Epson, ...), you must modify this
63 * part to accomodate your hardware...
64 */
65 const unsigned char MAC_ADDRESSES[][3] =
66 {
67 { 0x08, 0x00, 0x0E }, /* AT&T Wavelan (standard) & DEC RoamAbout */
68 { 0x08, 0x00, 0x6A }, /* AT&T Wavelan (alternate) */
69 { 0x00, 0x00, 0xE1 }, /* Hitachi Wavelan */
70 { 0x00, 0x60, 0x1D } /* Lucent Wavelan (another one) */
71 /* Add your card here and send me the patch ! */
72 };
73
74 /*
75 * Constants used to convert channels to frequencies
76 */
77
78 /* Frequency available in the 2.0 modem, in units of 250 kHz
79 * (as read in the offset register of the dac area).
80 * Used to map channel numbers used by `wfreqsel' to frequencies
81 */
82 const short channel_bands[] = { 0x30, 0x58, 0x64, 0x7A, 0x80, 0xA8,
83 0xD0, 0xF0, 0xF8, 0x150 };
84
85 /* Frequencies of the 1.0 modem (fixed frequencies).
86 * Use to map the PSA `subband' to a frequency
87 * Note : all frequencies apart from the first one need to be multiplied by 10
88 */
89 const int fixed_bands[] = { 915e6, 2.425e8, 2.46e8, 2.484e8, 2.4305e8 };
90
91 /*************************** PC INTERFACE ****************************/
92
93 /* WaveLAN host interface definitions */
94
95 #define LCCR(base) (base) /* LAN Controller Command Register */
96 #define LCSR(base) (base) /* LAN Controller Status Register */
97 #define HACR(base) (base+0x1) /* Host Adapter Command Register */
98 #define HASR(base) (base+0x1) /* Host Adapter Status Register */
99 #define PIORL(base) (base+0x2) /* Program I/O Register Low */
100 #define RPLL(base) (base+0x2) /* Receive Pointer Latched Low */
101 #define PIORH(base) (base+0x3) /* Program I/O Register High */
102 #define RPLH(base) (base+0x3) /* Receive Pointer Latched High */
103 #define PIOP(base) (base+0x4) /* Program I/O Port */
104 #define MMR(base) (base+0x6) /* MMI Address Register */
105 #define MMD(base) (base+0x7) /* MMI Data Register */
106
107 /* Host Adaptor Command Register bit definitions */
108
109 #define HACR_LOF (1 << 3) /* Lock Out Flag, toggle every 250ms */
110 #define HACR_PWR_STAT (1 << 4) /* Power State, 1=active, 0=sleep */
111 #define HACR_TX_DMA_RESET (1 << 5) /* Reset transmit DMA ptr on high */
112 #define HACR_RX_DMA_RESET (1 << 6) /* Reset receive DMA ptr on high */
113 #define HACR_ROM_WEN (1 << 7) /* EEPROM write enabled when true */
114
115 #define HACR_RESET (HACR_TX_DMA_RESET | HACR_RX_DMA_RESET)
116 #define HACR_DEFAULT (HACR_PWR_STAT)
117
118 /* Host Adapter Status Register bit definitions */
119
120 #define HASR_MMI_BUSY (1 << 2) /* MMI is busy when true */
121 #define HASR_LOF (1 << 3) /* Lock out flag status */
122 #define HASR_NO_CLK (1 << 4) /* active when modem not connected */
123
124 /* Miscellaneous bit definitions */
125
126 #define PIORH_SEL_TX (1 << 5) /* PIOR points to 0=rx/1=tx buffer */
127 #define MMR_MMI_WR (1 << 0) /* Next MMI cycle is 0=read, 1=write */
128 #define PIORH_MASK 0x1f /* only low 5 bits are significant */
129 #define RPLH_MASK 0x1f /* only low 5 bits are significant */
130 #define MMI_ADDR_MASK 0x7e /* Bits 1-6 of MMR are significant */
131
132 /* Attribute Memory map */
133
134 #define CIS_ADDR 0x0000 /* Card Information Status Register */
135 #define PSA_ADDR 0x0e00 /* Parameter Storage Area address */
136 #define EEPROM_ADDR 0x1000 /* EEPROM address (unused ?) */
137 #define COR_ADDR 0x4000 /* Configuration Option Register */
138
139 /* Configuration Option Register bit definitions */
140
141 #define COR_CONFIG (1 << 0) /* Config Index, 0 when unconfigured */
142 #define COR_SW_RESET (1 << 7) /* Software Reset on true */
143 #define COR_LEVEL_IRQ (1 << 6) /* Level IRQ */
144
145 /* Local Memory map */
146
147 #define RX_BASE 0x0000 /* Receive memory, 8 kB */
148 #define TX_BASE 0x2000 /* Transmit memory, 2 kB */
149 #define UNUSED_BASE 0x2800 /* Unused, 22 kB */
150 #define RX_SIZE (TX_BASE-RX_BASE) /* Size of receive area */
151 #define RX_SIZE_SHIFT 6 /* Bits to shift in stop register */
152
153 #define TRUE 1
154 #define FALSE 0
155
156 #define MOD_ENAL 1
157 #define MOD_PROM 2
158
159 /* Size of a MAC address */
160 #define WAVELAN_ADDR_SIZE 6
161
162 /* Maximum size of Wavelan packet */
163 #define WAVELAN_MTU 1500
164
165 #define MAXDATAZ (6 + 6 + 2 + WAVELAN_MTU)
166
167 /********************** PARAMETER STORAGE AREA **********************/
168
169 /*
170 * Parameter Storage Area (PSA).
171 */
172 typedef struct psa_t psa_t;
173 struct psa_t
174 {
175 /* For the PCMCIA Adapter, locations 0x00-0x0F are unused and fixed at 00 */
176 unsigned char psa_io_base_addr_1; /* [0x00] Base address 1 ??? */
177 unsigned char psa_io_base_addr_2; /* [0x01] Base address 2 */
178 unsigned char psa_io_base_addr_3; /* [0x02] Base address 3 */
179 unsigned char psa_io_base_addr_4; /* [0x03] Base address 4 */
180 unsigned char psa_rem_boot_addr_1; /* [0x04] Remote Boot Address 1 */
181 unsigned char psa_rem_boot_addr_2; /* [0x05] Remote Boot Address 2 */
182 unsigned char psa_rem_boot_addr_3; /* [0x06] Remote Boot Address 3 */
183 unsigned char psa_holi_params; /* [0x07] HOst Lan Interface (HOLI) Parameters */
184 unsigned char psa_int_req_no; /* [0x08] Interrupt Request Line */
185 unsigned char psa_unused0[7]; /* [0x09-0x0F] unused */
186
187 unsigned char psa_univ_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x10-0x15] Universal (factory) MAC Address */
188 unsigned char psa_local_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x16-1B] Local MAC Address */
189 unsigned char psa_univ_local_sel; /* [0x1C] Universal Local Selection */
190 #define PSA_UNIVERSAL 0 /* Universal (factory) */
191 #define PSA_LOCAL 1 /* Local */
192 unsigned char psa_comp_number; /* [0x1D] Compatability Number: */
193 #define PSA_COMP_PC_AT_915 0 /* PC-AT 915 MHz */
194 #define PSA_COMP_PC_MC_915 1 /* PC-MC 915 MHz */
195 #define PSA_COMP_PC_AT_2400 2 /* PC-AT 2.4 GHz */
196 #define PSA_COMP_PC_MC_2400 3 /* PC-MC 2.4 GHz */
197 #define PSA_COMP_PCMCIA_915 4 /* PCMCIA 915 MHz or 2.0 */
198 unsigned char psa_thr_pre_set; /* [0x1E] Modem Threshold Preset */
199 unsigned char psa_feature_select; /* [0x1F] Call code required (1=on) */
200 #define PSA_FEATURE_CALL_CODE 0x01 /* Call code required (Japan) */
201 unsigned char psa_subband; /* [0x20] Subband */
202 #define PSA_SUBBAND_915 0 /* 915 MHz or 2.0 */
203 #define PSA_SUBBAND_2425 1 /* 2425 MHz */
204 #define PSA_SUBBAND_2460 2 /* 2460 MHz */
205 #define PSA_SUBBAND_2484 3 /* 2484 MHz */
206 #define PSA_SUBBAND_2430_5 4 /* 2430.5 MHz */
207 unsigned char psa_quality_thr; /* [0x21] Modem Quality Threshold */
208 unsigned char psa_mod_delay; /* [0x22] Modem Delay ??? (reserved) */
209 unsigned char psa_nwid[2]; /* [0x23-0x24] Network ID */
210 unsigned char psa_nwid_select; /* [0x25] Network ID Select On Off */
211 unsigned char psa_encryption_select; /* [0x26] Encryption On Off */
212 unsigned char psa_encryption_key[8]; /* [0x27-0x2E] Encryption Key */
213 unsigned char psa_databus_width; /* [0x2F] AT bus width select 8/16 */
214 unsigned char psa_call_code[8]; /* [0x30-0x37] (Japan) Call Code */
215 unsigned char psa_nwid_prefix[2]; /* [0x38-0x39] Roaming domain */
216 unsigned char psa_reserved[2]; /* [0x3A-0x3B] Reserved - fixed 00 */
217 unsigned char psa_conf_status; /* [0x3C] Conf Status, bit 0=1:config*/
218 unsigned char psa_crc[2]; /* [0x3D] CRC-16 over PSA */
219 unsigned char psa_crc_status; /* [0x3F] CRC Valid Flag */
220 };
221
222 /* Size for structure checking (if padding is correct) */
223 #define PSA_SIZE 64
224
225 /* Calculate offset of a field in the above structure
226 * Warning : only even addresses are used */
227 #define psaoff(p,f) ((unsigned short) ((void *)(&((psa_t *) ((void *) NULL + (p)))->f) - (void *) NULL))
228
229 /******************** MODEM MANAGEMENT INTERFACE ********************/
230
231 /*
232 * Modem Management Controller (MMC) write structure.
233 */
234 typedef struct mmw_t mmw_t;
235 struct mmw_t
236 {
237 unsigned char mmw_encr_key[8]; /* encryption key */
238 unsigned char mmw_encr_enable; /* enable/disable encryption */
239 #define MMW_ENCR_ENABLE_MODE 0x02 /* Mode of security option */
240 #define MMW_ENCR_ENABLE_EN 0x01 /* Enable security option */
241 unsigned char mmw_unused0[1]; /* unused */
242 unsigned char mmw_des_io_invert; /* Encryption option */
243 #define MMW_DES_IO_INVERT_RES 0x0F /* Reserved */
244 #define MMW_DES_IO_INVERT_CTRL 0xF0 /* Control ??? (set to 0) */
245 unsigned char mmw_unused1[5]; /* unused */
246 unsigned char mmw_loopt_sel; /* looptest selection */
247 #define MMW_LOOPT_SEL_DIS_NWID 0x40 /* disable NWID filtering */
248 #define MMW_LOOPT_SEL_INT 0x20 /* activate Attention Request */
249 #define MMW_LOOPT_SEL_LS 0x10 /* looptest w/o collision avoidance */
250 #define MMW_LOOPT_SEL_LT3A 0x08 /* looptest 3a */
251 #define MMW_LOOPT_SEL_LT3B 0x04 /* looptest 3b */
252 #define MMW_LOOPT_SEL_LT3C 0x02 /* looptest 3c */
253 #define MMW_LOOPT_SEL_LT3D 0x01 /* looptest 3d */
254 unsigned char mmw_jabber_enable; /* jabber timer enable */
255 /* Abort transmissions > 200 ms */
256 unsigned char mmw_freeze; /* freeze / unfreeeze signal level */
257 /* 0 : signal level & qual updated for every new message, 1 : frozen */
258 unsigned char mmw_anten_sel; /* antenna selection */
259 #define MMW_ANTEN_SEL_SEL 0x01 /* direct antenna selection */
260 #define MMW_ANTEN_SEL_ALG_EN 0x02 /* antenna selection algo. enable */
261 unsigned char mmw_ifs; /* inter frame spacing */
262 /* min time between transmission in bit periods (.5 us) - bit 0 ignored */
263 unsigned char mmw_mod_delay; /* modem delay (synchro) */
264 unsigned char mmw_jam_time; /* jamming time (after collision) */
265 unsigned char mmw_unused2[1]; /* unused */
266 unsigned char mmw_thr_pre_set; /* level threshold preset */
267 /* Discard all packet with signal < this value (4) */
268 unsigned char mmw_decay_prm; /* decay parameters */
269 unsigned char mmw_decay_updat_prm; /* decay update parameterz */
270 unsigned char mmw_quality_thr; /* quality (z-quotient) threshold */
271 /* Discard all packet with quality < this value (3) */
272 unsigned char mmw_netw_id_l; /* NWID low order byte */
273 unsigned char mmw_netw_id_h; /* NWID high order byte */
274 /* Network ID or Domain : create virtual net on the air */
275
276 /* 2.0 Hardware extension - frequency selection support */
277 unsigned char mmw_mode_select; /* for analog tests (set to 0) */
278 unsigned char mmw_unused3[1]; /* unused */
279 unsigned char mmw_fee_ctrl; /* frequency eeprom control */
280 #define MMW_FEE_CTRL_PRE 0x10 /* Enable protected instructions */
281 #define MMW_FEE_CTRL_DWLD 0x08 /* Download eeprom to mmc */
282 #define MMW_FEE_CTRL_CMD 0x07 /* EEprom commands : */
283 #define MMW_FEE_CTRL_READ 0x06 /* Read */
284 #define MMW_FEE_CTRL_WREN 0x04 /* Write enable */
285 #define MMW_FEE_CTRL_WRITE 0x05 /* Write data to address */
286 #define MMW_FEE_CTRL_WRALL 0x04 /* Write data to all addresses */
287 #define MMW_FEE_CTRL_WDS 0x04 /* Write disable */
288 #define MMW_FEE_CTRL_PRREAD 0x16 /* Read addr from protect register */
289 #define MMW_FEE_CTRL_PREN 0x14 /* Protect register enable */
290 #define MMW_FEE_CTRL_PRCLEAR 0x17 /* Unprotect all registers */
291 #define MMW_FEE_CTRL_PRWRITE 0x15 /* Write addr in protect register */
292 #define MMW_FEE_CTRL_PRDS 0x14 /* Protect register disable */
293 /* Never issue this command (PRDS) : it's irreversible !!! */
294
295 unsigned char mmw_fee_addr; /* EEprom address */
296 #define MMW_FEE_ADDR_CHANNEL 0xF0 /* Select the channel */
297 #define MMW_FEE_ADDR_OFFSET 0x0F /* Offset in channel data */
298 #define MMW_FEE_ADDR_EN 0xC0 /* FEE_CTRL enable operations */
299 #define MMW_FEE_ADDR_DS 0x00 /* FEE_CTRL disable operations */
300 #define MMW_FEE_ADDR_ALL 0x40 /* FEE_CTRL all operations */
301 #define MMW_FEE_ADDR_CLEAR 0xFF /* FEE_CTRL clear operations */
302
303 unsigned char mmw_fee_data_l; /* Write data to EEprom */
304 unsigned char mmw_fee_data_h; /* high octet */
305 unsigned char mmw_ext_ant; /* Setting for external antenna */
306 #define MMW_EXT_ANT_EXTANT 0x01 /* Select external antenna */
307 #define MMW_EXT_ANT_POL 0x02 /* Polarity of the antenna */
308 #define MMW_EXT_ANT_INTERNAL 0x00 /* Internal antenna */
309 #define MMW_EXT_ANT_EXTERNAL 0x03 /* External antenna */
310 #define MMW_EXT_ANT_IQ_TEST 0x1C /* IQ test pattern (set to 0) */
311 };
312
313 /* Size for structure checking (if padding is correct) */
314 #define MMW_SIZE 37
315
316 /* Calculate offset of a field in the above structure */
317 #define mmwoff(p,f) (unsigned short)((void *)(&((mmw_t *)((void *)0 + (p)))->f) - (void *)0)
318
319 /*
320 * Modem Management Controller (MMC) read structure.
321 */
322 typedef struct mmr_t mmr_t;
323 struct mmr_t
324 {
325 unsigned char mmr_unused0[8]; /* unused */
326 unsigned char mmr_des_status; /* encryption status */
327 unsigned char mmr_des_avail; /* encryption available (0x55 read) */
328 #define MMR_DES_AVAIL_DES 0x55 /* DES available */
329 #define MMR_DES_AVAIL_AES 0x33 /* AES (AT&T) available */
330 unsigned char mmr_des_io_invert; /* des I/O invert register */
331 unsigned char mmr_unused1[5]; /* unused */
332 unsigned char mmr_dce_status; /* DCE status */
333 #define MMR_DCE_STATUS_RX_BUSY 0x01 /* receiver busy */
334 #define MMR_DCE_STATUS_LOOPT_IND 0x02 /* loop test indicated */
335 #define MMR_DCE_STATUS_TX_BUSY 0x04 /* transmitter on */
336 #define MMR_DCE_STATUS_JBR_EXPIRED 0x08 /* jabber timer expired */
337 #define MMR_DCE_STATUS 0x0F /* mask to get the bits */
338 unsigned char mmr_dsp_id; /* DSP id (AA = Daedalus rev A) */
339 unsigned char mmr_unused2[2]; /* unused */
340 unsigned char mmr_correct_nwid_l; /* # of correct NWID's rxd (low) */
341 unsigned char mmr_correct_nwid_h; /* # of correct NWID's rxd (high) */
342 /* Warning : Read high order octet first !!! */
343 unsigned char mmr_wrong_nwid_l; /* # of wrong NWID's rxd (low) */
344 unsigned char mmr_wrong_nwid_h; /* # of wrong NWID's rxd (high) */
345 unsigned char mmr_thr_pre_set; /* level threshold preset */
346 #define MMR_THR_PRE_SET 0x3F /* level threshold preset */
347 #define MMR_THR_PRE_SET_CUR 0x80 /* Current signal above it */
348 unsigned char mmr_signal_lvl; /* signal level */
349 #define MMR_SIGNAL_LVL 0x3F /* signal level */
350 #define MMR_SIGNAL_LVL_VALID 0x80 /* Updated since last read */
351 unsigned char mmr_silence_lvl; /* silence level (noise) */
352 #define MMR_SILENCE_LVL 0x3F /* silence level */
353 #define MMR_SILENCE_LVL_VALID 0x80 /* Updated since last read */
354 unsigned char mmr_sgnl_qual; /* signal quality */
355 #define MMR_SGNL_QUAL 0x0F /* signal quality */
356 #define MMR_SGNL_QUAL_ANT 0x80 /* current antenna used */
357 unsigned char mmr_netw_id_l; /* NWID low order byte ??? */
358 unsigned char mmr_unused3[3]; /* unused */
359
360 /* 2.0 Hardware extension - frequency selection support */
361 unsigned char mmr_fee_status; /* Status of frequency eeprom */
362 #define MMR_FEE_STATUS_ID 0xF0 /* Modem revision id */
363 #define MMR_FEE_STATUS_DWLD 0x08 /* Download in progress */
364 #define MMR_FEE_STATUS_BUSY 0x04 /* EEprom busy */
365 unsigned char mmr_unused4[1]; /* unused */
366 unsigned char mmr_fee_data_l; /* Read data from eeprom (low) */
367 unsigned char mmr_fee_data_h; /* Read data from eeprom (high) */
368 };
369
370 /* Size for structure checking (if padding is correct) */
371 #define MMR_SIZE 36
372
373 /* Calculate offset of a field in the above structure */
374 #define mmroff(p,f) (unsigned short)((void *)(&((mmr_t *)((void *)0 + (p)))->f) - (void *)0)
375
376 /* Make the two above structures one */
377 typedef union mm_t
378 {
379 struct mmw_t w; /* Write to the mmc */
380 struct mmr_t r; /* Read from the mmc */
381 } mm_t;
382
383 #endif /* _WAVELAN_H */
384