File: /usr/include/asm/msr.h

1     #ifndef __ASM_MSR_H
2     #define __ASM_MSR_H
3     
4     /*
5      * Access to machine-specific registers (available on 586 and better only)
6      * Note: the rd* operations modify the parameters directly (without using
7      * pointer indirection), this allows gcc to optimize better
8      */
9     
10     #define rdmsr(msr,val1,val2) \
11          __asm__ __volatile__("rdmsr" \
12     			  : "=a" (val1), "=d" (val2) \
13     			  : "c" (msr))
14     
15     #define wrmsr(msr,val1,val2) \
16          __asm__ __volatile__("wrmsr" \
17     			  : /* no outputs */ \
18     			  : "c" (msr), "a" (val1), "d" (val2))
19     
20     #define rdtsc(low,high) \
21          __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
22     
23     #define rdtscl(low) \
24          __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
25     
26     #define rdtscll(val) \
27          __asm__ __volatile__("rdtsc" : "=A" (val))
28     
29     #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
30     
31     #define rdpmc(counter,low,high) \
32          __asm__ __volatile__("rdpmc" \
33     			  : "=a" (low), "=d" (high) \
34     			  : "c" (counter))
35     
36     /* symbolic names for some interesting MSRs */
37     #define MSR_IA32_PLATFORM_ID		0x017
38     
39     #define MSR_IA32_APICBASE		0x01b
40     #define		MSR_IA32_APICBASE_BSP		(1<<8)
41     #define		MSR_IA32_APICBASE_ENABLE	(1<<11)
42     #define		MSR_IA32_APICBASE_BASE		(0xfffff<<12)
43     
44     #define MSR_IA32_UCODE_WRITE		0x079
45     #define MSR_IA32_UCODE_REV		0x08b
46     
47     #define MSR_IA32_PERFCTR0		0x0c1
48     #define MSR_IA32_PERFCTR1		0x0c2
49     
50     #define MSR_IA32_MCG_CAP		0x179
51     #define MSR_IA32_MCG_STATUS		0x17a
52     #define MSR_IA32_MCG_CTL		0x17b
53     
54     #define MSR_IA32_EVNTSEL0		0x186
55     #define MSR_IA32_EVNTSEL1		0x187
56     
57     #define MSR_IA32_DEBUGCTLMSR		0x1d9
58     #define MSR_IA32_LASTBRANCHFROMIP	0x1db
59     #define MSR_IA32_LASTBRANCHTOIP		0x1dc
60     #define MSR_IA32_LASTINTFROMIP		0x1dd
61     #define MSR_IA32_LASTINTTOIP		0x1de
62     
63     #define MSR_IA32_MC0_BASE		0x400
64     #define		MSR_IA32_MC0_CTL_OFFSET		0x0
65     #define		MSR_IA32_MC0_STATUS_OFFSET	0x1
66     #define		MSR_IA32_MC0_ADDR_OFFSET	0x2
67     #define		MSR_IA32_MC0_MISC_OFFSET	0x3
68     #define		MSR_IA32_MC0_BANK_COUNT		0x4
69     
70     #define MSR_K7_EVNTSEL0			0xC0010000
71     #define MSR_K7_PERFCTR0			0xC0010004
72     
73     #endif /* __ASM_MSR_H */
74