File: /usr/src/linux/drivers/net/sk98lin/h/skgehw.h
1 /******************************************************************************
2 *
3 * Name: skgehw.h
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5 * Version: $Revision: 1.36 $
6 * Date: $Date: 2000/11/09 12:32:49 $
7 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product
8 * Family
9 *
10 ******************************************************************************/
11
12 /******************************************************************************
13 *
14 * (C)Copyright 1998-2000 SysKonnect GmbH.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * The information in this file is provided "AS IS" without warranty.
22 *
23 ******************************************************************************/
24
25 /******************************************************************************
26 *
27 * History:
28 * $Log: skgehw.h,v $
29 * Revision 1.36 2000/11/09 12:32:49 rassmann
30 * Renamed variables.
31 *
32 * Revision 1.35 2000/05/19 10:17:13 cgoos
33 * Added inactivity check in PHY_READ (in DEBUG mode only).
34 *
35 * Revision 1.34 1999/11/22 13:53:40 cgoos
36 * Changed license header to GPL.
37 *
38 * Revision 1.33 1999/08/27 11:17:10 malthoff
39 * It's more savely to put bracket around marco parameters.
40 * Brackets added for PHY_READ and PHY_WRITE.
41 *
42 * Revision 1.32 1999/05/19 07:31:01 cgoos
43 * Changes for 1000Base-T.
44 * Added HWAC_LINK_LED macro.
45 *
46 * Revision 1.31 1999/03/12 13:27:40 malthoff
47 * Remove __STDC__.
48 *
49 * Revision 1.30 1999/02/09 09:28:20 malthoff
50 * Add PCI_ERRBITS.
51 *
52 * Revision 1.29 1999/01/26 08:55:48 malthoff
53 * Bugfix: The 16 bit field releations inside the descriptor are
54 * endianess dependend if the descriptor reversal feature
55 * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
56 * Drivers which use this feature has to set the define
57 * SK_USE_REV_DESC.
58 *
59 * Revision 1.28 1998/12/10 11:10:22 malthoff
60 * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted.
61 *
62 * Revision 1.27 1998/11/13 14:19:21 malthoff
63 * Bug Fix: The bit definition of B3_PA_CTRL has completely
64 * changed from HW Spec v1.3 to v1.5.
65 *
66 * Revision 1.26 1998/11/04 08:31:48 cgoos
67 * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros.
68 *
69 * Revision 1.25 1998/11/04 07:16:25 cgoos
70 * Changed byte ordering in XM_INADDR/XM_INHASH again.
71 *
72 * Revision 1.24 1998/11/02 11:08:43 malthoff
73 * RxCtrl and TxCtrl must be volatile.
74 *
75 * Revision 1.23 1998/10/28 13:50:45 malthoff
76 * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros.
77 *
78 * Revision 1.22 1998/10/26 08:01:36 malthoff
79 * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1,
80 * RX_MFF_STAT_TO, and RX_MFF_TIST_TO.
81 * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF.
82 *
83 * Revision 1.21 1998/10/20 07:43:10 malthoff
84 * Fix: XM_IN/OUT/ADDR/HASH macros:
85 * The pointer must be casted.
86 *
87 * Revision 1.20 1998/10/19 15:53:59 malthoff
88 * Remove ML proto definitions.
89 *
90 * Revision 1.19 1998/10/16 14:40:17 gklug
91 * fix: typo B0_XM_IMSK regs
92 *
93 * Revision 1.18 1998/10/16 09:46:54 malthoff
94 * Remove temp defines for ML diag prototyp.
95 * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA
96 * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR,
97 * B0_XS2_CSR, and B0_XA2_CSR.
98 *
99 * Revision 1.17 1998/10/14 06:03:14 cgoos
100 * Changed shifted constant to ULONG.
101 *
102 * Revision 1.16 1998/10/09 07:05:41 malthoff
103 * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL.
104 *
105 * Revision 1.15 1998/10/05 07:54:23 malthoff
106 * Split up RB_CTRL and it's bit definition into
107 * RB_CTRL, RB_TST1, and RB_TST2.
108 * Rename RB_RX_HTPP to RB_RX_LTPP.
109 * Add ALL_PA_ENA_TO. Modify F_WATER_MARK
110 * according to HW Spec. v1.5.
111 * Add MFF_TX_CTRL_DEF.
112 *
113 * Revision 1.14 1998/09/28 13:31:16 malthoff
114 * bug fix: B2_MAC_3 is 0x110 not 0x114
115 *
116 * Revision 1.13 1998/09/24 14:42:56 malthoff
117 * Split the RX_MFF_TST into RX_MFF_CTRL2,
118 * RX_MFF_TST1, and RX_MFF_TST2.
119 * Rename RX_MFF_CTRL to RX_MFF_CTRL1.
120 * Add BMU bit CSR_SV_IDLE.
121 * Add macros PHY_READ() and PHY_WRITE().
122 * Rename macro SK_ADDR() to SK_HW_ADDR()
123 * because of conflicts with the Address Module.
124 *
125 * Revision 1.12 1998/09/16 07:25:33 malthoff
126 * Change the parameter order in the XM_INxx and XM_OUTxx macros,
127 * to have the IoC as first parameter.
128 *
129 * Revision 1.11 1998/09/03 09:58:41 malthoff
130 * Rework the XM_xxx macros. Use {} instead of () to
131 * be compatible with SK_xxx macros which are defined
132 * with {}.
133 *
134 * Revision 1.10 1998/09/02 11:16:39 malthoff
135 * Temporary modify B2_I2C_SW to make tests with
136 * the GE/ML prototyp.
137 *
138 * Revision 1.9 1998/08/19 09:11:49 gklug
139 * fix: struct are removed from c-source (see CCC)
140 * add: typedefs for all structs
141 *
142 * Revision 1.8 1998/08/18 08:27:27 malthoff
143 * Add some temporary workarounds to test GE
144 * sources with the ML.
145 *
146 * Revision 1.7 1998/07/03 14:42:26 malthoff
147 * bug fix: Correct macro XMA().
148 * Add temporary workaround to access the PCI config space over IO
149 *
150 * Revision 1.6 1998/06/23 11:30:36 malthoff
151 * Remove ';' with ',' in macors.
152 *
153 * Revision 1.5 1998/06/22 14:20:57 malthoff
154 * Add macro SK_ADDR(Base,Addr).
155 *
156 * Revision 1.4 1998/06/19 13:35:43 malthoff
157 * change 'pGec' with 'pAC'
158 *
159 * Revision 1.3 1998/06/17 14:58:16 cvs
160 * Lost keywords reinserted.
161 *
162 * Revision 1.1 1998/06/17 14:16:36 cvs
163 * created
164 *
165 *
166 ******************************************************************************/
167
168 #ifndef __INC_SKGEHW_H
169 #define __INC_SKGEHW_H
170
171 #ifdef __cplusplus
172 extern "C" {
173 #endif /* __cplusplus */
174
175 /* defines ********************************************************************/
176
177 /*
178 * Configuration Space header
179 * Since this module is used for different OS', those may be
180 * duplicate on some of them (e.g. Linux). But to keep the
181 * common source, we have to live with this...
182 */
183 #define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
184 #define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
185 #define PCI_COMMAND 0x04 /* 16 bit Command */
186 #define PCI_STATUS 0x06 /* 16 bit Status */
187 #define PCI_REV_ID 0x08 /* 8 bit Revision ID */
188 #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
189 #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
190 #define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
191 #define PCI_HEADER_T 0x0e /* 8 bit Header Type */
192 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
193 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
194 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
195 /* Byte 18..2b: reserved */
196 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
197 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
198 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
199 /* Byte 34..33: reserved */
200 #define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
201 /* Byte 35..3b: reserved */
202 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
203 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
204 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
205 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
206 /* Device Dependent Region */
207 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
208 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
209 /* Power Management Region */
210 #define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
211 #define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
212 #define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
213 #define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
214 /* Byte 0x4e: reserved */
215 #define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
216 /* VPD Region */
217 #define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
218 #define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
219 #define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
220 #define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
221 /* Byte 58..ff: reserved */
222
223 /*
224 * I2C Address (PCI Config)
225 *
226 * Note: The temperature and voltage sensors are relocated on a different
227 * I2C bus.
228 */
229 #define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
230
231 /*
232 * Define Bits and Values of the registers
233 */
234 /* PCI_VENDOR_ID 16 bit Vendor ID */
235 /* PCI_DEVICE_ID 16 bit Device ID */
236 /* Values for Vendor ID and Device ID shall be patched into the code */
237 /* PCI_COMMAND 16 bit Command */
238 /* Bit 15..10: reserved */
239 #define PCI_FBTEN (1<<9) /* Bit 9: Fast Back-To-Back enable */
240 #define PCI_SERREN (1<<8) /* Bit 8: SERR enable */
241 #define PCI_ADSTEP (1<<7) /* Bit 7: Address Stepping */
242 #define PCI_PERREN (1<<6) /* Bit 6: Parity Report Response enable */
243 #define PCI_VGA_SNOOP (1<<5) /* Bit 5: VGA palette snoop */
244 #define PCI_MWIEN (1<<4) /* Bit 4: Memory write an inv cycl ena */
245 #define PCI_SCYCEN (1<<3) /* Bit 3: Special Cycle enable */
246 #define PCI_BMEN (1<<2) /* Bit 2: Bus Master enable */
247 #define PCI_MEMEN (1<<1) /* Bit 1: Memory Space Access enable */
248 #define PCI_IOEN (1<<0) /* Bit 0: IO Space Access enable */
249
250 /* PCI_STATUS 16 bit Status */
251 #define PCI_PERR (1<<15) /* Bit 15: Parity Error */
252 #define PCI_SERR (1<<14) /* Bit 14: Signaled SERR */
253 #define PCI_RMABORT (1<<13) /* Bit 13: Received Master Abort */
254 #define PCI_RTABORT (1<<12) /* Bit 12: Received Target Abort */
255 /* Bit 11: reserved */
256 #define PCI_DEVSEL (3<<9) /* Bit 10..9: DEVSEL Timing */
257 #define PCI_DEV_FAST (0<<9) /* fast */
258 #define PCI_DEV_MEDIUM (1<<9) /* medium */
259 #define PCI_DEV_SLOW (2<<9) /* slow */
260 #define PCI_DATAPERR (1<<8) /* Bit 8: DATA Parity error detected */
261 #define PCI_FB2BCAP (1<<7) /* Bit 7: Fast Back-to-Back Capability */
262 #define PCI_UDF (1<<6) /* Bit 6: User Defined Features */
263 #define PCI_66MHZCAP (1<<5) /* Bit 5: 66 MHz PCI bus clock capable */
264 #define PCI_NEWCAP (1<<4) /* Bit 4: New cap. list implemented */
265 /* Bit 3..0: reserved */
266
267 #define PCI_ERRBITS (PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
268 PCI_DATAPERR)
269
270 /* PCI_CLASS_CODE 24 bit Class Code */
271 /* Byte 2: Base Class (02) */
272 /* Byte 1: SubClass (00) */
273 /* Byte 0: Programming Interface (00) */
274
275 /* PCI_CACHE_LSZ 8 bit Cache Line Size */
276 /* Possible values: 0,2,4,8,16,32,64,128 */
277
278 /* PCI_HEADER_T 8 bit Header Type */
279 #define PCI_HD_MF_DEV (1<<7) /* Bit 7: 0= single, 1= multi-func dev */
280 #define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
281
282 /* PCI_BIST 8 bit Built-in selftest */
283 /* Built-in Self test not supported (optional) */
284
285 /* PCI_BASE_1ST 32 bit 1st Base address */
286 #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
287 #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
288 #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
289 #define PCI_PREFEN (1L<<3) /* Bit 3: Prefetchable */
290 #define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
291 #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
292 #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
293 #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
294 #define PCI_MEMSPACE (1L<<0) /* Bit 0: Memory Space Indic. */
295
296 /* PCI_BASE_2ND 32 bit 2nd Base address */
297 #define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */
298 #define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */
299 /* Bit 1: reserved */
300 #define PCI_IOSPACE (1L<<0) /* Bit 0: I/O Space Indicator */
301
302 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
303 #define PCI_ROMBASE (0xfffeL<<17) /* Bit 31..17: ROM BASE address (1st)*/
304 #define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */
305 #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
306 /* Bit 10.. 1: reserved */
307 #define PCI_ROMEN (0x1L<<0) /* Bit 0: Address Decode enable */
308
309 /* Device Dependent Region */
310 /* PCI_OUR_REG_1 32 bit Our Register 1 */
311 /* Bit 31..26: reserved */
312 #define PCI_VIO (1L<<25) /* Bit 25: PCI IO Voltage, */
313 /* 0 = 3.3V / 1 = 5V */
314 #define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
315 /* 1 = Don't boot wth ROM*/
316 /* 0 = Boot with ROM */
317 #define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
318 #define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */
319 /* 1 = Map Flash to Mem */
320 /* 0 = Disable addr. dec*/
321 #define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
322 #define PCI_PAGE_16 (0L<<20) /* 16 k pages */
323 #define PCI_PAGE_32K (1L<<20) /* 32 k pages */
324 #define PCI_PAGE_64K (2L<<20) /* 64 k pages */
325 #define PCI_PAGE_128K (3L<<20) /* 128 k pages */
326 /* Bit 19: reserved */
327 #define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
328 #define PCI_NOTAR (1L<<15) /* Bit 15: No turnaround cycle */
329 #define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */
330 #define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
331 #define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
332 #define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
333 #define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */
334 #define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */
335 #define PCI_DIS_PCI_CLK (1L<<8) /* Bit 8: Disable PCI clock driv*/
336 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */
337 #define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */
338
339
340 /* PCI_OUR_REG_2 32 bit Our Register 2 */
341 #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
342 #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
343 #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
344 /* Bit 13..12: reserved */
345 #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patchs dir 3..0 */
346 #define PCI_PATCH_DIR_0 (1L<<8)
347 #define PCI_PATCH_DIR_1 (1L<<9)
348 #define PCI_PATCH_DIR_2 (1L<<10)
349 #define PCI_PATCH_DIR_3 (1L<<11)
350 #define PCI_EXT_PATCHS (0xfL<<4) /* Bit 7..4: Extended Patches 3..0 */
351 #define PCI_EXT_PATCH_0 (1L<<4)
352 #define PCI_EXT_PATCH_1 (1L<<5)
353 #define PCI_EXT_PATCH_2 (1L<<6)
354 #define PCI_EXT_PATCH_3 (1L<<7)
355 #define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3: Enable Dummy Read */
356 #define PCI_REV_DESC (1L<<2) /* Bit 2: Reverse Desc. Bytes */
357 /* Bit 1: reserved */
358 #define PCI_USEDATA64 (1L<<0) /* Bit 0: Use 64Bit Data bus ext*/
359
360
361 /* Power Management Region */
362 /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
363 #define PCI_PME_SUP (0x1f<<11) /* Bit 15..11: PM Manag. Event Sup */
364 #define PCI_PM_D2_SUB (1<<10) /* Bit 10: D2 Support Bit */
365 #define PCI_PM_D1_SUB (1<<9) /* Bit 9: D1 Support Bit */
366 /* Bit 8..6: reserved */
367 #define PCI_PM_DSI (1<<5) /* Bit 5: Device Specific Init.*/
368 #define PCI_PM_APS (1<<4) /* Bit 4: Auxialiary Power Src */
369 #define PCI_PME_CLOCK (1<<3) /* Bit 3: PM Event Clock */
370 #define PCI_PM_VER (7<<0) /* Bit 2..0: PM PCI Spec. version */
371
372 /* PCI_PM_CTL_STS 16 bit Power Manag. Control/Status */
373 #define PCI_PME_STATUS (1<<15) /* Bit 15: PGA doesn't sup. PME# */
374 #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: dat reg Scaling factor*/
375 #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field*/
376 #define PCI_PME_EN (1<<8) /* Bit 8: PGA doesn't sup. PME# */
377 /* Bit 7.. 2: reserved */
378 #define PCI_PM_STATE (3<<0) /* Bit 1.. 0: Power Management State*/
379 #define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */
380 #define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */
381 #define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */
382 #define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */
383
384 /* VPD Region */
385 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
386 #define PCI_VPD_FLAG (1L<<15) /* Bit 15: starts VPD rd/wd cycle*/
387 #define PCI_VPD_ADDR (0x3fffL<<0) /* Bit 14..0: VPD address */
388
389 /*
390 * Control Register File:
391 * Bank 0
392 */
393 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
394 /* 0x0001 - 0x0003: reserved */
395 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
396 #define B0_LED 0x0006 /* 8 Bit LED register */
397 /* 0x0007: reserved */
398 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
399 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
400 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
401 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
402 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
403 /* 0x001c: reserved */
404
405 /* B0 XMAC 1 registers */
406 #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
407 /* 0x0022 - 0x0027 reserved */
408 #define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */
409 /* 0x002a - 0x002f reserved */
410 #define B0_XM1_PHY_ADDR 0x0030 /* 16 bit r/w XMAC 1 PHY Address Register */
411 /* 0x0032 - 0x0033 reserved */
412 #define B0_XM1_PHY_DATA 0x0034 /* 16 bit r/w XMAC 1 PHY Data Register */
413 /* 0x0036 - 0x003f reserved */
414
415 /* B0 XMAC 2 registers */
416 #define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/
417 /* 0x0042 - 0x0047 reserved */
418 #define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */
419 /* 0x004a - 0x004f reserved */
420 #define B0_XM2_PHY_ADDR 0x0050 /* 16 bit r/w XMAC 2 PHY Address Register */
421 /* 0x0052 - 0x0053 reserved */
422 #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
423 /* 0x0056 - 0x005f reserved */
424
425 /* BMU Control Status Registers */
426 #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
427 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
428 #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
429 #define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/
430 #define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
431 #define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/
432 /* x0078 - 0x007f reserved */
433
434 /*
435 * Bank 1
436 * - completely empty (this is the RAP Block window)
437 * Note: if RAP = 1 this page is reserved
438 */
439
440 /*
441 * Bank 2
442 */
443 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
444
445 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
446 /* 0x0106 - 0x0107 reserved */
447 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
448 /* 0x010e - 0x010f reserved */
449 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
450 /* 0x0116 - 0x0117 reserved */
451 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
452 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
453 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration */
454 #define B2_CHIP_REV 0x011b /* 8 bit Queen Chip Revision Number */
455 /* Eprom registers are currently of no use */
456 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 */
457 #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 */
458 #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
459 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
460 #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
461 #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
462 /* 0x0125 - 0x0127: reserved */
463 #define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */
464 #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
465 /* 0x012a - 0x012f: reserved */
466 #define B2_TI_INI 0x0130 /* 32 bit Timer init value */
467 #define B2_TI_VAL 0x0134 /* 32 bit Timer value */
468 #define B2_TI_CRTL 0x0138 /* 8 bit Timer control */
469 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
470 /* 0x013a - 0x013f: reserved */
471 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
472 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
473 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
474 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
475 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
476 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
477 /* 0x0154 - 0x0157: reserved */
478 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
479 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
480 /* 0x015a - 0x015b: reserved */
481 #define B2_GP_IO 0x015c /* 32 bit General Purpose IO Register */
482 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
483 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
484 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
485 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
486 #define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */
487 #define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */
488 #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
489 #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
490 #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
491 /* 0x017c - 0x017f: reserved */
492
493 /*
494 * Bank 3
495 */
496 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
497 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
498 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
499 /* 0x018c - 0x018f: reserved */
500 /* RAM Interface Registers */
501 /*
502 * The HW-Spec. call this registers Timeout Value 0..11. But this names are
503 * not usable in SW. Please notice these are NOT real timeouts, these are
504 * the number of qWords transfered continously.
505 */
506 #define B3_RI_WTO_R1 0x0190 /* 8 bit RAM Iface WR Timeout Queue R1 (TO0) */
507 #define B3_RI_WTO_XA1 0x0191 /* 8 bit RAM Iface WR Timeout Queue XA1 (TO1) */
508 #define B3_RI_WTO_XS1 0x0192 /* 8 bit RAM Iface WR Timeout Queue XS1 (TO2) */
509 #define B3_RI_RTO_R1 0x0193 /* 8 bit RAM Iface RD Timeout Queue R1 (TO3) */
510 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RAM Iface RD Timeout Queue XA1 (TO4) */
511 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RAM Iface RD Timeout Queue XS1 (TO5) */
512 #define B3_RI_WTO_R2 0x0196 /* 8 bit RAM Iface WR Timeout Queue R2 (TO6) */
513 #define B3_RI_WTO_XA2 0x0197 /* 8 bit RAM Iface WR Timeout Queue XA2 (TO7) */
514 #define B3_RI_WTO_XS2 0x0198 /* 8 bit RAM Iface WR Timeout Queue XS2 (TO8) */
515 #define B3_RI_RTO_R2 0x0199 /* 8 bit RAM Iface RD Timeout Queue R2 (TO9) */
516 #define B3_RI_RTO_XA2 0x019a /* 8 bit RAM Iface RD Timeout Queue XA2 (TO10)*/
517 #define B3_RI_RTO_XS2 0x019b /* 8 bit RAM Iface RD Timeout Queue XS2 (TO11)*/
518 #define B3_RI_TO_VAL 0x019c /* 8 bit RAM Iface Current Timeout Count Val */
519 /* 0x019d - 0x019f reserved */
520 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Iface Control Register */
521 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Iface Test Register */
522 /* 0x01a3 - 0x01af reserved */
523 /* MAC Arbiter Registers */
524 /* Please notice these are the number of qWord tranfered continously and */
525 /* NOT real timeouts */
526 #define B3_MA_TOINI_RX1 0x01b0 /* 8 bit Timeout Init Value Rx Path MAC 1 */
527 #define B3_MA_TOINI_RX2 0x01b1 /* 8 bit Timeout Init Value Rx Path MAC 2 */
528 #define B3_MA_TOINI_TX1 0x01b2 /* 8 bit Timeout Init Value Tx Path MAC 1 */
529 #define B3_MA_TOINI_TX2 0x01b3 /* 8 bit Timeout Init Value Tx Path MAC 2 */
530 #define B3_MA_TOVAL_RX1 0x01b4 /* 8 bit Timeout Value Rx Path MAC 1 */
531 #define B3_MA_TOVAL_RX2 0x01b5 /* 8 bit Timeout Value Rx Path MAC 1 */
532 #define B3_MA_TOVAL_TX1 0x01b6 /* 8 bit Timeout Value Tx Path MAC 2 */
533 #define B3_MA_TOVAL_TX2 0x01b7 /* 8 bit Timeout Value Tx Path MAC 2 */
534 #define B3_MA_TO_CTRL 0x01b8 /* 16 bit MAC Arbiter Timeout Ctrl Reg */
535 #define B3_MA_TO_TEST 0x01ba /* 16 bit MAC Arbiter Timeout Test Reg */
536 /* 0x01bc - 0x01bf reserved */
537 #define B3_MA_RCINI_RX1 0x01c0 /* 8 bit Recovery Init Value Rx Path MAC 1 */
538 #define B3_MA_RCINI_RX2 0x01c1 /* 8 bit Recovery Init Value Rx Path MAC 2 */
539 #define B3_MA_RCINI_TX1 0x01c2 /* 8 bit Recovery Init Value Tx Path MAC 1 */
540 #define B3_MA_RCINI_TX2 0x01c3 /* 8 bit Recovery Init Value Tx Path MAC 2 */
541 #define B3_MA_RCVAL_RX1 0x01c4 /* 8 bit Recovery Value Rx Path MAC 1 */
542 #define B3_MA_RCVAL_RX2 0x01c5 /* 8 bit Recovery Value Rx Path MAC 1 */
543 #define B3_MA_RCVAL_TX1 0x01c6 /* 8 bit Recovery Value Tx Path MAC 2 */
544 #define B3_MA_RCVAL_TX2 0x01c7 /* 8 bit Recovery Value Tx Path MAC 2 */
545 #define B3_MA_RC_CTRL 0x01c8 /* 16 bit MAC Arbiter Recovery Ctrl Reg */
546 #define B3_MA_RC_TEST 0x01ca /* 16 bit MAC Arbiter Recovery Test Reg */
547 /* 0x01cc - 0x01cf reserved */
548 /* Packet Arbiter Registers, This are real timeouts */
549 #define B3_PA_TOINI_RX1 0x01d0 /* 16 bit Timeout Init Val Rx Path MAC 1*/
550 /* 0x01d2 - 0x01d3: reserved */
551 #define B3_PA_TOINI_RX2 0x01d4 /* 16 bit Timeout Init Val Rx Path MAC 2*/
552 /* 0x01d6 - 0x01d7: reserved */
553 #define B3_PA_TOINI_TX1 0x01d8 /* 16 bit Timeout Init Val Tx Path MAC 1*/
554 /* 0x01da - 0x01db: reserved */
555 #define B3_PA_TOINI_TX2 0x01dc /* 16 bit Timeout Init Val Tx Path MAC 2*/
556 /* 0x01de - 0x01df: reserved */
557 #define B3_PA_TOVAL_RX1 0x01e0 /* 16 bit Timeout Val Rx Path MAC 1 */
558 /* 0x01e2 - 0x01e3: reserved */
559 #define B3_PA_TOVAL_RX2 0x01e4 /* 16 bit Timeout Val Rx Path MAC 2 */
560 /* 0x01e6 - 0x01e7: reserved */
561 #define B3_PA_TOVAL_TX1 0x01e8 /* 16 bit Timeout Val Tx Path MAC 1 */
562 /* 0x01ea - 0x01eb: reserved */
563 #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
564 /* 0x01ee - 0x01ef: reserved */
565 #define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
566 #define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
567 /* 0x01f4 - 0x01ff: reserved */
568
569 /*
570 * Bank 4 - 5
571 */
572
573 /* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
574 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
575 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
576 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
577 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
578 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
579 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
580 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
581 /* 0x0213 - 0x027f: reserved */
582
583 /*
584 * Bank 6
585 */
586 /* External registers */
587 #define B6_EXT_REG 0x0300
588
589 /*
590 * Bank 7
591 */
592 /* This is a copy of the Configuration register file (lower half) */
593 #define B7_CFG_SPC 0x0380
594
595 /*
596 * Bank 8 - 15
597 */
598 /* Receive and Transmit Queue Registers, use Q_ADDR() to access */
599 #define B8_Q_REGS 0x0400
600
601 /* Queue Register Offsets, use Q_ADDR() to access */
602 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
603 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
604 #define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
605 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
606 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
607 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
608 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
609 #define Q_F 0x38 /* 32 bit Flag Register */
610 #define Q_T1 0x3c /* 32 bit Test Register 1 */
611 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
612 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
613 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
614 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
615 #define Q_T2 0x40 /* 32 bit Test Register 2 */
616 #define Q_T3 0x44 /* 32 bit Test Register 3 */
617 /* 0x48 - 0x7f: reserved */
618
619 /*
620 * Bank 16 - 23
621 */
622 /* RAM Buffer Registers */
623 #define B16_RAM_REGS 0x0800
624
625 /* RAM Buffer Register Offsets */
626 /* use RB_ADDR(Queue,Offs) to address */
627 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
628 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
629 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
630 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
631 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack*/
632 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack*/
633 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
634 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
635 /* 0x10 - 0x1f: reserved for Tx RAM Buffer Registers */
636 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
637 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
638 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
639 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
640 #define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
641 /* 0x2c - 0x7f: reserved */
642
643 /*
644 * Bank 24 - 25
645 */
646 /* Receive MAC FIFO, Receive LED, and Link Sync regs, use MR_ADDR() to address*/
647 #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
648 #define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer*/
649 /* 0x0c08 - 0x0c0b reserved */
650 #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
651 #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
652 #define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */
653 #define RX_MFF_CTRL1 0x0c18 /* 16 bit Receive MAC FIFO Control Reg 1*/
654 #define RX_MFF_STAT_TO 0x0c1a /* 8 bit Receive MAC Status Timeout */
655 #define RX_MFF_TIST_TO 0x0c1b /* 8 bit Receive MAC Timestamp Timeout */
656 #define RX_MFF_CTRL2 0x0c1c /* 8 bit Receive MAC FIFO Control Reg 2*/
657 #define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */
658 #define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */
659 /* 0x0c1f reserved */
660 #define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */
661 #define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */
662 #define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */
663 #define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */
664 /* 0x0c2a - 0x0c2f reserved */
665 #define LNK_SYNC_INI 0x0c30 /* 32 bit Link Sync Cnt Init Value */
666 #define LNK_SYNC_VAL 0x0c34 /* 32 bit Link Sync Cnt Current Value */
667 #define LNK_SYNC_CTRL 0x0c38 /* 8 bit Link Sync Cnt Control Register*/
668 #define LNK_SYNC_TST 0x0c39 /* 8 bit Link Sync Cnt Test Register */
669 /* 0x0c3a - 0x0c3b reserved */
670 #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
671 /* 0x0c3d - 0x0c7f reserved */
672
673 /*
674 * Bank 26 - 27
675 */
676 /* Transmit MAC FIFO and Transmit LED Registers, use MR_ADDR() to address */
677 #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
678 #define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
679 #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Pt*/
680 #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
681 #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
682 #define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */
683 #define TX_MFF_CTRL1 0x0d18 /* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
684 #define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush*/
685 /* 0x0c1b reserved */
686 #define TX_MFF_CTRL2 0x0d1c /* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
687 #define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */
688 #define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */
689 /* 0x0d1f reserved */
690 #define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */
691 #define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */
692 #define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */
693 #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Register*/
694 /* 0x0d2a - 0x0d7f reserved */
695
696 /*
697 * Bank 28
698 */
699 /* Descriptor Poll Timer Registers */
700 #define B28_DPT_INI 0x0e00 /* 32 bit Descriptor Poll Timer Init Val*/
701 #define B28_DPT_VAL 0x0e04 /* 32 bit Descriptor Poll Timer Curr Val*/
702 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg*/
703 /* 0x0e09: reserved */
704 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg*/
705 /* 0x0e0b - 0x0e8f: reserved */
706
707 /*
708 * Bank 29 - 31
709 */
710 /* 0x0e90 - 0x0fff: reserved */
711
712 /*
713 * Bank 0x20 - 0x3f
714 */
715 /* 0x1000 - 0x1fff: reserved */
716
717 /*
718 * Bank 0x40 - 0x4f
719 */
720 /* XMAC 1 registers */
721 #define B40_XMAC1 0x2000
722
723 /*
724 * Bank 0x50 - 0x5f
725 */
726 /* 0x2800 - 0x2fff: reserved */
727
728 /*
729 * Bank 0x60 - 0x6f
730 */
731 /* XMAC 2 registers */
732 #define B40_XMAC2 0x3000
733
734 /*
735 * Bank 0x70 - 0x7f
736 */
737 /* 0x3800 - 0x3fff: reserved */
738
739 /*
740 * Control Register Bit Definitions:
741 */
742 /* B0_RAP 8 bit Register Address Port */
743 /* Bit 7: reserved */
744 #define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0, .., 6f = block 6f*/
745
746 /* B0_CTST 16 bit Control/Status register */
747 /* Bit 15..10: reserved */
748 #define CS_BUS_CLOCK (1<<9) /* Bit 9: Bus Clock 0/1 = 33/66MHz */
749 #define CS_BUS_SLOT_SZ (1<<8) /* Bit 8: Slot Size 0/1 = 32/64 bit slot*/
750 #define CS_ST_SW_IRQ (1<<7) /* Bit 7: Set IRQ SW Request */
751 #define CS_CL_SW_IRQ (1<<6) /* Bit 6: Clear IRQ SW Request */
752 #define CS_STOP_DONE (1<<5) /* Bit 5: Stop Master is finished */
753 #define CS_STOP_MAST (1<<4) /* Bit 4: Command Bit to stop the master*/
754 #define CS_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */
755 #define CS_MRST_SET (1<<2) /* Bit 2: Set Master reset */
756 #define CS_RST_CLR (1<<1) /* Bit 1: Clear Software reset */
757 #define CS_RST_SET (1<<0) /* Bit 0: Set Software reset */
758
759 /* B0_LED 8 Bit LED register */
760 /* Bit 7..2: reserved */
761 #define LED_STAT_ON (1<<1) /* Bit 1: Status LED on */
762 #define LED_STAT_OFF (1<<0) /* Bit 0: Status LED off */
763
764 /* B0_ISRC 32 bit Interrupt Source Register */
765 /* B0_IMSK 32 bit Interrupt Mask Register */
766 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
767 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
768 #define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */
769 #define IS_HW_ERR (1UL<<31) /* Bit 31: Interrupt HW Error */
770 /* Bit 30: reserved */
771 #define IS_PA_TO_RX1 (1L<<29) /* Bit 29: Packet Arb Timeout Rx1*/
772 #define IS_PA_TO_RX2 (1L<<28) /* Bit 28: Packet Arb Timeout Rx2*/
773 #define IS_PA_TO_TX1 (1L<<27) /* Bit 27: Packet Arb Timeout Tx1*/
774 #define IS_PA_TO_TX2 (1L<<26) /* Bit 26: Packet Arb Timeout Tx2*/
775 #define IS_I2C_READY (1L<<25) /* Bit 25: IRQ on end of I2C tx */
776 #define IS_IRQ_SW (1L<<24) /* Bit 24: SW forced IRQ */
777 #define IS_EXT_REG (1L<<23) /* Bit 23: IRQ from external reg */
778 #define IS_TIMINT (1L<<22) /* Bit 22: IRQ from Timer */
779 #define IS_MAC1 (1L<<21) /* Bit 21: IRQ from MAC 1 */
780 #define IS_LNK_SYNC_M1 (1L<<20) /* Bit 20: Link Sync Cnt wrap M1 */
781 #define IS_MAC2 (1L<<19) /* Bit 19: IRQ from MAC 2 */
782 #define IS_LNK_SYNC_M2 (1L<<18) /* Bit 18: Link Sync Cnt wrap M2 */
783 /* Receive Queue 1 */
784 #define IS_R1_B (1L<<17) /* Bit 17: Q_R1 End of Buffer */
785 #define IS_R1_F (1L<<16) /* Bit 16: Q_R1 End of Frame */
786 #define IS_R1_C (1L<<15) /* Bit 15: Q_R1 Encoding Error */
787 /* Receive Queue 2 */
788 #define IS_R2_B (1L<<14) /* Bit 14: Q_R2 End of Buffer */
789 #define IS_R2_F (1L<<13) /* Bit 13: Q_R2 End of Frame */
790 #define IS_R2_C (1L<<12) /* Bit 12: Q_R2 Encoding Error */
791 /* Synchronous Transmit Queue 1 */
792 #define IS_XS1_B (1L<<11) /* Bit 11: Q_XS1 End of Buffer */
793 #define IS_XS1_F (1L<<10) /* Bit 10: Q_XS1 End of Frame */
794 #define IS_XS1_C (1L<<9) /* Bit 9: Q_XS1 Encoding Error */
795 /* Asynchronous Transmit Queue 1 */
796 #define IS_XA1_B (1L<<8) /* Bit 8: Q_XA1 End of Buffer */
797 #define IS_XA1_F (1L<<7) /* Bit 7: Q_XA1 End of Frame */
798 #define IS_XA1_C (1L<<6) /* Bit 6: Q_XA1 Encoding Error */
799 /* Synchronous Transmit Queue 2 */
800 #define IS_XS2_B (1L<<5) /* Bit 5: Q_XS2 End of Buffer */
801 #define IS_XS2_F (1L<<4) /* Bit 4: Q_XS2 End of Frame */
802 #define IS_XS2_C (1L<<3) /* Bit 3: Q_XS2 Encoding Error */
803 /* Asynchronous Transmit Queue 2 */
804 #define IS_XA2_B (1L<<2) /* Bit 2: Q_XA2 End of Buffer */
805 #define IS_XA2_F (1L<<1) /* Bit 1: Q_XA2 End of Frame */
806 #define IS_XA2_C (1L<<0) /* Bit 0: Q_XA2 Encoding Error */
807
808
809 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
810 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
811 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
812 #define IS_ERR_MSK 0x00000fffL /* All Error bits */
813 /* Bit 31..12: reserved */
814 #define IS_IRQ_MST_ERR (1L<<11) /* Bit 11: IRQ master error */
815 /* PERR,RMABORT,RTABORT,DATAPERR */
816 #define IS_IRQ_STAT (1L<<10) /* Bit 10: IRQ status execption */
817 /* RMABORT, RTABORT, DATAPERR */
818 #define IS_NO_STAT_M1 (1L<<9) /* Bit 9: No Rx Status from MAC1*/
819 #define IS_NO_STAT_M2 (1L<<8) /* Bit 8: No Rx Status from MAC2*/
820 #define IS_NO_TIST_M1 (1L<<7) /* Bit 7: No Timestamp from MAC1*/
821 #define IS_NO_TIST_M2 (1L<<6) /* Bit 6: No Timestamp from MAC2*/
822 #define IS_RAM_RD_PAR (1L<<5) /* Bit 5: RAM Read Parity Error */
823 #define IS_RAM_WR_PAR (1L<<4) /* Bit 4: RAM Write Parity Error*/
824 #define IS_M1_PAR_ERR (1L<<3) /* Bit 3: MAC 1 Parity Error */
825 #define IS_M2_PAR_ERR (1L<<2) /* Bit 2: MAC 2 Parity Error */
826 #define IS_R1_PAR_ERR (1L<<1) /* Bit 1: Queue R1 Parity Error */
827 #define IS_R2_PAR_ERR (1L<<0) /* Bit 0: Queue R2 Parity Error */
828
829 /* B2_CONN_TYP 8 bit Connector type */
830 /* B2_PMD_TYP 8 bit PMD type */
831 /* Values of connector and PMD type comply to SysKonnect internal std */
832
833 /* B2_MAC_CFG 8 bit MAC Configuration */
834 /* Bit 7..2: reserved */
835 #define CFG_DIS_M2_CLK (1<<1) /* Bit 1: Disable Clock for 2nd MAC */
836 #define CFG_SNG_MAC (1<<0) /* Bit 0: MAC Config: 1=2 MACs / 0=1 MAC*/
837
838 /* B2_CHIP_REV 8 bit Queen Chip Revision Number */
839 #define FIRST_CHIP_REV 0x0a /* Initial Revision Value */
840
841 /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
842 #define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
843
844 /* B2_LD_CRTL 8 bit EPROM loader control register */
845 /* Bits are currently reserved */
846
847 /* B2_LD_TEST 8 bit EPROM loader test register */
848 /* Bit 7..4: reserved */
849 #define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */
850 #define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */
851 #define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */
852 #define LD_START (1<<0) /* Bit 0: Start loading FPROM */
853
854 /*
855 * Timer Section
856 */
857 /* B2_TI_CRTL 8 bit Timer control */
858 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
859 /* Bit 7..3: reserved */
860 #define TIM_START (1<<2) /* Bit 2: Start Timer */
861 #define TIM_STOP (1<<1) /* Bit 1: Stop Timer */
862 #define TIM_CLR_IRQ (1<<0) /* Bit 0: Clear Timer IRQ, (!IRQM) */
863
864 /* B2_TI_TEST 8 Bit Timer Test */
865 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
866 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
867 /* Bit 7..3: reserved */
868 #define TIM_T_ON (1<<2) /* Bit 2: Test mode on */
869 #define TIM_T_OFF (1<<1) /* Bit 1: Test mode off */
870 #define TIM_T_STEP (1<<0) /* Bit 0: Test step */
871
872 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
873 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
874 /* Bit 31..24: reserved */
875 #define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */
876
877 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
878 /* Bit 7..2: reserved */
879 #define DPT_START (1<<1) /* Bit 1: Start Desciptor Poll Timer */
880 #define DPT_STOP (1<<0) /* Bit 0: Stop Desciptor Poll Timer */
881
882
883 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
884 #define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RD */
885 #define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR */
886 #define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RD */
887 #define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR */
888 #define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */
889 #define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */
890 #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: Enable Config Reg WR */
891 #define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: Disable Config Reg WR */
892
893 /* B2_TST_CTRL2 8 bit Test Control Register 2 */
894 /* Bit 7..4: reserved */
895 /* force the following error on */
896 /* the next master read/write */
897 #define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */
898 #define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */
899 #define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */
900 #define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */
901
902 /* B2_GP_IO 32 bit General Purpose IO Register */
903 /* Bit 31..26: reserved */
904 #define GP_DIR_9 (1L<<25) /* Bit 25: IO_9 direct, 0=I/1=O */
905 #define GP_DIR_8 (1L<<24) /* Bit 24: IO_8 direct, 0=I/1=O */
906 #define GP_DIR_7 (1L<<23) /* Bit 23: IO_7 direct, 0=I/1=O */
907 #define GP_DIR_6 (1L<<22) /* Bit 22: IO_6 direct, 0=I/1=O */
908 #define GP_DIR_5 (1L<<21) /* Bit 21: IO_5 direct, 0=I/1=O */
909 #define GP_DIR_4 (1L<<20) /* Bit 20: IO_4 direct, 0=I/1=O */
910 #define GP_DIR_3 (1L<<19) /* Bit 19: IO_3 direct, 0=I/1=O */
911 #define GP_DIR_2 (1L<<18) /* Bit 18: IO_2 direct, 0=I/1=O */
912 #define GP_DIR_1 (1L<<17) /* Bit 17: IO_1 direct, 0=I/1=O */
913 #define GP_DIR_0 (1L<<16) /* Bit 16: IO_0 direct, 0=I/1=O */
914 /* Bit 15..10: reserved */
915 #define GP_IO_9 (1L<<9) /* Bit 9: IO_9 pin */
916 #define GP_IO_8 (1L<<8) /* Bit 8: IO_8 pin */
917 #define GP_IO_7 (1L<<7) /* Bit 7: IO_7 pin */
918 #define GP_IO_6 (1L<<6) /* Bit 6: IO_6 pin */
919 #define GP_IO_5 (1L<<5) /* Bit 5: IO_5 pin */
920 #define GP_IO_4 (1L<<4) /* Bit 4: IO_4 pin */
921 #define GP_IO_3 (1L<<3) /* Bit 3: IO_3 pin */
922 #define GP_IO_2 (1L<<2) /* Bit 2: IO_2 pin */
923 #define GP_IO_1 (1L<<1) /* Bit 1: IO_1 pin */
924 #define GP_IO_0 (1L<<0) /* Bit 0: IO_0 pin */
925
926 /* B2_I2C_CTRL 32 bit I2C HW Control Register */
927 #define I2C_FLAG (1UL<<31) /* Bit 31: Start read/write if WR*/
928 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
929 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
930 /* Bit 8.. 5: reserved */
931 #define I2C_BURST_LEN (1L<<4) /* Bit 4: Burst Len, 1/4 bytes */
932 #define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */
933 #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */
934 #define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
935 #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
936 #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
937 #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
938 #define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
939 #define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
940 #define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
941 #define I2C_STOP (1L<<0) /* Bit 0: Interrupt I2C transfer*/
942
943 /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
944 /* Bit 31..1 reserved */
945 #define I2C_CLR_IRQ (1<<0) /* Bit 0: Clear I2C IRQ */
946
947 /* B2_I2C_SW 32 bit I2C HW SW Port Register */
948 /* Bit 7..3: reserved */
949 #define I2C_DATA_DIR (1<<2) /* Bit 2: direction of I2C_DATA */
950 #define I2C_DATA (1<<1) /* Bit 1: I2C Data Port */
951 #define I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
952
953 /*
954 * I2C Address
955 */
956 #define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
957
958
959 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
960 /* Bit 7..2: reserved */
961 #define BSC_START (1<<1) /* Bit 1: Start Blink Source Counter */
962 #define BSC_STOP (1<<0) /* Bit 0: Stop Blink Source Counter */
963
964 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
965 /* Bit 7..1: reserved */
966 #define BSC_SRC (1<<0) /* Bit 0: Blink Source, 0=Off / 1=On */
967
968 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
969 #define BSC_T_ON (1<<2) /* Bit 2: Test mode on */
970 #define BSC_T_OFF (1<<1) /* Bit 1: Test mode off */
971 #define BSC_T_STEP (1<<0) /* Bit 0: Test step */
972
973
974 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
975 /* Bit 31..19: reserved */
976 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
977
978 /* RAM Interface Registers */
979 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
980 /* Bit 15..10: reserved */
981 #define RI_CLR_RD_PERR (1<<9) /* Bit 9: Clear IRQ RAM Read Parity Err */
982 #define RI_CLR_WR_PERR (1<<8) /* Bit 8: Clear IRQ RAM Write Parity Err*/
983 /* Bit 7..2: reserved */
984 #define RI_RST_CLR (1<<1) /* Bit 1: Clear RAM Interface Reset */
985 #define RI_RST_SET (1<<0) /* Bit 0: Set RAM Interface Reset */
986
987 /* B3_RI_TEST 8 bit RAM Iface Test Register */
988 /* Bit 15..4: reserved */
989 #define RI_T_EV (1<<3) /* Bit 3: Timeout Event occured */
990 #define RI_T_ON (1<<2) /* Bit 2: Timeout Timer Test On */
991 #define RI_T_OFF (1<<1) /* Bit 1: Timeout Timer Test Off */
992 #define RI_T_STEP (1<<0) /* Bit 0: Timeout Timer Step */
993
994 /* MAC Arbiter Registers */
995 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
996 /* Bit 15..4: reserved */
997 #define MA_FOE_ON (1<<3) /* Bit 3: XMAC Fast Output Enable ON */
998 #define MA_FOE_OFF (1<<2) /* Bit 2: XMAC Fast Output Enable OFF */
999 #define MA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
1000 #define MA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
1001
1002 /* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
1003 /* Bit 15..8: reserved */
1004 #define MA_ENA_REC_TX2 (1<<7) /* Bit 7: Enable Recovery Timer TX2 */
1005 #define MA_DIS_REC_TX2 (1<<6) /* Bit 6: Disable Recovery Timer TX2 */
1006 #define MA_ENA_REC_TX1 (1<<5) /* Bit 5: Enable Recovery Timer TX1 */
1007 #define MA_DIS_REC_TX1 (1<<4) /* Bit 4: Disable Recovery Timer TX1 */
1008 #define MA_ENA_REC_RX2 (1<<3) /* Bit 3: Enable Recovery Timer RX2 */
1009 #define MA_DIS_REC_RX2 (1<<2) /* Bit 2: Disable Recovery Timer RX2 */
1010 #define MA_ENA_REC_RX1 (1<<1) /* Bit 1: Enable Recovery Timer RX1 */
1011 #define MA_DIS_REC_RX1 (1<<0) /* Bit 0: Disable Recovery Timer RX1 */
1012
1013 /* Packet Arbiter Registers */
1014 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
1015 /* Bit 15..14: reserved */
1016 #define PA_CLR_TO_TX2 (1<<13) /* Bit 13: Clear IRQ Packet Timeout TX2 */
1017 #define PA_CLR_TO_TX1 (1<<12) /* Bit 12: Clear IRQ Packet Timeout TX1 */
1018 #define PA_CLR_TO_RX2 (1<<11) /* Bit 11: Clear IRQ Packet Timeout RX2 */
1019 #define PA_CLR_TO_RX1 (1<<10) /* Bit 10: Clear IRQ Packet Timeout RX1 */
1020 #define PA_ENA_TO_TX2 (1<<9) /* Bit 9: Enable Timeout Timer TX2 */
1021 #define PA_DIS_TO_TX2 (1<<8) /* Bit 8: Disable Timeout Timer TX2 */
1022 #define PA_ENA_TO_TX1 (1<<7) /* Bit 7: Enable Timeout Timer TX1 */
1023 #define PA_DIS_TO_TX1 (1<<6) /* Bit 6: Disable Timeout Timer TX1 */
1024 #define PA_ENA_TO_RX2 (1<<5) /* Bit 5: Enable Timeout Timer RX2 */
1025 #define PA_DIS_TO_RX2 (1<<4) /* Bit 4: Disable Timeout Timer RX2 */
1026 #define PA_ENA_TO_RX1 (1<<3) /* Bit 3: Enable Timeout Timer RX1 */
1027 #define PA_DIS_TO_RX1 (1<<2) /* Bit 2: Disable Timeout Timer RX1 */
1028 #define PA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
1029 #define PA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
1030
1031 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
1032 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
1033
1034 /* Rx/Tx Path related Arbiter Test Registers */
1035 /* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
1036 /* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
1037 /* B3_PA_TEST 16 bit Packet Arbiter Test Register */
1038 /* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
1039 #define TX2_T_EV (1<<15) /* Bit 15: TX2 Timeout/Recv Event occured*/
1040 #define TX2_T_ON (1<<14) /* Bit 14: TX2 Timeout/Recv Timer Test On*/
1041 #define TX2_T_OFF (1<<13) /* Bit 13: TX2 Timeout/Recv Timer Tst Off*/
1042 #define TX2_T_STEP (1<<12) /* Bit 12: TX2 Timeout/Recv Timer Step */
1043 #define TX1_T_EV (1<<11) /* Bit 11: TX1 Timeout/Recv Event occured*/
1044 #define TX1_T_ON (1<<10) /* Bit 10: TX1 Timeout/Recv Timer Test On*/
1045 #define TX1_T_OFF (1<<9) /* Bit 9: TX1 Timeout/Recv Timer Tst Off*/
1046 #define TX1_T_STEP (1<<8) /* Bit 8: TX1 Timeout/Recv Timer Step */
1047 #define RX2_T_EV (1<<7) /* Bit 7: RX2 Timeout/Recv Event occured*/
1048 #define RX2_T_ON (1<<6) /* Bit 6: RX2 Timeout/Recv Timer Test On*/
1049 #define RX2_T_OFF (1<<5) /* Bit 5: RX2 Timeout/Recv Timer Tst Off*/
1050 #define RX2_T_STEP (1<<4) /* Bit 4: RX2 Timeout/Recv Timer Step */
1051 #define RX1_T_EV (1<<3) /* Bit 3: RX1 Timeout/Recv Event occured*/
1052 #define RX1_T_ON (1<<2) /* Bit 2: RX1 Timeout/Recv Timer Test On*/
1053 #define RX1_T_OFF (1<<1) /* Bit 1: RX1 Timeout/Recv Timer Tst Off*/
1054 #define RX1_T_STEP (1<<0) /* Bit 0: RX1 Timeout/Recv Timer Step */
1055
1056
1057 /* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
1058 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
1059 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
1060 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
1061 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
1062 /* Bit 31..24: reserved */
1063 #define TXA_MAX_VAL 0x00ffffffL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
1064
1065 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
1066 #define TXA_ENA_FSYNC (1<<7) /* Bit 7: Enable force of sync tx queue */
1067 #define TXA_DIS_FSYNC (1<<6) /* Bit 6: Disable force of sync tx queue*/
1068 #define TXA_ENA_ALLOC (1<<5) /* Bit 5: Enable alloc of free bandwidth*/
1069 #define TXA_DIS_ALLOC (1<<4) /* Bit 4: Disabl alloc of free bandwidth*/
1070 #define TXA_START_RC (1<<3) /* Bit 3: Start sync Rate Control */
1071 #define TXA_STOP_RC (1<<2) /* Bit 2: Stop sync Rate Control */
1072 #define TXA_ENA_ARB (1<<1) /* Bit 1: Enable Tx Arbiter */
1073 #define TXA_DIS_ARB (1<<0) /* Bit 0: Disable Tx Arbiter */
1074
1075 /* TXA_TEST 8 bit Tx Arbiter Test Register */
1076 /* Bit 7..6: reserved */
1077 #define TXA_INT_T_ON (1<<5) /* Bit 5: Tx Arb Interval Timer Test On */
1078 #define TXA_INT_T_OFF (1<<4) /* Bit 4: Tx Arb Interval Timer Test Off*/
1079 #define TXA_INT_T_STEP (1<<3) /* Bit 3: Tx Arb Interval Timer Step */
1080 #define TXA_LIM_T_ON (1<<2) /* Bit 2: Tx Arb Limit Timer Test On */
1081 #define TXA_LIM_T_OFF (1<<1) /* Bit 1: Tx Arb Limit Timer Test Off */
1082 #define TXA_LIM_T_STEP (1<<0) /* Bit 0: Tx Arb Limit Timer Step */
1083
1084 /* TXA_STAT 8 bit Tx Arbiter Status Register */
1085 /* Bit 7..1: reserved */
1086 #define TXA_PRIO_XS (1<<0) /* Bit 0: sync queue has prio to send */
1087
1088 /* Q_BC 32 bit Current Byte Counter */
1089 /* Bit 31..16: reserved */
1090 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
1091
1092 /* BMU Control Status Registers */
1093 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
1094 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
1095 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
1096 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
1097 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
1098 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
1099 /* Q_CSR 32 bit BMU Control/Status Register */
1100 /* Bit 31..25: reserved */
1101 #define CSR_SV_IDLE (1L<<24) /* Bit 24: BMU SM Idle */
1102 /* Bit 23..22: reserved */
1103 #define CSR_DESC_CLR (1L<<21) /* Bit 21: Clear Reset for Descr */
1104 #define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
1105 #define CSR_FIFO_CLR (1L<<19) /* Bit 19: Clear Reset for FIFO */
1106 #define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
1107 #define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
1108 #define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
1109 #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
1110 #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
1111 #define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
1112 #define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
1113 #define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
1114 #define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
1115 #define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
1116 #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
1117 #define CSR_ENA_POL (1L<<7) /* Bit 7: Enable Descr Polling */
1118 #define CSR_DIS_POL (1L<<6) /* Bit 6: Disable Descr Polling */
1119 #define CSR_STOP (1L<<5) /* Bit 5: Stop Rx/Tx Queue */
1120 #define CSR_START (1L<<4) /* Bit 4: Start Rx/Tx Queue */
1121 #define CSR_IRQ_CL_P (1L<<3) /* Bit 3: (Rx) Clear Parity IRQ */
1122 #define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
1123 #define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
1124 #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
1125
1126 #define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
1127 CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
1128 #define CSR_CLR_RESET (CSR_DESC_CLR|CSR_FIFO_CLR|CSR_HPI_RUN|CSR_SV_RUN|\
1129 CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
1130
1131
1132 /* Q_F 32 bit Flag Register */
1133 /* Bit 28..31: reserved */
1134 #define F_ALM_FULL (1L<<27) (Rx) /* Bit 27: (Rx) FIFO almost full */
1135 #define F_EMPTY (1L<<27) (Tx) /* Bit 27: (Tx) FIFO empty flag */
1136 #define F_FIFO_EOF (1L<<26) /* Bit 26: Fag bit in FIFO */
1137 #define F_WM_REACHED (1L<<25) /* Bit 25: Watermark reached */
1138 /* Bit 24: reserved */
1139 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
1140 /* Bit 15..11: reserved */
1141 #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
1142
1143 /* Q_T1 32 bit Test Register 1 */
1144 /* Holds four State Machine control Bytes */
1145 #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
1146 #define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */
1147 #define SM_CRTL_WR (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */
1148 #define SM_CRTL_TR (0xffL<<0) /* Bit 7.. 0: Control Transfer SM */
1149
1150 /* Q_T1_TR 8 bit Test Register 1 Transfer SM */
1151 /* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */
1152 /* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */
1153 /* Q_T1_SV 8 bit Test Register 1 Supervisor SM */
1154 /* The control status byte of each machine looks like ... */
1155 #define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */
1156 #define SM_LOAD (1<<3) /* Bit 3: Load the SM with SM_STATE */
1157 #define SM_TEST_ON (1<<2) /* Bit 2: Switch on SM Test Mode */
1158 #define SM_TEST_OFF (1<<1) /* Bit 1: Go off the Test Mode */
1159 #define SM_STEP (1<<0) /* Bit 0: Step the State Machine */
1160 /* The encoding of the states is not supported by the Diagnostics Tool */
1161
1162 /* Q_T2 32 bit Test Register 2 */
1163 /* Bit 31..8: reserved */
1164 #define T2_AC_T_ON (1<<7) /* Bit 7: Address Counter Test Mode on */
1165 #define T2_AC_T_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/
1166 #define T2_BC_T_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */
1167 #define T2_BC_T_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */
1168 #define T2_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */
1169 #define T2_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */
1170 #define T2_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */
1171 #define T2_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */
1172
1173 /* Q_T3 32 bit Test Register 3 */
1174 /* Bit 31..7: reserved */
1175 #define T3_MUX (7<<4) /* Bit 6.. 4: Mux Position */
1176 /* Bit 3: reserved */
1177 #define T3_VRAM (7<<0) /* Bit 2.. 0: Virtual RAM Buffer Address */
1178
1179 /* RAM Buffer Register Offsets */
1180 /* use RB_ADDR(Queue,Offs) to address */
1181 /* RB_START 32 bit RAM Buffer Start Address */
1182 /* RB_END 32 bit RAM Buffer End Address */
1183 /* RB_WP 32 bit RAM Buffer Write Pointer */
1184 /* RB_RP 32 bit RAM Buffer Read Pointer */
1185 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
1186 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pasue Pack */
1187 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
1188 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
1189 /* RB_PC 32 bit RAM Buffer Packet Counter */
1190 /* RB_LEV 32 bit RAM Buffer Level Register */
1191 /* Bit 31..19: reserved */
1192 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
1193
1194 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
1195 /* Bit 4..7: reserved */
1196 #define RB_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
1197 #define RB_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
1198 #define RB_PC_T_OFF (1<<1) /* Bit 1: Packet Counter Tst Off */
1199 #define RB_PC_INC (1<<0) /* Bit 0: Packet Counter Increm */
1200
1201 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
1202 /* Bit 7: reserved */
1203 #define RB_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
1204 #define RB_WP_T_OFF (1<<5) /* Bit 5: Write Pointer Test Off */
1205 #define RB_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
1206 /* Bit 3: reserved */
1207 #define RB_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
1208 #define RB_RP_T_OFF (1<<1) /* Bit 1: Read Pointer Test Off */
1209 #define RB_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
1210
1211 /* RB_CTRL 8 bit RAM Buffer Control Register */
1212 /* Bit 7..6: reserved */
1213 #define RB_ENA_STFWD (1<<5) /* Bit 5: Enable Store & Forward */
1214 #define RB_DIS_STFWD (1<<4) /* Bit 4: Disab. Store & Forward */
1215 #define RB_ENA_OP_MD (1<<3) /* Bit 3: Enable Operation Mode */
1216 #define RB_DIS_OP_MD (1<<2) /* Bit 2: Disab. Operation Mode */
1217 #define RB_RST_CLR (1<<1) /* Bit 1: Clr RAM Buf STM Reset */
1218 #define RB_RST_SET (1<<0) /* Bit 0: Set RAM Buf STM Reset */
1219
1220
1221 /* Receive and Transmit MAC FIFO Registers, use MR_ADDR() to address */
1222 /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
1223 /* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
1224 /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
1225 /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter*/
1226 /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
1227 /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
1228 /* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer*/
1229 /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pt*/
1230 /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
1231 /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
1232 /* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */
1233 /* Bit 31..6: reserved */
1234 #define MFF_MSK 0x007fL /* Bit 5..0: MAC FIFO Address/Pointer Bits */
1235
1236 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
1237 /* Bit 15..14: reserved */
1238 #define MFF_ENA_RDY_PAT (1<<13) /* Bit 13: Enable Ready Patch */
1239 #define MFF_DIS_RDY_PAT (1<<12) /* Bit 12: Disable Ready Patch */
1240 #define MFF_ENA_TIM_PAT (1<<11) /* Bit 11: Enable Timing Patch */
1241 #define MFF_DIS_TIM_PAT (1<<10) /* Bit 10: Disable Timing Patch */
1242 #define MFF_ENA_ALM_FUL (1<<9) /* Bit 9: Enable AlmostFull Sign*/
1243 #define MFF_DIS_ALM_FUL (1<<8) /* Bit 8: Disab. AlmostFull Sign*/
1244 #define MFF_ENA_PAUSE (1<<7) /* Bit 7: Enable Pause Signaling*/
1245 #define MFF_DIS_PAUSE (1<<6) /* Bit 6: Disab. Pause Signaling*/
1246 #define MFF_ENA_FLUSH (1<<5) /* Bit 5: Enable Frame Flushing */
1247 #define MFF_DIS_FLUSH (1<<4) /* Bit 4: Disab. Frame Flushing */
1248 #define MFF_ENA_TIST (1<<3) /* Bit 3: Enable Timestamp Gener*/
1249 #define MFF_DIS_TIST (1<<2) /* Bit 2: Disab. Timestamp Gener*/
1250 #define MFF_CLR_INTIST (1<<1) /* Bit 1: Clear IRQ No Timestamp*/
1251 #define MFF_CLR_INSTAT (1<<0) /* Bit 0: Clear IRQ No Status */
1252
1253 #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
1254
1255 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
1256 #define MFF_CLR_PERR (1<<15) /* Bit 15: Clear Parity Error IRQ*/
1257 /* Bit 14: reserved */
1258 #define MFF_ENA_PKT_REC (1<<13) /* Bit 13: Enable Packet Recovery*/
1259 #define MFF_DIS_PKT_REC (1<<12) /* Bit 12: Disable Packet Recov. */
1260 /* MFF_ENA_TIM_PAT (see RX_MFF_CTRL1)Bit 11: Enable Timing Patch */
1261 /* MFF_DIS_TIM_PAT (see RX_MFF_CTRL1)Bit 10: Disable Timing Patch */
1262 /* MFF_ENA_ALM_FUL (see RX_MFF_CTRL1)Bit 9: Enable AlmostFull Sign*/
1263 /* MFF_DIS_ALM_FUL (see RX_MFF_CTRL1)Bit 8: Disab. AlmostFull Sign*/
1264 #define MFF_ENA_W4E (1<<7) /* Bit 7: Enable Wait for Empty */
1265 #define MFF_DIS_W4E (1<<6) /* Bit 6: Disab. Wait for Empty */
1266 /* MFF_ENA_FLUSH (see RX_MFF_CTRL1)Bit 5: Enable Frame Flushing */
1267 /* MFF_DIS_FLUSH (see RX_MFF_CTRL1)Bit 4: Disab. Frame Flushing */
1268 #define MFF_ENA_LOOPB (1<<3) /* Bit 3: Enable Loopback */
1269 #define MFF_DIS_LOOPB (1<<2) /* Bit 2: Disable Loopback */
1270 #define MFF_CLR_MAC_RST (1<<1) /* Bit 1: Clear XMAC Reset */
1271 #define MFF_SET_MAC_RST (1<<0) /* Bit 0: Set XMAC Reset */
1272
1273 #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
1274
1275 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
1276 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
1277 /* Bit 7: reserved */
1278 #define MFF_WSP_T_ON (1<<6) /* Bit 6: (Tx) Write Shadow Pt TestOn */
1279 #define MFF_WSP_T_OFF (1<<5) /* Bit 5: (Tx) Write Shadow Pt TstOff */
1280 #define MFF_WSP_INC (1<<4) /* Bit 4: (Tx) Write Shadow Pt Increm */
1281 #define MFF_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
1282 #define MFF_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
1283 #define MFF_PC_T_OFF (1<<1) /* Bit 1: Packet Counter Tst Off */
1284 #define MFF_PC_INC (1<<0) /* Bit 0: Packet Counter Increm */
1285
1286 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
1287 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
1288 /* Bit 7: reserved */
1289 #define MFF_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
1290 #define MFF_WP_T_OFF (1<<5) /* Bit 5: Write Pointer Test Off */
1291 #define MFF_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
1292 /* Bit 3: reserved */
1293 #define MFF_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
1294 #define MFF_RP_T_OFF (1<<1) /* Bit 1: Read Pointer Test Off */
1295 #define MFF_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
1296
1297 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
1298 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
1299 /* Bit 7..4: reserved */
1300 #define MFF_ENA_OP_MD (1<<3) /* Bit 3: Enable Operation Mode */
1301 #define MFF_DIS_OP_MD (1<<2) /* Bit 2: Disab. Operation Mode */
1302 #define MFF_RST_CLR (1<<1) /* Bit 1: Clear MAC FIFO Reset */
1303 #define MFF_RST_SET (1<<0) /* Bit 0: Set MAC FIFO Reset */
1304
1305
1306 /* Receive, Transmit, and Link LED Counter Registers */
1307 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
1308 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
1309 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
1310 /* Bit 7..3: reserved */
1311 #define LED_START (1<<2) /* Bit 2: Start Timer */
1312 #define LED_STOP (1<<1) /* Bit 1: Stop Timer */
1313 #define LED_STATE (1<<0) /* Bit 0:(Rx/Tx)LED State, 1=LED on */
1314 #define LED_CLR_IRQ (1<<0) /* Bit 0:(Lnk) Clear Link IRQ */
1315
1316 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
1317 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
1318 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
1319 /* Bit 7..3: reserved */
1320 #define LED_T_ON (1<<2) /* Bit 2: LED Counter Testmode On */
1321 #define LED_T_OFF (1<<1) /* Bit 1: LED Counter Testmode Off */
1322 #define LED_T_STEP (1<<0) /* Bit 0: LED Counter Step */
1323
1324 /* LNK_LED_REG 8 bit Link LED Register */
1325 /* Bit 7..6: reserved */
1326 #define LED_BLK_ON (1<<5) /* Bit 5: Link LED Blinking On */
1327 #define LED_BLK_OFF (1<<4) /* Bit 4: Link LED Blinking Off */
1328 #define LED_SYNC_ON (1<<3) /* Bit 3: Use Sync Wire to switch LED */
1329 #define LED_SYNC_OFF (1<<2) /* Bit 2: Disable Sync Wire Input */
1330 #define LED_ON (1<<1) /* Bit 1: switch LED on */
1331 #define LED_OFF (1<<0) /* Bit 0: switch LED off */
1332
1333
1334 /* Receive and Transmit Descriptors ******************************************/
1335
1336 /* Transmit Descriptor struct */
1337 typedef struct s_HwTxd {
1338 SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
1339 SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
1340 SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
1341 SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
1342 SK_U32 TxStat; /* Transmit Frame Status Word */
1343 #ifndef SK_USE_REV_DESC
1344 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
1345 SK_U16 TxRes1; /* 16 bit reserved field */
1346 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
1347 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
1348 #else /* SK_USE_REV_DESC */
1349 SK_U16 TxRes1; /* 16 bit reserved field */
1350 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
1351 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
1352 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
1353 #endif /* SK_USE_REV_DESC */
1354 SK_U32 TxRes2; /* 32 bit reserved field */
1355 } SK_HWTXD;
1356
1357 /* Receive Descriptor struct */
1358 typedef struct s_HwRxd {
1359 SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
1360 SK_U32 RxNext; /* Physical Address Pointer to the next TxD */
1361 SK_U32 RxAdrLo; /* Physical Receive Buffer Address lower dword*/
1362 SK_U32 RxAdrHi; /* Physical Receive Buffer Address upper dword*/
1363 SK_U32 RxStat; /* Receive Frame Status Word */
1364 SK_U32 RxTiSt; /* Receive Timestamp provided by the XMAC */
1365 #ifndef SK_USE_REV_DESC
1366 SK_U16 RxTcpSum1; /* TCP Checksum 1 */
1367 SK_U16 RxTcpSum2; /* TCP Checksum 2 */
1368 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
1369 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
1370 #else /* SK_USE_REV_DESC */
1371 SK_U16 RxTcpSum2; /* TCP Checksum 2 */
1372 SK_U16 RxTcpSum1; /* TCP Checksum 1 */
1373 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
1374 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
1375 #endif /* SK_USE_REV_DESC */
1376 } SK_HWRXD;
1377
1378 /*
1379 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
1380 * should set the define SK_USE_REV_DESC.
1381 * Structures are 'normaly' not endianess dependent. But in
1382 * this case the SK_U16 fields are bound to bit positions inside the
1383 * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
1384 * The bit positions inside a DWord are of course endianess dependent and
1385 * swaps if the DWord is swaped by the hardware.
1386 */
1387
1388
1389 /* Descriptor Bit Definition */
1390 /* TxCtrl Transmit Buffer Control Field */
1391 /* RxCtrl Receive Buffer Control Field */
1392 #define BMU_OWN (1UL<<31) /* Bit 31: OWN bit: 0=host/1=BMU */
1393 #define BMU_STF (1L<<30) /* Bit 30: Start of Frame ? */
1394 #define BMU_EOF (1L<<29) /* Bit 29: End of Frame ? */
1395 #define BMU_IRQ_EOB (1L<<28) /* Bit 28: Req "End of Buff" IRQ */
1396 #define BMU_IRQ_EOF (1L<<27) /* Bit 27: Req "End of Frame" IRQ*/
1397 /* TxCtrl specific bits */
1398 #define BMU_STFWD (1L<<26) /* Bit 26: (Tx) Store&Forward Frame */
1399 #define BMU_NO_FCS (1L<<25) /* Bit 25: (Tx) disable XMAC FCS gener*/
1400 #define BMU_SW (1L<<24) /* Bit 24: (Tx) 1 bit res. for SW use */
1401 /* RxCtrl specific bits */
1402 #define BMU_DEV_0 (1L<<26) /* Bit 26: (Rx) transfer data to Dev0 */
1403 #define BMU_STAT_VAL (1L<<25) /* Bit 25: (Rx) RxStat Valid */
1404 #define BMU_TIST_VAL (1L<<24) /* Bit 24: (Rx) RxTiSt Valid */
1405 /* Bit 23..16: BMU Check Opcodes */
1406 #define BMU_CHECK 0x00550000L /* Default BMU check */
1407 #define BMU_TCP_CHECK 0x00560000L /* Descr with TCP ext */
1408 #define BMU_BBC 0x0000FFFFL /* Bit 15..0: Buffer Byte Counter */
1409
1410 /* TxStat Transmit Frame Status Word */
1411 /* RxStat Receive Frame Status Word */
1412 /*
1413 *Note: TxStat is reserved for ASIC loopback mode only
1414 *
1415 * The Bits of the Status words are defined in xmac_ii.h
1416 * (see XMR_FS bits)
1417 */
1418
1419 /* other defines *************************************************************/
1420
1421 /*
1422 * FlashProm specification
1423 */
1424 #define MAX_PAGES 0x20000L /* Every byte has a single page */
1425 #define MAX_FADDR 1 /* 1 byte per page */
1426 #define SKFDDI_PSZ 8 /* address PROM size */
1427
1428 /* macros ********************************************************************/
1429
1430 /*
1431 * Receive and Transmit Queues
1432 */
1433 #define Q_R1 0x0000 /* Receive Queue 1 */
1434 #define Q_R2 0x0080 /* Receive Queue 2 */
1435 #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */
1436 #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */
1437 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
1438 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
1439
1440 /*
1441 * Macro Q_ADDR()
1442 *
1443 * Use this macro to address the Receive and Transmit Queue Registers.
1444 *
1445 * para Queue Queue to address.
1446 * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
1447 * Offs Queue register offset.
1448 * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
1449 *
1450 * usage SK_IN32(pAC,Q_ADDR(Q_R2,Q_BC),pVal)
1451 */
1452 #define Q_ADDR(Queue,Offs) (B8_Q_REGS + (Queue) + (Offs))
1453
1454 /*
1455 * Macro RB_ADDR()
1456 *
1457 * Use this macro to address the RAM Buffer Registers.
1458 *
1459 * para Queue Queue to address.
1460 * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
1461 * Offs Queue register offset.
1462 * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
1463 *
1464 * usage SK_IN32(pAC,RB_ADDR(Q_R2,RB_RP),pVal)
1465 */
1466 #define RB_ADDR(Queue,Offs) (B16_RAM_REGS + (Queue) + (Offs))
1467
1468
1469 /*
1470 * MAC Related Registers
1471 */
1472 #define MAC_1 0 /* belongs to the port near the slot */
1473 #define MAC_2 1 /* belongs to the port far away from the slot */
1474
1475 /*
1476 * Macro MR_ADDR()
1477 *
1478 * Use this macro to address a MAC Related Registers in side the ASIC.
1479 *
1480 * para Queue Queue to address.
1481 * Values: TXA_ITI_INI ... TXA_TEST,
1482 * RX_MFF_EA ... RX_LED_TST,
1483 * LNK_SYNC_INI ... LNK_LED_REG, and
1484 * TX_MFF_EA ... TX_LED_TST
1485 * Mac MAC to address.
1486 * Values: MAC_1, MAC_2
1487 *
1488 * usage SK_IN32(pAC,MR_ADDR(MAC_1,TX_MFF_EA),pVal)
1489 */
1490 #define MR_ADDR(Mac,Offs) (((Mac) << 7) + (Offs))
1491
1492
1493
1494 /*
1495 * macros to access the XMAC
1496 *
1497 * XM_IN16(), to read a 16 bit register (e.g. XM_MMU_CMD)
1498 * XM_OUT16(), to write a 16 bit register (e.g. XM_MMU_CMD)
1499 * XM_IN32(), to read a 32 bit register (e.g. XM_TX_EV_CNT)
1500 * XM_OUT32(), to write a 32 bit register (e.g. XM_TX_EV_CNT)
1501 * XM_INADDR(), to read a network address register (e.g. XM_SRC_CHK)
1502 * XM_OUTADDR(), to write a network address register (e.g. XM_SRC_CHK)
1503 * XM_INHASH(), to read the XM_HSM_CHK register
1504 * XM_OUTHASH() to write the XM_HSM_CHK register
1505 *
1506 * para: Mac XMAC to address values: MAC_1 or MAC_2
1507 * IoC I/O context needed for SK IO macros
1508 * Reg XMAC Register to read or write
1509 * (p)Val Value or pointer to the value which should be read or
1510 * written.
1511 *
1512 * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value);
1513 */
1514
1515 #ifdef SK_LITTLE_ENDIAN
1516 #define XM_WORD_LO 0
1517 #define XM_WORD_HI 1
1518 #else /* !SK_LITTLE_ENDIAN */
1519 #define XM_WORD_LO 1
1520 #define XM_WORD_HI 0
1521 #endif /* !SK_LITTLE_ENDIAN */
1522
1523 #define XMA(Mac,Reg) (((0x1000 << (Mac)) + 0x1000) | ((Reg) << 1))
1524
1525 #define XM_IN16(IoC,Mac,Reg,pVal) SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
1526 #define XM_OUT16(IoC,Mac,Reg,Val) SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
1527
1528 #define XM_IN32(IoC,Mac,Reg,pVal) { \
1529 SK_IN16((IoC), XMA((Mac), (Reg)), \
1530 (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \
1531 SK_IN16((IoC), XMA((Mac), (Reg+2)), \
1532 (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \
1533 }
1534
1535 #define XM_OUT32(IoC,Mac,Reg,Val) { \
1536 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0x0000ffffL)); \
1537 SK_OUT16((IoC), XMA((Mac), (Reg+2)),(SK_U16)(((Val)>>16) & 0x0000ffffL)); \
1538 }
1539
1540 /*
1541 * Remember: we are always writing to / reading from LITTLE ENDIAN memory
1542 */
1543
1544 #define XM_INADDR(IoC, Mac, Reg, pVal) { \
1545 SK_U16 Word; \
1546 SK_U8 *pByte; \
1547 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1548 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
1549 pByte[0] = (SK_U8)(Word & 0x00ff); \
1550 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
1551 SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
1552 pByte[2] = (SK_U8)(Word & 0x00ff); \
1553 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
1554 SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
1555 pByte[4] = (SK_U8)(Word & 0x00ff); \
1556 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
1557 }
1558
1559 #define XM_OUTADDR(IoC, Mac, Reg, pVal) { \
1560 SK_U8 *pByte; \
1561 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1562 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
1563 (((SK_U16)(pByte[0]) & 0x00ff) | \
1564 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
1565 SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
1566 (((SK_U16)(pByte[2]) & 0x00ff) | \
1567 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
1568 SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
1569 (((SK_U16)(pByte[4]) & 0x00ff) | \
1570 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
1571 }
1572
1573 #define XM_INHASH(IoC, Mac, Reg, pVal) { \
1574 SK_U16 Word; \
1575 SK_U8 *pByte; \
1576 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1577 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
1578 pByte[0] = (SK_U8)(Word & 0x00ff); \
1579 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
1580 SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
1581 pByte[2] = (SK_U8)(Word & 0x00ff); \
1582 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
1583 SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
1584 pByte[4] = (SK_U8)(Word & 0x00ff); \
1585 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
1586 SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
1587 pByte[6] = (SK_U8)(Word & 0x00ff); \
1588 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
1589 }
1590
1591 #define XM_OUTHASH(IoC, Mac, Reg, pVal) { \
1592 SK_U8 *pByte; \
1593 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
1594 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
1595 (((SK_U16)(pByte[0]) & 0x00ff)| \
1596 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
1597 SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
1598 (((SK_U16)(pByte[2]) & 0x00ff)| \
1599 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
1600 SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
1601 (((SK_U16)(pByte[4]) & 0x00ff)| \
1602 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
1603 SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
1604 (((SK_U16)(pByte[6]) & 0x00ff)| \
1605 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
1606 }
1607
1608 /*
1609 * Different PHY Types
1610 */
1611 #define SK_PHY_XMAC 0 /* integrated in Xmac II*/
1612 #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
1613 #define SK_PHY_LONE 2 /* Level One LXT1000 */
1614 #define SK_PHY_NAT 3 /* National DP83891 */
1615
1616 /*
1617 * PHY addresses (bits 8..12 of PHY address reg)
1618 */
1619 #define PHY_ADDR_XMAC (0<<8)
1620 #define PHY_ADDR_BCOM (1<<8)
1621 #define PHY_ADDR_LONE (3<<8)
1622 #define PHY_ADDR_NAT (0<<8)
1623
1624 /*
1625 * macros to access the PHY
1626 *
1627 * PHY_READ() read a 16 bit value from the PHY
1628 * PHY_WIRTE() write a 16 bit value to the PHY
1629 *
1630 * para: IoC I/O context needed for SK IO macros
1631 * pPort Pointer to port struct for PhyAddr
1632 * Mac XMAC to address values: MAC_1 or MAC_2
1633 * PhyReg PHY Register to read or write
1634 * (p)Val Value or pointer to the value which should be read or
1635 * written.
1636 *
1637 * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
1638 * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
1639 * comes back. This is checked in DEBUG mode.
1640 */
1641 #ifndef DEBUG
1642 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
1643 SK_U16 Mmu; \
1644 \
1645 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
1646 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
1647 if ((pPort)->PhyType != SK_PHY_XMAC) { \
1648 do { \
1649 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
1650 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
1651 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
1652 } \
1653 }
1654 #else
1655 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
1656 SK_U16 Mmu; \
1657 int __i = 0; \
1658 \
1659 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
1660 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
1661 if ((pPort)->PhyType != SK_PHY_XMAC) { \
1662 do { \
1663 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
1664 __i++; \
1665 if (__i > 100000) { \
1666 SK_DBG_PRINTF("*****************************\n"); \
1667 SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n"); \
1668 SK_DBG_PRINTF("*****************************\n"); \
1669 break; \
1670 } \
1671 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
1672 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
1673 } \
1674 }
1675 #endif
1676
1677 #define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \
1678 SK_U16 Mmu; \
1679 \
1680 if ((pPort)->PhyType != SK_PHY_XMAC) { \
1681 do { \
1682 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
1683 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
1684 } \
1685 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
1686 XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
1687 if ((pPort)->PhyType != SK_PHY_XMAC) { \
1688 do { \
1689 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
1690 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
1691 } \
1692 }
1693
1694 /*
1695 * Macro PCI_C()
1696 *
1697 * Use this macro to address PCI config register from the IO space.
1698 *
1699 * para Addr PCI configuration register to address.
1700 * Values: PCI_VENDOR_ID ... PCI_VPD_ADDR,
1701 *
1702 * usage SK_IN16(pAC,PCI_C(PCI_VENDOR_ID),pVal);
1703 */
1704 #define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
1705
1706 /*
1707 * Macro SK_ADDR(Base,Addr)
1708 *
1709 * Calculates the effective HW address
1710 *
1711 * para Base IO- or memory base address
1712 * Addr Address offset
1713 *
1714 * usage: May be used in SK_INxx and SK_OUTxx macros
1715 * #define SK_IN8(pAC,Addr,pVal) ...\
1716 * *pVal = (SK_U8) inp(SK_ADDR(pAC->Hw.Iop,Addr)))
1717 */
1718 #ifdef SK_MEM_MAPPED_IO
1719 #define SK_HW_ADDR(Base,Addr) ((Base)+(Addr))
1720 #else /* SK_MEM_MAPPED_IO */
1721 #define SK_HW_ADDR(Base,Addr) ((Base)+(((Addr)&0x7F)|((Addr)>>7 ? 0x80:0)))
1722 #endif /* SK_MEM_MAPPED_IO */
1723
1724 #define SZ_LONG (sizeof(SK_U32))
1725
1726 /*
1727 * Macro SK_HWAC_LINK_LED()
1728 *
1729 * Use this macro to set the link LED mode.
1730 * para pAC Pointer to adapter context struct
1731 * IoC I/O context needed for SK IO macros
1732 * Port Port number
1733 * Mode Mode to set for this LED
1734 */
1735 #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
1736 SK_OUT8(IoC, MR_ADDR(Port,LNK_LED_REG), Mode);
1737
1738
1739 /* typedefs *******************************************************************/
1740
1741
1742 /* function prototypes ********************************************************/
1743
1744 #ifdef __cplusplus
1745 }
1746 #endif /* __cplusplus */
1747
1748 #endif /* __INC_SKGEHW_H */
1749