File: /usr/src/linux/drivers/net/skfp/h/fplustm.h
1 /******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15 /*
16 * AMD Fplus in tag mode data structs
17 * defs for fplustm.c
18 */
19
20 #ifndef _FPLUS_
21 #define _FPLUS_
22
23 #ifndef HW_PTR
24 #ifdef MEM_MAPPED_IO
25 #define HW_PTR u_long
26 #else
27 #define HW_PTR u_short
28 #endif
29 #endif
30
31 /*
32 * fplus error statistic structure
33 */
34 struct err_st {
35 u_long err_valid ; /* memory status valid */
36 u_long err_abort ; /* memory status receive abort */
37 u_long err_e_indicator ; /* error indicator */
38 u_long err_crc ; /* error detected (CRC or length) */
39 u_long err_llc_frame ; /* LLC frame */
40 u_long err_mac_frame ; /* MAC frame */
41 u_long err_smt_frame ; /* SMT frame */
42 u_long err_imp_frame ; /* implementer frame */
43 u_long err_no_buf ; /* no buffer available */
44 u_long err_too_long ; /* longer than max. buffer */
45 u_long err_bec_stat ; /* beacon state entered */
46 u_long err_clm_stat ; /* claim state entered */
47 u_long err_sifg_det ; /* short interframe gap detect */
48 u_long err_phinv ; /* PHY invalid */
49 u_long err_tkiss ; /* token issued */
50 u_long err_tkerr ; /* token error */
51 } ;
52
53 /*
54 * Transmit Descriptor struct
55 */
56 struct s_smt_fp_txd {
57 u_int txd_tbctrl ; /* transmit buffer control */
58 u_int txd_txdscr ; /* transmit frame status word */
59 u_int txd_tbadr ; /* physical tx buffer address */
60 u_int txd_ntdadr ; /* physical pointer to the next TxD */
61 #ifdef ENA_64BIT_SUP
62 u_int txd_tbadr_hi ; /* physical tx buffer addr (high dword)*/
63 #endif
64 char far *txd_virt ; /* virtual pointer to the data frag */
65 /* virt pointer to the next TxD */
66 struct s_smt_fp_txd volatile far *txd_next ;
67 struct s_txd_os txd_os ; /* OS - specific struct */
68 } ;
69
70 /*
71 * Receive Descriptor struct
72 */
73 struct s_smt_fp_rxd {
74 u_int rxd_rbctrl ; /* receive buffer control */
75 u_int rxd_rfsw ; /* receive frame status word */
76 u_int rxd_rbadr ; /* physical rx buffer address */
77 u_int rxd_nrdadr ; /* physical pointer to the next RxD */
78 #ifdef ENA_64BIT_SUP
79 u_int rxd_rbadr_hi ; /* physical tx buffer addr (high dword)*/
80 #endif
81 char far *rxd_virt ; /* virtual pointer to the data frag */
82 /* virt pointer to the next RxD */
83 struct s_smt_fp_rxd volatile far *rxd_next ;
84 struct s_rxd_os rxd_os ; /* OS - specific struct */
85 } ;
86
87 /*
88 * Descriptor Union Definition
89 */
90 union s_fp_descr {
91 struct s_smt_fp_txd t ; /* pointer to the TxD */
92 struct s_smt_fp_rxd r ; /* pointer to the RxD */
93 } ;
94
95 /*
96 * TxD Ring Control struct
97 */
98 struct s_smt_tx_queue {
99 struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */
100 struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */
101 struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/
102 u_short tx_free ; /* count of free TxD's */
103 u_short tx_used ; /* count of used TxD's */
104 HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */
105 HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */
106 } ;
107
108 /*
109 * RxD Ring Control struct
110 */
111 struct s_smt_rx_queue {
112 struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */
113 struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */
114 struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */
115 u_short rx_free ; /* count of free RxD's */
116 u_short rx_used ; /* count of used RxD's */
117 HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */
118 HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */
119 } ;
120
121 #define VOID_FRAME_OFF 0x00
122 #define CLAIM_FRAME_OFF 0x08
123 #define BEACON_FRAME_OFF 0x10
124 #define DBEACON_FRAME_OFF 0x18
125 #define RX_FIFO_OFF 0x21 /* to get a prime number for */
126 /* the RX_FIFO_SPACE */
127
128 #define RBC_MEM_SIZE 0x8000
129 #define SEND_ASYNC_AS_SYNC 0x1
130 #define SYNC_TRAFFIC_ON 0x2
131
132 /* big FIFO memory */
133 #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
134 #define TX_FIFO_SPACE 0x4000
135
136 #define TX_SMALL_FIFO 0x0900
137 #define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2
138 #define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO
139
140 #define RX_SMALL_FIFO 0x0900
141 #define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO
142
143 struct s_smt_fifo_conf {
144 u_short rbc_ram_start ; /* FIFO start address */
145 u_short rbc_ram_end ; /* FIFO size */
146 u_short rx1_fifo_start ; /* rx queue start address */
147 u_short rx1_fifo_size ; /* rx queue size */
148 u_short rx2_fifo_start ; /* rx queue start address */
149 u_short rx2_fifo_size ; /* rx queue size */
150 u_short tx_s_start ; /* sync queue start address */
151 u_short tx_s_size ; /* sync queue size */
152 u_short tx_a0_start ; /* async queue A0 start address */
153 u_short tx_a0_size ; /* async queue A0 size */
154 u_short fifo_config_mode ; /* FIFO configuration mode */
155 } ;
156
157 #define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
158
159 struct s_smt_fp {
160 u_short mdr2init ; /* mode register 2 init value */
161 u_short mdr3init ; /* mode register 3 init value */
162 u_short frselreg_init ; /* frame selection register init val */
163 u_short rx_mode ; /* address mode broad/multi/promisc */
164 u_short nsa_mode ;
165 u_short rx_prom ;
166 u_short exgpa ;
167
168 struct err_st err_stats ; /* error statistics */
169
170 /*
171 * MAC buffers
172 */
173 struct fddi_mac_sf { /* special frame build buffer */
174 u_char mac_fc ;
175 struct fddi_addr mac_dest ;
176 struct fddi_addr mac_source ;
177 u_char mac_info[0x20] ;
178 } mac_sfb ;
179
180
181 /*
182 * queues
183 */
184 #define QUEUE_S 0
185 #define QUEUE_A0 1
186 #define QUEUE_R1 0
187 #define QUEUE_R2 1
188 #define USED_QUEUES 2
189
190 /*
191 * queue pointers; points to the queue dependent variables
192 */
193 struct s_smt_tx_queue *tx[USED_QUEUES] ;
194 struct s_smt_rx_queue *rx[USED_QUEUES] ;
195
196 /*
197 * queue dependent variables
198 */
199 struct s_smt_tx_queue tx_q[USED_QUEUES] ;
200 struct s_smt_rx_queue rx_q[USED_QUEUES] ;
201
202 /*
203 * FIFO configuration struct
204 */
205 struct s_smt_fifo_conf fifo ;
206
207 /* last formac status */
208 u_short s2u ;
209 u_short s2l ;
210
211 /* calculated FORMAC+ reg.addr. */
212 HW_PTR fm_st1u ;
213 HW_PTR fm_st1l ;
214 HW_PTR fm_st2u ;
215 HW_PTR fm_st2l ;
216 HW_PTR fm_st3u ;
217 HW_PTR fm_st3l ;
218
219
220 /*
221 * multicast table
222 */
223 #define FPMAX_MULTICAST 32
224 #define SMT_MAX_MULTI 4
225 struct {
226 struct s_fpmc {
227 struct fddi_addr a ; /* mc address */
228 u_char n ; /* usage counter */
229 u_char perm ; /* flag: permanent */
230 } table[FPMAX_MULTICAST] ;
231 } mc ;
232 struct fddi_addr group_addr ;
233 u_long func_addr ; /* functional address */
234 int smt_slots_used ; /* count of table entries for the SMT */
235 int os_slots_used ; /* count of table entries */
236 /* used by the os-specific module */
237 } ;
238
239 /*
240 * modes for mac_set_rx_mode()
241 */
242 #define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */
243 #define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */
244 #define RX_ENABLE_PROMISC 3 /* enable promiscous */
245 #define RX_DISABLE_PROMISC 4 /* disable promiscous */
246 #define RX_ENABLE_NSA 5 /* enable reception of NSA frames */
247 #define RX_DISABLE_NSA 6 /* disable reception of NSA frames */
248
249
250 /*
251 * support for byte reversal in AIX
252 * (descriptors and pointers must be byte reversed in memory
253 * CPU is big endian; M-Channel is little endian)
254 */
255 #ifdef AIX
256 #define MDR_REV
257 #define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
258 (((x)<< 8L)&0x00ff0000L) + \
259 (((x)>> 8L)&0x0000ff00L) + \
260 (((x)>>24L)&0x000000ffL))
261 #else
262 #ifndef AIX_REVERSE
263 #define AIX_REVERSE(x) (x)
264 #endif
265 #endif
266
267 #ifdef MDR_REV
268 #define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
269 (((x)<< 8L)&0x00ff0000L) + \
270 (((x)>> 8L)&0x0000ff00L) + \
271 (((x)>>24L)&0x000000ffL))
272 #else
273 #ifndef MDR_REVERSE
274 #define MDR_REVERSE(x) (x)
275 #endif
276 #endif
277
278 #endif
279