File: /usr/src/linux/drivers/net/sungem.h
1 /* $Id: sungem.h,v 1.7 2001/04/04 14:49:40 davem Exp $
2 * sungem.h: Definitions for Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
5 */
6
7 #ifndef _SUNGEM_H
8 #define _SUNGEM_H
9
10 /* Global Registers */
11 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
12 #define GREG_CFG 0x0004UL /* Configuration Register */
13 #define GREG_STAT 0x000CUL /* Status Register */
14 #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
15 #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
16 #define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */
17 #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
18 #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
19 #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
20 #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
21 #define GREG_SWRST 0x1010UL /* Software Reset Register */
22
23 /* Global SEB State Register */
24 #define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */
25 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
26
27 /* Global Configuration Register */
28 #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */
29 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
30 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
31
32 /* Global Interrupt Status Register.
33 *
34 * Reading this register automatically clears bits 0 through 6.
35 * This auto-clearing does not occur when the alias at GREG_STAT2
36 * is read instead. The rest of the interrupt bits only clear when
37 * the secondary interrupt status register corresponding to that
38 * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by
39 * reading PCS_ISTAT).
40 */
41 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
42 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
43 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
44 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
45 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
46 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
47 #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
48 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
49 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
50 #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
51 #define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */
52 #define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */
53 #define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */
54 #define GREG_STAT_TXNR_SHIFT 19
55
56 #define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \
57 GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \
58 GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR)
59
60 /* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT.
61 * Bits set in GREG_IMASK will prevent that interrupt type from being
62 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
63 * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6.
64 * Setting the bit will clear that interrupt, clear bits will have no effect
65 * on GREG_STAT.
66 */
67
68 /* Global PCI Error Status Register */
69 #define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */
70 #define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */
71 #define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */
72
73 /* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT.
74 * Bits set in GREG_PCIEMASK will prevent that interrupt type from being
75 * signalled to the cpu.
76 */
77
78 /* Global BIF Configuration Register */
79 #define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */
80 #define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/
81 #define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */
82
83 /* Global BIF Diagnostics Register */
84 #define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */
85 #define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */
86
87 /* Global Software Reset Register.
88 *
89 * This register is used to perform a global reset of the RX and TX portions
90 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
91 * The driver _MUST_ poll these bits until they clear. One may not attempt
92 * to program any other part of GEM until the bits clear.
93 */
94 #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */
95 #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */
96 #define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */
97
98 /* TX DMA Registers */
99 #define TXDMA_KICK 0x2000UL /* TX Kick Register */
100 #define TXDMA_CFG 0x2004UL /* TX Configuration Register */
101 #define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */
102 #define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */
103 #define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */
104 #define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */
105 #define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */
106 #define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */
107 #define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */
108 #define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */
109 #define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */
110 #define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */
111 #define TXDMA_TXDONE 0x2100UL /* TX Completion Register */
112 #define TXDMA_FADDR 0x2104UL /* TX FIFO Address */
113 #define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */
114 #define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */
115 #define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */
116 #define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */
117 #define TXDMA_FSZ 0x2118UL /* TX FIFO Size */
118
119 /* TX Kick Register.
120 *
121 * This 13-bit register is programmed by the driver to hold the descriptor
122 * entry index which follows the last valid transmit descriptor.
123 */
124
125 /* TX Completion Register.
126 *
127 * This 13-bit register is updated by GEM to hold to descriptor entry index
128 * which follows the last descriptor already processed by GEM. Note that
129 * this value is mirrored in GREG_STAT which eliminates the need to even
130 * access this register in the driver during interrupt processing.
131 */
132
133 /* TX Configuration Register.
134 *
135 * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature
136 * that was meant to be used with jumbo packets. It should be set to the
137 * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
138 */
139 #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
140 #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */
141 #define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */
142 #define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */
143 #define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */
144 #define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */
145 #define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */
146 #define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */
147 #define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */
148 #define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */
149 #define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */
150 #define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */
151 #define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */
152 #define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/
153
154 /* TX Descriptor Base Low/High.
155 *
156 * These two registers store the 53 most significant bits of the base address
157 * of the TX descriptor table. The 11 least significant bits are always
158 * zero. As a result, the TX descriptor table must be 2K aligned.
159 */
160
161 /* The rest of the TXDMA_* registers are for diagnostics and debug, I will document
162 * them later. -DaveM
163 */
164
165 /* Receive DMA Registers */
166 #define RXDMA_CFG 0x4000UL /* RX Configuration Register */
167 #define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */
168 #define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */
169 #define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */
170 #define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */
171 #define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */
172 #define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */
173 #define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */
174 #define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */
175 #define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */
176 #define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */
177 #define RXDMA_KICK 0x4100UL /* RX Kick Register */
178 #define RXDMA_DONE 0x4104UL /* RX Completion Register */
179 #define RXDMA_BLANK 0x4108UL /* RX Blanking Register */
180 #define RXDMA_FADDR 0x410CUL /* RX FIFO Address */
181 #define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */
182 #define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */
183 #define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */
184 #define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */
185 #define RXDMA_FSZ 0x4120UL /* RX FIFO Size */
186
187 /* RX Configuration Register. */
188 #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
189 #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */
190 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
191 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
192 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
193 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
194 #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
195 #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
196 #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
197 #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
198 #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
199 #define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */
200 #define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */
201 #define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */
202 #define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */
203 #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
204 #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
205 #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
206 #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
207 #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
208 #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
209
210 /* RX Descriptor Base Low/High.
211 *
212 * These two registers store the 53 most significant bits of the base address
213 * of the RX descriptor table. The 11 least significant bits are always
214 * zero. As a result, the RX descriptor table must be 2K aligned.
215 */
216
217 /* RX PAUSE Thresholds.
218 *
219 * These values determine when XOFF and XON PAUSE frames are emitted by
220 * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes.
221 */
222 #define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */
223 #define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */
224
225 /* RX Kick Register.
226 *
227 * This 13-bit register is written by the host CPU and holds the last
228 * valid RX descriptor number plus one. This is, if 'N' is written to
229 * this register, it means that all RX descriptors up to but excluding
230 * 'N' are valid.
231 *
232 * The hardware requires that RX descriptors are posted in increments
233 * of 4. This means 'N' must be a multiple of four. For the best
234 * performance, the first new descriptor being posted should be (PCI)
235 * cache line aligned.
236 */
237
238 /* RX Completion Register.
239 *
240 * This 13-bit register is updated by GEM to indicate which RX descriptors
241 * have already been used for receive frames. All descriptors up to but
242 * excluding the value in this register are ready to be processed. GEM
243 * updates this register value after the RX FIFO empties completely into
244 * the RX descriptor's buffer, but before the RX_DONE bit is set in the
245 * interrupt status register.
246 */
247
248 /* RX Blanking Register. */
249 #define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this
250 * many packets received since
251 * previous RX_DONE.
252 */
253 #define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this
254 * many clocks (measured in 2048
255 * PCI clocks) were counted since
256 * the previous RX_DONE.
257 */
258
259 /* RX FIFO Size.
260 *
261 * This 11-bit read-only register indicates how large, in units of 64-bytes,
262 * the RX FIFO is. The driver uses this to properly configure the RX PAUSE
263 * thresholds.
264 */
265
266 /* The rest of the RXDMA_* registers are for diagnostics and debug, I will document
267 * them later. -DaveM
268 */
269
270 /* MAC Registers */
271 #define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/
272 #define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/
273 #define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */
274 #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */
275 #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */
276 #define MAC_CSTAT 0x6018UL /* MAC Control Status Register */
277 #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */
278 #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */
279 #define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */
280 #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/
281 #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/
282 #define MAC_MCCFG 0x6038UL /* MAC Control Config Register */
283 #define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */
284 #define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */
285 #define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */
286 #define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */
287 #define MAC_STIME 0x604CUL /* SlotTime Register */
288 #define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */
289 #define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */
290 #define MAC_PASIZE 0x6058UL /* PA Size Register */
291 #define MAC_JAMSIZE 0x605CUL /* JamSize Register */
292 #define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */
293 #define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */
294 #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */
295 #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */
296 #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */
297 #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */
298 #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */
299 #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */
300 #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */
301 #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */
302 #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */
303 #define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */
304 #define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */
305 #define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */
306 #define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */
307 #define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */
308 #define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */
309 #define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */
310 #define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */
311 #define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */
312 #define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */
313 #define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */
314 #define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */
315 #define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */
316 #define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */
317 #define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */
318 #define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */
319 #define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */
320 #define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */
321 #define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */
322 #define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */
323 #define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */
324 #define MAC_NCOLL 0x6100UL /* Normal Collision Counter */
325 #define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */
326 #define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */
327 #define MAC_LCOLL 0x610CUL /* Late Collision Counter */
328 #define MAC_DTIMER 0x6110UL /* Defer Timer */
329 #define MAC_PATMPS 0x6114UL /* Peak Attempts Register */
330 #define MAC_RFCTR 0x6118UL /* Receive Frame Counter */
331 #define MAC_LERR 0x611CUL /* Length Error Counter */
332 #define MAC_AERR 0x6120UL /* Alignment Error Counter */
333 #define MAC_FCSERR 0x6124UL /* FCS Error Counter */
334 #define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */
335 #define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */
336 #define MAC_SMACHINE 0x6134UL /* State Machine Register */
337
338 /* TX MAC Software Reset Command. */
339 #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
340
341 /* RX MAC Software Reset Command. */
342 #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
343
344 /* Send Pause Command. */
345 #define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in
346 * Send_Pause and flow-control
347 * handshakes.
348 */
349 #define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC
350 * to send a Pause Flow Control
351 * frame onto the network.
352 */
353
354 /* TX MAC Status Register. */
355 #define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */
356 #define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */
357 #define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */
358 #define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */
359 #define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */
360 #define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */
361 #define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */
362 #define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */
363 #define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */
364
365 /* RX MAC Status Register. */
366 #define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */
367 #define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */
368 #define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */
369 #define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */
370 #define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */
371 #define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */
372 #define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */
373
374 /* MAC Control Status Register. */
375 #define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */
376 #define MAC_CSTAT_PS 0x00000002 /* Paused State */
377 #define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */
378 #define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */
379
380 /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
381 * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent
382 * that interrupt type from being signalled to front end of GEM. For
383 * the interrupt to actually get sent to the cpu, it is necessary to
384 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
385 */
386
387 /* TX MAC Configuration Register.
388 *
389 * NOTE: The TX MAC Enable bit must be cleared and polled until
390 * zero before any other bits in this register are changed.
391 *
392 * Also, enabling the Carrier Extension feature of GEM is
393 * a 3 step process 1) Set TX Carrier Extension 2) Set
394 * RX Carrier Extension 3) Set Slot Time to 0x200. This
395 * mode must be enabled when in half-duplex at 1Gbps, else
396 * it must be disabled.
397 */
398 #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
399 #define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */
400 #define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */
401 #define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */
402 #define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */
403 #define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */
404 #define MAC_TXCFG_NBO 0x00000040 /* No Backoff */
405 #define MAC_TXCFG_SD 0x00000080 /* Slow Down */
406 #define MAC_TXCFG_NFCS 0x00000100 /* No FCS */
407 #define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */
408
409 /* RX MAC Configuration Register.
410 *
411 * NOTE: The RX MAC Enable bit must be cleared and polled until
412 * zero before any other bits in this register are changed.
413 *
414 * Similar rules apply to the Hash Filter Enable bit when
415 * programming the hash table registers, and the Address Filter
416 * Enable bit when programming the address filter registers.
417 */
418 #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
419 #define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */
420 #define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */
421 #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */
422 #define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */
423 #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
424 #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */
425 #define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */
426 #define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */
427
428 /* MAC Control Config Register. */
429 #define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */
430 #define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */
431 #define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */
432
433 /* XIF Configuration Register.
434 *
435 * NOTE: When leaving or entering loopback mode, a global hardware
436 * init of GEM should be performed.
437 */
438 #define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */
439 #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
440 #define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */
441 #define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */
442 #define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */
443 #define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */
444 #define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */
445
446 /* InterPacketGap0 Register. This 8-bit value is used as an extension
447 * to the InterPacketGap1 Register. Specifically it contributes to the
448 * timing of the RX-to-TX IPG. This value is ignored and presumed to
449 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
450 * is cleared in the TX MAC Configuration Register.
451 *
452 * This value in this register in terms of media byte time.
453 *
454 * Recommended value: 0x00
455 */
456
457 /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
458 * portion of the Inter Packet Gap.
459 *
460 * This value in this register in terms of media byte time.
461 *
462 * Recommended value: 0x08
463 */
464
465 /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
466 * portion of the Inter Packet Gap.
467 *
468 * This value in this register in terms of media byte time.
469 *
470 * Recommended value: 0x04
471 */
472
473 /* Slot Time Register. This 10-bit value specifies the slot time
474 * parameter in units of media byte time. It determines the physical
475 * span of the network.
476 *
477 * Recommended value: 0x40
478 */
479
480 /* Minimum Frame Size Register. This 10-bit register specifies the
481 * smallest sized frame the TXMAC will send onto the medium, and the
482 * RXMAC will receive from the medium.
483 *
484 * Recommended value: 0x40
485 */
486
487 /* Maximum Frame and Burst Size Register.
488 *
489 * This register specifies two things. First it specifies the maximum
490 * sized frame the TXMAC will send and the RXMAC will recognize as
491 * valid. Second, it specifies the maximum run length of a burst of
492 * packets sent in half-duplex gigabit modes.
493 *
494 * Recommended value: 0x200005ee
495 */
496 #define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */
497 #define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */
498
499 /* PA Size Register. This 10-bit register specifies the number of preamble
500 * bytes which will be transmitted at the beginning of each frame. A
501 * value of two or greater should be programmed here.
502 *
503 * Recommended value: 0x07
504 */
505
506 /* Jam Size Register. This 4-bit register specifies the duration of
507 * the jam in units of media byte time.
508 *
509 * Recommended value: 0x04
510 */
511
512 /* Attempts Limit Register. This 8-bit register specifies the number
513 * of attempts that the TXMAC will make to transmit a frame, before it
514 * resets its Attempts Counter. After reaching the Attempts Limit the
515 * TXMAC may or may not drop the frame, as determined by the NGU
516 * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC
517 * Configuration Register.
518 *
519 * Recommended value: 0x10
520 */
521
522 /* MAX Control Type Register. This 16-bit register specifies the
523 * "type" field of a MAC Control frame. The TXMAC uses this field to
524 * encapsulate the MAC Control frame for transmission, and the RXMAC
525 * uses it for decoding valid MAC Control frames received from the
526 * network.
527 *
528 * Recommended value: 0x8808
529 */
530
531 /* MAC Address Registers. Each of these registers specify the
532 * ethernet MAC of the interface, 16-bits at a time. Register
533 * 0 specifies bits [47:32], register 1 bits [31:16], and register
534 * 2 bits [15:0].
535 *
536 * Registers 3 through and including 5 specify an alternate
537 * MAC address for the interface.
538 *
539 * Registers 6 through and including 8 specify the MAC Control
540 * Address, which must be the reserved multicast address for MAC
541 * Control frames.
542 *
543 * Example: To program primary station address a:b:c:d:e:f into
544 * the chip.
545 * MAC_Address_2 = (a << 8) | b
546 * MAC_Address_1 = (c << 8) | d
547 * MAC_Address_0 = (e << 8) | f
548 */
549
550 /* Address Filter Registers. Registers 0 through 2 specify bit
551 * fields [47:32] through [15:0], respectively, of the address
552 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
553 * nibble mask for Address Filter Registers 2 and 1. The Address
554 * Filter 0 Mask Register denotes the 16-bit mask for the Address
555 * Filter Register 0.
556 */
557
558 /* Hash Table Registers. Registers 0 through 15 specify bit fields
559 * [255:240] through [15:0], respectively, of the hash table.
560 */
561
562 /* Statistics Registers. All of these registers are 16-bits and
563 * track occurances of a specific event. GEM can be configured
564 * to interrupt the host cpu when any of these counters overflow.
565 * They should all be explicitly initialized to zero when the interface
566 * is brought up.
567 */
568
569 /* Random Number Seed Register. This 10-bit value is used as the
570 * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is
571 * recommended to program this register to the 10 LSB of the
572 * interfaces MAC address.
573 */
574
575 /* Pause Timer, read-only. This 16-bit timer is used to time the pause
576 * interval as indicated by a received pause flow control frame.
577 * A non-zero value in this timer indicates that the MAC is currently in
578 * the paused state.
579 */
580
581 /* MIF Registers */
582 #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
583 #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
584 #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
585 #define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */
586 #define MIF_CFG 0x6210UL /* MIF Configuration Register */
587 #define MIF_MASK 0x6214UL /* MIF Mask Register */
588 #define MIF_STATUS 0x6218UL /* MIF Status Register */
589 #define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */
590
591 /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
592 * MDC clock waveform on the MII Management Interface when the MIF is
593 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
594 * this register will create a rising edge on the MDC, while writing
595 * a '0' after a '1' will create a falling edge. For every bit that
596 * is transferred on the management interface, both edges have to be
597 * generated.
598 */
599
600 /* MIF Bit-Bang Data. This 1-bit register is used to generate the
601 * outgoing data (MDO) on the MII Management Interface when the MIF
602 * is programmed in the "Bit-Bang" mode. The daa will be steered to the
603 * appropriate MDIO based on the state of the PHY_Select bit in the MIF
604 * Configuration Register.
605 */
606
607 /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
608 * ('1') or disable ('0') the I-directional driver on the MII when the
609 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
610 * when data bits are transferred from the MIF to the transceiver, and it
611 * should be disabled when the interface is idle or when data bits are
612 * transferred from the transceiver to the MIF (data portion of a read
613 * instruction). Only one MDIO will be enabled at a given time, depending
614 * on the state of the PHY_Select bit in the MIF Configuration Register.
615 */
616
617 /* MIF Configuration Register. This 15-bit register controls the operation
618 * of the MIF.
619 */
620 #define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */
621 #define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */
622 #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
623 #define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */
624 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
625 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
626 #define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */
627
628 /* MIF Frame/Output Register. This 32-bit register allows the host to
629 * communicate with a transceiver in frame mode (as opposed to big-bang
630 * mode). Writes by the host specify an instrution. After being issued
631 * the host must poll this register for completion. Also, after
632 * completion this register holds the data returned by the transceiver
633 * if applicable.
634 */
635 #define MIF_FRAME_ST 0xc0000000 /* STart of frame */
636 #define MIF_FRAME_OP 0x30000000 /* OPcode */
637 #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */
638 #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
639 #define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */
640 #define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */
641 #define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */
642
643 /* MIF Status Register. This register reports status when the MIF is
644 * operating in the poll mode. The poll status field is auto-clearing
645 * on read.
646 */
647 #define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */
648 #define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */
649
650 /* MIF Mask Register. This 16-bit register is used when in poll mode
651 * to say which bits of the polled register will cause an interrupt
652 * when changed.
653 */
654
655 /* PCS/Serialink Registers */
656 #define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */
657 #define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */
658 #define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */
659 #define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */
660 #define PCS_CFG 0x9010UL /* PCS Configuration Register */
661 #define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */
662 #define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */
663 #define PCS_DMODE 0x9050UL /* Datapath Mode Register */
664 #define PCS_SCTRL 0x9054UL /* Serialink Control Register */
665 #define PCS_SOS 0x9058UL /* Shared Output Select Reg */
666 #define PCS_SSTATE 0x905CUL /* Serialink State Register */
667
668 /* PCD MII Control Register. */
669 #define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */
670 #define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */
671 #define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */
672 #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
673 #define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */
674 #define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */
675 #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
676 #define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */
677 #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
678 * input side of Serialink
679 */
680 #define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */
681
682 /* PCS MII Status Register. */
683 #define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */
684 #define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */
685 #define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */
686 #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
687 #define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */
688 #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
689 #define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */
690
691 /* PCS MII Advertisement Register. */
692 #define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */
693 #define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */
694 #define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */
695 #define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */
696 #define PCS_MIIADV_RF 0x00003000 /* Remote Fault */
697 #define PCS_MIIADV_ACK 0x00004000 /* Read-only */
698 #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
699
700 /* PCS MII Link Partner Ability Register. This register is equivalent
701 * to the Link Partnet Ability Register of the standard MII register set.
702 * It's layout corresponds to the PCS MII Advertisement Register.
703 */
704
705 /* PCS Configuration Register. */
706 #define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing
707 * PCS MII advertisement reg.
708 */
709 #define PCS_CFG_SDO 0x00000002 /* Signal detect override */
710 #define PCS_CFG_SDL 0x00000004 /* Signal detect active low */
711 #define PCS_CFG_JS 0x00000018 /* Jitter-study:
712 * 0 = normal operation
713 * 1 = high-frequency test pattern
714 * 2 = low-frequency test pattern
715 * 3 = reserved
716 */
717 #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
718
719 /* PCS Interrupt Status Register. This register is self-clearing
720 * when read.
721 */
722 #define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */
723
724 /* Datapath Mode Register. */
725 #define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */
726 #define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */
727 #define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */
728 #define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */
729
730 /* Serialink Control Register.
731 *
732 * NOTE: When in SERDES mode, the loopback bit has inverse logic.
733 */
734 #define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */
735 #define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */
736 #define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */
737 #define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */
738 #define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */
739 #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
740 #define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */
741 #define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */
742 #define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */
743 #define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */
744
745 /* Shared Output Select Register. For test and debug, allows multiplexing
746 * test outputs into the PROM address pins. Set to zero for normal
747 * operation.
748 */
749 #define PCS_SOS_PADDR 0x00000003 /* PROM Address */
750
751 /* PROM Image Space */
752 #define PROM_START 0x100000UL /* Expansion ROM run time access*/
753 #define PROM_SIZE 0x0fffffUL /* Size of ROM */
754 #define PROM_END 0x200000UL /* End of ROM */
755
756 /* MII phy registers */
757 #define PHY_CTRL 0x00
758 #define PHY_STAT 0x01
759 #define PHY_ADV 0x04
760 #define PHY_LPA 0x05
761
762 #define PHY_CTRL_FDPLX 0x0100 /* Full duplex */
763 #define PHY_CTRL_ISO 0x0400 /* Isloate MII from PHY */
764 #define PHY_CTRL_ANRES 0x0200 /* Auto-negotiation restart */
765 #define PHY_CTRL_ANENAB 0x1000 /* Auto-negotiation enable */
766 #define PHY_CTRL_SPD100 0x2000 /* Select 100Mbps */
767 #define PHY_CTRL_RST 0x8000 /* Reset PHY */
768
769 #define PHY_STAT_LSTAT 0x0004 /* Link status */
770 #define PHY_STAT_ANEGC 0x0020 /* Auto-negotiation complete */
771
772 #define PHY_ADV_10HALF 0x0020
773 #define PHY_ADV_10FULL 0x0040
774 #define PHY_ADV_100HALF 0x0080
775 #define PHY_ADV_100FULL 0x0100
776
777 #define PHY_LPA_10HALF 0x0020
778 #define PHY_LPA_10FULL 0x0040
779 #define PHY_LPA_100HALF 0x0080
780 #define PHY_LPA_100FULL 0x0100
781 #define PHY_LPA_FAULT 0x2000
782
783 /* When it can, GEM internally caches 4 aligned TX descriptors
784 * at a time, so that it can use full cacheline DMA reads.
785 *
786 * Note that unlike HME, there is no ownership bit in the descriptor
787 * control word. The same functionality is obtained via the TX-Kick
788 * and TX-Complete registers. As a result, GEM need not write back
789 * updated values to the TX descriptor ring, it only performs reads.
790 *
791 * Since TX descriptors are never modified by GEM, the driver can
792 * use the buffer DMA address as a place to keep track of allocated
793 * DMA mappings for a transmitted packet.
794 */
795 struct gem_txd {
796 u64 control_word;
797 u64 buffer;
798 };
799
800 #define TXDCTRL_BUFSZ 0x0000000000007fff /* Buffer Size */
801 #define TXDCTRL_CSTART 0x00000000001f8000 /* CSUM Start Offset */
802 #define TXDCTRL_COFF 0x000000001fe00000 /* CSUM Stuff Offset */
803 #define TXDCTRL_CENAB 0x0000000020000000 /* CSUM Enable */
804 #define TXDCTRL_EOF 0x0000000040000000 /* End of Frame */
805 #define TXDCTRL_SOF 0x0000000080000000 /* Start of Frame */
806 #define TXDCTRL_INTME 0x0000000100000000 /* "Interrupt Me" */
807 #define TXDCTRL_NOCRC 0x0000000200000000 /* No CRC Present */
808
809 /* GEM requires that RX descriptors are provided four at a time,
810 * aligned. Also, the RX ring may not wrap around. This means that
811 * there will be at least 4 unused desciptor entries in the middle
812 * of the RX ring at all times.
813 *
814 * Similar to HME, GEM assumes that it can write garbage bytes before
815 * the beginning of the buffer and right after the end in order to DMA
816 * whole cachelines.
817 *
818 * Unlike for TX, GEM does update the status word in the RX descriptors
819 * when packets arrive. Therefore an ownership bit does exist in the
820 * RX descriptors. It is advisory, GEM clears it but does not check
821 * it in any way. So when buffers are posted to the RX ring (via the
822 * RX Kick register) by the driver it must make sure the buffers are
823 * truly ready and that the ownership bits are set properly.
824 *
825 * Even though GEM modifies the RX descriptors, it guarentees that the
826 * buffer DMA address field will stay the same when it performs these
827 * updates. Therefore it can be used to keep track of DMA mappings
828 * by the host driver just as in the TX descriptor case above.
829 */
830 struct gem_rxd {
831 u64 status_word;
832 u64 buffer;
833 };
834
835 #define RXDCTRL_TCPCSUM 0x000000000000ffff /* TCP Pseudo-CSUM */
836 #define RXDCTRL_BUFSZ 0x000000007fff0000 /* Buffer Size */
837 #define RXDCTRL_OWN 0x0000000080000000 /* GEM owns this entry */
838 #define RXDCTRL_HASHVAL 0x0ffff00000000000 /* Hash Value */
839 #define RXDCTRL_HPASS 0x1000000000000000 /* Passed Hash Filter */
840 #define RXDCTRL_ALTMAC 0x2000000000000000 /* Matched ALT MAC */
841 #define RXDCTRL_BAD 0x4000000000000000 /* Frame has bad CRC */
842
843 #define RXDCTRL_FRESH(gp) \
844 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
845 RXDCTRL_OWN)
846
847 #define TX_RING_SIZE 128
848 #define RX_RING_SIZE 128
849
850 #if TX_RING_SIZE == 32
851 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32
852 #elif TX_RING_SIZE == 64
853 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64
854 #elif TX_RING_SIZE == 128
855 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128
856 #elif TX_RING_SIZE == 256
857 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256
858 #elif TX_RING_SIZE == 512
859 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512
860 #elif TX_RING_SIZE == 1024
861 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K
862 #elif TX_RING_SIZE == 2048
863 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K
864 #elif TX_RING_SIZE == 4096
865 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K
866 #elif TX_RING_SIZE == 8192
867 #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K
868 #else
869 #error TX_RING_SIZE value is illegal...
870 #endif
871
872 #if RX_RING_SIZE == 32
873 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32
874 #elif RX_RING_SIZE == 64
875 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64
876 #elif RX_RING_SIZE == 128
877 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128
878 #elif RX_RING_SIZE == 256
879 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256
880 #elif RX_RING_SIZE == 512
881 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512
882 #elif RX_RING_SIZE == 1024
883 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K
884 #elif RX_RING_SIZE == 2048
885 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K
886 #elif RX_RING_SIZE == 4096
887 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K
888 #elif RX_RING_SIZE == 8192
889 #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K
890 #else
891 #error RX_RING_SIZE is illegal...
892 #endif
893
894 #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
895 #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
896
897 #define TX_BUFFS_AVAIL(GP) \
898 (((GP)->tx_old <= (GP)->tx_new) ? \
899 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
900 (GP)->tx_old - (GP)->tx_new - 1)
901
902 #define RX_OFFSET 2
903 #define RX_BUF_ALLOC_SIZE(gp) ((gp)->dev->mtu + 46 + RX_OFFSET + 64)
904
905 #define RX_COPY_THRESHOLD 256
906
907 struct gem_init_block {
908 struct gem_txd txd[TX_RING_SIZE];
909 struct gem_rxd rxd[RX_RING_SIZE];
910 };
911
912 enum gem_phy_type {
913 phy_mii_mdio0,
914 phy_mii_mdio1,
915 phy_serialink,
916 phy_serdes,
917 };
918
919 enum link_state {
920 aneg_wait,
921 force_wait,
922 };
923
924 struct gem {
925 spinlock_t lock;
926 unsigned long regs;
927 int rx_new, rx_old;
928 int tx_new, tx_old;
929
930 struct gem_init_block *init_block;
931
932 struct sk_buff *rx_skbs[RX_RING_SIZE];
933 struct sk_buff *tx_skbs[RX_RING_SIZE];
934
935 struct net_device_stats net_stats;
936
937 enum gem_phy_type phy_type;
938 int tx_fifo_sz;
939 int rx_fifo_sz;
940 int rx_pause_off;
941 int rx_pause_on;
942 int mii_phy_addr;
943
944 /* Diagnostic counters and state. */
945 u64 pause_entered;
946 u16 pause_last_time_recvd;
947
948 struct timer_list link_timer;
949 int timer_ticks;
950 enum link_state lstate;
951
952 dma_addr_t gblock_dvma;
953 struct pci_dev *pdev;
954 struct net_device *dev;
955 };
956
957 #define ALIGNED_RX_SKB_ADDR(addr) \
958 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
959 static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)
960 {
961 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
962
963 if (skb) {
964 int offset = (int) ALIGNED_RX_SKB_ADDR(skb->data);
965 if (offset)
966 skb_reserve(skb, offset);
967 }
968
969 return skb;
970 }
971
972 #endif /* _SUNGEM_H */
973