File: /usr/src/linux/drivers/net/sungem.c
1 /* $Id: sungem.c,v 1.20 2001/09/19 00:04:32 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/module.h>
8
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/types.h>
12 #include <linux/fcntl.h>
13 #include <linux/interrupt.h>
14 #include <linux/ptrace.h>
15 #include <linux/ioport.h>
16 #include <linux/in.h>
17 #include <linux/slab.h>
18 #include <linux/string.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26
27 #include <asm/system.h>
28 #include <asm/bitops.h>
29 #include <asm/io.h>
30 #include <asm/byteorder.h>
31
32 #ifdef __sparc__
33 #include <asm/idprom.h>
34 #include <asm/openprom.h>
35 #include <asm/oplib.h>
36 #include <asm/pbm.h>
37 #endif
38
39 #ifdef __powerpc__
40 #include <asm/pci-bridge.h>
41 #include <asm/prom.h>
42 #endif
43
44 #include "sungem.h"
45
46 static char version[] __devinitdata =
47 "sungem.c:v0.75 21/Mar/01 David S. Miller (davem@redhat.com)\n";
48
49 MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
50 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
51 MODULE_PARM(gem_debug, "i");
52 MODULE_PARM_DESC(gem_debug, "(ignored)");
53
54 #define GEM_MODULE_NAME "gem"
55 #define PFX GEM_MODULE_NAME ": "
56
57 #ifdef GEM_DEBUG
58 int gem_debug = GEM_DEBUG;
59 #else
60 int gem_debug = 1;
61 #endif
62
63 static struct pci_device_id gem_pci_tbl[] __devinitdata = {
64 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
65 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
66
67 /* These models only differ from the original GEM in
68 * that their tx/rx fifos are of a different size and
69 * they only support 10/100 speeds. -DaveM
70 */
71 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
73 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
75 {0, }
76 };
77
78 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
79
80 static u16 phy_read(struct gem *gp, int reg)
81 {
82 u32 cmd;
83 int limit = 10000;
84
85 cmd = (1 << 30);
86 cmd |= (2 << 28);
87 cmd |= (gp->mii_phy_addr << 23) & MIF_FRAME_PHYAD;
88 cmd |= (reg << 18) & MIF_FRAME_REGAD;
89 cmd |= (MIF_FRAME_TAMSB);
90 writel(cmd, gp->regs + MIF_FRAME);
91
92 while (limit--) {
93 cmd = readl(gp->regs + MIF_FRAME);
94 if (cmd & MIF_FRAME_TALSB)
95 break;
96
97 udelay(10);
98 }
99
100 if (!limit)
101 cmd = 0xffff;
102
103 return cmd & MIF_FRAME_DATA;
104 }
105
106 static void phy_write(struct gem *gp, int reg, u16 val)
107 {
108 u32 cmd;
109 int limit = 10000;
110
111 cmd = (1 << 30);
112 cmd |= (1 << 28);
113 cmd |= (gp->mii_phy_addr << 23) & MIF_FRAME_PHYAD;
114 cmd |= (reg << 18) & MIF_FRAME_REGAD;
115 cmd |= (MIF_FRAME_TAMSB);
116 cmd |= (val & MIF_FRAME_DATA);
117 writel(cmd, gp->regs + MIF_FRAME);
118
119 while (limit--) {
120 cmd = readl(gp->regs + MIF_FRAME);
121 if (cmd & MIF_FRAME_TALSB)
122 break;
123
124 udelay(10);
125 }
126 }
127
128 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
129 {
130 }
131
132 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
133 {
134 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
135 u32 pcs_miistat;
136
137 if (!(pcs_istat & PCS_ISTAT_LSC)) {
138 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
139 dev->name);
140 return 0;
141 }
142
143 /* The link status bit latches on zero, so you must
144 * read it twice in such a case to see a transition
145 * to the link being up.
146 */
147 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
148 if (!(pcs_miistat & PCS_MIISTAT_LS))
149 pcs_miistat |=
150 (readl(gp->regs + PCS_MIISTAT) &
151 PCS_MIISTAT_LS);
152
153 if (pcs_miistat & PCS_MIISTAT_ANC) {
154 /* The remote-fault indication is only valid
155 * when autoneg has completed.
156 */
157 if (pcs_miistat & PCS_MIISTAT_RF)
158 printk(KERN_INFO "%s: PCS AutoNEG complete, "
159 "RemoteFault\n", dev->name);
160 else
161 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
162 dev->name);
163 }
164
165 if (pcs_miistat & PCS_MIISTAT_LS) {
166 printk(KERN_INFO "%s: PCS link is now up.\n",
167 dev->name);
168 } else {
169 printk(KERN_INFO "%s: PCS link is now down.\n",
170 dev->name);
171
172 /* If this happens and the link timer is not running,
173 * reset so we re-negotiate.
174 */
175 if (!timer_pending(&gp->link_timer))
176 return 1;
177 }
178
179 return 0;
180 }
181
182 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
183 {
184 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
185
186 /* Defer timer expiration is quite normal,
187 * don't even log the event.
188 */
189 if ((txmac_stat & MAC_TXSTAT_DTE) &&
190 !(txmac_stat & ~MAC_TXSTAT_DTE))
191 return 0;
192
193 if (txmac_stat & MAC_TXSTAT_URUN) {
194 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
195 dev->name);
196 gp->net_stats.tx_fifo_errors++;
197 }
198
199 if (txmac_stat & MAC_TXSTAT_MPE) {
200 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
201 dev->name);
202 gp->net_stats.tx_errors++;
203 }
204
205 /* The rest are all cases of one of the 16-bit TX
206 * counters expiring.
207 */
208 if (txmac_stat & MAC_TXSTAT_NCE)
209 gp->net_stats.collisions += 0x10000;
210
211 if (txmac_stat & MAC_TXSTAT_ECE) {
212 gp->net_stats.tx_aborted_errors += 0x10000;
213 gp->net_stats.collisions += 0x10000;
214 }
215
216 if (txmac_stat & MAC_TXSTAT_LCE) {
217 gp->net_stats.tx_aborted_errors += 0x10000;
218 gp->net_stats.collisions += 0x10000;
219 }
220
221 /* We do not keep track of MAC_TXSTAT_FCE and
222 * MAC_TXSTAT_PCE events.
223 */
224 return 0;
225 }
226
227 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
228 {
229 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
230
231 if (rxmac_stat & MAC_RXSTAT_OFLW) {
232 printk(KERN_ERR "%s: RX MAC fifo overflow.\n",
233 dev->name);
234 gp->net_stats.rx_over_errors++;
235 gp->net_stats.rx_fifo_errors++;
236 }
237
238 if (rxmac_stat & MAC_RXSTAT_ACE)
239 gp->net_stats.rx_frame_errors += 0x10000;
240
241 if (rxmac_stat & MAC_RXSTAT_CCE)
242 gp->net_stats.rx_crc_errors += 0x10000;
243
244 if (rxmac_stat & MAC_RXSTAT_LCE)
245 gp->net_stats.rx_length_errors += 0x10000;
246
247 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
248 * events.
249 */
250 return 0;
251 }
252
253 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
254 {
255 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
256
257 /* This interrupt is just for pause frame and pause
258 * tracking. It is useful for diagnostics and debug
259 * but probably by default we will mask these events.
260 */
261 if (mac_cstat & MAC_CSTAT_PS)
262 gp->pause_entered++;
263
264 if (mac_cstat & MAC_CSTAT_PRCV)
265 gp->pause_last_time_recvd = (mac_cstat >> 16);
266
267 return 0;
268 }
269
270 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
271 {
272 u32 mif_status = readl(gp->regs + MIF_STATUS);
273 u32 reg_val, changed_bits;
274
275 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
276 changed_bits = (mif_status & MIF_STATUS_STAT);
277
278 gem_handle_mif_event(gp, reg_val, changed_bits);
279
280 return 0;
281 }
282
283 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
284 {
285 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
286
287 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
288 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
289 printk(KERN_ERR "%s: PCI error [%04x] ",
290 dev->name, pci_estat);
291
292 if (pci_estat & GREG_PCIESTAT_BADACK)
293 printk("<No ACK64# during ABS64 cycle> ");
294 if (pci_estat & GREG_PCIESTAT_DTRTO)
295 printk("<Delayed transaction timeout> ");
296 if (pci_estat & GREG_PCIESTAT_OTHER)
297 printk("<other>");
298 printk("\n");
299 } else {
300 pci_estat |= GREG_PCIESTAT_OTHER;
301 printk(KERN_ERR "%s: PCI error\n", dev->name);
302 }
303
304 if (pci_estat & GREG_PCIESTAT_OTHER) {
305 u16 pci_cfg_stat;
306
307 /* Interrogate PCI config space for the
308 * true cause.
309 */
310 pci_read_config_word(gp->pdev, PCI_STATUS,
311 &pci_cfg_stat);
312 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
313 dev->name, pci_cfg_stat);
314 if (pci_cfg_stat & PCI_STATUS_PARITY)
315 printk(KERN_ERR "%s: PCI parity error detected.\n",
316 dev->name);
317 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
318 printk(KERN_ERR "%s: PCI target abort.\n",
319 dev->name);
320 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
321 printk(KERN_ERR "%s: PCI master acks target abort.\n",
322 dev->name);
323 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
324 printk(KERN_ERR "%s: PCI master abort.\n",
325 dev->name);
326 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
327 printk(KERN_ERR "%s: PCI system error SERR#.\n",
328 dev->name);
329 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
330 printk(KERN_ERR "%s: PCI parity error.\n",
331 dev->name);
332
333 /* Write the error bits back to clear them. */
334 pci_cfg_stat &= (PCI_STATUS_PARITY |
335 PCI_STATUS_SIG_TARGET_ABORT |
336 PCI_STATUS_REC_TARGET_ABORT |
337 PCI_STATUS_REC_MASTER_ABORT |
338 PCI_STATUS_SIG_SYSTEM_ERROR |
339 PCI_STATUS_DETECTED_PARITY);
340 pci_write_config_word(gp->pdev,
341 PCI_STATUS, pci_cfg_stat);
342 }
343
344 /* For all PCI errors, we should reset the chip. */
345 return 1;
346 }
347
348 static void gem_stop(struct gem *, unsigned long);
349 static void gem_init_rings(struct gem *, int);
350 static void gem_init_hw(struct gem *);
351
352 /* All non-normal interrupt conditions get serviced here.
353 * Returns non-zero if we should just exit the interrupt
354 * handler right now (ie. if we reset the card which invalidates
355 * all of the other original irq status bits).
356 */
357 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
358 {
359 if (gem_status & GREG_STAT_RXNOBUF) {
360 /* Frame arrived, no free RX buffers available. */
361 gp->net_stats.rx_dropped++;
362 }
363
364 if (gem_status & GREG_STAT_RXTAGERR) {
365 /* corrupt RX tag framing */
366 gp->net_stats.rx_errors++;
367
368 goto do_reset;
369 }
370
371 if (gem_status & GREG_STAT_PCS) {
372 if (gem_pcs_interrupt(dev, gp, gem_status))
373 goto do_reset;
374 }
375
376 if (gem_status & GREG_STAT_TXMAC) {
377 if (gem_txmac_interrupt(dev, gp, gem_status))
378 goto do_reset;
379 }
380
381 if (gem_status & GREG_STAT_RXMAC) {
382 if (gem_rxmac_interrupt(dev, gp, gem_status))
383 goto do_reset;
384 }
385
386 if (gem_status & GREG_STAT_MAC) {
387 if (gem_mac_interrupt(dev, gp, gem_status))
388 goto do_reset;
389 }
390
391 if (gem_status & GREG_STAT_MIF) {
392 if (gem_mif_interrupt(dev, gp, gem_status))
393 goto do_reset;
394 }
395
396 if (gem_status & GREG_STAT_PCIERR) {
397 if (gem_pci_interrupt(dev, gp, gem_status))
398 goto do_reset;
399 }
400
401 return 0;
402
403 do_reset:
404 gem_stop(gp, gp->regs);
405 gem_init_rings(gp, 1);
406 gem_init_hw(gp);
407 return 1;
408 }
409
410 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
411 {
412 int entry, limit;
413
414 entry = gp->tx_old;
415 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
416 while (entry != limit) {
417 struct sk_buff *skb;
418 struct gem_txd *txd;
419 u32 dma_addr, dma_len;
420 int frag;
421
422 skb = gp->tx_skbs[entry];
423 if (skb_shinfo(skb)->nr_frags) {
424 int last = entry + skb_shinfo(skb)->nr_frags;
425 int walk = entry;
426 int incomplete = 0;
427
428 last &= (TX_RING_SIZE - 1);
429 for (;;) {
430 walk = NEXT_TX(walk);
431 if (walk == limit)
432 incomplete = 1;
433 if (walk == last)
434 break;
435 }
436 if (incomplete)
437 break;
438 }
439 gp->tx_skbs[entry] = NULL;
440 gp->net_stats.tx_bytes += skb->len;
441
442 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
443 txd = &gp->init_block->txd[entry];
444
445 dma_addr = (u32) le64_to_cpu(txd->buffer);
446 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
447
448 pci_unmap_single(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
449 entry = NEXT_TX(entry);
450 }
451
452 gp->net_stats.tx_packets++;
453 dev_kfree_skb_irq(skb);
454 }
455 gp->tx_old = entry;
456
457 if (netif_queue_stopped(dev) &&
458 TX_BUFFS_AVAIL(gp) > 0)
459 netif_wake_queue(dev);
460 }
461
462 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
463 {
464 int cluster_start, curr, count, kick;
465
466 cluster_start = curr = (gp->rx_new & ~(4 - 1));
467 count = 0;
468 kick = -1;
469 while (curr != limit) {
470 curr = NEXT_RX(curr);
471 if (++count == 4) {
472 struct gem_rxd *rxd =
473 &gp->init_block->rxd[cluster_start];
474 for (;;) {
475 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
476 rxd++;
477 cluster_start = NEXT_RX(cluster_start);
478 if (cluster_start == curr)
479 break;
480 }
481 kick = curr;
482 count = 0;
483 }
484 }
485 if (kick >= 0)
486 writel(kick, gp->regs + RXDMA_KICK);
487 }
488
489 static void gem_rx(struct gem *gp)
490 {
491 int entry, drops;
492
493 entry = gp->rx_new;
494 drops = 0;
495 for (;;) {
496 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
497 struct sk_buff *skb;
498 u64 status = cpu_to_le64(rxd->status_word);
499 u32 dma_addr;
500 int len;
501
502 if ((status & RXDCTRL_OWN) != 0)
503 break;
504
505 skb = gp->rx_skbs[entry];
506
507 len = (status & RXDCTRL_BUFSZ) >> 16;
508 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
509 gp->net_stats.rx_errors++;
510 if (len < ETH_ZLEN)
511 gp->net_stats.rx_length_errors++;
512 if (len & RXDCTRL_BAD)
513 gp->net_stats.rx_crc_errors++;
514
515 /* We'll just return it to GEM. */
516 drop_it:
517 gp->net_stats.rx_dropped++;
518 goto next;
519 }
520
521 dma_addr = (u32) cpu_to_le64(rxd->buffer);
522 if (len > RX_COPY_THRESHOLD) {
523 struct sk_buff *new_skb;
524
525 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
526 if (new_skb == NULL) {
527 drops++;
528 goto drop_it;
529 }
530 pci_unmap_single(gp->pdev, dma_addr,
531 RX_BUF_ALLOC_SIZE(gp), PCI_DMA_FROMDEVICE);
532 gp->rx_skbs[entry] = new_skb;
533 new_skb->dev = gp->dev;
534 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
535 rxd->buffer = cpu_to_le64(pci_map_single(gp->pdev,
536 new_skb->data,
537 RX_BUF_ALLOC_SIZE(gp),
538 PCI_DMA_FROMDEVICE));
539 skb_reserve(new_skb, RX_OFFSET);
540
541 /* Trim the original skb for the netif. */
542 skb_trim(skb, len);
543 } else {
544 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
545
546 if (copy_skb == NULL) {
547 drops++;
548 goto drop_it;
549 }
550
551 copy_skb->dev = gp->dev;
552 skb_reserve(copy_skb, 2);
553 skb_put(copy_skb, len);
554 pci_dma_sync_single(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
555 memcpy(copy_skb->data, skb->data, len);
556
557 /* We'll reuse the original ring buffer. */
558 skb = copy_skb;
559 }
560
561 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
562 skb->ip_summed = CHECKSUM_HW;
563 skb->protocol = eth_type_trans(skb, gp->dev);
564 netif_rx(skb);
565
566 gp->net_stats.rx_packets++;
567 gp->net_stats.rx_bytes += len;
568 gp->dev->last_rx = jiffies;
569
570 next:
571 entry = NEXT_RX(entry);
572 }
573
574 gem_post_rxds(gp, entry);
575
576 gp->rx_new = entry;
577
578 if (drops)
579 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
580 gp->dev->name);
581 }
582
583 static void gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
584 {
585 struct net_device *dev = dev_id;
586 struct gem *gp = dev->priv;
587 u32 gem_status = readl(gp->regs + GREG_STAT);
588
589 spin_lock(&gp->lock);
590
591 if (gem_status & GREG_STAT_ABNORMAL) {
592 if (gem_abnormal_irq(dev, gp, gem_status))
593 goto out;
594 }
595 if (gem_status & (GREG_STAT_TXALL | GREG_STAT_TXINTME))
596 gem_tx(dev, gp, gem_status);
597 if (gem_status & GREG_STAT_RXDONE)
598 gem_rx(gp);
599
600 out:
601 spin_unlock(&gp->lock);
602 }
603
604 static void gem_tx_timeout(struct net_device *dev)
605 {
606 struct gem *gp = dev->priv;
607
608 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
609 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
610 dev->name,
611 readl(gp->regs + TXDMA_CFG),
612 readl(gp->regs + MAC_TXSTAT),
613 readl(gp->regs + MAC_TXCFG));
614 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
615 dev->name,
616 readl(gp->regs + RXDMA_CFG),
617 readl(gp->regs + MAC_RXSTAT),
618 readl(gp->regs + MAC_RXCFG));
619
620 spin_lock_irq(&gp->lock);
621
622 gem_stop(gp, gp->regs);
623 gem_init_rings(gp, 1);
624 gem_init_hw(gp);
625
626 spin_unlock_irq(&gp->lock);
627
628 netif_wake_queue(dev);
629 }
630
631 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
632 {
633 struct gem *gp = dev->priv;
634 int entry;
635 u64 ctrl;
636
637 ctrl = 0;
638 if (skb->ip_summed == CHECKSUM_HW) {
639 u64 csum_start_off, csum_stuff_off;
640
641 csum_start_off = (u64) (skb->h.raw - skb->data);
642 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
643
644 ctrl = (TXDCTRL_CENAB |
645 (csum_start_off << 15) |
646 (csum_stuff_off << 21));
647 }
648
649 spin_lock_irq(&gp->lock);
650
651 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
652 netif_stop_queue(dev);
653 spin_unlock_irq(&gp->lock);
654 return 1;
655 }
656
657 entry = gp->tx_new;
658 gp->tx_skbs[entry] = skb;
659
660 if (skb_shinfo(skb)->nr_frags == 0) {
661 struct gem_txd *txd = &gp->init_block->txd[entry];
662 u32 mapping, len;
663
664 len = skb->len;
665 mapping = pci_map_single(gp->pdev, skb->data, len, PCI_DMA_TODEVICE);
666 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
667 txd->buffer = cpu_to_le64(mapping);
668 txd->control_word = cpu_to_le64(ctrl);
669 entry = NEXT_TX(entry);
670 } else {
671 struct gem_txd *txd;
672 u32 first_len, first_mapping;
673 int frag, first_entry = entry;
674
675 /* We must give this initial chunk to the device last.
676 * Otherwise we could race with the device.
677 */
678 first_len = skb->len - skb->data_len;
679 first_mapping = pci_map_single(gp->pdev, skb->data,
680 first_len, PCI_DMA_TODEVICE);
681 entry = NEXT_TX(entry);
682
683 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
684 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
685 u32 len, mapping;
686 u64 this_ctrl;
687
688 len = this_frag->size;
689 mapping = pci_map_single(gp->pdev,
690 ((void *) page_address(this_frag->page) +
691 this_frag->page_offset),
692 len, PCI_DMA_TODEVICE);
693 this_ctrl = ctrl;
694 if (frag == skb_shinfo(skb)->nr_frags - 1)
695 this_ctrl |= TXDCTRL_EOF;
696
697 txd = &gp->init_block->txd[entry];
698 txd->buffer = cpu_to_le64(mapping);
699 txd->control_word = cpu_to_le64(this_ctrl | len);
700
701 entry = NEXT_TX(entry);
702 }
703 txd = &gp->init_block->txd[first_entry];
704 txd->buffer = cpu_to_le64(first_mapping);
705 txd->control_word = cpu_to_le64(ctrl | TXDCTRL_SOF | first_len);
706 }
707
708 gp->tx_new = entry;
709 if (TX_BUFFS_AVAIL(gp) <= 0)
710 netif_stop_queue(dev);
711
712 writel(gp->tx_new, gp->regs + TXDMA_KICK);
713 spin_unlock_irq(&gp->lock);
714
715 dev->trans_start = jiffies;
716
717 return 0;
718 }
719
720 /* Jumbo-grams don't seem to work :-( */
721 #if 1
722 #define MAX_MTU 1500
723 #else
724 #define MAX_MTU 9000
725 #endif
726
727 static int gem_change_mtu(struct net_device *dev, int new_mtu)
728 {
729 struct gem *gp = dev->priv;
730
731 if (new_mtu < 0 || new_mtu > MAX_MTU)
732 return -EINVAL;
733
734 spin_lock_irq(&gp->lock);
735 gem_stop(gp, gp->regs);
736 dev->mtu = new_mtu;
737 gem_init_rings(gp, 1);
738 gem_init_hw(gp);
739 spin_unlock_irq(&gp->lock);
740
741 return 0;
742 }
743
744 #define STOP_TRIES 32
745
746 static void gem_stop(struct gem *gp, unsigned long regs)
747 {
748 int limit;
749 u32 val;
750
751 writel(GREG_SWRST_TXRST | GREG_SWRST_RXRST, regs + GREG_SWRST);
752
753 limit = STOP_TRIES;
754
755 do {
756 udelay(20);
757 val = readl(regs + GREG_SWRST);
758 if (limit-- <= 0)
759 break;
760 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
761
762 if (limit <= 0)
763 printk(KERN_ERR "gem: SW reset is ghetto.\n");
764 }
765
766 /* A link-up condition has occurred, initialize and enable the
767 * rest of the chip.
768 */
769 static void gem_set_link_modes(struct gem *gp)
770 {
771 u32 val;
772 int full_duplex, speed;
773
774 full_duplex = 0;
775 speed = 10;
776 if (gp->phy_type == phy_mii_mdio0 ||
777 gp->phy_type == phy_mii_mdio1) {
778 if (gp->lstate == aneg_wait) {
779 val = phy_read(gp, PHY_LPA);
780 if (val & (PHY_LPA_10FULL | PHY_LPA_100FULL))
781 full_duplex = 1;
782 if (val & (PHY_LPA_100FULL | PHY_LPA_100HALF))
783 speed = 100;
784 } else {
785 val = phy_read(gp, PHY_CTRL);
786 if (val & PHY_CTRL_FDPLX)
787 full_duplex = 1;
788 if (val & PHY_CTRL_SPD100)
789 speed = 100;
790 }
791 } else {
792 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
793
794 if (pcs_lpa & PCS_MIIADV_FD)
795 full_duplex = 1;
796 speed = 1000;
797 }
798
799 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
800 gp->dev->name, speed, (full_duplex ? "full" : "half"));
801
802 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
803 if (full_duplex) {
804 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
805 } else {
806 /* MAC_TXCFG_NBO must be zero. */
807 }
808 writel(val, gp->regs + MAC_TXCFG);
809
810 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
811 if (!full_duplex &&
812 (gp->phy_type == phy_mii_mdio0 ||
813 gp->phy_type == phy_mii_mdio1)) {
814 val |= MAC_XIFCFG_DISE;
815 } else if (full_duplex) {
816 val |= MAC_XIFCFG_FLED;
817 }
818
819 if (speed == 1000)
820 val |= (MAC_XIFCFG_GMII);
821
822 writel(val, gp->regs + MAC_XIFCFG);
823
824 /* If gigabit and half-duplex, enable carrier extension
825 * mode. Else, disable it.
826 */
827 if (speed == 1000 && !full_duplex) {
828 val = readl(gp->regs + MAC_TXCFG);
829 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
830
831 val = readl(gp->regs + MAC_RXCFG);
832 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
833 } else {
834 val = readl(gp->regs + MAC_TXCFG);
835 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
836
837 val = readl(gp->regs + MAC_RXCFG);
838 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
839 }
840
841 if (gp->phy_type == phy_serialink ||
842 gp->phy_type == phy_serdes) {
843 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
844
845 val = readl(gp->regs + MAC_MCCFG);
846 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
847 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
848 else
849 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
850 writel(val, gp->regs + MAC_MCCFG);
851
852 if (!full_duplex)
853 writel(512, gp->regs + MAC_STIME);
854 else
855 writel(64, gp->regs + MAC_STIME);
856 } else {
857 /* Set slot-time of 64. */
858 writel(64, gp->regs + MAC_STIME);
859 }
860
861 /* We are ready to rock, turn everything on. */
862 val = readl(gp->regs + TXDMA_CFG);
863 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
864 val = readl(gp->regs + RXDMA_CFG);
865 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
866 val = readl(gp->regs + MAC_TXCFG);
867 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
868 val = readl(gp->regs + MAC_RXCFG);
869 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
870 }
871
872 static int gem_mdio_link_not_up(struct gem *gp)
873 {
874 if (gp->lstate == aneg_wait) {
875 u16 val = phy_read(gp, PHY_CTRL);
876
877 /* Try forced modes. */
878 val &= ~(PHY_CTRL_ANRES | PHY_CTRL_ANENAB);
879 val &= ~(PHY_CTRL_FDPLX);
880 val |= PHY_CTRL_SPD100;
881 phy_write(gp, PHY_CTRL, val);
882 gp->timer_ticks = 0;
883 gp->lstate = force_wait;
884 return 1;
885 } else {
886 /* Downgrade from 100 to 10 Mbps if necessary.
887 * If already at 10Mbps, warn user about the
888 * situation every 10 ticks.
889 */
890 u16 val = phy_read(gp, PHY_CTRL);
891 if (val & PHY_CTRL_SPD100) {
892 val &= ~PHY_CTRL_SPD100;
893 phy_write(gp, PHY_CTRL, val);
894 gp->timer_ticks = 0;
895 return 1;
896 } else {
897 printk(KERN_ERR "%s: Link down, cable problem?\n",
898 gp->dev->name);
899 val |= (PHY_CTRL_ANRES | PHY_CTRL_ANENAB);
900 phy_write(gp, PHY_CTRL, val);
901 gp->timer_ticks = 1;
902 gp->lstate = aneg_wait;
903 return 1;
904 }
905 }
906 }
907
908 static void gem_link_timer(unsigned long data)
909 {
910 struct gem *gp = (struct gem *) data;
911 int restart_timer = 0;
912
913 gp->timer_ticks++;
914 if (gp->phy_type == phy_mii_mdio0 ||
915 gp->phy_type == phy_mii_mdio1) {
916 u16 val = phy_read(gp, PHY_STAT);
917
918 if (val & PHY_STAT_LSTAT) {
919 gem_set_link_modes(gp);
920 } else if (gp->timer_ticks < 10) {
921 restart_timer = 1;
922 } else {
923 restart_timer = gem_mdio_link_not_up(gp);
924 }
925 } else {
926 u32 val = readl(gp->regs + PCS_MIISTAT);
927
928 if (!(val & PCS_MIISTAT_LS))
929 val = readl(gp->regs + PCS_MIISTAT);
930
931 if ((val & PCS_MIISTAT_LS) == 0) {
932 restart_timer = 1;
933 } else {
934 gem_set_link_modes(gp);
935 }
936 }
937
938 if (restart_timer) {
939 gp->link_timer.expires = jiffies + ((12 * HZ) / 10);
940 add_timer(&gp->link_timer);
941 }
942 }
943
944 static void gem_clean_rings(struct gem *gp)
945 {
946 struct gem_init_block *gb = gp->init_block;
947 struct sk_buff *skb;
948 int i;
949 u32 dma_addr;
950
951 for (i = 0; i < RX_RING_SIZE; i++) {
952 struct gem_rxd *rxd;
953
954 rxd = &gb->rxd[i];
955 if (gp->rx_skbs[i] != NULL) {
956
957 skb = gp->rx_skbs[i];
958 dma_addr = (u32) le64_to_cpu(rxd->buffer);
959 pci_unmap_single(gp->pdev, dma_addr,
960 RX_BUF_ALLOC_SIZE(gp),
961 PCI_DMA_FROMDEVICE);
962 dev_kfree_skb_any(skb);
963 gp->rx_skbs[i] = NULL;
964 }
965 rxd->status_word = 0;
966 rxd->buffer = 0;
967 }
968
969 for (i = 0; i < TX_RING_SIZE; i++) {
970 if (gp->tx_skbs[i] != NULL) {
971 struct gem_txd *txd;
972 int frag;
973
974 skb = gp->tx_skbs[i];
975 gp->tx_skbs[i] = NULL;
976
977 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
978 txd = &gb->txd[i];
979 dma_addr = (u32) le64_to_cpu(txd->buffer);
980 pci_unmap_single(gp->pdev, dma_addr,
981 le64_to_cpu(txd->control_word) &
982 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
983
984 if (frag != skb_shinfo(skb)->nr_frags)
985 i++;
986 }
987 dev_kfree_skb_any(skb);
988 }
989 }
990 }
991
992 static void gem_init_rings(struct gem *gp, int from_irq)
993 {
994 struct gem_init_block *gb = gp->init_block;
995 struct net_device *dev = gp->dev;
996 int i, gfp_flags = GFP_KERNEL;
997 u32 dma_addr;
998
999 if (from_irq)
1000 gfp_flags = GFP_ATOMIC;
1001
1002 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1003
1004 gem_clean_rings(gp);
1005
1006 for (i = 0; i < RX_RING_SIZE; i++) {
1007 struct sk_buff *skb;
1008 struct gem_rxd *rxd = &gb->rxd[i];
1009
1010 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), gfp_flags);
1011 if (!skb) {
1012 rxd->buffer = 0;
1013 rxd->status_word = 0;
1014 continue;
1015 }
1016
1017 gp->rx_skbs[i] = skb;
1018 skb->dev = dev;
1019 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1020 dma_addr = pci_map_single(gp->pdev, skb->data,
1021 RX_BUF_ALLOC_SIZE(gp),
1022 PCI_DMA_FROMDEVICE);
1023 rxd->buffer = cpu_to_le64(dma_addr);
1024 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1025 skb_reserve(skb, RX_OFFSET);
1026 }
1027
1028 for (i = 0; i < TX_RING_SIZE; i++) {
1029 struct gem_txd *txd = &gb->txd[i];
1030
1031 txd->control_word = 0;
1032 txd->buffer = 0;
1033 }
1034 }
1035
1036 static void gem_init_phy(struct gem *gp)
1037 {
1038 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1039 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1040 u32 val;
1041
1042 /* Init datapath mode register. */
1043 if (gp->phy_type == phy_mii_mdio0 ||
1044 gp->phy_type == phy_mii_mdio1) {
1045 val = PCS_DMODE_MGM;
1046 } else if (gp->phy_type == phy_serialink) {
1047 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1048 } else {
1049 val = PCS_DMODE_ESM;
1050 }
1051
1052 writel(val, gp->regs + PCS_DMODE);
1053 }
1054
1055 if (gp->phy_type == phy_mii_mdio0 ||
1056 gp->phy_type == phy_mii_mdio1) {
1057 u16 val = phy_read(gp, PHY_CTRL);
1058 int limit = 10000;
1059
1060 /* Take PHY out of isloate mode and reset it. */
1061 val &= ~PHY_CTRL_ISO;
1062 val |= PHY_CTRL_RST;
1063 phy_write(gp, PHY_CTRL, val);
1064
1065 while (limit--) {
1066 val = phy_read(gp, PHY_CTRL);
1067 if ((val & PHY_CTRL_RST) == 0)
1068 break;
1069 udelay(10);
1070 }
1071
1072 /* Init advertisement and enable autonegotiation. */
1073 phy_write(gp, PHY_ADV,
1074 (PHY_ADV_10HALF | PHY_ADV_10FULL |
1075 PHY_ADV_100HALF | PHY_ADV_100FULL));
1076
1077 val |= (PHY_CTRL_ANRES | PHY_CTRL_ANENAB);
1078 phy_write(gp, PHY_CTRL, val);
1079 } else {
1080 u32 val;
1081 int limit;
1082
1083 /* Reset PCS unit. */
1084 val = readl(gp->regs + PCS_MIICTRL);
1085 val |= PCS_MIICTRL_RST;
1086 writeb(val, gp->regs + PCS_MIICTRL);
1087
1088 limit = 32;
1089 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1090 udelay(100);
1091 if (limit-- <= 0)
1092 break;
1093 }
1094 if (limit <= 0)
1095 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1096 gp->dev->name);
1097
1098 /* Make sure PCS is disabled while changing advertisement
1099 * configuration.
1100 */
1101 val = readl(gp->regs + PCS_CFG);
1102 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1103 writel(val, gp->regs + PCS_CFG);
1104
1105 /* Advertise all capabilities. */
1106 val = readl(gp->regs + PCS_MIIADV);
1107 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1108 PCS_MIIADV_SP | PCS_MIIADV_AP);
1109 writel(val, gp->regs + PCS_MIIADV);
1110
1111 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1112 * and re-enable PCS.
1113 */
1114 val = readl(gp->regs + PCS_MIICTRL);
1115 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1116 val &= ~PCS_MIICTRL_WB;
1117 writel(val, gp->regs + PCS_MIICTRL);
1118
1119 val = readl(gp->regs + PCS_CFG);
1120 val |= PCS_CFG_ENABLE;
1121 writel(val, gp->regs + PCS_CFG);
1122
1123 /* Make sure serialink loopback is off. The meaning
1124 * of this bit is logically inverted based upon whether
1125 * you are in Serialink or SERDES mode.
1126 */
1127 val = readl(gp->regs + PCS_SCTRL);
1128 if (gp->phy_type == phy_serialink)
1129 val &= ~PCS_SCTRL_LOOP;
1130 else
1131 val |= PCS_SCTRL_LOOP;
1132 writel(val, gp->regs + PCS_SCTRL);
1133 }
1134 }
1135
1136 static void gem_init_dma(struct gem *gp)
1137 {
1138 u32 val;
1139
1140 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1141 writel(val, gp->regs + TXDMA_CFG);
1142
1143 writel(0, gp->regs + TXDMA_DBHI);
1144 writel(gp->gblock_dvma, gp->regs + TXDMA_DBLOW);
1145
1146 writel(0, gp->regs + TXDMA_KICK);
1147
1148 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1149 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_512);
1150 writel(val, gp->regs + RXDMA_CFG);
1151
1152 writel(0, gp->regs + RXDMA_DBHI);
1153 writel((gp->gblock_dvma +
1154 (TX_RING_SIZE * sizeof(struct gem_txd))),
1155 gp->regs + RXDMA_DBLOW);
1156
1157 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1158
1159 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1160 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1161 writel(val, gp->regs + RXDMA_PTHRESH);
1162
1163 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1164 writel(((6 & RXDMA_BLANK_IPKTS) |
1165 ((4 << 12) & RXDMA_BLANK_ITIME)),
1166 gp->regs + RXDMA_BLANK);
1167 else
1168 writel(((6 & RXDMA_BLANK_IPKTS) |
1169 ((2 << 12) & RXDMA_BLANK_ITIME)),
1170 gp->regs + RXDMA_BLANK);
1171 }
1172
1173 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
1174
1175 static void gem_init_mac(struct gem *gp)
1176 {
1177 unsigned char *e = &gp->dev->dev_addr[0];
1178 u32 rxcfg;
1179
1180 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1181 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM)
1182 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1183
1184 writel(0x00, gp->regs + MAC_IPG0);
1185 writel(0x08, gp->regs + MAC_IPG1);
1186 writel(0x04, gp->regs + MAC_IPG2);
1187 writel(0x40, gp->regs + MAC_STIME);
1188 writel(0x40, gp->regs + MAC_MINFSZ);
1189 writel(0x20000000 | (gp->dev->mtu + 18), gp->regs + MAC_MAXFSZ);
1190 writel(0x07, gp->regs + MAC_PASIZE);
1191 writel(0x04, gp->regs + MAC_JAMSIZE);
1192 writel(0x10, gp->regs + MAC_ATTLIM);
1193 writel(0x8808, gp->regs + MAC_MCTYPE);
1194
1195 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1196
1197 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1198 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1199 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1200
1201 writel(0, gp->regs + MAC_ADDR3);
1202 writel(0, gp->regs + MAC_ADDR4);
1203 writel(0, gp->regs + MAC_ADDR5);
1204
1205 writel(0x0001, gp->regs + MAC_ADDR6);
1206 writel(0xc200, gp->regs + MAC_ADDR7);
1207 writel(0x0180, gp->regs + MAC_ADDR8);
1208
1209 writel(0, gp->regs + MAC_AFILT0);
1210 writel(0, gp->regs + MAC_AFILT1);
1211 writel(0, gp->regs + MAC_AFILT2);
1212 writel(0, gp->regs + MAC_AF21MSK);
1213 writel(0, gp->regs + MAC_AF0MSK);
1214
1215 rxcfg = 0;
1216 if ((gp->dev->flags & IFF_ALLMULTI) ||
1217 (gp->dev->mc_count > 256)) {
1218 writel(0xffff, gp->regs + MAC_HASH0);
1219 writel(0xffff, gp->regs + MAC_HASH1);
1220 writel(0xffff, gp->regs + MAC_HASH2);
1221 writel(0xffff, gp->regs + MAC_HASH3);
1222 writel(0xffff, gp->regs + MAC_HASH4);
1223 writel(0xffff, gp->regs + MAC_HASH5);
1224 writel(0xffff, gp->regs + MAC_HASH6);
1225 writel(0xffff, gp->regs + MAC_HASH7);
1226 writel(0xffff, gp->regs + MAC_HASH8);
1227 writel(0xffff, gp->regs + MAC_HASH9);
1228 writel(0xffff, gp->regs + MAC_HASH10);
1229 writel(0xffff, gp->regs + MAC_HASH11);
1230 writel(0xffff, gp->regs + MAC_HASH12);
1231 writel(0xffff, gp->regs + MAC_HASH13);
1232 writel(0xffff, gp->regs + MAC_HASH14);
1233 writel(0xffff, gp->regs + MAC_HASH15);
1234 } else if (gp->dev->flags & IFF_PROMISC) {
1235 rxcfg |= MAC_RXCFG_PROM;
1236 } else {
1237 u16 hash_table[16];
1238 u32 crc, poly = CRC_POLYNOMIAL_LE;
1239 struct dev_mc_list *dmi = gp->dev->mc_list;
1240 int i, j, bit, byte;
1241
1242 for (i = 0; i < 16; i++)
1243 hash_table[i] = 0;
1244
1245 for (i = 0; i < gp->dev->mc_count; i++) {
1246 char *addrs = dmi->dmi_addr;
1247
1248 dmi = dmi->next;
1249
1250 if (!(*addrs & 1))
1251 continue;
1252
1253 crc = 0xffffffffU;
1254 for (byte = 0; byte < 6; byte++) {
1255 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1256 int test;
1257
1258 test = ((bit ^ crc) & 0x01);
1259 crc >>= 1;
1260 if (test)
1261 crc = crc ^ poly;
1262 }
1263 }
1264 crc >>= 24;
1265 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1266 }
1267 writel(hash_table[0], gp->regs + MAC_HASH0);
1268 writel(hash_table[1], gp->regs + MAC_HASH1);
1269 writel(hash_table[2], gp->regs + MAC_HASH2);
1270 writel(hash_table[3], gp->regs + MAC_HASH3);
1271 writel(hash_table[4], gp->regs + MAC_HASH4);
1272 writel(hash_table[5], gp->regs + MAC_HASH5);
1273 writel(hash_table[6], gp->regs + MAC_HASH6);
1274 writel(hash_table[7], gp->regs + MAC_HASH7);
1275 writel(hash_table[8], gp->regs + MAC_HASH8);
1276 writel(hash_table[9], gp->regs + MAC_HASH9);
1277 writel(hash_table[10], gp->regs + MAC_HASH10);
1278 writel(hash_table[11], gp->regs + MAC_HASH11);
1279 writel(hash_table[12], gp->regs + MAC_HASH12);
1280 writel(hash_table[13], gp->regs + MAC_HASH13);
1281 writel(hash_table[14], gp->regs + MAC_HASH14);
1282 writel(hash_table[15], gp->regs + MAC_HASH15);
1283 }
1284
1285 writel(0, gp->regs + MAC_NCOLL);
1286 writel(0, gp->regs + MAC_FASUCC);
1287 writel(0, gp->regs + MAC_ECOLL);
1288 writel(0, gp->regs + MAC_LCOLL);
1289 writel(0, gp->regs + MAC_DTIMER);
1290 writel(0, gp->regs + MAC_PATMPS);
1291 writel(0, gp->regs + MAC_RFCTR);
1292 writel(0, gp->regs + MAC_LERR);
1293 writel(0, gp->regs + MAC_AERR);
1294 writel(0, gp->regs + MAC_FCSERR);
1295 writel(0, gp->regs + MAC_RXCVERR);
1296
1297 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1298 * them once a link is established.
1299 */
1300 writel(0, gp->regs + MAC_TXCFG);
1301 writel(rxcfg, gp->regs + MAC_RXCFG);
1302 writel(0, gp->regs + MAC_MCCFG);
1303 writel(0, gp->regs + MAC_XIFCFG);
1304
1305 writel((MAC_TXSTAT_URUN | MAC_TXSTAT_MPE |
1306 MAC_TXSTAT_NCE | MAC_TXSTAT_ECE |
1307 MAC_TXSTAT_LCE | MAC_TXSTAT_FCE |
1308 MAC_TXSTAT_DTE | MAC_TXSTAT_PCE), gp->regs + MAC_TXMASK);
1309 writel((MAC_RXSTAT_OFLW | MAC_RXSTAT_FCE |
1310 MAC_RXSTAT_ACE | MAC_RXSTAT_CCE |
1311 MAC_RXSTAT_LCE | MAC_RXSTAT_VCE), gp->regs + MAC_RXMASK);
1312 writel(0, gp->regs + MAC_MCMASK);
1313 }
1314
1315 static void gem_init_hw(struct gem *gp)
1316 {
1317 gem_init_phy(gp);
1318 gem_init_dma(gp);
1319 gem_init_mac(gp);
1320
1321 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
1322
1323 gp->timer_ticks = 0;
1324 gp->lstate = aneg_wait;
1325 gp->link_timer.expires = jiffies + ((12 * HZ) / 10);
1326 add_timer(&gp->link_timer);
1327 }
1328
1329 static int gem_open(struct net_device *dev)
1330 {
1331 struct gem *gp = dev->priv;
1332 unsigned long regs = gp->regs;
1333
1334 del_timer(&gp->link_timer);
1335
1336 if (request_irq(gp->pdev->irq, gem_interrupt,
1337 SA_SHIRQ, dev->name, (void *)dev))
1338 return -EAGAIN;
1339
1340 gem_stop(gp, regs);
1341 gem_init_rings(gp, 0);
1342 gem_init_hw(gp);
1343
1344 return 0;
1345 }
1346
1347 static int gem_close(struct net_device *dev)
1348 {
1349 struct gem *gp = dev->priv;
1350
1351 del_timer(&gp->link_timer);
1352 gem_stop(gp, gp->regs);
1353 gem_clean_rings(gp);
1354 free_irq(gp->pdev->irq, (void *)dev);
1355 return 0;
1356 }
1357
1358 static struct net_device_stats *gem_get_stats(struct net_device *dev)
1359 {
1360 struct gem *gp = dev->priv;
1361 struct net_device_stats *stats = &gp->net_stats;
1362
1363 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
1364 writel(0, gp->regs + MAC_FCSERR);
1365
1366 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
1367 writel(0, gp->regs + MAC_AERR);
1368
1369 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
1370 writel(0, gp->regs + MAC_LERR);
1371
1372 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
1373 stats->collisions +=
1374 (readl(gp->regs + MAC_ECOLL) +
1375 readl(gp->regs + MAC_LCOLL));
1376 writel(0, gp->regs + MAC_ECOLL);
1377 writel(0, gp->regs + MAC_LCOLL);
1378
1379 return &gp->net_stats;
1380 }
1381
1382 static void gem_set_multicast(struct net_device *dev)
1383 {
1384 struct gem *gp = dev->priv;
1385
1386 netif_stop_queue(dev);
1387
1388 if ((gp->dev->flags & IFF_ALLMULTI) ||
1389 (gp->dev->mc_count > 256)) {
1390 writel(0xffff, gp->regs + MAC_HASH0);
1391 writel(0xffff, gp->regs + MAC_HASH1);
1392 writel(0xffff, gp->regs + MAC_HASH2);
1393 writel(0xffff, gp->regs + MAC_HASH3);
1394 writel(0xffff, gp->regs + MAC_HASH4);
1395 writel(0xffff, gp->regs + MAC_HASH5);
1396 writel(0xffff, gp->regs + MAC_HASH6);
1397 writel(0xffff, gp->regs + MAC_HASH7);
1398 writel(0xffff, gp->regs + MAC_HASH8);
1399 writel(0xffff, gp->regs + MAC_HASH9);
1400 writel(0xffff, gp->regs + MAC_HASH10);
1401 writel(0xffff, gp->regs + MAC_HASH11);
1402 writel(0xffff, gp->regs + MAC_HASH12);
1403 writel(0xffff, gp->regs + MAC_HASH13);
1404 writel(0xffff, gp->regs + MAC_HASH14);
1405 writel(0xffff, gp->regs + MAC_HASH15);
1406 } else if (gp->dev->flags & IFF_PROMISC) {
1407 u32 rxcfg = readl(gp->regs + MAC_RXCFG);
1408 int limit = 10000;
1409
1410 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1411 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
1412 if (!limit--)
1413 break;
1414 udelay(10);
1415 }
1416
1417 rxcfg |= MAC_RXCFG_PROM;
1418 writel(rxcfg, gp->regs + MAC_RXCFG);
1419 } else {
1420 u16 hash_table[16];
1421 u32 crc, poly = CRC_POLYNOMIAL_LE;
1422 struct dev_mc_list *dmi = gp->dev->mc_list;
1423 int i, j, bit, byte;
1424
1425 for (i = 0; i < 16; i++)
1426 hash_table[i] = 0;
1427
1428 for (i = 0; i < dev->mc_count; i++) {
1429 char *addrs = dmi->dmi_addr;
1430
1431 dmi = dmi->next;
1432
1433 if (!(*addrs & 1))
1434 continue;
1435
1436 crc = 0xffffffffU;
1437 for (byte = 0; byte < 6; byte++) {
1438 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1439 int test;
1440
1441 test = ((bit ^ crc) & 0x01);
1442 crc >>= 1;
1443 if (test)
1444 crc = crc ^ poly;
1445 }
1446 }
1447 crc >>= 24;
1448 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1449 }
1450 writel(hash_table[0], gp->regs + MAC_HASH0);
1451 writel(hash_table[1], gp->regs + MAC_HASH1);
1452 writel(hash_table[2], gp->regs + MAC_HASH2);
1453 writel(hash_table[3], gp->regs + MAC_HASH3);
1454 writel(hash_table[4], gp->regs + MAC_HASH4);
1455 writel(hash_table[5], gp->regs + MAC_HASH5);
1456 writel(hash_table[6], gp->regs + MAC_HASH6);
1457 writel(hash_table[7], gp->regs + MAC_HASH7);
1458 writel(hash_table[8], gp->regs + MAC_HASH8);
1459 writel(hash_table[9], gp->regs + MAC_HASH9);
1460 writel(hash_table[10], gp->regs + MAC_HASH10);
1461 writel(hash_table[11], gp->regs + MAC_HASH11);
1462 writel(hash_table[12], gp->regs + MAC_HASH12);
1463 writel(hash_table[13], gp->regs + MAC_HASH13);
1464 writel(hash_table[14], gp->regs + MAC_HASH14);
1465 writel(hash_table[15], gp->regs + MAC_HASH15);
1466 }
1467
1468 netif_wake_queue(dev);
1469 }
1470
1471 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1472 {
1473 return -EINVAL;
1474 }
1475
1476 static int __devinit gem_check_invariants(struct gem *gp)
1477 {
1478 struct pci_dev *pdev = gp->pdev;
1479 u32 mif_cfg = readl(gp->regs + MIF_CFG);
1480
1481 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1482 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1483 /* One of the MII PHYs _must_ be present
1484 * as this chip has no gigabit PHY.
1485 */
1486 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1487 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1488 mif_cfg);
1489 return -1;
1490 }
1491 }
1492
1493 /* Determine initial PHY interface type guess. MDIO1 is the
1494 * external PHY and thus takes precedence over MDIO0.
1495 */
1496 if (mif_cfg & MIF_CFG_MDI1) {
1497 gp->phy_type = phy_mii_mdio1;
1498 mif_cfg |= MIF_CFG_PSELECT;
1499 writel(mif_cfg, gp->regs + MIF_CFG);
1500 } else if (mif_cfg & MIF_CFG_MDI0) {
1501 gp->phy_type = phy_mii_mdio0;
1502 mif_cfg &= ~MIF_CFG_PSELECT;
1503 writel(mif_cfg, gp->regs + MIF_CFG);
1504 } else {
1505 gp->phy_type = phy_serialink;
1506 }
1507 if (gp->phy_type == phy_mii_mdio1 ||
1508 gp->phy_type == phy_mii_mdio0) {
1509 int i;
1510
1511 for (i = 0; i < 32; i++) {
1512 gp->mii_phy_addr = i;
1513 if (phy_read(gp, PHY_CTRL) != 0xffff)
1514 break;
1515 }
1516 if (i == 32) {
1517 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
1518 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
1519 return -1;
1520 }
1521 gp->phy_type = phy_serdes;
1522 }
1523 }
1524
1525 /* Fetch the FIFO configurations now too. */
1526 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1527 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1528
1529 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
1530 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1531 if (gp->tx_fifo_sz != (9 * 1024) ||
1532 gp->rx_fifo_sz != (20 * 1024)) {
1533 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1534 gp->tx_fifo_sz, gp->rx_fifo_sz);
1535 return -1;
1536 }
1537 } else {
1538 if (gp->tx_fifo_sz != (2 * 1024) ||
1539 gp->rx_fifo_sz != (2 * 1024)) {
1540 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1541 gp->tx_fifo_sz, gp->rx_fifo_sz);
1542 return -1;
1543 }
1544 }
1545 }
1546
1547 /* Calculate pause thresholds. Setting the OFF threshold to the
1548 * full RX fifo size effectively disables PAUSE generation which
1549 * is what we do for 10/100 only GEMs which have FIFOs too small
1550 * to make real gains from PAUSE.
1551 */
1552 if (gp->rx_fifo_sz <= (2 * 1024)) {
1553 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1554 } else {
1555 int off = (gp->rx_fifo_sz - (5 * 1024));
1556 int on = off - 1024;
1557
1558 gp->rx_pause_off = off;
1559 gp->rx_pause_on = on;
1560 }
1561
1562 {
1563 u32 cfg = readl(gp->regs + GREG_BIFCFG);
1564
1565 cfg |= GREG_BIFCFG_B64DIS;
1566 writel(cfg, gp->regs + GREG_BIFCFG);
1567
1568 cfg = GREG_CFG_IBURST;
1569 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1570 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1571 writel(cfg, gp->regs + GREG_CFG);
1572 }
1573
1574 return 0;
1575 }
1576
1577 static int __devinit gem_get_device_address(struct gem *gp)
1578 {
1579 #if defined(__sparc__) || defined(__powerpc__)
1580 struct net_device *dev = gp->dev;
1581 struct pci_dev *pdev = gp->pdev;
1582 #endif
1583
1584 #ifdef __sparc__
1585 struct pcidev_cookie *pcp = pdev->sysdata;
1586 int node = -1;
1587
1588 if (pcp != NULL) {
1589 node = pcp->prom_node;
1590 if (prom_getproplen(node, "local-mac-address") == 6)
1591 prom_getproperty(node, "local-mac-address",
1592 dev->dev_addr, 6);
1593 else
1594 node = -1;
1595 }
1596 if (node == -1)
1597 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
1598 #endif
1599 #ifdef __powerpc__
1600 struct device_node *gem_node;
1601 unsigned char *addr;
1602
1603 gem_node = pci_device_to_OF_node(pdev);
1604 addr = get_property(gem_node, "local-mac-address", NULL);
1605 if (addr == NULL) {
1606 printk("\n");
1607 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
1608 return -1;
1609 }
1610 memcpy(dev->dev_addr, addr, MAX_ADDR_LEN);
1611 #endif
1612 return 0;
1613 }
1614
1615 static int __devinit gem_init_one(struct pci_dev *pdev,
1616 const struct pci_device_id *ent)
1617 {
1618 static int gem_version_printed = 0;
1619 unsigned long gemreg_base, gemreg_len;
1620 struct net_device *dev;
1621 struct gem *gp;
1622 int i, err;
1623
1624 if (gem_version_printed++ == 0)
1625 printk(KERN_INFO "%s", version);
1626
1627 err = pci_enable_device(pdev);
1628 if (err) {
1629 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
1630 "aborting.\n");
1631 return err;
1632 }
1633 pci_set_master(pdev);
1634
1635 gemreg_base = pci_resource_start(pdev, 0);
1636 gemreg_len = pci_resource_len(pdev, 0);
1637
1638 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
1639 printk(KERN_ERR PFX "Cannot find proper PCI device "
1640 "base address, aborting.\n");
1641 return -ENODEV;
1642 }
1643
1644 dev = init_etherdev(NULL, sizeof(*gp));
1645 if (!dev) {
1646 printk(KERN_ERR PFX "Etherdev init failed, aborting.\n");
1647 return -ENOMEM;
1648 }
1649 SET_MODULE_OWNER(dev);
1650
1651 if (!request_mem_region(gemreg_base, gemreg_len, dev->name)) {
1652 printk(KERN_ERR PFX "MMIO resource (0x%lx@0x%lx) unavailable, "
1653 "aborting.\n", gemreg_base, gemreg_len);
1654 goto err_out_free_netdev;
1655 }
1656
1657 gp = dev->priv;
1658
1659 gp->pdev = pdev;
1660 dev->base_addr = (long) pdev;
1661 gp->dev = dev;
1662
1663 spin_lock_init(&gp->lock);
1664
1665 gp->regs = (unsigned long) ioremap(gemreg_base, gemreg_len);
1666 if (gp->regs == 0UL) {
1667 printk(KERN_ERR PFX "Cannot map device registers, "
1668 "aborting.\n");
1669 goto err_out_free_mmio_res;
1670 }
1671
1672 if (gem_check_invariants(gp))
1673 goto err_out_iounmap;
1674
1675 /* It is guarenteed that the returned buffer will be at least
1676 * PAGE_SIZE aligned.
1677 */
1678 gp->init_block = (struct gem_init_block *)
1679 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
1680 &gp->gblock_dvma);
1681 if (!gp->init_block) {
1682 printk(KERN_ERR PFX "Cannot allocate init block, "
1683 "aborting.\n");
1684 goto err_out_iounmap;
1685 }
1686
1687 pci_set_drvdata(pdev, dev);
1688
1689 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
1690 dev->name);
1691
1692 if (gem_get_device_address(gp))
1693 goto err_out_iounmap;
1694
1695 for (i = 0; i < 6; i++)
1696 printk("%2.2x%c", dev->dev_addr[i],
1697 i == 5 ? ' ' : ':');
1698 printk("\n");
1699
1700 init_timer(&gp->link_timer);
1701 gp->link_timer.function = gem_link_timer;
1702 gp->link_timer.data = (unsigned long) gp;
1703
1704 dev->open = gem_open;
1705 dev->stop = gem_close;
1706 dev->hard_start_xmit = gem_start_xmit;
1707 dev->get_stats = gem_get_stats;
1708 dev->set_multicast_list = gem_set_multicast;
1709 dev->do_ioctl = gem_ioctl;
1710 dev->tx_timeout = gem_tx_timeout;
1711 dev->watchdog_timeo = 5 * HZ;
1712 dev->change_mtu = gem_change_mtu;
1713 dev->irq = pdev->irq;
1714 dev->dma = 0;
1715
1716 /* GEM can do it all... */
1717 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
1718
1719 return 0;
1720
1721 err_out_iounmap:
1722 iounmap((void *) gp->regs);
1723
1724 err_out_free_mmio_res:
1725 release_mem_region(gemreg_base, gemreg_len);
1726
1727 err_out_free_netdev:
1728 unregister_netdev(dev);
1729 kfree(dev);
1730
1731 return -ENODEV;
1732
1733 }
1734
1735 static void __devexit gem_remove_one(struct pci_dev *pdev)
1736 {
1737 struct net_device *dev = pci_get_drvdata(pdev);
1738
1739 if (dev) {
1740 struct gem *gp = dev->priv;
1741
1742 unregister_netdev(dev);
1743
1744 pci_free_consistent(pdev,
1745 sizeof(struct gem_init_block),
1746 gp->init_block,
1747 gp->gblock_dvma);
1748 iounmap((void *) gp->regs);
1749 release_mem_region(pci_resource_start(pdev, 0),
1750 pci_resource_len(pdev, 0));
1751 kfree(dev);
1752
1753 pci_set_drvdata(pdev, NULL);
1754 }
1755 }
1756
1757 static struct pci_driver gem_driver = {
1758 name: GEM_MODULE_NAME,
1759 id_table: gem_pci_tbl,
1760 probe: gem_init_one,
1761 remove: gem_remove_one,
1762 };
1763
1764 static int __init gem_init(void)
1765 {
1766 return pci_module_init(&gem_driver);
1767 }
1768
1769 static void __exit gem_cleanup(void)
1770 {
1771 pci_unregister_driver(&gem_driver);
1772 }
1773
1774 module_init(gem_init);
1775 module_exit(gem_cleanup);
1776