File: /usr/src/linux/drivers/net/wan/dscc4.c
1 /*
2 * drivers/net/wan/dscc4/dscc4_main.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * Jens David has built an adapter based on the same chipset. Take a look
25 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
26 * driver.
27 * Sample code (2 revisions) is available at Infineon.
28 *
29 * II. Board-specific settings
30 *
31 * Pcisync can transmit some clock signal to the outside world on the
32 * *first two* ports provided you put a quartz and a line driver on it and
33 * remove the jumpers. The operation is described on Etinc web site. If you
34 * go DCE on these ports, don't forget to use an adequate cable.
35 *
36 * Sharing of the PCI interrupt line for this board is possible.
37 *
38 * III. Driver operation
39 *
40 * The rx/tx operations are based on a linked list of descriptor. I haven't
41 * tried the start/stop descriptor method as this one looks like the cheapest
42 * in terms of PCI manipulation.
43 *
44 * Tx direction
45 * Once the data section of the current descriptor processed, the next linked
46 * descriptor is loaded if the HOLD bit isn't set in the current descriptor.
47 * If HOLD is met, the transmission is stopped until the host unsets it and
48 * signals the change via TxPOLL.
49 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
50 * The device is supposed to be enabled again during an ALLS irq (we could
51 * use HI but as it's easy to loose events, it's fscked).
52 *
53 * Rx direction
54 * The received frames aren't supposed to span over multiple receiving areas.
55 * I may implement it some day but it isn't the highest ranked item.
56 *
57 * IV. Notes
58 * The chipset is buggy. Typically, under some specific load patterns (I
59 * wouldn't call them "high"), the irq queues and the descriptors look like
60 * some event has been lost. Even assuming some fancy PCI feature, it won't
61 * explain the reproductible missing "C" bit in the descriptors. Faking an
62 * irq in the periodic timer isn't really elegant but at least it seems
63 * reliable.
64 * The current error (XDU, RFO) recovery code is untested.
65 * So far, RDO takes his RX channel down and the right sequence to enable it
66 * again is still a mistery. If RDO happens, plan a reboot. More details
67 * in the code (NB: as this happens, TX still works).
68 * Don't mess the cables during operation, especially on DTE ports. I don't
69 * suggest it for DCE either but at least one can get some messages instead
70 * of a complete instant freeze.
71 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
72 * the documentation/chipset releases. An on-line errata would be welcome.
73 *
74 * TODO:
75 * - some trivial error lurk,
76 * - the stats are fscked,
77 * - use polling at high irq/s,
78 * - performance analysis,
79 * - endianness.
80 *
81 */
82
83 #include <linux/version.h>
84 #include <linux/module.h>
85 #include <linux/types.h>
86 #include <linux/errno.h>
87 #include <linux/ioport.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
90 #include <linux/mm.h>
91
92 #include <asm/system.h>
93 #include <asm/cache.h>
94 #include <asm/byteorder.h>
95 #include <asm/uaccess.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98
99 #include <linux/init.h>
100 #include <linux/string.h>
101
102 #include <linux/if_arp.h>
103 #include <linux/netdevice.h>
104 #include <linux/skbuff.h>
105 #include <linux/delay.h>
106 #include <net/syncppp.h>
107 #include <linux/hdlc.h>
108
109 /* Version */
110 static const char version[] = "$Id: dscc4.c,v 1.130 2001/02/25 15:27:34 romieu Exp $\n";
111 static int debug;
112
113
114 /* Module parameters */
115 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
116 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller");
117 MODULE_LICENSE("GPL");
118 MODULE_PARM(debug,"i");
119
120 /* Structures */
121 struct TxFD {
122 u32 state;
123 u32 next;
124 u32 data;
125 u32 complete;
126 u32 jiffies; /* more hack to come :o) */
127 };
128
129 struct RxFD {
130 u32 state1;
131 u32 next;
132 u32 data;
133 u32 state2;
134 u32 end;
135 };
136
137 #define DEBUG
138 #define DEBUG_PARANOID
139 #define TX_RING_SIZE 32
140 #define RX_RING_SIZE 32
141 #define IRQ_RING_SIZE 64 /* Keep it A multiple of 32 */
142 #define TX_TIMEOUT (HZ/10)
143 #define BRR_DIVIDER_MAX 64*0x00008000
144 #define dev_per_card 4
145
146 #define SOURCE_ID(flags) ((flags >> 28 ) & 0x03)
147 #define TO_SIZE(state) ((state >> 16) & 0x1fff)
148 #define TO_STATE(len) cpu_to_le32((len & TxSizeMax) << 16)
149 #define RX_MAX(len) ((((len) >> 5) + 1) << 5)
150 #define SCC_REG_START(id) SCC_START+(id)*SCC_OFFSET
151
152 #undef DEBUG
153
154 struct dscc4_pci_priv {
155 u32 *iqcfg;
156 int cfg_cur;
157 spinlock_t lock;
158 struct pci_dev *pdev;
159
160 struct net_device *root;
161 dma_addr_t iqcfg_dma;
162 u32 xtal_hz;
163 };
164
165 struct dscc4_dev_priv {
166 struct sk_buff *rx_skbuff[RX_RING_SIZE];
167 struct sk_buff *tx_skbuff[TX_RING_SIZE];
168
169 struct RxFD *rx_fd;
170 struct TxFD *tx_fd;
171 u32 *iqrx;
172 u32 *iqtx;
173
174 u32 rx_current;
175 u32 tx_current;
176 u32 iqrx_current;
177 u32 iqtx_current;
178
179 u32 tx_dirty;
180 int bad_tx_frame;
181 int bad_rx_frame;
182 int rx_needs_refill;
183
184 dma_addr_t tx_fd_dma;
185 dma_addr_t rx_fd_dma;
186 dma_addr_t iqtx_dma;
187 dma_addr_t iqrx_dma;
188
189 struct net_device_stats stats;
190 struct timer_list timer;
191
192 struct dscc4_pci_priv *pci_priv;
193 spinlock_t lock;
194
195 int dev_id;
196 u32 flags;
197 u32 timer_help;
198 u32 hi_expected;
199
200 struct hdlc_device_struct hdlc;
201 int usecount;
202 };
203
204 /* GLOBAL registers definitions */
205 #define GCMDR 0x00
206 #define GSTAR 0x04
207 #define GMODE 0x08
208 #define IQLENR0 0x0C
209 #define IQLENR1 0x10
210 #define IQRX0 0x14
211 #define IQTX0 0x24
212 #define IQCFG 0x3c
213 #define FIFOCR1 0x44
214 #define FIFOCR2 0x48
215 #define FIFOCR3 0x4c
216 #define FIFOCR4 0x34
217 #define CH0CFG 0x50
218 #define CH0BRDA 0x54
219 #define CH0BTDA 0x58
220
221 /* SCC registers definitions */
222 #define SCC_START 0x0100
223 #define SCC_OFFSET 0x80
224 #define CMDR 0x00
225 #define STAR 0x04
226 #define CCR0 0x08
227 #define CCR1 0x0c
228 #define CCR2 0x10
229 #define BRR 0x2C
230 #define RLCR 0x40
231 #define IMR 0x54
232 #define ISR 0x58
233
234 /* Bit masks */
235 #define IntRxScc0 0x10000000
236 #define IntTxScc0 0x01000000
237
238 #define TxPollCmd 0x00000400
239 #define RxActivate 0x08000000
240 #define MTFi 0x04000000
241 #define Rdr 0x00400000
242 #define Rdt 0x00200000
243 #define Idr 0x00100000
244 #define Idt 0x00080000
245 #define TxSccRes 0x01000000
246 #define RxSccRes 0x00010000
247 #define TxSizeMax 0x1ffc
248 #define RxSizeMax 0x1ffc
249
250 #define Ccr0ClockMask 0x0000003f
251 #define Ccr1LoopMask 0x00000200
252 #define BrrExpMask 0x00000f00
253 #define BrrMultMask 0x0000003f
254 #define EncodingMask 0x00700000
255 #define Hold 0x40000000
256 #define SccBusy 0x10000000
257 #define FrameOk (FrameVfr | FrameCrc)
258 #define FrameVfr 0x80
259 #define FrameRdo 0x40
260 #define FrameCrc 0x20
261 #define FrameAborted 0x00000200
262 #define FrameEnd 0x80000000
263 #define DataComplete 0x40000000
264 #define LengthCheck 0x00008000
265 #define SccEvt 0x02000000
266 #define NoAck 0x00000200
267 #define Action 0x00000001
268 #define HiDesc 0x20000000
269
270 /* SCC events */
271 #define RxEvt 0xf0000000
272 #define TxEvt 0x0f000000
273 #define Alls 0x00040000
274 #define Xdu 0x00010000
275 #define Xmr 0x00002000
276 #define Xpr 0x00001000
277 #define Rdo 0x00000080
278 #define Rfs 0x00000040
279 #define Rfo 0x00000002
280 #define Flex 0x00000001
281
282 /* DMA core events */
283 #define Cfg 0x00200000
284 #define Hi 0x00040000
285 #define Fi 0x00020000
286 #define Err 0x00010000
287 #define Arf 0x00000002
288 #define ArAck 0x00000001
289
290 /* Misc */
291 #define NeedIDR 0x00000001
292 #define NeedIDT 0x00000002
293 #define RdoSet 0x00000004
294
295 /* Functions prototypes */
296 static __inline__ void dscc4_rx_irq(struct dscc4_pci_priv *, struct net_device *);
297 static __inline__ void dscc4_tx_irq(struct dscc4_pci_priv *, struct net_device *);
298 static int dscc4_found1(struct pci_dev *, unsigned long ioaddr);
299 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
300 static int dscc4_open(struct net_device *);
301 static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
302 static int dscc4_close(struct net_device *);
303 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
304 static int dscc4_change_mtu(struct net_device *dev, int mtu);
305 static int dscc4_init_ring(struct net_device *);
306 static void dscc4_release_ring(struct dscc4_dev_priv *);
307 static void dscc4_timer(unsigned long);
308 static void dscc4_tx_timeout(struct net_device *);
309 static void dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs);
310 static struct net_device_stats *dscc4_get_stats(struct net_device *);
311 static int dscc4_attach_hdlc_device(struct net_device *);
312 static void dscc4_unattach_hdlc_device(struct net_device *);
313 static int dscc4_hdlc_open(struct hdlc_device_struct *);
314 static void dscc4_hdlc_close(struct hdlc_device_struct *);
315 static int dscc4_hdlc_ioctl(struct hdlc_device_struct *, struct ifreq *, int);
316 static int dscc4_hdlc_xmit(hdlc_device *, struct sk_buff *);
317 #ifdef EXPERIMENTAL_POLLING
318 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
319 #endif
320
321 void inline reset_TxFD(struct TxFD *tx_fd) {
322 /* FIXME: test with the last arg (size specification) = 0 */
323 tx_fd->state = FrameEnd | Hold | 0x00100000;
324 tx_fd->complete = 0x00000000;
325 }
326
327 void inline dscc4_release_ring_skbuff(struct sk_buff **p, int n)
328 {
329 for(; n > 0; n--) {
330 if (*p)
331 dev_kfree_skb(*p);
332 p++;
333 }
334 }
335
336 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
337 {
338 struct pci_dev *pdev = dpriv->pci_priv->pdev;
339
340 pci_free_consistent(pdev, TX_RING_SIZE*sizeof(struct TxFD),
341 dpriv->tx_fd, dpriv->tx_fd_dma);
342 pci_free_consistent(pdev, RX_RING_SIZE*sizeof(struct RxFD),
343 dpriv->rx_fd, dpriv->rx_fd_dma);
344 dscc4_release_ring_skbuff(dpriv->tx_skbuff, TX_RING_SIZE);
345 dscc4_release_ring_skbuff(dpriv->rx_skbuff, RX_RING_SIZE);
346 }
347
348 void inline try_get_rx_skb(struct dscc4_dev_priv *priv, int cur, struct net_device *dev)
349 {
350 struct sk_buff *skb;
351
352 skb = dev_alloc_skb(RX_MAX(HDLC_MAX_MRU+2));
353 priv->rx_skbuff[cur] = skb;
354 if (!skb) {
355 priv->rx_fd[cur--].data = (u32) NULL;
356 priv->rx_fd[cur%RX_RING_SIZE].state1 |= Hold;
357 priv->rx_needs_refill++;
358 return;
359 }
360 skb->dev = dev;
361 skb->protocol = htons(ETH_P_IP);
362 skb->mac.raw = skb->data;
363 priv->rx_fd[cur].data = pci_map_single(priv->pci_priv->pdev, skb->data,
364 skb->len, PCI_DMA_FROMDEVICE);
365 }
366
367 /*
368 * IRQ/thread/whatever safe
369 */
370 static int dscc4_wait_ack_cec(u32 ioaddr, struct net_device *dev, char *msg)
371 {
372 s16 i = 0;
373
374 while (readl(ioaddr + STAR) & SccBusy) {
375 if (i++ < 0) {
376 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
377 return -1;
378 }
379 }
380 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name, msg, i);
381 return 0;
382 }
383
384 static int dscc4_do_action(struct net_device *dev, char *msg)
385 {
386 unsigned long ioaddr = dev->base_addr;
387 u32 state;
388 s16 i;
389
390 writel(Action, ioaddr + GCMDR);
391 ioaddr += GSTAR;
392 for (i = 0; i >= 0; i++) {
393 state = readl(ioaddr);
394 if (state & Arf) {
395 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
396 writel(Arf, ioaddr);
397 return -1;
398 } else if (state & ArAck) {
399 printk(KERN_DEBUG "%s: %s ack (%d try)\n",
400 dev->name, msg, i);
401 writel(ArAck, ioaddr);
402 return 0;
403 }
404 }
405 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
406 return -1;
407 }
408
409 static __inline__ int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
410 {
411 int cur;
412 s16 i;
413
414 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
415 for (i = 0; i >= 0; i++) {
416 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
417 (dpriv->iqtx[cur] & Xpr))
418 return 0;
419 }
420 printk(KERN_ERR "%s: %s timeout\n", "dscc4", "XPR");
421 return -1;
422 }
423
424 static __inline__ void dscc4_rx_skb(struct dscc4_dev_priv *dpriv, int cur,
425 struct RxFD *rx_fd, struct net_device *dev)
426 {
427 struct pci_dev *pdev = dpriv->pci_priv->pdev;
428 struct sk_buff *skb;
429 int pkt_len;
430
431 skb = dpriv->rx_skbuff[cur];
432 pkt_len = TO_SIZE(rx_fd->state2) - 1;
433 pci_dma_sync_single(pdev, rx_fd->data, pkt_len + 1, PCI_DMA_FROMDEVICE);
434 if((skb->data[pkt_len] & FrameOk) == FrameOk) {
435 pci_unmap_single(pdev, rx_fd->data, skb->len, PCI_DMA_FROMDEVICE);
436 dpriv->stats.rx_packets++;
437 dpriv->stats.rx_bytes += pkt_len;
438 skb->tail += pkt_len;
439 skb->len = pkt_len;
440 if (netif_running(hdlc_to_dev(&dpriv->hdlc)))
441 hdlc_netif_rx(&dpriv->hdlc, skb);
442 else
443 netif_rx(skb);
444 try_get_rx_skb(dpriv, cur, dev);
445 } else {
446 if(skb->data[pkt_len] & FrameRdo)
447 dpriv->stats.rx_fifo_errors++;
448 else if(!(skb->data[pkt_len] | ~FrameCrc))
449 dpriv->stats.rx_crc_errors++;
450 else if(!(skb->data[pkt_len] | ~FrameVfr))
451 dpriv->stats.rx_length_errors++;
452 else
453 dpriv->stats.rx_errors++;
454 }
455 rx_fd->state1 |= Hold;
456 rx_fd->state2 = 0x00000000;
457 rx_fd->end = 0xbabeface;
458 if (!rx_fd->data)
459 return;
460 rx_fd--;
461 if (!cur)
462 rx_fd += RX_RING_SIZE;
463 rx_fd->state1 &= ~Hold;
464 }
465
466 static int __init dscc4_init_one (struct pci_dev *pdev,
467 const struct pci_device_id *ent)
468 {
469 struct dscc4_pci_priv *priv;
470 struct dscc4_dev_priv *dpriv;
471 int i;
472 static int cards_found = 0;
473 unsigned long ioaddr;
474
475 printk(KERN_DEBUG "%s", version);
476
477 if (pci_enable_device(pdev))
478 goto err_out;
479 if (!request_mem_region(pci_resource_start(pdev, 0),
480 pci_resource_len(pdev, 0), "registers")) {
481 printk (KERN_ERR "dscc4: can't reserve MMIO region (regs)\n");
482 goto err_out;
483 }
484 if (!request_mem_region(pci_resource_start(pdev, 1),
485 pci_resource_len(pdev, 1), "LBI interface")) {
486 printk (KERN_ERR "dscc4: can't reserve MMIO region (lbi)\n");
487 goto err_out_free_mmio_region0;
488 }
489 ioaddr = (unsigned long)ioremap(pci_resource_start(pdev, 0),
490 pci_resource_len(pdev, 0));
491 if (!ioaddr) {
492 printk(KERN_ERR "dscc4: cannot remap MMIO region %lx @ %lx\n",
493 pci_resource_len(pdev, 0), pci_resource_start(pdev, 0));
494 goto err_out_free_mmio_region;
495 }
496 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#lx (regs), %#lx (lbi), IRQ %d.\n",
497 pci_resource_start(pdev, 0),
498 pci_resource_start(pdev, 1), pdev->irq);
499
500 /* High PCI latency useless. Cf app. note. */
501 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x10);
502 pci_set_master(pdev);
503
504 if (dscc4_found1(pdev, ioaddr))
505 goto err_out_iounmap;
506
507 priv = (struct dscc4_pci_priv *)pci_get_drvdata(pdev);
508
509 if (request_irq(pdev->irq, &dscc4_irq, SA_SHIRQ, "dscc4", priv->root)) {
510 printk(KERN_WARNING "dscc4: IRQ %d is busy\n", pdev->irq);
511 goto err_out_iounmap;
512 }
513 priv->pdev = pdev;
514
515 /* power up/little endian/dma core controlled via hold bit */
516 writel(0x00000000, ioaddr + GMODE);
517 /* Shared interrupt queue */
518 {
519 u32 bits;
520
521 bits = (IRQ_RING_SIZE >> 5) - 1;
522 bits |= bits << 4;
523 bits |= bits << 8;
524 bits |= bits << 16;
525 writel(bits, ioaddr + IQLENR0);
526 }
527 /* Global interrupt queue */
528 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
529 priv->iqcfg = (u32 *) pci_alloc_consistent(pdev,
530 IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma);
531 if (!priv->iqcfg)
532 goto err_out_free_irq;
533 writel(priv->iqcfg_dma, ioaddr + IQCFG);
534
535 /*
536 * SCC 0-3 private rx/tx irq structures
537 * IQRX/TXi needs to be set soon. Learned it the hard way...
538 */
539 for(i = 0; i < dev_per_card; i++) {
540 dpriv = (struct dscc4_dev_priv *)(priv->root + i)->priv;
541 dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev,
542 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
543 if (!dpriv->iqtx)
544 goto err_out_free_iqtx;
545 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
546 }
547 for(i = 0; i < dev_per_card; i++) {
548 dpriv = (struct dscc4_dev_priv *)(priv->root + i)->priv;
549 dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev,
550 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
551 if (!dpriv->iqrx)
552 goto err_out_free_iqrx;
553 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
554 }
555
556 /*
557 * Cf application hint. Beware of hard-lock condition on
558 * threshold .
559 */
560 writel(0x42104000, ioaddr + FIFOCR1);
561 //writel(0x9ce69800, ioaddr + FIFOCR2);
562 writel(0xdef6d800, ioaddr + FIFOCR2);
563 //writel(0x11111111, ioaddr + FIFOCR4);
564 writel(0x18181818, ioaddr + FIFOCR4);
565 // FIXME: should depend on the chipset revision
566 writel(0x0000000e, ioaddr + FIFOCR3);
567
568 writel(0xff200001, ioaddr + GCMDR);
569
570 cards_found++;
571 return 0;
572
573 err_out_free_iqrx:
574 while (--i >= 0) {
575 dpriv = (struct dscc4_dev_priv *)(priv->root + i)->priv;
576 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
577 dpriv->iqrx, dpriv->iqrx_dma);
578 }
579 i = dev_per_card;
580 err_out_free_iqtx:
581 while (--i >= 0) {
582 dpriv = (struct dscc4_dev_priv *)(priv->root + i)->priv;
583 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
584 dpriv->iqtx, dpriv->iqtx_dma);
585 }
586 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
587 priv->iqcfg_dma);
588 err_out_free_irq:
589 free_irq(pdev->irq, priv->root);
590 err_out_iounmap:
591 iounmap ((void *)ioaddr);
592 err_out_free_mmio_region:
593 release_mem_region(pci_resource_start(pdev, 1),
594 pci_resource_len(pdev, 1));
595 err_out_free_mmio_region0:
596 release_mem_region(pci_resource_start(pdev, 0),
597 pci_resource_len(pdev, 0));
598 err_out:
599 return -ENODEV;
600 };
601
602 static int dscc4_found1(struct pci_dev *pdev, unsigned long ioaddr)
603 {
604 struct dscc4_pci_priv *ppriv;
605 struct dscc4_dev_priv *dpriv;
606 struct net_device *dev;
607 int i = 0;
608
609 dpriv = (struct dscc4_dev_priv *)
610 kmalloc(dev_per_card*sizeof(struct dscc4_dev_priv), GFP_KERNEL);
611 if (!dpriv) {
612 printk(KERN_ERR "dscc4: can't allocate data\n");
613 goto err_out;
614 }
615 memset(dpriv, 0, dev_per_card*sizeof(struct dscc4_dev_priv));
616
617 dev = (struct net_device *)
618 kmalloc(dev_per_card*sizeof(struct net_device), GFP_KERNEL);
619 if (!dev) {
620 printk(KERN_ERR "dscc4: can't allocate net_device\n");
621 goto err_dealloc_priv;
622 }
623 memset(dev, 0, dev_per_card*sizeof(struct net_device));
624
625 ppriv = (struct dscc4_pci_priv *)
626 kmalloc(sizeof(struct dscc4_pci_priv), GFP_KERNEL);
627 if (!ppriv) {
628 printk(KERN_ERR "dscc4: can't allocate pci private data.\n");
629 goto err_dealloc_dev;
630 }
631 memset(ppriv, 0, sizeof(struct dscc4_pci_priv));
632
633 for (i = 0; i < dev_per_card; i++) {
634 struct dscc4_dev_priv *p;
635 struct net_device *d;
636
637 d = dev + i;
638 d->base_addr = ioaddr;
639 d->init = NULL;
640 d->irq = pdev->irq;
641 /* The card adds the crc */
642 d->type = ARPHRD_RAWHDLC;
643 d->open = dscc4_open;
644 d->stop = dscc4_close;
645 d->hard_start_xmit = dscc4_start_xmit;
646 d->set_multicast_list = NULL;
647 d->do_ioctl = dscc4_ioctl;
648 d->get_stats = dscc4_get_stats;
649 d->change_mtu = dscc4_change_mtu;
650 d->mtu = HDLC_MAX_MTU;
651 d->flags = IFF_MULTICAST|IFF_POINTOPOINT|IFF_NOARP;
652 d->tx_timeout = dscc4_tx_timeout;
653 d->watchdog_timeo = TX_TIMEOUT;
654
655 p = dpriv + i;
656 p->dev_id = i;
657 p->pci_priv = ppriv;
658 spin_lock_init(&p->lock);
659 d->priv = p;
660
661 if (dev_alloc_name(d, "scc%d")<0) {
662 printk(KERN_ERR "dev_alloc_name failed for scc.\n");
663 goto err_dealloc_dev;
664 }
665 if (register_netdev(d)) {
666 printk(KERN_ERR "%s: register_netdev != 0.\n", d->name);
667 goto err_dealloc_dev;
668 }
669 dscc4_attach_hdlc_device(d);
670 SET_MODULE_OWNER(d);
671 }
672 ppriv->root = dev;
673 ppriv->pdev = pdev;
674 spin_lock_init(&ppriv->lock);
675 pdev->driver_data = ppriv;
676 pci_set_drvdata(pdev, ppriv);
677 return 0;
678
679 err_dealloc_dev:
680 while (--i >= 0)
681 unregister_netdev(dev + i);
682 kfree(dev);
683 err_dealloc_priv:
684 kfree(dpriv);
685 err_out:
686 return -1;
687 };
688
689 static void dscc4_timer(unsigned long data)
690 {
691 struct net_device *dev = (struct net_device *)data;
692 struct dscc4_dev_priv *dpriv;
693 struct dscc4_pci_priv *ppriv;
694
695 dpriv = dev->priv;
696 if (netif_queue_stopped(dev) &&
697 ((jiffies - dev->trans_start) > TX_TIMEOUT)) {
698 ppriv = dpriv->pci_priv;
699 if (dpriv->iqtx[dpriv->iqtx_current%IRQ_RING_SIZE]) {
700 u32 flags;
701
702 printk(KERN_DEBUG "%s: pending events\n", dev->name);
703 dev->trans_start = jiffies;
704 spin_lock_irqsave(&ppriv->lock, flags);
705 dscc4_tx_irq(ppriv, dev);
706 spin_unlock_irqrestore(&ppriv->lock, flags);
707 } else {
708 struct TxFD *tx_fd;
709 struct sk_buff *skb;
710 int i,j;
711
712 printk(KERN_DEBUG "%s: missing events\n", dev->name);
713 i = dpriv->tx_dirty%TX_RING_SIZE;
714 j = dpriv->tx_current - dpriv->tx_dirty;
715 dpriv->stats.tx_dropped += j;
716 while(j--) {
717 skb = dpriv->tx_skbuff[i];
718 tx_fd = dpriv->tx_fd + i;
719 if (skb) {
720 dpriv->tx_skbuff[i] = NULL;
721 pci_unmap_single(ppriv->pdev, tx_fd->data, skb->len,
722 PCI_DMA_TODEVICE);
723 dev_kfree_skb_irq(skb);
724 } else
725 printk(KERN_INFO "%s: hardware on drugs!\n", dev->name);
726 tx_fd->data = 0; /* DEBUG */
727 tx_fd->complete &= ~DataComplete;
728 i++;
729 i %= TX_RING_SIZE;
730 }
731 dpriv->tx_dirty = dpriv->tx_current;
732 dev->trans_start = jiffies;
733 netif_wake_queue(dev);
734 printk(KERN_DEBUG "%s: re-enabled\n", dev->name);
735 }
736 }
737 dpriv->timer.expires = jiffies + TX_TIMEOUT;
738 add_timer(&dpriv->timer);
739 }
740
741 static void dscc4_tx_timeout(struct net_device *dev)
742 {
743 /* FIXME: something is missing there */
744 };
745
746 static int dscc4_open(struct net_device *dev)
747 {
748 struct dscc4_dev_priv *dpriv = (struct dscc4_dev_priv *)dev->priv;
749 struct dscc4_pci_priv *ppriv;
750 u32 ioaddr = 0;
751
752 MOD_INC_USE_COUNT;
753
754 ppriv = dpriv->pci_priv;
755
756 if (dscc4_init_ring(dev))
757 goto err_out;
758
759 ioaddr = dev->base_addr + SCC_REG_START(dpriv->dev_id);
760
761 /* FIXME: VIS */
762 writel(readl(ioaddr + CCR0) | 0x80001000, ioaddr + CCR0);
763
764 writel(LengthCheck | (HDLC_MAX_MRU >> 5), ioaddr + RLCR);
765
766 /* no address recognition/crc-CCITT/cts enabled */
767 writel(readl(ioaddr + CCR1) | 0x021c8000, ioaddr + CCR1);
768
769 /* Ccr2.Rac = 0 */
770 writel(0x00050008 & ~RxActivate, ioaddr + CCR2);
771
772 #ifdef EXPERIMENTAL_POLLING
773 writel(0xfffeef7f, ioaddr + IMR); /* Interrupt mask */
774 #else
775 /* Don't mask RDO. Ever. */
776 //writel(0xfffaef7f, ioaddr + IMR); /* Interrupt mask */
777 writel(0xfffaef7e, ioaddr + IMR); /* Interrupt mask */
778 #endif
779 /* IDT+IDR during XPR */
780 dpriv->flags = NeedIDR | NeedIDT;
781
782 /*
783 * The following is a bit paranoid...
784 *
785 * NB: the datasheet "...CEC will stay active if the SCC is in
786 * power-down mode or..." and CCR2.RAC = 1 are two different
787 * situations.
788 */
789 if (readl(ioaddr + STAR) & SccBusy) {
790 printk(KERN_ERR "%s busy. Try later\n", dev->name);
791 goto err_free_ring;
792 }
793 writel(TxSccRes | RxSccRes, ioaddr + CMDR);
794
795 /* ... the following isn't */
796 if (dscc4_wait_ack_cec(ioaddr, dev, "Cec"))
797 goto err_free_ring;
798
799 /*
800 * I would expect XPR near CE completion (before ? after ?).
801 * At worst, this code won't see a late XPR and people
802 * will have to re-issue an ifconfig (this is harmless).
803 * WARNING, a really missing XPR usually means a hardware
804 * reset is needed. Suggestions anyone ?
805 */
806 if (dscc4_xpr_ack(dpriv))
807 goto err_free_ring;
808
809 netif_start_queue(dev);
810
811 init_timer(&dpriv->timer);
812 dpriv->timer.expires = jiffies + 10*HZ;
813 dpriv->timer.data = (unsigned long)dev;
814 dpriv->timer.function = &dscc4_timer;
815 add_timer(&dpriv->timer);
816 netif_carrier_on(dev);
817
818 return 0;
819
820 err_free_ring:
821 dscc4_release_ring(dpriv);
822 err_out:
823 MOD_DEC_USE_COUNT;
824 return -EAGAIN;
825 }
826
827 #ifdef EXPERIMENTAL_POLLING
828 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
829 {
830 /* FIXME: it's gonna be easy (TM), for sure */
831 }
832 #endif /* EXPERIMENTAL_POLLING */
833
834 static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
835 {
836 struct dscc4_dev_priv *dpriv = dev->priv;
837 struct dscc4_pci_priv *ppriv;
838 struct TxFD *tx_fd;
839 int cur, next;
840
841 ppriv = dpriv->pci_priv;
842 cur = dpriv->tx_current++%TX_RING_SIZE;
843 next = dpriv->tx_current%TX_RING_SIZE;
844 dpriv->tx_skbuff[next] = skb;
845 tx_fd = dpriv->tx_fd + next;
846 tx_fd->state = FrameEnd | Hold | TO_STATE(skb->len & TxSizeMax);
847 tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
848 PCI_DMA_TODEVICE);
849 tx_fd->complete = 0x00000000;
850 mb(); // FIXME: suppress ?
851
852 #ifdef EXPERIMENTAL_POLLING
853 spin_lock(&dpriv->lock);
854 while(dscc4_tx_poll(dpriv, dev));
855 spin_unlock(&dpriv->lock);
856 #endif
857 /*
858 * I know there's a window for a race in the following lines but
859 * dscc4_timer will take good care of it. The chipset eats events
860 * (especially the net_dev re-enabling ones) thus there is no
861 * reason to try and be smart.
862 */
863 if ((dpriv->tx_dirty + 16) < dpriv->tx_current) {
864 netif_stop_queue(dev);
865 dpriv->hi_expected = 2;
866 }
867 tx_fd = dpriv->tx_fd + cur;
868 tx_fd->state &= ~Hold;
869 mb(); // FIXME: suppress ?
870
871 /*
872 * One may avoid some pci transactions during intense TX periods.
873 * Not sure it's worth the pain...
874 */
875 writel((TxPollCmd << dpriv->dev_id) | NoAck, dev->base_addr + GCMDR);
876 dev->trans_start = jiffies;
877 return 0;
878 }
879
880 static int dscc4_close(struct net_device *dev)
881 {
882 struct dscc4_dev_priv *dpriv = (struct dscc4_dev_priv *)dev->priv;
883 u32 ioaddr = dev->base_addr;
884 int dev_id;
885
886 del_timer_sync(&dpriv->timer);
887 netif_stop_queue(dev);
888
889 dev_id = dpriv->dev_id;
890
891 writel(0x00050000, ioaddr + SCC_REG_START(dev_id) + CCR2);
892 writel(MTFi|Rdr|Rdt, ioaddr + CH0CFG + dev_id*0x0c); /* Reset Rx/Tx */
893 writel(0x00000001, ioaddr + GCMDR);
894
895 dscc4_release_ring(dpriv);
896
897 MOD_DEC_USE_COUNT;
898 return 0;
899 }
900
901 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
902 {
903 struct dscc4_dev_priv *dpriv = (struct dscc4_dev_priv *)dev->priv;
904 u32 brr;
905
906 *state &= ~Ccr0ClockMask;
907 if (*bps) { /* DCE */
908 u32 n = 0, m = 0, divider;
909 int xtal;
910
911 xtal = dpriv->pci_priv->xtal_hz;
912 if (!xtal)
913 return -1;
914 divider = xtal / *bps;
915 if (divider > BRR_DIVIDER_MAX) {
916 divider >>= 4;
917 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
918 } else
919 *state |= 0x00000037; /* Clock mode 7b (BRG) */
920 if (divider >> 22) {
921 n = 63;
922 m = 15;
923 } else if (divider) {
924 /* Extraction of the 6 highest weighted bits */
925 m = 0;
926 while (0xffffffc0 & divider) {
927 m++;
928 divider >>= 1;
929 }
930 n = divider;
931 }
932 brr = (m << 8) | n;
933 divider = n << m;
934 if (!(*state & 0x00000001)) /* Clock mode 6b */
935 divider <<= 4;
936 *bps = xtal / divider;
937 } else { /* DTE */
938 /*
939 * "state" already reflects Clock mode 0a.
940 * Nothing more to be done
941 */
942 brr = 0;
943 }
944 writel(brr, dev->base_addr + BRR + SCC_REG_START(dpriv->dev_id));
945
946 return 0;
947 }
948
949 #ifdef LATER_PLEASE
950 /*
951 * -*- [RFC] Configuring Synchronous Interfaces in Linux -*-
952 */
953
954 // FIXME: MEDIA already defined in linux/hdlc.h
955 #define HDLC_MEDIA_V35 0
956 #define HDLC_MEDIA_RS232 1
957 #define HDLC_MEDIA_X21 2
958 #define HDLC_MEDIA_E1 3
959 #define HDLC_MEDIA_HSSI 4
960
961 #define HDLC_CODING_NRZ 0
962 #define HDLC_CODING_NRZI 1
963 #define HDLC_CODING_FM0 2
964 #define HDLC_CODING_FM1 3
965 #define HDLC_CODING_MANCHESTER 4
966
967 #define HDLC_CRC_NONE 0
968 #define HDLC_CRC_16 1
969 #define HDLC_CRC_32 2
970 #define HDLC_CRC_CCITT 3
971
972 /* RFC: add the crc reset value ? */
973 struct hdlc_physical {
974 u8 media;
975 u8 coding;
976 u32 rate;
977 u8 crc;
978 u8 crc_siz; /* 2 or 4 bytes */
979 u8 shared_flags; /* Discouraged on the DSCC4 */
980 };
981
982 // FIXME: PROTO already defined in linux/hdlc.h
983 #define HDLC_PROTO_RAW 0
984 #define HDLC_PROTO_FR 1
985 #define HDLC_PROTO_X25 2
986 #define HDLC_PROTO_PPP 3
987 #define HDLC_PROTO_CHDLC 4
988
989 struct hdlc_protocol {
990 u8 proto;
991
992 union {
993 } u;
994 };
995
996 struct screq {
997 u16 media_group;
998
999 union {
1000 struct hdlc_physical hdlc_phy;
1001 struct hdlc_protocol hdlc_proto;
1002 } u;
1003 };
1004
1005 // FIXME: go sub-module
1006 static struct {
1007 u16 coding;
1008 u16 bits;
1009 } map[] = {
1010 {HDLC_CODING_NRZ, 0x00},
1011 {HDLC_CODING_NRZI, 0x20},
1012 {HDLC_CODING_FM0, 0x40},
1013 {HDLC_CODING_FM1, 0x50},
1014 {HDLC_CODING_MANCHESTER, 0x60},
1015 {65535, 0x00}
1016 };
1017 #endif /* LATER_PLEASE */
1018
1019 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1020 {
1021 struct dscc4_dev_priv *dpriv = dev->priv;
1022 u32 state, ioaddr;
1023
1024 if (dev->flags & IFF_UP)
1025 return -EBUSY;
1026
1027 switch (cmd) {
1028 /* Set built-in quartz frequency */
1029 case SIOCDEVPRIVATE: {
1030 u32 hz;
1031
1032 hz = ifr->ifr_ifru.ifru_ivalue;
1033 if (hz >= 33000000) /* 33 MHz */
1034 return -EOPNOTSUPP;
1035 dpriv->pci_priv->xtal_hz = hz;
1036 return 0;
1037 }
1038 /* Set/unset loopback */
1039 case SIOCDEVPRIVATE+1: {
1040 u32 flags;
1041
1042 ioaddr = dev->base_addr + CCR1 +
1043 SCC_REG_START(dpriv->dev_id);
1044 state = readl(ioaddr);
1045 flags = ifr->ifr_ifru.ifru_ivalue;
1046 if (flags & 0x00000001) {
1047 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1048 state |= 0x00000100;
1049 } else {
1050 printk(KERN_DEBUG "%s: normal\n", dev->name);
1051 state &= ~0x00000100;
1052 }
1053 writel(state, ioaddr);
1054 return 0;
1055 }
1056
1057 #ifdef LATER_PLEASE
1058 case SIOCDEVPRIVATE+2: {
1059 {
1060 struct screq scr;
1061
1062 err = copy_from_user(&scr, ifr->ifr_ifru.ifru_data, sizeof(struct screq));
1063 if (err)
1064 return err;
1065 do {
1066 if (scr.u.hdlc_phy.coding == map[i].coding)
1067 break;
1068 } while (map[++i].coding != 65535);
1069 if (!map[i].coding)
1070 return -EOPNOTSUPP;
1071
1072 ioaddr = dev->base_addr + CCR0 +
1073 SCC_REG_START(dpriv->dev_id);
1074 state = readl(ioaddr) & ~EncodingMask;
1075 state |= (u32)map[i].bits << 16;
1076 writel(state, ioaddr);
1077 printk("state: %08x\n", state); /* DEBUG */
1078 return 0;
1079 }
1080 case SIOCDEVPRIVATE+3: {
1081 struct screq *scr = (struct screq *)ifr->ifr_ifru.ifru_data;
1082
1083 ioaddr = dev->base_addr + CCR0 +
1084 SCC_REG_START(dpriv->dev_id);
1085 state = (readl(ioaddr) & EncodingMask) >> 16;
1086 do {
1087 if (state == map[i].bits)
1088 break;
1089 } while (map[++i].coding);
1090 return put_user(map[i].coding, (u16 *)scr->u.hdlc_phy.coding);
1091 }
1092 #endif /* LATER_PLEASE */
1093
1094 case HDLCSCLOCKRATE:
1095 {
1096 u32 state, bps;
1097
1098 bps = ifr->ifr_ifru.ifru_ivalue;
1099 ioaddr = dev->base_addr + CCR0 +
1100 SCC_REG_START(dpriv->dev_id);
1101 state = readl(ioaddr);
1102 if(dscc4_set_clock(dev, &bps, &state) < 0)
1103 return -EOPNOTSUPP;
1104 if (bps) { /* DCE */
1105 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n",
1106 dev->name);
1107 ifr->ifr_ifru.ifru_ivalue = bps;
1108 } else { /* DTE */
1109 state = 0x80001000;
1110 printk(KERN_DEBUG "%s: external RxClk (DTE)\n",
1111 dev->name);
1112 }
1113 writel(state, ioaddr);
1114 return 0;
1115 }
1116 case HDLCGCLOCKRATE: {
1117 u32 brr;
1118 int bps;
1119
1120 brr = readl(dev->base_addr + BRR +
1121 SCC_REG_START(dpriv->dev_id));
1122 bps = dpriv->pci_priv->xtal_hz >> (brr >> 8);
1123 bps /= (brr & 0x3f) + 1;
1124 ifr->ifr_ifru.ifru_ivalue = bps;
1125 return 0;
1126 }
1127
1128 default:
1129 return -EOPNOTSUPP;
1130 }
1131 }
1132
1133 static int dscc4_change_mtu(struct net_device *dev, int mtu)
1134 {
1135 /* FIXME: chainsaw coded... */
1136 if ((mtu <= 3) || (mtu > 65531))
1137 return -EINVAL;
1138 if(dev->flags & IFF_UP)
1139 return -EBUSY;
1140 dev->mtu = mtu;
1141 return(0);
1142 }
1143
1144 static void dscc4_irq(int irq, void *dev_instance, struct pt_regs *ptregs)
1145 {
1146 struct net_device *dev = dev_instance;
1147 struct dscc4_pci_priv *priv;
1148 u32 ioaddr, state;
1149 unsigned long flags;
1150 int i;
1151
1152 priv = ((struct dscc4_dev_priv *)dev->priv)->pci_priv;
1153 /*
1154 * FIXME: shorten the protected area (set some bit telling we're
1155 * in an interrupt or increment some work-to-do counter etc...)
1156 */
1157 spin_lock_irqsave(&priv->lock, flags);
1158
1159 ioaddr = dev->base_addr;
1160
1161 state = readl(ioaddr + GSTAR);
1162 if (!state)
1163 goto out;
1164 writel(state, ioaddr + GSTAR);
1165
1166 if (state & Arf) {
1167 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1168 dev->name);
1169 goto out;
1170 }
1171 state &= ~ArAck;
1172 if (state & Cfg) {
1173 if (debug)
1174 printk(KERN_DEBUG "CfgIV\n");
1175 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
1176 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1177 if (!(state &= ~Cfg))
1178 goto out;
1179 }
1180 if (state & RxEvt) {
1181 i = dev_per_card - 1;
1182 do {
1183 dscc4_rx_irq(priv, dev + i);
1184 } while (--i >= 0);
1185 state &= ~RxEvt;
1186 }
1187 if (state & TxEvt) {
1188 i = dev_per_card - 1;
1189 do {
1190 dscc4_tx_irq(priv, dev + i);
1191 } while (--i >= 0);
1192 state &= ~TxEvt;
1193 }
1194 out:
1195 spin_unlock_irqrestore(&priv->lock, flags);
1196 }
1197
1198 static __inline__ void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1199 struct net_device *dev)
1200 {
1201 struct dscc4_dev_priv *dpriv = dev->priv;
1202 u32 state;
1203 int cur, loop = 0;
1204
1205 try:
1206 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1207 state = dpriv->iqtx[cur];
1208 if (!state) {
1209 #ifdef DEBUG
1210 if (loop > 1)
1211 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1212 #endif
1213 if (loop && netif_queue_stopped(dev))
1214 if ((dpriv->tx_dirty + 8) >= dpriv->tx_current)
1215 netif_wake_queue(dev);
1216 return;
1217 }
1218 loop++;
1219 dpriv->iqtx[cur] = 0;
1220 dpriv->iqtx_current++;
1221
1222 #ifdef DEBUG_PARANOID
1223 if (SOURCE_ID(state) != dpriv->dev_id) {
1224 printk(KERN_DEBUG "%s (Tx): Source Id=%d, state=%08x\n",
1225 dev->name, SOURCE_ID(state), state );
1226 return;
1227 }
1228 if (state & 0x0df80c00) {
1229 printk(KERN_DEBUG "%s (Tx): state=%08x (UFO alert)\n",
1230 dev->name, state);
1231 return;
1232 }
1233 #endif
1234 // state &= 0x0fffffff; /* Tracking the analyzed bits */
1235 if (state & SccEvt) {
1236 if (state & Alls) {
1237 struct TxFD *tx_fd;
1238 struct sk_buff *skb;
1239
1240 cur = dpriv->tx_dirty%TX_RING_SIZE;
1241 tx_fd = dpriv->tx_fd + cur;
1242
1243 skb = dpriv->tx_skbuff[cur];
1244
1245 /* XXX: hideous kludge - to be removed "later" */
1246 if (!skb) {
1247 printk(KERN_ERR "%s: NULL skb in tx_irq at index %d\n", dev->name, cur);
1248 goto try;
1249 }
1250 dpriv->tx_dirty++; // MUST be after skb test
1251
1252 /* Happens sometime. Don't know what triggers it */
1253 if (!(tx_fd->complete & DataComplete)) {
1254 u32 ioaddr, isr;
1255
1256 ioaddr = dev->base_addr +
1257 SCC_REG_START(dpriv->dev_id) + ISR;
1258 isr = readl(ioaddr);
1259 printk(KERN_DEBUG
1260 "%s: DataComplete=0 cur=%d isr=%08x state=%08x\n",
1261 dev->name, cur, isr, state);
1262 writel(isr, ioaddr);
1263 dpriv->stats.tx_dropped++;
1264 } else {
1265 tx_fd->complete &= ~DataComplete;
1266 if (tx_fd->state & FrameEnd) {
1267 dpriv->stats.tx_packets++;
1268 dpriv->stats.tx_bytes += skb->len;
1269 }
1270 }
1271
1272 dpriv->tx_skbuff[cur] = NULL;
1273 pci_unmap_single(ppriv->pdev, tx_fd->data, skb->len,
1274 PCI_DMA_TODEVICE);
1275 tx_fd->data = 0; /* DEBUG */
1276 dev_kfree_skb_irq(skb);
1277 { // DEBUG
1278 cur = (dpriv->tx_dirty-1)%TX_RING_SIZE;
1279 tx_fd = dpriv->tx_fd + cur;
1280 tx_fd->state |= Hold;
1281 }
1282 if (!(state &= ~Alls))
1283 goto try;
1284 }
1285 /*
1286 * Transmit Data Underrun
1287 */
1288 if (state & Xdu) {
1289 printk(KERN_ERR "dscc4: XDU. Contact maintainer\n");
1290 dpriv->flags = NeedIDT;
1291 /* Tx reset */
1292 writel(MTFi | Rdt,
1293 dev->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1294 writel(0x00000001, dev->base_addr + GCMDR);
1295 return;
1296 }
1297 if (state & Xmr) {
1298 /* Frame needs to be sent again - FIXME */
1299 //dscc4_start_xmit(dpriv->tx_skbuff[dpriv->tx_dirty], dev);
1300 if (!(state &= ~0x00002000)) /* DEBUG */
1301 goto try;
1302 }
1303 if (state & Xpr) {
1304 unsigned long ioaddr = dev->base_addr;
1305 unsigned long scc_offset;
1306 u32 scc_addr;
1307
1308 scc_offset = ioaddr + SCC_REG_START(dpriv->dev_id);
1309 scc_addr = ioaddr + 0x0c*dpriv->dev_id;
1310 if (readl(scc_offset + STAR) & SccBusy)
1311 printk(KERN_DEBUG "%s busy. Fatal\n",
1312 dev->name);
1313 /*
1314 * Keep this order: IDT before IDR
1315 */
1316 if (dpriv->flags & NeedIDT) {
1317 writel(MTFi | Idt, scc_addr + CH0CFG);
1318 writel(dpriv->tx_fd_dma +
1319 (dpriv->tx_dirty%TX_RING_SIZE)*
1320 sizeof(struct TxFD), scc_addr + CH0BTDA);
1321 if(dscc4_do_action(dev, "IDT"))
1322 goto err_xpr;
1323 dpriv->flags &= ~NeedIDT;
1324 mb();
1325 }
1326 if (dpriv->flags & NeedIDR) {
1327 writel(MTFi | Idr, scc_addr + CH0CFG);
1328 writel(dpriv->rx_fd_dma +
1329 (dpriv->rx_current%RX_RING_SIZE)*
1330 sizeof(struct RxFD), scc_addr + CH0BRDA);
1331 if(dscc4_do_action(dev, "IDR"))
1332 goto err_xpr;
1333 dpriv->flags &= ~NeedIDR;
1334 mb();
1335 /* Activate receiver and misc */
1336 writel(0x08050008, scc_offset + CCR2);
1337 }
1338 err_xpr:
1339 if (!(state &= ~Xpr))
1340 goto try;
1341 }
1342 } else { /* ! SccEvt */
1343 if (state & Hi) {
1344 #ifdef EXPERIMENTAL_POLLING
1345 while(!dscc4_tx_poll(dpriv, dev));
1346 #endif
1347 state &= ~Hi;
1348 }
1349 /*
1350 * FIXME: it may be avoided. Re-re-re-read the manual.
1351 */
1352 if (state & Err) {
1353 printk(KERN_ERR "%s: Tx ERR\n", dev->name);
1354 dpriv->stats.tx_errors++;
1355 state &= ~Err;
1356 }
1357 }
1358 goto try;
1359 }
1360
1361 static __inline__ void dscc4_rx_irq(struct dscc4_pci_priv *priv, struct net_device *dev)
1362 {
1363 struct dscc4_dev_priv *dpriv = dev->priv;
1364 u32 state;
1365 int cur;
1366
1367 try:
1368 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1369 state = dpriv->iqrx[cur];
1370 if (!state)
1371 return;
1372 dpriv->iqrx[cur] = 0;
1373 dpriv->iqrx_current++;
1374
1375 #ifdef DEBUG_PARANOID
1376 if (SOURCE_ID(state) != dpriv->dev_id) {
1377 printk(KERN_DEBUG "%s (Rx): Source Id=%d, state=%08x\n",
1378 dev->name, SOURCE_ID(state), state);
1379 goto try;
1380 }
1381 if (state & 0x0df80c00) {
1382 printk(KERN_DEBUG "%s (Rx): state=%08x (UFO alert)\n",
1383 dev->name, state);
1384 goto try;
1385 }
1386 #endif
1387 if (!(state & SccEvt)){
1388 struct RxFD *rx_fd;
1389
1390 state &= 0x00ffffff;
1391 if (state & Err) { /* Hold or reset */
1392 printk(KERN_DEBUG "%s (Rx): ERR\n", dev->name);
1393 cur = dpriv->rx_current;
1394 rx_fd = dpriv->rx_fd + cur;
1395 /*
1396 * Presume we're not facing a DMAC receiver reset.
1397 * As We use the rx size-filtering feature of the
1398 * DSCC4, the beginning of a new frame is waiting in
1399 * the rx fifo. I bet a Receive Data Overflow will
1400 * happen most of time but let's try and avoid it.
1401 * Btw (as for RDO) if one experiences ERR whereas
1402 * the system looks rather idle, there may be a
1403 * problem with latency. In this case, increasing
1404 * RX_RING_SIZE may help.
1405 */
1406 while (dpriv->rx_needs_refill) {
1407 while(!(rx_fd->state1 & Hold)) {
1408 rx_fd++;
1409 cur++;
1410 if (!(cur = cur%RX_RING_SIZE))
1411 rx_fd = dpriv->rx_fd;
1412 }
1413 dpriv->rx_needs_refill--;
1414 try_get_rx_skb(dpriv, cur, dev);
1415 if (!rx_fd->data)
1416 goto try;
1417 rx_fd->state1 &= ~Hold;
1418 rx_fd->state2 = 0x00000000;
1419 rx_fd->end = 0xbabeface;
1420 }
1421 goto try;
1422 }
1423 if (state & Fi) {
1424 cur = dpriv->rx_current%RX_RING_SIZE;
1425 rx_fd = dpriv->rx_fd + cur;
1426 dscc4_rx_skb(dpriv, cur, rx_fd, dev);
1427 dpriv->rx_current++;
1428 goto try;
1429 }
1430 if (state & Hi ) { /* HI bit */
1431 state &= ~Hi;
1432 goto try;
1433 }
1434 } else { /* ! SccEvt */
1435 #ifdef DEBUG_PARANOIA
1436 int i;
1437 static struct {
1438 u32 mask;
1439 const char *irq_name;
1440 } evts[] = {
1441 { 0x00008000, "TIN"},
1442 { 0x00004000, "CSC"},
1443 { 0x00000020, "RSC"},
1444 { 0x00000010, "PCE"},
1445 { 0x00000008, "PLLA"},
1446 { 0x00000004, "CDSC"},
1447 { 0, NULL}
1448 };
1449 #endif /* DEBUG_PARANOIA */
1450 state &= 0x00ffffff;
1451 #ifdef DEBUG_PARANOIA
1452 for (i = 0; evts[i].irq_name; i++) {
1453 if (state & evts[i].mask) {
1454 printk(KERN_DEBUG "dscc4(%s): %s\n",
1455 dev->name, evts[i].irq_name);
1456 if (!(state &= ~evts[i].mask))
1457 goto try;
1458 }
1459 }
1460 #endif /* DEBUG_PARANOIA */
1461 /*
1462 * Receive Data Overflow (FIXME: untested)
1463 */
1464 if (state & Rdo) {
1465 u32 ioaddr, scc_offset, scc_addr;
1466 struct RxFD *rx_fd;
1467 int cur;
1468
1469 //if (debug)
1470 // dscc4_rx_dump(dpriv);
1471 ioaddr = dev->base_addr;
1472 scc_addr = ioaddr + 0x0c*dpriv->dev_id;
1473 scc_offset = ioaddr + SCC_REG_START(dpriv->dev_id);
1474
1475 writel(readl(scc_offset + CCR2) & ~RxActivate,
1476 scc_offset + CCR2);
1477 /*
1478 * This has no effect. Why ?
1479 * ORed with TxSccRes, one sees the CFG ack (for
1480 * the TX part only).
1481 */
1482 writel(RxSccRes, scc_offset + CMDR);
1483 dpriv->flags |= RdoSet;
1484
1485 /*
1486 * Let's try and save something in the received data.
1487 * rx_current must be incremented at least once to
1488 * avoid HOLD in the BRDA-to-be-pointed desc.
1489 */
1490 do {
1491 cur = dpriv->rx_current++%RX_RING_SIZE;
1492 rx_fd = dpriv->rx_fd + cur;
1493 if (!(rx_fd->state2 & DataComplete))
1494 break;
1495 if (rx_fd->state2 & FrameAborted) {
1496 dpriv->stats.rx_over_errors++;
1497 rx_fd->state1 |= Hold;
1498 rx_fd->state2 = 0x00000000;
1499 rx_fd->end = 0xbabeface;
1500 } else
1501 dscc4_rx_skb(dpriv, cur, rx_fd, dev);
1502 } while (1);
1503
1504 if (debug) {
1505 if (dpriv->flags & RdoSet)
1506 printk(KERN_DEBUG
1507 "dscc4: no RDO in Rx data\n");
1508 }
1509 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1510 /*
1511 * FIXME: must the reset be this violent ?
1512 */
1513 writel(dpriv->rx_fd_dma +
1514 (dpriv->rx_current%RX_RING_SIZE)*
1515 sizeof(struct RxFD), scc_addr + CH0BRDA);
1516 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1517 if(dscc4_do_action(dev, "RDR")) {
1518 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1519 dev->name, "RDR");
1520 goto rdo_end;
1521 }
1522 writel(MTFi|Idr, scc_addr + CH0CFG);
1523 if(dscc4_do_action(dev, "IDR")) {
1524 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1525 dev->name, "IDR");
1526 goto rdo_end;
1527 }
1528 rdo_end:
1529 #endif
1530 writel(readl(scc_offset + CCR2) | RxActivate,
1531 scc_offset + CCR2);
1532 goto try;
1533 }
1534 /* These will be used later */
1535 if (state & Rfs) {
1536 if (!(state &= ~Rfs))
1537 goto try;
1538 }
1539 if (state & Rfo) {
1540 if (!(state &= ~Rfo))
1541 goto try;
1542 }
1543 if (state & Flex) {
1544 if (!(state &= ~Flex))
1545 goto try;
1546 }
1547 }
1548 }
1549
1550 static int dscc4_init_ring(struct net_device *dev)
1551 {
1552 struct dscc4_dev_priv *dpriv = (struct dscc4_dev_priv *)dev->priv;
1553 struct TxFD *tx_fd;
1554 struct RxFD *rx_fd;
1555 int i;
1556
1557 tx_fd = (struct TxFD *) pci_alloc_consistent(dpriv->pci_priv->pdev,
1558 TX_RING_SIZE*sizeof(struct TxFD), &dpriv->tx_fd_dma);
1559 if (!tx_fd)
1560 goto err_out;
1561 rx_fd = (struct RxFD *) pci_alloc_consistent(dpriv->pci_priv->pdev,
1562 RX_RING_SIZE*sizeof(struct RxFD), &dpriv->rx_fd_dma);
1563 if (!rx_fd)
1564 goto err_free_dma_tx;
1565
1566 dpriv->tx_fd = tx_fd;
1567 dpriv->rx_fd = rx_fd;
1568 dpriv->rx_current = 0;
1569 dpriv->tx_current = 0;
1570 dpriv->tx_dirty = 0;
1571
1572 /* the dma core of the dscc4 will be locked on the first desc */
1573 for(i = 0; i < TX_RING_SIZE; ) {
1574 reset_TxFD(tx_fd);
1575 /* FIXME: NULL should be ok - to be tried */
1576 tx_fd->data = dpriv->tx_fd_dma;
1577 dpriv->tx_skbuff[i] = NULL;
1578 i++;
1579 tx_fd->next = (u32)(dpriv->tx_fd_dma + i*sizeof(struct TxFD));
1580 tx_fd++;
1581 }
1582 (--tx_fd)->next = (u32)dpriv->tx_fd_dma;
1583 {
1584 /*
1585 * XXX: I would expect the following to work for the first descriptor
1586 * (tx_fd->state = 0xc0000000)
1587 * - Hold=1 (don't try and branch to the next descripto);
1588 * - No=0 (I want an empty data section, i.e. size=0);
1589 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1590 * Alas, it fails (and locks solid). Thus the introduction of a dummy
1591 * skb to avoid No=0 (choose one: Ugly [ ] Tasteless [ ] VMS [ ]).
1592 * TODO: fiddle the tx threshold when time permits.
1593 */
1594 struct sk_buff *skb;
1595
1596 skb = dev_alloc_skb(32);
1597 if (!skb)
1598 goto err_free_dma_tx;
1599 skb->len = 32;
1600 memset(skb->data, 0xaa, 16);
1601 tx_fd -= (TX_RING_SIZE - 1);
1602 tx_fd->state = 0xc0000000;
1603 tx_fd->state |= ((u32)(skb->len & TxSizeMax)) << 16;
1604 tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
1605 skb->len, PCI_DMA_TODEVICE);
1606 dpriv->tx_skbuff[0] = skb;
1607 }
1608 for (i = 0; i < RX_RING_SIZE;) {
1609 /* size set by the host. Multiple of 4 bytes please */
1610 rx_fd->state1 = HiDesc; /* Hi, no Hold */
1611 rx_fd->state2 = 0x00000000;
1612 rx_fd->end = 0xbabeface;
1613 rx_fd->state1 |= ((u32)(HDLC_MAX_MRU & RxSizeMax)) << 16;
1614 try_get_rx_skb(dpriv, i, dev);
1615 i++;
1616 rx_fd->next = (u32)(dpriv->rx_fd_dma + i*sizeof(struct RxFD));
1617 rx_fd++;
1618 }
1619 (--rx_fd)->next = (u32)dpriv->rx_fd_dma;
1620 rx_fd->state1 |= 0x40000000; /* Hold */
1621
1622 return 0;
1623
1624 err_free_dma_tx:
1625 pci_free_consistent(dpriv->pci_priv->pdev, TX_RING_SIZE*sizeof(*tx_fd),
1626 tx_fd, dpriv->tx_fd_dma);
1627 err_out:
1628 return -1;
1629 }
1630
1631 static struct net_device_stats *dscc4_get_stats(struct net_device *dev)
1632 {
1633 struct dscc4_dev_priv *priv = (struct dscc4_dev_priv *)dev->priv;
1634
1635 return &priv->stats;
1636 }
1637
1638 static void __exit dscc4_remove_one(struct pci_dev *pdev)
1639 {
1640 struct dscc4_pci_priv *ppriv;
1641 struct net_device *root;
1642 int i;
1643
1644 ppriv = pci_get_drvdata(pdev);
1645 root = ppriv->root;
1646
1647 free_irq(pdev->irq, root);
1648 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1649 ppriv->iqcfg_dma);
1650 for (i=0; i < dev_per_card; i++) {
1651 struct dscc4_dev_priv *dpriv;
1652 struct net_device *dev;
1653
1654 dev = ppriv->root + i;
1655 dscc4_unattach_hdlc_device(dev);
1656
1657 dpriv = (struct dscc4_dev_priv *)dev->priv;
1658 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1659 dpriv->iqrx, dpriv->iqrx_dma);
1660 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1661 dpriv->iqtx, dpriv->iqtx_dma);
1662 unregister_netdev(dev);
1663 }
1664 kfree(root->priv);
1665
1666 iounmap((void *)root->base_addr);
1667 kfree(root);
1668
1669 kfree(ppriv);
1670
1671 release_mem_region(pci_resource_start(pdev, 1),
1672 pci_resource_len(pdev, 1));
1673 release_mem_region(pci_resource_start(pdev, 0),
1674 pci_resource_len(pdev, 0));
1675 }
1676
1677 static int dscc4_hdlc_ioctl(struct hdlc_device_struct *hdlc, struct ifreq *ifr, int cmd)
1678 {
1679 struct net_device *dev = (struct net_device *)hdlc->netdev.base_addr;
1680 int result;
1681
1682 /* FIXME: locking ? */
1683 result = dscc4_ioctl(dev, ifr, cmd);
1684 return result;
1685 }
1686
1687 static int dscc4_hdlc_open(struct hdlc_device_struct *hdlc)
1688 {
1689 struct net_device *dev = (struct net_device *)(hdlc->netdev.base_addr);
1690
1691 if (netif_running(dev)) {
1692 printk(KERN_DEBUG "%s: already running\n", dev->name); // DEBUG
1693 return 0;
1694 }
1695 return dscc4_open(dev);
1696 }
1697
1698 static int dscc4_hdlc_xmit(hdlc_device *hdlc, struct sk_buff *skb)
1699 {
1700 struct net_device *dev = (struct net_device *)hdlc->netdev.base_addr;
1701
1702 return dscc4_start_xmit(skb, dev);
1703 }
1704
1705 static void dscc4_hdlc_close(struct hdlc_device_struct *hdlc)
1706 {
1707 struct net_device *dev = (struct net_device *)hdlc->netdev.base_addr;
1708 struct dscc4_dev_priv *dpriv;
1709
1710 dpriv = dev->priv;
1711 --dpriv->usecount;
1712 }
1713
1714 /* Operated under dev lock */
1715 static int dscc4_attach_hdlc_device(struct net_device *dev)
1716 {
1717 struct dscc4_dev_priv *dpriv = dev->priv;
1718 struct hdlc_device_struct *hdlc;
1719 int result;
1720
1721 hdlc = &dpriv->hdlc;
1722 /* XXX: Don't look at the next line */
1723 hdlc->netdev.base_addr = (unsigned long)dev;
1724 hdlc->set_mode = NULL;
1725 hdlc->open = dscc4_hdlc_open;
1726 hdlc->close = dscc4_hdlc_close;
1727 hdlc->ioctl = dscc4_hdlc_ioctl;
1728 hdlc->xmit = dscc4_hdlc_xmit;
1729
1730 result = register_hdlc_device(hdlc);
1731 if (!result)
1732 dpriv->usecount++;
1733 return result;
1734 }
1735
1736 /* Operated under dev lock */
1737 static void dscc4_unattach_hdlc_device(struct net_device *dev)
1738 {
1739 struct dscc4_dev_priv *dpriv = dev->priv;
1740
1741 unregister_hdlc_device(&dpriv->hdlc);
1742 dpriv->usecount--;
1743 }
1744
1745 static struct pci_device_id dscc4_pci_tbl[] __devinitdata = {
1746 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
1747 PCI_ANY_ID, PCI_ANY_ID, },
1748 { 0,}
1749 };
1750 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
1751
1752 static struct pci_driver dscc4_driver = {
1753 name: "dscc4",
1754 id_table: dscc4_pci_tbl,
1755 probe: dscc4_init_one,
1756 remove: dscc4_remove_one,
1757 };
1758
1759 static int __init dscc4_init_module(void)
1760 {
1761 return pci_module_init(&dscc4_driver);
1762 }
1763
1764 static void __exit dscc4_cleanup_module(void)
1765 {
1766 pci_unregister_driver(&dscc4_driver);
1767 }
1768
1769 module_init(dscc4_init_module);
1770 module_exit(dscc4_cleanup_module);
1771