File: /usr/src/linux/drivers/net/wan/lmc/lmc_var.h
1 #ifndef _LMC_VAR_H_
2 #define _LMC_VAR_H_
3
4 /* $Id: lmc_var.h,v 1.17 2000/04/06 12:16:47 asj Exp $ */
5
6 /*
7 * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
8 * All rights reserved. www.lanmedia.com
9 *
10 * This code is written by:
11 * Andrew Stanley-Jones (asj@cban.com)
12 * Rob Braun (bbraun@vix.com),
13 * Michael Graff (explorer@vix.com) and
14 * Matt Thomas (matt@3am-software.com).
15 *
16 * This software may be used and distributed according to the terms
17 * of the GNU General Public License version 2, incorporated herein by reference.
18 */
19
20 #include <linux/timer.h>
21
22 #ifndef __KERNEL__
23 typedef signed char s8;
24 typedef unsigned char u8;
25
26 typedef signed short s16;
27 typedef unsigned short u16;
28
29 typedef signed int s32;
30 typedef unsigned int u32;
31
32 typedef signed long long s64;
33 typedef unsigned long long u64;
34
35 #define BITS_PER_LONG 32
36
37 #endif
38
39 /*
40 * basic definitions used in lmc include files
41 */
42
43 typedef struct lmc___softc lmc_softc_t;
44 typedef struct lmc___media lmc_media_t;
45 typedef struct lmc___ctl lmc_ctl_t;
46
47 #define lmc_csrptr_t unsigned long
48 #define u_int16_t u16
49 #define u_int8_t u8
50 #define tulip_uint32_t u32
51 #if LINUX_VERSION_CODE < 0x20155
52 #define u_int32_t u32
53 #endif
54
55 #define LMC_REG_RANGE 0x80
56
57 #define LMC_PRINTF_FMT "%s"
58 #define LMC_PRINTF_ARGS (sc->lmc_device->name)
59
60 #define TX_TIMEOUT (2*HZ)
61
62 #define LMC_TXDESCS 32
63 #define LMC_RXDESCS 32
64
65 #define LMC_LINK_UP 1
66 #define LMC_LINK_DOWN 0
67
68 /* These macros for generic read and write to and from the dec chip */
69 #define LMC_CSR_READ(sc, csr) \
70 inl((sc)->lmc_csrs.csr)
71 #define LMC_CSR_WRITE(sc, reg, val) \
72 outl((val), (sc)->lmc_csrs.reg)
73
74 //#ifdef _LINUX_DELAY_H
75 // #define SLOW_DOWN_IO udelay(2);
76 // #undef __SLOW_DOWN_IO
77 // #define __SLOW_DOWN_IO udelay(2);
78 //#endif
79
80 #define DELAY(n) SLOW_DOWN_IO
81
82 #define lmc_delay() inl(sc->lmc_csrs.csr_9)
83
84 /* This macro sync's up with the mii so that reads and writes can take place */
85 #define LMC_MII_SYNC(sc) do {int n=32; while( n >= 0 ) { \
86 LMC_CSR_WRITE((sc), csr_9, 0x20000); \
87 lmc_delay(); \
88 LMC_CSR_WRITE((sc), csr_9, 0x30000); \
89 lmc_delay(); \
90 n--; }} while(0);
91
92 struct lmc_regfile_t {
93 lmc_csrptr_t csr_busmode; /* CSR0 */
94 lmc_csrptr_t csr_txpoll; /* CSR1 */
95 lmc_csrptr_t csr_rxpoll; /* CSR2 */
96 lmc_csrptr_t csr_rxlist; /* CSR3 */
97 lmc_csrptr_t csr_txlist; /* CSR4 */
98 lmc_csrptr_t csr_status; /* CSR5 */
99 lmc_csrptr_t csr_command; /* CSR6 */
100 lmc_csrptr_t csr_intr; /* CSR7 */
101 lmc_csrptr_t csr_missed_frames; /* CSR8 */
102 lmc_csrptr_t csr_9; /* CSR9 */
103 lmc_csrptr_t csr_10; /* CSR10 */
104 lmc_csrptr_t csr_11; /* CSR11 */
105 lmc_csrptr_t csr_12; /* CSR12 */
106 lmc_csrptr_t csr_13; /* CSR13 */
107 lmc_csrptr_t csr_14; /* CSR14 */
108 lmc_csrptr_t csr_15; /* CSR15 */
109 };
110
111 #define csr_enetrom csr_9 /* 21040 */
112 #define csr_reserved csr_10 /* 21040 */
113 #define csr_full_duplex csr_11 /* 21040 */
114 #define csr_bootrom csr_10 /* 21041/21140A/?? */
115 #define csr_gp csr_12 /* 21140* */
116 #define csr_watchdog csr_15 /* 21140* */
117 #define csr_gp_timer csr_11 /* 21041/21140* */
118 #define csr_srom_mii csr_9 /* 21041/21140* */
119 #define csr_sia_status csr_12 /* 2104x */
120 #define csr_sia_connectivity csr_13 /* 2104x */
121 #define csr_sia_tx_rx csr_14 /* 2104x */
122 #define csr_sia_general csr_15 /* 2104x */
123
124 /* tulip length/control transmit descriptor definitions
125 * used to define bits in the second tulip_desc_t field (length)
126 * for the transmit descriptor -baz */
127
128 #define LMC_TDES_FIRST_BUFFER_SIZE ((u_int32_t)(0x000007FF))
129 #define LMC_TDES_SECOND_BUFFER_SIZE ((u_int32_t)(0x003FF800))
130 #define LMC_TDES_HASH_FILTERING ((u_int32_t)(0x00400000))
131 #define LMC_TDES_DISABLE_PADDING ((u_int32_t)(0x00800000))
132 #define LMC_TDES_SECOND_ADDR_CHAINED ((u_int32_t)(0x01000000))
133 #define LMC_TDES_END_OF_RING ((u_int32_t)(0x02000000))
134 #define LMC_TDES_ADD_CRC_DISABLE ((u_int32_t)(0x04000000))
135 #define LMC_TDES_SETUP_PACKET ((u_int32_t)(0x08000000))
136 #define LMC_TDES_INVERSE_FILTERING ((u_int32_t)(0x10000000))
137 #define LMC_TDES_FIRST_SEGMENT ((u_int32_t)(0x20000000))
138 #define LMC_TDES_LAST_SEGMENT ((u_int32_t)(0x40000000))
139 #define LMC_TDES_INTERRUPT_ON_COMPLETION ((u_int32_t)(0x80000000))
140
141 #define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER 11
142 #define TDES_COLLISION_COUNT_BIT_NUMBER 3
143
144 /* Constants for the RCV descriptor RDES */
145
146 #define LMC_RDES_OVERFLOW ((u_int32_t)(0x00000001))
147 #define LMC_RDES_CRC_ERROR ((u_int32_t)(0x00000002))
148 #define LMC_RDES_DRIBBLING_BIT ((u_int32_t)(0x00000004))
149 #define LMC_RDES_REPORT_ON_MII_ERR ((u_int32_t)(0x00000008))
150 #define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u_int32_t)(0x00000010))
151 #define LMC_RDES_FRAME_TYPE ((u_int32_t)(0x00000020))
152 #define LMC_RDES_COLLISION_SEEN ((u_int32_t)(0x00000040))
153 #define LMC_RDES_FRAME_TOO_LONG ((u_int32_t)(0x00000080))
154 #define LMC_RDES_LAST_DESCRIPTOR ((u_int32_t)(0x00000100))
155 #define LMC_RDES_FIRST_DESCRIPTOR ((u_int32_t)(0x00000200))
156 #define LMC_RDES_MULTICAST_FRAME ((u_int32_t)(0x00000400))
157 #define LMC_RDES_RUNT_FRAME ((u_int32_t)(0x00000800))
158 #define LMC_RDES_DATA_TYPE ((u_int32_t)(0x00003000))
159 #define LMC_RDES_LENGTH_ERROR ((u_int32_t)(0x00004000))
160 #define LMC_RDES_ERROR_SUMMARY ((u_int32_t)(0x00008000))
161 #define LMC_RDES_FRAME_LENGTH ((u_int32_t)(0x3FFF0000))
162 #define LMC_RDES_OWN_BIT ((u_int32_t)(0x80000000))
163
164 #define RDES_FRAME_LENGTH_BIT_NUMBER 16
165
166 #define LMC_RDES_ERROR_MASK ( (u_int32_t)( \
167 LMC_RDES_OVERFLOW \
168 | LMC_RDES_DRIBBLING_BIT \
169 | LMC_RDES_REPORT_ON_MII_ERR \
170 | LMC_RDES_COLLISION_SEEN ) )
171
172
173 /*
174 * Ioctl info
175 */
176
177 typedef struct {
178 u_int32_t n;
179 u_int32_t m;
180 u_int32_t v;
181 u_int32_t x;
182 u_int32_t r;
183 u_int32_t f;
184 u_int32_t exact;
185 } lmc_av9110_t;
186
187 /*
188 * Common structure passed to the ioctl code.
189 */
190 struct lmc___ctl {
191 u_int32_t cardtype;
192 u_int32_t clock_source; /* HSSI, T1 */
193 u_int32_t clock_rate; /* T1 */
194 u_int32_t crc_length;
195 u_int32_t cable_length; /* DS3 */
196 u_int32_t scrambler_onoff; /* DS3 */
197 u_int32_t cable_type; /* T1 */
198 u_int32_t keepalive_onoff; /* protocol */
199 u_int32_t ticks; /* ticks/sec */
200 union {
201 lmc_av9110_t ssi;
202 } cardspec;
203 u_int32_t circuit_type; /* T1 or E1 */
204 };
205
206
207 /*
208 * Carefull, look at the data sheet, there's more to this
209 * structure than meets the eye. It should probably be:
210 *
211 * struct tulip_desc_t {
212 * u8 own:1;
213 * u32 status:31;
214 * u32 control:10;
215 * u32 buffer1;
216 * u32 buffer2;
217 * };
218 * You could also expand status control to provide more bit information
219 */
220
221 struct tulip_desc_t {
222 s32 status;
223 s32 length;
224 u32 buffer1;
225 u32 buffer2;
226 };
227
228 /*
229 * media independent methods to check on media status, link, light LEDs,
230 * etc.
231 */
232 struct lmc___media {
233 void (* init)(lmc_softc_t * const);
234 void (* defaults)(lmc_softc_t * const);
235 void (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
236 void (* set_clock_source)(lmc_softc_t * const, int);
237 void (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
238 void (* set_cable_length)(lmc_softc_t * const, int);
239 void (* set_scrambler)(lmc_softc_t * const, int);
240 int (* get_link_status)(lmc_softc_t * const);
241 void (* set_link_status)(lmc_softc_t * const, int);
242 void (* set_crc_length)(lmc_softc_t * const, int);
243 void (* set_circuit_type)(lmc_softc_t * const, int);
244 void (* watchdog)(lmc_softc_t * const);
245 };
246
247
248 #define STATCHECK 0xBEEFCAFE
249
250 /* Included in this structure are first
251 * - standard net_device_stats
252 * - some other counters used for debug and driver performance
253 * evaluation -baz
254 */
255 struct lmc_statistics
256 {
257 unsigned long rx_packets; /* total packets received */
258 unsigned long tx_packets; /* total packets transmitted */
259 unsigned long rx_bytes;
260 unsigned long tx_bytes;
261
262 unsigned long rx_errors; /* bad packets received */
263 unsigned long tx_errors; /* packet transmit problems */
264 unsigned long rx_dropped; /* no space in linux buffers */
265 unsigned long tx_dropped; /* no space available in linux */
266 unsigned long multicast; /* multicast packets received */
267 unsigned long collisions;
268
269 /* detailed rx_errors: */
270 unsigned long rx_length_errors;
271 unsigned long rx_over_errors; /* receiver ring buff overflow */
272 unsigned long rx_crc_errors; /* recved pkt with crc error */
273 unsigned long rx_frame_errors; /* recv'd frame alignment error */
274 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
275 unsigned long rx_missed_errors; /* receiver missed packet */
276
277 /* detailed tx_errors */
278 unsigned long tx_aborted_errors;
279 unsigned long tx_carrier_errors;
280 unsigned long tx_fifo_errors;
281 unsigned long tx_heartbeat_errors;
282 unsigned long tx_window_errors;
283
284 /* for cslip etc */
285 unsigned long rx_compressed;
286 unsigned long tx_compressed;
287
288 /* -------------------------------------
289 * Custom stats & counters follow -baz */
290 u_int32_t version_size;
291 u_int32_t lmc_cardtype;
292
293 u_int32_t tx_ProcTimeout;
294 u_int32_t tx_IntTimeout;
295 u_int32_t tx_NoCompleteCnt;
296 u_int32_t tx_MaxXmtsB4Int;
297 u_int32_t tx_TimeoutCnt;
298 u_int32_t tx_OutOfSyncPtr;
299 u_int32_t tx_tbusy0;
300 u_int32_t tx_tbusy1;
301 u_int32_t tx_tbusy_calls;
302 u_int32_t resetCount;
303 u_int32_t lmc_txfull;
304 u_int32_t tbusy;
305 u_int32_t dirtyTx;
306 u_int32_t lmc_next_tx;
307 u_int32_t otherTypeCnt;
308 u_int32_t lastType;
309 u_int32_t lastTypeOK;
310 u_int32_t txLoopCnt;
311 u_int32_t usedXmtDescripCnt;
312 u_int32_t txIndexCnt;
313 u_int32_t rxIntLoopCnt;
314
315 u_int32_t rx_SmallPktCnt;
316 u_int32_t rx_BadPktSurgeCnt;
317 u_int32_t rx_BuffAllocErr;
318 u_int32_t tx_lossOfClockCnt;
319
320 /* T1 error counters */
321 u_int32_t framingBitErrorCount;
322 u_int32_t lineCodeViolationCount;
323
324 u_int32_t lossOfFrameCount;
325 u_int32_t changeOfFrameAlignmentCount;
326 u_int32_t severelyErroredFrameCount;
327
328 u_int32_t check;
329 };
330
331
332 typedef struct lmc_xinfo {
333 u_int32_t Magic0; /* BEEFCAFE */
334
335 u_int32_t PciCardType;
336 u_int32_t PciSlotNumber; /* PCI slot number */
337
338 u_int16_t DriverMajorVersion;
339 u_int16_t DriverMinorVersion;
340 u_int16_t DriverSubVersion;
341
342 u_int16_t XilinxRevisionNumber;
343 u_int16_t MaxFrameSize;
344
345 u_int16_t t1_alarm1_status;
346 u_int16_t t1_alarm2_status;
347
348 int link_status;
349 u_int32_t mii_reg16;
350
351 u_int32_t Magic1; /* DEADBEEF */
352 } LMC_XINFO;
353
354
355 /*
356 * forward decl
357 */
358 struct lmc___softc {
359 void *if_ptr; /* General purpose pointer (used by SPPP) */
360 char *name;
361 u8 board_idx;
362 struct lmc_statistics stats;
363 struct net_device *lmc_device;
364
365 int hang, rxdesc, bad_packet, some_counter;
366 u_int32_t txgo;
367 struct lmc_regfile_t lmc_csrs;
368 volatile u_int32_t lmc_txtick;
369 volatile u_int32_t lmc_rxtick;
370 u_int32_t lmc_flags;
371 u_int32_t lmc_intrmask; /* our copy of csr_intr */
372 u_int32_t lmc_cmdmode; /* our copy of csr_cmdmode */
373 u_int32_t lmc_busmode; /* our copy of csr_busmode */
374 u_int32_t lmc_gpio_io; /* state of in/out settings */
375 u_int32_t lmc_gpio; /* state of outputs */
376 struct sk_buff* lmc_txq[LMC_TXDESCS];
377 struct sk_buff* lmc_rxq[LMC_RXDESCS];
378 volatile
379 struct tulip_desc_t lmc_rxring[LMC_RXDESCS];
380 volatile
381 struct tulip_desc_t lmc_txring[LMC_TXDESCS];
382 unsigned int lmc_next_rx, lmc_next_tx;
383 volatile
384 unsigned int lmc_taint_tx, lmc_taint_rx;
385 int lmc_tx_start, lmc_txfull;
386 int lmc_txbusy;
387 u_int16_t lmc_miireg16;
388 int lmc_ok;
389 int last_link_status;
390 int lmc_cardtype;
391 u_int32_t last_frameerr;
392 lmc_media_t *lmc_media;
393 struct timer_list timer;
394 lmc_ctl_t ictl;
395 u_int32_t TxDescriptControlInit;
396 struct net_device *next_module; /* Link to the next module */
397 int tx_TimeoutInd; /* additional driver state */
398 int tx_TimeoutDisplay;
399 unsigned int lastlmc_taint_tx;
400 int lasttx_packets;
401 u_int32_t tx_clockState;
402 u_int32_t lmc_crcSize;
403 LMC_XINFO lmc_xinfo;
404 char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
405 char lmc_timing; /* for HSSI and SSI */
406 int got_irq;
407
408 char last_led_err[4];
409
410 u32 last_int;
411 u32 num_int;
412
413 #if LINUX_VERSION_CODE >= 0x20200
414 spinlock_t lmc_lock;
415 #endif
416 u_int16_t if_type; /* PPP or NET */
417 struct ppp_device *pd;
418
419 /* Failure cases */
420 u8 failed_ring;
421 u8 failed_recv_alloc;
422
423 /* Structure check */
424 u32 check;
425 };
426
427 #define LMC_PCI_TIME 1
428 #define LMC_EXT_TIME 0
429
430 #define PKT_BUF_SZ 1542 /* was 1536 */
431
432 /* CSR5 settings */
433 #define TIMER_INT 0x00000800
434 #define TP_LINK_FAIL 0x00001000
435 #define TP_LINK_PASS 0x00000010
436 #define NORMAL_INT 0x00010000
437 #define ABNORMAL_INT 0x00008000
438 #define RX_JABBER_INT 0x00000200
439 #define RX_DIED 0x00000100
440 #define RX_NOBUFF 0x00000080
441 #define RX_INT 0x00000040
442 #define TX_FIFO_UNDER 0x00000020
443 #define TX_JABBER 0x00000008
444 #define TX_NOBUFF 0x00000004
445 #define TX_DIED 0x00000002
446 #define TX_INT 0x00000001
447
448 /* CSR6 settings */
449 #define OPERATION_MODE 0x00000200 /* Full Duplex */
450 #define PROMISC_MODE 0x00000040 /* Promiscuous Mode */
451 #define RECIEVE_ALL 0x40000000 /* Recieve All */
452 #define PASS_BAD_FRAMES 0x00000008 /* Pass Bad Frames */
453
454 /* Dec control registers CSR6 as well */
455 #define LMC_DEC_ST 0x00002000
456 #define LMC_DEC_SR 0x00000002
457
458 /* CSR15 settings */
459 #define RECV_WATCHDOG_DISABLE 0x00000010
460 #define JABBER_DISABLE 0x00000001
461
462 /* More settings */
463 /*
464 * aSR6 -- Command (Operation Mode) Register
465 */
466 #define TULIP_CMD_RECEIVEALL 0x40000000L /* (RW) Receivel all frames? */
467 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */
468 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */
469 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (21140) */
470 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */
471 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */
472 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */
473 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */
474 #define TULIP_CMD_PROMISCUOUS 0x00000041L /* (RW) Promiscuous Mode */
475 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */
476 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */
477
478 #define TULIP_GP_PINSET 0x00000100L
479 #define TULIP_BUSMODE_SWRESET 0x00000001L
480 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L
481 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L
482
483 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */
484 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */
485 #define TULIP_STS_ERI 0x00004000L /* (RW) Early Receive Interrupt */
486 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */
487 #define TULIP_STS_GTE 0x00000800L /* (RW) General Pupose Timer Exp */
488 #define TULIP_STS_ETI 0x00000400L /* (RW) Early Transmit Interrupt */
489 #define TULIP_STS_RXWT 0x00000200L /* (RW) Receiver Watchdog Timeout */
490 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receiver Process Stopped */
491 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buf Unavail */
492 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */
493 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */
494 #define TULIP_STS_TXJABER 0x00000008L /* (RW) Jabber timeout */
495 #define TULIP_STS_TXNOBUF 0x00000004L
496 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */
497 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */
498
499 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */
500
501 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */
502 #define TULIP_STS_RXNOBUF 0x00000080L
503
504 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */
505 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */
506 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */
507 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */
508 #define TULIP_DSTS_RxMIIERR 0x00000008
509 #define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR)
510
511 #define TULIP_DEFAULT_INTR_MASK (TULIP_STS_NORMALINTR \
512 | TULIP_STS_RXINTR \
513 | TULIP_STS_TXINTR \
514 | TULIP_STS_ABNRMLINTR \
515 | TULIP_STS_SYSERROR \
516 | TULIP_STS_TXSTOPPED \
517 | TULIP_STS_TXUNDERFLOW\
518 | TULIP_STS_RXSTOPPED )
519
520 #define DESC_OWNED_BY_SYSTEM ((u_int32_t)(0x00000000))
521 #define DESC_OWNED_BY_DC21X4 ((u_int32_t)(0x80000000))
522
523 #ifndef TULIP_CMD_RECEIVEALL
524 #define TULIP_CMD_RECEIVEALL 0x40000000L
525 #endif
526
527
528 /* PCI register values */
529 #define CORRECT_VENDOR_ID 0x1011
530 #define CORRECT_DEV_ID 9
531
532 #define PCI_VENDOR_LMC 0x1376
533 #define PCI_PRODUCT_LMC_HSSI 0x0003
534 #define PCI_PRODUCT_LMC_DS3 0x0004
535 #define PCI_PRODUCT_LMC_SSI 0x0005
536 #define PCI_PRODUCT_LMC_T1 0x0006
537
538 /* Adapcter module number */
539 #define LMC_ADAP_HSSI 2
540 #define LMC_ADAP_DS3 3
541 #define LMC_ADAP_SSI 4
542 #define LMC_ADAP_T1 5
543
544 #define HDLC_HDR_LEN 4
545 #define HDLC_ADDR_LEN 1
546 #define HDLC_SLARP 0x8035
547 #define LMC_MTU 1500
548 #define SLARP_LINECHECK 2
549
550 #define LMC_CRC_LEN_16 2 /* 16-bit CRC */
551 #define LMC_CRC_LEN_32 4
552
553 #if LINUX_VERSION_CODE < 0x20100
554 #define test_and_set_bit(val, addr) set_bit(val, addr)
555 #endif
556
557 #ifdef LMC_HDLC
558 /* definition of an hdlc header. */
559 struct hdlc_hdr
560 {
561 u8 address;
562 u8 control;
563 u16 type;
564 };
565
566 /* definition of a slarp header. */
567 struct slarp
568 {
569 long code;
570 union sl
571 {
572 struct
573 {
574 ulong address;
575 ulong mask;
576 ushort unused;
577 } add;
578 struct
579 {
580 ulong mysequence;
581 ulong yoursequence;
582 ushort reliability;
583 ulong time;
584 } chk;
585 } t;
586 };
587 #endif /* LMC_HDLC */
588
589
590 #endif /* _LMC_VAR_H_ */
591