File: /usr/src/linux/drivers/net/winbond-840.c
1 /* winbond-840.c: A Linux PCI network adapter device driver. */
2 /*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright infomation.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39
40 TODO:
41 * enable pci_power_off
42 * Wake-On-LAN
43 */
44
45 #define DRV_NAME "winbond-840"
46 #define DRV_VERSION "1.01-c"
47 #define DRV_RELDATE "6/30/2000"
48
49
50 /* Automatically extracted configuration info:
51 probe-func: winbond840_probe
52 config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
53
54 c-help-name: Winbond W89c840 PCI Ethernet support
55 c-help-symbol: CONFIG_WINBOND_840
56 c-help: This driver is for the Winbond W89c840 chip. It also works with
57 c-help: the TX9882 chip on the Compex RL100-ATX board.
58 c-help: More specific information and updates are available from
59 c-help: http://www.scyld.com/network/drivers.html
60 */
61
62 /* The user-configurable values.
63 These may be modified when a driver module is loaded.*/
64
65 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
66 static int max_interrupt_work = 20;
67 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
68 The '840 uses a 64 element hash table based on the Ethernet CRC. */
69 static int multicast_filter_limit = 32;
70
71 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
72 Setting to > 1518 effectively disables this feature. */
73 static int rx_copybreak;
74
75 /* Used to pass the media type, etc.
76 Both 'options[]' and 'full_duplex[]' should exist for driver
77 interoperability.
78 The media type is usually passed in 'options[]'.
79 */
80 #define MAX_UNITS 8 /* More are supported, limit only on options */
81 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
82 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
83
84 /* Operational parameters that are set at compile time. */
85
86 /* Keep the ring sizes a power of two for compile efficiency.
87 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
88 Making the Tx ring too large decreases the effectiveness of channel
89 bonding and packet priority.
90 There are no ill effects from too-large receive rings. */
91 #define TX_RING_SIZE 16
92 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
93 #define TX_QUEUE_LEN_RESTART 5
94 #define RX_RING_SIZE 32
95
96 #define TX_BUFLIMIT (1024-128)
97
98 /* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
99 To avoid overflowing we don't queue again until we have room for a
100 full-size packet.
101 */
102 #define TX_FIFO_SIZE (2048)
103 #define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
104
105
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
109
110 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
111
112 #ifndef __KERNEL__
113 #define __KERNEL__
114 #endif
115 #if !defined(__OPTIMIZE__)
116 #warning You must compile this file with the correct options!
117 #warning See the last lines of the source file.
118 #error You must compile this driver with "-O".
119 #endif
120
121 /* Include files, designed to support most kernel versions 2.0.0 and later. */
122 #include <linux/module.h>
123 #include <linux/kernel.h>
124 #include <linux/string.h>
125 #include <linux/timer.h>
126 #include <linux/errno.h>
127 #include <linux/ioport.h>
128 #include <linux/slab.h>
129 #include <linux/interrupt.h>
130 #include <linux/pci.h>
131 #include <linux/netdevice.h>
132 #include <linux/etherdevice.h>
133 #include <linux/skbuff.h>
134 #include <linux/init.h>
135 #include <linux/delay.h>
136 #include <linux/ethtool.h>
137 #include <linux/mii.h>
138 #include <linux/rtnetlink.h>
139 #include <asm/uaccess.h>
140 #include <asm/processor.h> /* Processor type for cache alignment. */
141 #include <asm/bitops.h>
142 #include <asm/io.h>
143 #include <asm/irq.h>
144
145 /* These identify the driver base version and may not be removed. */
146 static char version[] __devinitdata =
147 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
148 KERN_INFO " http://www.scyld.com/network/drivers.html\n";
149
150 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
151 MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
152 MODULE_PARM(max_interrupt_work, "i");
153 MODULE_PARM(debug, "i");
154 MODULE_PARM(rx_copybreak, "i");
155 MODULE_PARM(multicast_filter_limit, "i");
156 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
157 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
158 MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
159 MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
160 MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
161 MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
162 MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
163 MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
164
165 /*
166 Theory of Operation
167
168 I. Board Compatibility
169
170 This driver is for the Winbond w89c840 chip.
171
172 II. Board-specific settings
173
174 None.
175
176 III. Driver operation
177
178 This chip is very similar to the Digital 21*4* "Tulip" family. The first
179 twelve registers and the descriptor format are nearly identical. Read a
180 Tulip manual for operational details.
181
182 A significant difference is that the multicast filter and station address are
183 stored in registers rather than loaded through a pseudo-transmit packet.
184
185 Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
186 full-sized packet we must use both data buffers in a descriptor. Thus the
187 driver uses ring mode where descriptors are implicitly sequential in memory,
188 rather than using the second descriptor address as a chain pointer to
189 subsequent descriptors.
190
191 IV. Notes
192
193 If you are going to almost clone a Tulip, why not go all the way and avoid
194 the need for a new driver?
195
196 IVb. References
197
198 http://www.scyld.com/expert/100mbps.html
199 http://www.scyld.com/expert/NWay.html
200 http://www.winbond.com.tw/
201
202 IVc. Errata
203
204 A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
205 correctly detect a full FIFO, and queuing more than 2048 bytes may result in
206 silent data corruption.
207
208 Test with 'ping -s 10000' on a fast computer.
209
210 */
211
212
213
214 /*
215 PCI probe table.
216 */
217 enum pci_id_flags_bits {
218 /* Set PCI command register bits before calling probe1(). */
219 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
220 /* Read and map the single following PCI BAR. */
221 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
222 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
223 };
224 enum chip_capability_flags {
225 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,};
226 #ifdef USE_IO_OPS
227 #define W840_FLAGS (PCI_USES_IO | PCI_ADDR0 | PCI_USES_MASTER)
228 #else
229 #define W840_FLAGS (PCI_USES_MEM | PCI_ADDR1 | PCI_USES_MASTER)
230 #endif
231
232 static struct pci_device_id w840_pci_tbl[] __devinitdata = {
233 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
234 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
235 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
236 { 0, }
237 };
238 MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
239
240 struct pci_id_info {
241 const char *name;
242 struct match_info {
243 int pci, pci_mask, subsystem, subsystem_mask;
244 int revision, revision_mask; /* Only 8 bits. */
245 } id;
246 enum pci_id_flags_bits pci_flags;
247 int io_size; /* Needed for I/O region check or ioremap(). */
248 int drv_flags; /* Driver use, intended as capability flags. */
249 };
250 static struct pci_id_info pci_id_tbl[] = {
251 {"Winbond W89c840", /* Sometime a Level-One switch card. */
252 { 0x08401050, 0xffffffff, 0x81530000, 0xffff0000 },
253 W840_FLAGS, 128, CanHaveMII | HasBrokenTx | FDXOnNoMII},
254 {"Winbond W89c840", { 0x08401050, 0xffffffff, },
255 W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
256 {"Compex RL100-ATX", { 0x201111F6, 0xffffffff,},
257 W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
258 {0,}, /* 0 terminated list. */
259 };
260
261 /* This driver was written to use PCI memory space, however some x86 systems
262 work only with I/O space accesses. Pass -DUSE_IO_OPS to use PCI I/O space
263 accesses instead of memory space. */
264
265 #ifdef USE_IO_OPS
266 #undef readb
267 #undef readw
268 #undef readl
269 #undef writeb
270 #undef writew
271 #undef writel
272 #define readb inb
273 #define readw inw
274 #define readl inl
275 #define writeb outb
276 #define writew outw
277 #define writel outl
278 #endif
279
280 /* Offsets to the Command and Status Registers, "CSRs".
281 While similar to the Tulip, these registers are longword aligned.
282 Note: It's not useful to define symbolic names for every register bit in
283 the device. The name can only partially document the semantics and make
284 the driver longer and more difficult to read.
285 */
286 enum w840_offsets {
287 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
288 RxRingPtr=0x0C, TxRingPtr=0x10,
289 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
290 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
291 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
292 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
293 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
294 };
295
296 /* Bits in the interrupt status/enable registers. */
297 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
298 enum intr_status_bits {
299 NormalIntr=0x10000, AbnormalIntr=0x8000,
300 IntrPCIErr=0x2000, TimerInt=0x800,
301 IntrRxDied=0x100, RxNoBuf=0x80, IntrRxDone=0x40,
302 TxFIFOUnderflow=0x20, RxErrIntr=0x10,
303 TxIdle=0x04, IntrTxStopped=0x02, IntrTxDone=0x01,
304 };
305
306 /* Bits in the NetworkConfig register. */
307 enum rx_mode_bits {
308 AcceptErr=0x80, AcceptRunt=0x40,
309 AcceptBroadcast=0x20, AcceptMulticast=0x10,
310 AcceptAllPhys=0x08, AcceptMyPhys=0x02,
311 };
312
313 enum mii_reg_bits {
314 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
315 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
316 };
317
318 /* The Tulip Rx and Tx buffer descriptors. */
319 struct w840_rx_desc {
320 s32 status;
321 s32 length;
322 u32 buffer1;
323 u32 buffer2;
324 };
325
326 struct w840_tx_desc {
327 s32 status;
328 s32 length;
329 u32 buffer1, buffer2;
330 };
331
332 /* Bits in network_desc.status */
333 enum desc_status_bits {
334 DescOwn=0x80000000, DescEndRing=0x02000000, DescUseLink=0x01000000,
335 DescWholePkt=0x60000000, DescStartPkt=0x20000000, DescEndPkt=0x40000000,
336 DescIntr=0x80000000,
337 };
338
339 #define PRIV_ALIGN 15 /* Required alignment mask */
340 #define MII_CNT 1 /* winbond only supports one MII */
341 struct netdev_private {
342 struct w840_rx_desc *rx_ring;
343 dma_addr_t rx_addr[RX_RING_SIZE];
344 struct w840_tx_desc *tx_ring;
345 dma_addr_t tx_addr[RX_RING_SIZE];
346 dma_addr_t ring_dma_addr;
347 /* The addresses of receive-in-place skbuffs. */
348 struct sk_buff* rx_skbuff[RX_RING_SIZE];
349 /* The saved address of a sent-in-place packet/buffer, for later free(). */
350 struct sk_buff* tx_skbuff[TX_RING_SIZE];
351 struct net_device_stats stats;
352 struct timer_list timer; /* Media monitoring timer. */
353 /* Frequently used values: keep some adjacent for cache effect. */
354 spinlock_t lock;
355 int chip_id, drv_flags;
356 struct pci_dev *pci_dev;
357 int csr6;
358 struct w840_rx_desc *rx_head_desc;
359 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
360 unsigned int rx_buf_sz; /* Based on MTU+slack. */
361 unsigned int cur_tx, dirty_tx;
362 unsigned int tx_q_bytes;
363 unsigned int tx_full; /* The Tx queue is full. */
364 /* These values are keep track of the transceiver/media in use. */
365 unsigned int full_duplex:1; /* Full-duplex operation requested. */
366 unsigned int duplex_lock:1;
367 /* MII transceiver section. */
368 int mii_cnt; /* MII device addresses. */
369 u16 advertising; /* NWay media advertisement */
370 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
371 u32 mii;
372 };
373
374 static int eeprom_read(long ioaddr, int location);
375 static int mdio_read(struct net_device *dev, int phy_id, int location);
376 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
377 static int netdev_open(struct net_device *dev);
378 static int update_link(struct net_device *dev);
379 static void netdev_timer(unsigned long data);
380 static void init_rxtx_rings(struct net_device *dev);
381 static void free_rxtx_rings(struct netdev_private *np);
382 static void init_registers(struct net_device *dev);
383 static void tx_timeout(struct net_device *dev);
384 static int alloc_ringdesc(struct net_device *dev);
385 static void free_ringdesc(struct netdev_private *np);
386 static int start_tx(struct sk_buff *skb, struct net_device *dev);
387 static void intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
388 static void netdev_error(struct net_device *dev, int intr_status);
389 static int netdev_rx(struct net_device *dev);
390 static inline unsigned ether_crc(int length, unsigned char *data);
391 static u32 __set_rx_mode(struct net_device *dev);
392 static void set_rx_mode(struct net_device *dev);
393 static struct net_device_stats *get_stats(struct net_device *dev);
394 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
395 static int netdev_close(struct net_device *dev);
396
397
398
399 static int __devinit w840_probe1 (struct pci_dev *pdev,
400 const struct pci_device_id *ent)
401 {
402 struct net_device *dev;
403 struct netdev_private *np;
404 static int find_cnt;
405 int chip_idx = ent->driver_data;
406 int irq;
407 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
408 long ioaddr;
409
410 i = pci_enable_device(pdev);
411 if (i) return i;
412
413 pci_set_master(pdev);
414
415 irq = pdev->irq;
416
417 if (pci_set_dma_mask(pdev,0xFFFFffff)) {
418 printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n",
419 pdev->slot_name);
420 return -EIO;
421 }
422 dev = alloc_etherdev(sizeof(*np));
423 if (!dev)
424 return -ENOMEM;
425 SET_MODULE_OWNER(dev);
426
427 if (pci_request_regions(pdev, DRV_NAME))
428 goto err_out_netdev;
429
430 #ifdef USE_IO_OPS
431 ioaddr = pci_resource_start(pdev, 0);
432 #else
433 ioaddr = pci_resource_start(pdev, 1);
434 ioaddr = (long) ioremap (ioaddr, pci_id_tbl[chip_idx].io_size);
435 if (!ioaddr)
436 goto err_out_free_res;
437 #endif
438
439 for (i = 0; i < 3; i++)
440 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(eeprom_read(ioaddr, i));
441
442 /* Reset the chip to erase previous misconfiguration.
443 No hold time required! */
444 writel(0x00000001, ioaddr + PCIBusCfg);
445
446 dev->base_addr = ioaddr;
447 dev->irq = irq;
448
449 np = dev->priv;
450 np->pci_dev = pdev;
451 np->chip_id = chip_idx;
452 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
453 spin_lock_init(&np->lock);
454
455 pci_set_drvdata(pdev, dev);
456
457 if (dev->mem_start)
458 option = dev->mem_start;
459
460 /* The lower four bits are the media type. */
461 if (option > 0) {
462 if (option & 0x200)
463 np->full_duplex = 1;
464 if (option & 15)
465 printk(KERN_INFO "%s: ignoring user supplied media type %d",
466 dev->name, option & 15);
467 }
468 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
469 np->full_duplex = 1;
470
471 if (np->full_duplex)
472 np->duplex_lock = 1;
473
474 /* The chip-specific entries in the device structure. */
475 dev->open = &netdev_open;
476 dev->hard_start_xmit = &start_tx;
477 dev->stop = &netdev_close;
478 dev->get_stats = &get_stats;
479 dev->set_multicast_list = &set_rx_mode;
480 dev->do_ioctl = &netdev_ioctl;
481 dev->tx_timeout = &tx_timeout;
482 dev->watchdog_timeo = TX_TIMEOUT;
483
484 i = register_netdev(dev);
485 if (i)
486 goto err_out_cleardev;
487
488 printk(KERN_INFO "%s: %s at 0x%lx, ",
489 dev->name, pci_id_tbl[chip_idx].name, ioaddr);
490 for (i = 0; i < 5; i++)
491 printk("%2.2x:", dev->dev_addr[i]);
492 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
493
494 if (np->drv_flags & CanHaveMII) {
495 int phy, phy_idx = 0;
496 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
497 int mii_status = mdio_read(dev, phy, 1);
498 if (mii_status != 0xffff && mii_status != 0x0000) {
499 np->phys[phy_idx++] = phy;
500 np->advertising = mdio_read(dev, phy, 4);
501 np->mii = (mdio_read(dev, phy, 2) << 16)+
502 mdio_read(dev, phy, 3);
503 printk(KERN_INFO "%s: MII PHY %8.8xh found at address %d, status "
504 "0x%4.4x advertising %4.4x.\n",
505 dev->name, np->mii, phy, mii_status, np->advertising);
506 }
507 }
508 np->mii_cnt = phy_idx;
509 if (phy_idx == 0) {
510 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
511 "not operate correctly.\n", dev->name);
512 }
513 }
514
515 find_cnt++;
516 return 0;
517
518 err_out_cleardev:
519 pci_set_drvdata(pdev, NULL);
520 #ifndef USE_IO_OPS
521 iounmap((void *)ioaddr);
522 err_out_free_res:
523 #endif
524 pci_release_regions(pdev);
525 err_out_netdev:
526 kfree (dev);
527 return -ENODEV;
528 }
529
530
531 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
532 often serial bit streams generated by the host processor.
533 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
534
535 /* Delay between EEPROM clock transitions.
536 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
537 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
538 made udelay() unreliable.
539 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
540 depricated.
541 */
542 #define eeprom_delay(ee_addr) readl(ee_addr)
543
544 enum EEPROM_Ctrl_Bits {
545 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
546 EE_ChipSelect=0x801, EE_DataIn=0x08,
547 };
548
549 /* The EEPROM commands include the alway-set leading bit. */
550 enum EEPROM_Cmds {
551 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
552 };
553
554 static int eeprom_read(long addr, int location)
555 {
556 int i;
557 int retval = 0;
558 int ee_addr = addr + EECtrl;
559 int read_cmd = location | EE_ReadCmd;
560 writel(EE_ChipSelect, ee_addr);
561
562 /* Shift the read command bits out. */
563 for (i = 10; i >= 0; i--) {
564 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
565 writel(dataval, ee_addr);
566 eeprom_delay(ee_addr);
567 writel(dataval | EE_ShiftClk, ee_addr);
568 eeprom_delay(ee_addr);
569 }
570 writel(EE_ChipSelect, ee_addr);
571 eeprom_delay(ee_addr);
572
573 for (i = 16; i > 0; i--) {
574 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
575 eeprom_delay(ee_addr);
576 retval = (retval << 1) | ((readl(ee_addr) & EE_DataIn) ? 1 : 0);
577 writel(EE_ChipSelect, ee_addr);
578 eeprom_delay(ee_addr);
579 }
580
581 /* Terminate the EEPROM access. */
582 writel(0, ee_addr);
583 return retval;
584 }
585
586 /* MII transceiver control section.
587 Read and write the MII registers using software-generated serial
588 MDIO protocol. See the MII specifications or DP83840A data sheet
589 for details.
590
591 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
592 met by back-to-back 33Mhz PCI cycles. */
593 #define mdio_delay(mdio_addr) readl(mdio_addr)
594
595 /* Set iff a MII transceiver on any interface requires mdio preamble.
596 This only set with older tranceivers, so the extra
597 code size of a per-interface flag is not worthwhile. */
598 static char mii_preamble_required = 1;
599
600 #define MDIO_WRITE0 (MDIO_EnbOutput)
601 #define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
602
603 /* Generate the preamble required for initial synchronization and
604 a few older transceivers. */
605 static void mdio_sync(long mdio_addr)
606 {
607 int bits = 32;
608
609 /* Establish sync by sending at least 32 logic ones. */
610 while (--bits >= 0) {
611 writel(MDIO_WRITE1, mdio_addr);
612 mdio_delay(mdio_addr);
613 writel(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
614 mdio_delay(mdio_addr);
615 }
616 }
617
618 static int mdio_read(struct net_device *dev, int phy_id, int location)
619 {
620 long mdio_addr = dev->base_addr + MIICtrl;
621 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
622 int i, retval = 0;
623
624 if (mii_preamble_required)
625 mdio_sync(mdio_addr);
626
627 /* Shift the read command bits out. */
628 for (i = 15; i >= 0; i--) {
629 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
630
631 writel(dataval, mdio_addr);
632 mdio_delay(mdio_addr);
633 writel(dataval | MDIO_ShiftClk, mdio_addr);
634 mdio_delay(mdio_addr);
635 }
636 /* Read the two transition, 16 data, and wire-idle bits. */
637 for (i = 20; i > 0; i--) {
638 writel(MDIO_EnbIn, mdio_addr);
639 mdio_delay(mdio_addr);
640 retval = (retval << 1) | ((readl(mdio_addr) & MDIO_DataIn) ? 1 : 0);
641 writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
642 mdio_delay(mdio_addr);
643 }
644 return (retval>>1) & 0xffff;
645 }
646
647 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
648 {
649 struct netdev_private *np = dev->priv;
650 long mdio_addr = dev->base_addr + MIICtrl;
651 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
652 int i;
653
654 if (location == 4 && phy_id == np->phys[0])
655 np->advertising = value;
656
657 if (mii_preamble_required)
658 mdio_sync(mdio_addr);
659
660 /* Shift the command bits out. */
661 for (i = 31; i >= 0; i--) {
662 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
663
664 writel(dataval, mdio_addr);
665 mdio_delay(mdio_addr);
666 writel(dataval | MDIO_ShiftClk, mdio_addr);
667 mdio_delay(mdio_addr);
668 }
669 /* Clear out extra bits. */
670 for (i = 2; i > 0; i--) {
671 writel(MDIO_EnbIn, mdio_addr);
672 mdio_delay(mdio_addr);
673 writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
674 mdio_delay(mdio_addr);
675 }
676 return;
677 }
678
679
680 static int netdev_open(struct net_device *dev)
681 {
682 struct netdev_private *np = dev->priv;
683 long ioaddr = dev->base_addr;
684 int i;
685
686 writel(0x00000001, ioaddr + PCIBusCfg); /* Reset */
687
688 netif_device_detach(dev);
689 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
690 if (i)
691 goto out_err;
692
693 if (debug > 1)
694 printk(KERN_DEBUG "%s: w89c840_open() irq %d.\n",
695 dev->name, dev->irq);
696
697 if((i=alloc_ringdesc(dev)))
698 goto out_err;
699
700 spin_lock_irq(&np->lock);
701 netif_device_attach(dev);
702 init_registers(dev);
703 spin_unlock_irq(&np->lock);
704
705 netif_start_queue(dev);
706 if (debug > 2)
707 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
708
709 /* Set the timer to check for link beat. */
710 init_timer(&np->timer);
711 np->timer.expires = jiffies + 1*HZ;
712 np->timer.data = (unsigned long)dev;
713 np->timer.function = &netdev_timer; /* timer handler */
714 add_timer(&np->timer);
715 return 0;
716 out_err:
717 netif_device_attach(dev);
718 return i;
719 }
720
721 #define MII_DAVICOM_DM9101 0x0181b800
722
723 static int update_link(struct net_device *dev)
724 {
725 struct netdev_private *np = dev->priv;
726 int duplex, fasteth, result, mii_reg;
727
728 /* BSMR */
729 mii_reg = mdio_read(dev, np->phys[0], 1);
730
731 if (mii_reg == 0xffff)
732 return np->csr6;
733 /* reread: the link status bit is sticky */
734 mii_reg = mdio_read(dev, np->phys[0], 1);
735 if (!(mii_reg & 0x4)) {
736 if (netif_carrier_ok(dev)) {
737 if (debug)
738 printk(KERN_INFO "%s: MII #%d reports no link. Disabling watchdog.\n",
739 dev->name, np->phys[0]);
740 netif_carrier_off(dev);
741 }
742 return np->csr6;
743 }
744 if (!netif_carrier_ok(dev)) {
745 if (debug)
746 printk(KERN_INFO "%s: MII #%d link is back. Enabling watchdog.\n",
747 dev->name, np->phys[0]);
748 netif_carrier_on(dev);
749 }
750
751 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
752 /* If the link partner doesn't support autonegotiation
753 * the MII detects it's abilities with the "parallel detection".
754 * Some MIIs update the LPA register to the result of the parallel
755 * detection, some don't.
756 * The Davicom PHY [at least 0181b800] doesn't.
757 * Instead bit 9 and 13 of the BMCR are updated to the result
758 * of the negotiation..
759 */
760 mii_reg = mdio_read(dev, np->phys[0], 0);
761 duplex = mii_reg & 0x100;
762 fasteth = mii_reg & 0x2000;
763 } else {
764 int negotiated;
765 mii_reg = mdio_read(dev, np->phys[0], 5);
766 negotiated = mii_reg & np->advertising;
767
768 duplex = (negotiated & 0x0100) || ((negotiated & 0x02C0) == 0x0040);
769 fasteth = negotiated & 0x380;
770 }
771 duplex |= np->duplex_lock;
772 /* remove fastether and fullduplex */
773 result = np->csr6 & ~0x20000200;
774 if (duplex)
775 result |= 0x200;
776 if (fasteth)
777 result |= 0x20000000;
778 if (result != np->csr6 && debug)
779 printk(KERN_INFO "%s: Setting %dMBit-%s-duplex based on MII#%d\n",
780 dev->name, fasteth ? 100 : 10,
781 duplex ? "full" : "half", np->phys[0]);
782 return result;
783 }
784
785 #define RXTX_TIMEOUT 2000
786 static inline void update_csr6(struct net_device *dev, int new)
787 {
788 struct netdev_private *np = dev->priv;
789 long ioaddr = dev->base_addr;
790 int limit = RXTX_TIMEOUT;
791
792 if (!netif_device_present(dev))
793 new = 0;
794 if (new==np->csr6)
795 return;
796 /* stop both Tx and Rx processes */
797 writel(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
798 /* wait until they have really stopped */
799 for (;;) {
800 int csr5 = readl(ioaddr + IntrStatus);
801 int t;
802
803 t = (csr5 >> 17) & 0x07;
804 if (t==0||t==1) {
805 /* rx stopped */
806 t = (csr5 >> 20) & 0x07;
807 if (t==0||t==1)
808 break;
809 }
810
811 limit--;
812 if(!limit) {
813 printk(KERN_INFO "%s: couldn't stop rxtx, IntrStatus %xh.\n",
814 dev->name, csr5);
815 break;
816 }
817 udelay(1);
818 }
819 np->csr6 = new;
820 /* and restart them with the new configuration */
821 writel(np->csr6, ioaddr + NetworkConfig);
822 if (new & 0x200)
823 np->full_duplex = 1;
824 }
825
826 static void netdev_timer(unsigned long data)
827 {
828 struct net_device *dev = (struct net_device *)data;
829 struct netdev_private *np = dev->priv;
830 long ioaddr = dev->base_addr;
831
832 if (debug > 2)
833 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
834 "config %8.8x.\n",
835 dev->name, (int)readl(ioaddr + IntrStatus),
836 (int)readl(ioaddr + NetworkConfig));
837 spin_lock_irq(&np->lock);
838 update_csr6(dev, update_link(dev));
839 spin_unlock_irq(&np->lock);
840 np->timer.expires = jiffies + 10*HZ;
841 add_timer(&np->timer);
842 }
843
844 static void init_rxtx_rings(struct net_device *dev)
845 {
846 struct netdev_private *np = dev->priv;
847 int i;
848
849 np->rx_head_desc = &np->rx_ring[0];
850 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
851
852 /* Initial all Rx descriptors. */
853 for (i = 0; i < RX_RING_SIZE; i++) {
854 np->rx_ring[i].length = np->rx_buf_sz;
855 np->rx_ring[i].status = 0;
856 np->rx_skbuff[i] = 0;
857 }
858 /* Mark the last entry as wrapping the ring. */
859 np->rx_ring[i-1].length |= DescEndRing;
860
861 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
862 for (i = 0; i < RX_RING_SIZE; i++) {
863 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
864 np->rx_skbuff[i] = skb;
865 if (skb == NULL)
866 break;
867 skb->dev = dev; /* Mark as being used by this device. */
868 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->tail,
869 skb->len,PCI_DMA_FROMDEVICE);
870
871 np->rx_ring[i].buffer1 = np->rx_addr[i];
872 np->rx_ring[i].status = DescOwn;
873 }
874
875 np->cur_rx = 0;
876 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
877
878 /* Initialize the Tx descriptors */
879 for (i = 0; i < TX_RING_SIZE; i++) {
880 np->tx_skbuff[i] = 0;
881 np->tx_ring[i].status = 0;
882 }
883 np->tx_full = 0;
884 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
885
886 writel(np->ring_dma_addr, dev->base_addr + RxRingPtr);
887 writel(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
888 dev->base_addr + TxRingPtr);
889
890 }
891
892 static void free_rxtx_rings(struct netdev_private* np)
893 {
894 int i;
895 /* Free all the skbuffs in the Rx queue. */
896 for (i = 0; i < RX_RING_SIZE; i++) {
897 np->rx_ring[i].status = 0;
898 if (np->rx_skbuff[i]) {
899 pci_unmap_single(np->pci_dev,
900 np->rx_addr[i],
901 np->rx_skbuff[i]->len,
902 PCI_DMA_FROMDEVICE);
903 dev_kfree_skb(np->rx_skbuff[i]);
904 }
905 np->rx_skbuff[i] = 0;
906 }
907 for (i = 0; i < TX_RING_SIZE; i++) {
908 if (np->tx_skbuff[i]) {
909 pci_unmap_single(np->pci_dev,
910 np->tx_addr[i],
911 np->tx_skbuff[i]->len,
912 PCI_DMA_TODEVICE);
913 dev_kfree_skb(np->tx_skbuff[i]);
914 }
915 np->tx_skbuff[i] = 0;
916 }
917 }
918
919 static void init_registers(struct net_device *dev)
920 {
921 struct netdev_private *np = dev->priv;
922 long ioaddr = dev->base_addr;
923 int i;
924
925 for (i = 0; i < 6; i++)
926 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
927
928 /* Initialize other registers. */
929 #ifdef __BIG_ENDIAN
930 i = (1<<20); /* Big-endian descriptors */
931 #else
932 i = 0;
933 #endif
934 i |= (0x04<<2); /* skip length 4 u32 */
935 i |= 0x02; /* give Rx priority */
936
937 /* Configure the PCI bus bursts and FIFO thresholds.
938 486: Set 8 longword cache alignment, 8 longword burst.
939 586: Set 16 longword cache alignment, no burst limit.
940 Cache alignment bits 15:14 Burst length 13:8
941 0000 <not allowed> 0000 align to cache 0800 8 longwords
942 4000 8 longwords 0100 1 longword 1000 16 longwords
943 8000 16 longwords 0200 2 longwords 2000 32 longwords
944 C000 32 longwords 0400 4 longwords */
945
946 #if defined (__i386__) && !defined(MODULE)
947 /* When not a module we can work around broken '486 PCI boards. */
948 if (boot_cpu_data.x86 <= 4) {
949 i |= 0x4800;
950 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache "
951 "alignment to 8 longwords.\n", dev->name);
952 } else {
953 i |= 0xE000;
954 }
955 #elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
956 i |= 0xE000;
957 #elif defined(__sparc__)
958 i |= 0x4800;
959 #else
960 #warning Processor architecture undefined
961 i |= 0x4800;
962 #endif
963 writel(i, ioaddr + PCIBusCfg);
964
965 np->csr6 = 0;
966 /* 128 byte Tx threshold;
967 Transmit on; Receive on; */
968 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
969
970 /* Clear and Enable interrupts by setting the interrupt mask. */
971 writel(0x1A0F5, ioaddr + IntrStatus);
972 writel(0x1A0F5, ioaddr + IntrEnable);
973
974 writel(0, ioaddr + RxStartDemand);
975 }
976
977 static void tx_timeout(struct net_device *dev)
978 {
979 struct netdev_private *np = dev->priv;
980 long ioaddr = dev->base_addr;
981
982 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
983 " resetting...\n", dev->name, (int)readl(ioaddr + IntrStatus));
984
985 {
986 int i;
987 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
988 for (i = 0; i < RX_RING_SIZE; i++)
989 printk(" %8.8x", (unsigned int)np->rx_ring[i].status);
990 printk("\n"KERN_DEBUG" Tx ring %p: ", np->tx_ring);
991 for (i = 0; i < TX_RING_SIZE; i++)
992 printk(" %8.8x", np->tx_ring[i].status);
993 printk("\n");
994 }
995 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d.\n",
996 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
997 printk(KERN_DEBUG "Tx Descriptor addr %xh.\n",readl(ioaddr+0x4C));
998
999 disable_irq(dev->irq);
1000 spin_lock_irq(&np->lock);
1001 /*
1002 * Under high load dirty_tx and the internal tx descriptor pointer
1003 * come out of sync, thus perform a software reset and reinitialize
1004 * everything.
1005 */
1006
1007 writel(1, dev->base_addr+PCIBusCfg);
1008 udelay(1);
1009
1010 free_rxtx_rings(np);
1011 init_rxtx_rings(dev);
1012 init_registers(dev);
1013 spin_unlock_irq(&np->lock);
1014 enable_irq(dev->irq);
1015
1016 netif_wake_queue(dev);
1017 dev->trans_start = jiffies;
1018 np->stats.tx_errors++;
1019 return;
1020 }
1021
1022 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1023 static int alloc_ringdesc(struct net_device *dev)
1024 {
1025 struct netdev_private *np = dev->priv;
1026
1027 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1028
1029 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1030 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
1031 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
1032 &np->ring_dma_addr);
1033 if(!np->rx_ring)
1034 return -ENOMEM;
1035 init_rxtx_rings(dev);
1036 return 0;
1037 }
1038
1039 static void free_ringdesc(struct netdev_private *np)
1040 {
1041 pci_free_consistent(np->pci_dev,
1042 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
1043 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
1044 np->rx_ring, np->ring_dma_addr);
1045
1046 }
1047
1048 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1049 {
1050 struct netdev_private *np = dev->priv;
1051 unsigned entry;
1052
1053 /* Caution: the write order is important here, set the field
1054 with the "ownership" bits last. */
1055
1056 /* Calculate the next Tx descriptor entry. */
1057 entry = np->cur_tx % TX_RING_SIZE;
1058
1059 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1060 skb->data,skb->len, PCI_DMA_TODEVICE);
1061 np->tx_skbuff[entry] = skb;
1062
1063 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1064 if (skb->len < TX_BUFLIMIT) {
1065 np->tx_ring[entry].length = DescWholePkt | skb->len;
1066 } else {
1067 int len = skb->len - TX_BUFLIMIT;
1068
1069 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1070 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1071 }
1072 if(entry == TX_RING_SIZE-1)
1073 np->tx_ring[entry].length |= DescEndRing;
1074
1075 /* Now acquire the irq spinlock.
1076 * The difficult race is the the ordering between
1077 * increasing np->cur_tx and setting DescOwn:
1078 * - if np->cur_tx is increased first the interrupt
1079 * handler could consider the packet as transmitted
1080 * since DescOwn is cleared.
1081 * - If DescOwn is set first the NIC could report the
1082 * packet as sent, but the interrupt handler would ignore it
1083 * since the np->cur_tx was not yet increased.
1084 */
1085 spin_lock_irq(&np->lock);
1086 np->cur_tx++;
1087
1088 wmb(); /* flush length, buffer1, buffer2 */
1089 np->tx_ring[entry].status = DescOwn;
1090 wmb(); /* flush status and kick the hardware */
1091 writel(0, dev->base_addr + TxStartDemand);
1092 np->tx_q_bytes += skb->len;
1093 /* Work around horrible bug in the chip by marking the queue as full
1094 when we do not have FIFO room for a maximum sized packet. */
1095 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1096 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1097 netif_stop_queue(dev);
1098 wmb();
1099 np->tx_full = 1;
1100 }
1101 spin_unlock_irq(&np->lock);
1102
1103 dev->trans_start = jiffies;
1104
1105 if (debug > 4) {
1106 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1107 dev->name, np->cur_tx, entry);
1108 }
1109 return 0;
1110 }
1111
1112 static void netdev_tx_done(struct net_device *dev)
1113 {
1114 struct netdev_private *np = dev->priv;
1115 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1116 int entry = np->dirty_tx % TX_RING_SIZE;
1117 int tx_status = np->tx_ring[entry].status;
1118
1119 if (tx_status < 0)
1120 break;
1121 if (tx_status & 0x8000) { /* There was an error, log it. */
1122 #ifndef final_version
1123 if (debug > 1)
1124 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1125 dev->name, tx_status);
1126 #endif
1127 np->stats.tx_errors++;
1128 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1129 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1130 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1131 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1132 if ((tx_status & 0x0080) && np->full_duplex == 0)
1133 np->stats.tx_heartbeat_errors++;
1134 #ifdef ETHER_STATS
1135 if (tx_status & 0x0100) np->stats.collisions16++;
1136 #endif
1137 } else {
1138 #ifdef ETHER_STATS
1139 if (tx_status & 0x0001) np->stats.tx_deferred++;
1140 #endif
1141 #ifndef final_version
1142 if (debug > 3)
1143 printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %8.8x.\n",
1144 dev->name, entry, tx_status);
1145 #endif
1146 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1147 np->stats.collisions += (tx_status >> 3) & 15;
1148 np->stats.tx_packets++;
1149 }
1150 /* Free the original skb. */
1151 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1152 np->tx_skbuff[entry]->len,
1153 PCI_DMA_TODEVICE);
1154 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1155 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1156 np->tx_skbuff[entry] = 0;
1157 }
1158 if (np->tx_full &&
1159 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1160 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1161 /* The ring is no longer full, clear tbusy. */
1162 np->tx_full = 0;
1163 wmb();
1164 netif_wake_queue(dev);
1165 }
1166 }
1167
1168 /* The interrupt handler does all of the Rx thread work and cleans up
1169 after the Tx thread. */
1170 static void intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1171 {
1172 struct net_device *dev = (struct net_device *)dev_instance;
1173 struct netdev_private *np = dev->priv;
1174 long ioaddr = dev->base_addr;
1175 int work_limit = max_interrupt_work;
1176
1177 if (!netif_device_present(dev))
1178 return;
1179 do {
1180 u32 intr_status = readl(ioaddr + IntrStatus);
1181
1182 /* Acknowledge all of the current interrupt sources ASAP. */
1183 writel(intr_status & 0x001ffff, ioaddr + IntrStatus);
1184
1185 if (debug > 4)
1186 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1187 dev->name, intr_status);
1188
1189 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1190 break;
1191
1192 if (intr_status & (IntrRxDone | RxNoBuf))
1193 netdev_rx(dev);
1194 if (intr_status & RxNoBuf)
1195 writel(0, ioaddr + RxStartDemand);
1196
1197 if (intr_status & (TxIdle | IntrTxDone) &&
1198 np->cur_tx != np->dirty_tx) {
1199 spin_lock(&np->lock);
1200 netdev_tx_done(dev);
1201 spin_unlock(&np->lock);
1202 }
1203
1204 /* Abnormal error summary/uncommon events handlers. */
1205 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | IntrPCIErr |
1206 TimerInt | IntrTxStopped))
1207 netdev_error(dev, intr_status);
1208
1209 if (--work_limit < 0) {
1210 printk(KERN_WARNING "%s: Too much work at interrupt, "
1211 "status=0x%4.4x.\n", dev->name, intr_status);
1212 /* Set the timer to re-enable the other interrupts after
1213 10*82usec ticks. */
1214 spin_lock(&np->lock);
1215 if (netif_device_present(dev)) {
1216 writel(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1217 writel(10, ioaddr + GPTimer);
1218 }
1219 spin_unlock(&np->lock);
1220 break;
1221 }
1222 } while (1);
1223
1224 if (debug > 3)
1225 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1226 dev->name, (int)readl(ioaddr + IntrStatus));
1227 }
1228
1229 /* This routine is logically part of the interrupt handler, but separated
1230 for clarity and better register allocation. */
1231 static int netdev_rx(struct net_device *dev)
1232 {
1233 struct netdev_private *np = dev->priv;
1234 int entry = np->cur_rx % RX_RING_SIZE;
1235 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1236
1237 if (debug > 4) {
1238 printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n",
1239 entry, np->rx_ring[entry].status);
1240 }
1241
1242 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1243 while (--work_limit >= 0) {
1244 struct w840_rx_desc *desc = np->rx_head_desc;
1245 s32 status = desc->status;
1246
1247 if (debug > 4)
1248 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1249 status);
1250 if (status < 0)
1251 break;
1252 if ((status & 0x38008300) != 0x0300) {
1253 if ((status & 0x38000300) != 0x0300) {
1254 /* Ingore earlier buffers. */
1255 if ((status & 0xffff) != 0x7fff) {
1256 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1257 "multiple buffers, entry %#x status %4.4x!\n",
1258 dev->name, np->cur_rx, status);
1259 np->stats.rx_length_errors++;
1260 }
1261 } else if (status & 0x8000) {
1262 /* There was a fatal error. */
1263 if (debug > 2)
1264 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1265 dev->name, status);
1266 np->stats.rx_errors++; /* end of a packet.*/
1267 if (status & 0x0890) np->stats.rx_length_errors++;
1268 if (status & 0x004C) np->stats.rx_frame_errors++;
1269 if (status & 0x0002) np->stats.rx_crc_errors++;
1270 }
1271 } else {
1272 struct sk_buff *skb;
1273 /* Omit the four octet CRC from the length. */
1274 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1275
1276 #ifndef final_version
1277 if (debug > 4)
1278 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1279 " status %x.\n", pkt_len, status);
1280 #endif
1281 /* Check if the packet is long enough to accept without copying
1282 to a minimally-sized skbuff. */
1283 if (pkt_len < rx_copybreak
1284 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1285 skb->dev = dev;
1286 skb_reserve(skb, 2); /* 16 byte align the IP header */
1287 pci_dma_sync_single(np->pci_dev,np->rx_addr[entry],
1288 np->rx_skbuff[entry]->len,
1289 PCI_DMA_FROMDEVICE);
1290 /* Call copy + cksum if available. */
1291 #if HAS_IP_COPYSUM
1292 eth_copy_and_sum(skb, np->rx_skbuff[entry]->tail, pkt_len, 0);
1293 skb_put(skb, pkt_len);
1294 #else
1295 memcpy(skb_put(skb, pkt_len), np->rx_skbuff[entry]->tail,
1296 pkt_len);
1297 #endif
1298 } else {
1299 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1300 np->rx_skbuff[entry]->len,
1301 PCI_DMA_FROMDEVICE);
1302 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1303 np->rx_skbuff[entry] = NULL;
1304 }
1305 #ifndef final_version /* Remove after testing. */
1306 /* You will want this info for the initial debug. */
1307 if (debug > 5)
1308 printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:"
1309 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x "
1310 "%d.%d.%d.%d.\n",
1311 skb->data[0], skb->data[1], skb->data[2], skb->data[3],
1312 skb->data[4], skb->data[5], skb->data[6], skb->data[7],
1313 skb->data[8], skb->data[9], skb->data[10],
1314 skb->data[11], skb->data[12], skb->data[13],
1315 skb->data[14], skb->data[15], skb->data[16],
1316 skb->data[17]);
1317 #endif
1318 skb->protocol = eth_type_trans(skb, dev);
1319 netif_rx(skb);
1320 dev->last_rx = jiffies;
1321 np->stats.rx_packets++;
1322 np->stats.rx_bytes += pkt_len;
1323 }
1324 entry = (++np->cur_rx) % RX_RING_SIZE;
1325 np->rx_head_desc = &np->rx_ring[entry];
1326 }
1327
1328 /* Refill the Rx ring buffers. */
1329 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1330 struct sk_buff *skb;
1331 entry = np->dirty_rx % RX_RING_SIZE;
1332 if (np->rx_skbuff[entry] == NULL) {
1333 skb = dev_alloc_skb(np->rx_buf_sz);
1334 np->rx_skbuff[entry] = skb;
1335 if (skb == NULL)
1336 break; /* Better luck next round. */
1337 skb->dev = dev; /* Mark as being used by this device. */
1338 np->rx_addr[entry] = pci_map_single(np->pci_dev,
1339 skb->tail,
1340 skb->len, PCI_DMA_FROMDEVICE);
1341 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1342 }
1343 wmb();
1344 np->rx_ring[entry].status = DescOwn;
1345 }
1346
1347 return 0;
1348 }
1349
1350 static void netdev_error(struct net_device *dev, int intr_status)
1351 {
1352 long ioaddr = dev->base_addr;
1353 struct netdev_private *np = dev->priv;
1354
1355 if (debug > 2)
1356 printk(KERN_DEBUG "%s: Abnormal event, %8.8x.\n",
1357 dev->name, intr_status);
1358 if (intr_status == 0xffffffff)
1359 return;
1360 spin_lock(&np->lock);
1361 if (intr_status & TxFIFOUnderflow) {
1362 int new;
1363 /* Bump up the Tx threshold */
1364 #if 0
1365 /* This causes lots of dropped packets,
1366 * and under high load even tx_timeouts
1367 */
1368 new = np->csr6 + 0x4000;
1369 #else
1370 new = (np->csr6 >> 14)&0x7f;
1371 if (new < 64)
1372 new *= 2;
1373 else
1374 new = 127; /* load full packet before starting */
1375 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1376 #endif
1377 printk(KERN_DEBUG "%s: Tx underflow, new csr6 %8.8x.\n",
1378 dev->name, new);
1379 update_csr6(dev, new);
1380 }
1381 if (intr_status & IntrRxDied) { /* Missed a Rx frame. */
1382 np->stats.rx_errors++;
1383 }
1384 if (intr_status & TimerInt) {
1385 /* Re-enable other interrupts. */
1386 if (netif_device_present(dev))
1387 writel(0x1A0F5, ioaddr + IntrEnable);
1388 }
1389 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1390 writel(0, ioaddr + RxStartDemand);
1391 spin_unlock(&np->lock);
1392 }
1393
1394 static struct net_device_stats *get_stats(struct net_device *dev)
1395 {
1396 long ioaddr = dev->base_addr;
1397 struct netdev_private *np = dev->priv;
1398
1399 /* The chip only need report frame silently dropped. */
1400 spin_lock_irq(&np->lock);
1401 if (netif_running(dev) && netif_device_present(dev))
1402 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1403 spin_unlock_irq(&np->lock);
1404
1405 return &np->stats;
1406 }
1407
1408 static unsigned const ethernet_polynomial = 0x04c11db7U;
1409 static inline u32 ether_crc(int length, unsigned char *data)
1410 {
1411 int crc = -1;
1412
1413 while(--length >= 0) {
1414 unsigned char current_octet = *data++;
1415 int bit;
1416 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1417 crc = (crc << 1) ^
1418 ((crc < 0) ^ (current_octet & 1) ? ethernet_polynomial : 0);
1419 }
1420 }
1421 return crc;
1422 }
1423
1424 static u32 __set_rx_mode(struct net_device *dev)
1425 {
1426 long ioaddr = dev->base_addr;
1427 u32 mc_filter[2]; /* Multicast hash filter */
1428 u32 rx_mode;
1429
1430 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1431 /* Unconditionally log net taps. */
1432 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1433 memset(mc_filter, 0xff, sizeof(mc_filter));
1434 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAllPhys
1435 | AcceptMyPhys;
1436 } else if ((dev->mc_count > multicast_filter_limit)
1437 || (dev->flags & IFF_ALLMULTI)) {
1438 /* Too many to match, or accept all multicasts. */
1439 memset(mc_filter, 0xff, sizeof(mc_filter));
1440 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1441 } else {
1442 struct dev_mc_list *mclist;
1443 int i;
1444 memset(mc_filter, 0, sizeof(mc_filter));
1445 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1446 i++, mclist = mclist->next) {
1447 set_bit((ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F,
1448 mc_filter);
1449 }
1450 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1451 }
1452 writel(mc_filter[0], ioaddr + MulticastFilter0);
1453 writel(mc_filter[1], ioaddr + MulticastFilter1);
1454 return rx_mode;
1455 }
1456
1457 static void set_rx_mode(struct net_device *dev)
1458 {
1459 struct netdev_private *np = dev->priv;
1460 u32 rx_mode = __set_rx_mode(dev);
1461 spin_lock_irq(&np->lock);
1462 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1463 spin_unlock_irq(&np->lock);
1464 }
1465
1466 static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
1467 {
1468 struct netdev_private *np = dev->priv;
1469 u32 ethcmd;
1470
1471 if (copy_from_user(ðcmd, useraddr, sizeof(ethcmd)))
1472 return -EFAULT;
1473
1474 switch (ethcmd) {
1475 case ETHTOOL_GDRVINFO: {
1476 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
1477 strcpy(info.driver, DRV_NAME);
1478 strcpy(info.version, DRV_VERSION);
1479 strcpy(info.bus_info, np->pci_dev->slot_name);
1480 if (copy_to_user(useraddr, &info, sizeof(info)))
1481 return -EFAULT;
1482 return 0;
1483 }
1484
1485 }
1486
1487 return -EOPNOTSUPP;
1488 }
1489
1490 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1491 {
1492 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1493 struct netdev_private *np = dev->priv;
1494
1495 switch(cmd) {
1496 case SIOCETHTOOL:
1497 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
1498 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1499 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1500 data->phy_id = ((struct netdev_private *)dev->priv)->phys[0] & 0x1f;
1501 /* Fall Through */
1502
1503 case SIOCGMIIREG: /* Read MII PHY register. */
1504 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1505 spin_lock_irq(&np->lock);
1506 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1507 spin_unlock_irq(&np->lock);
1508 return 0;
1509
1510 case SIOCSMIIREG: /* Write MII PHY register. */
1511 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1512 if (!capable(CAP_NET_ADMIN))
1513 return -EPERM;
1514 spin_lock_irq(&np->lock);
1515 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1516 spin_unlock_irq(&np->lock);
1517 return 0;
1518 default:
1519 return -EOPNOTSUPP;
1520 }
1521 }
1522
1523 static int netdev_close(struct net_device *dev)
1524 {
1525 long ioaddr = dev->base_addr;
1526 struct netdev_private *np = dev->priv;
1527
1528 netif_stop_queue(dev);
1529
1530 if (debug > 1) {
1531 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %8.8x "
1532 "Config %8.8x.\n", dev->name, (int)readl(ioaddr + IntrStatus),
1533 (int)readl(ioaddr + NetworkConfig));
1534 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1535 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1536 }
1537
1538 /* Stop the chip's Tx and Rx processes. */
1539 spin_lock_irq(&np->lock);
1540 netif_device_detach(dev);
1541 update_csr6(dev, 0);
1542 writel(0x0000, ioaddr + IntrEnable);
1543 spin_unlock_irq(&np->lock);
1544
1545 free_irq(dev->irq, dev);
1546 wmb();
1547 netif_device_attach(dev);
1548
1549 if (readl(ioaddr + NetworkConfig) != 0xffffffff)
1550 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1551
1552 #ifdef __i386__
1553 if (debug > 2) {
1554 int i;
1555
1556 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1557 (int)np->tx_ring);
1558 for (i = 0; i < TX_RING_SIZE; i++)
1559 printk(" #%d desc. %4.4x %4.4x %8.8x.\n",
1560 i, np->tx_ring[i].length,
1561 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1562 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1563 (int)np->rx_ring);
1564 for (i = 0; i < RX_RING_SIZE; i++) {
1565 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1566 i, np->rx_ring[i].length,
1567 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1568 }
1569 }
1570 #endif /* __i386__ debugging only */
1571
1572 del_timer_sync(&np->timer);
1573
1574 free_rxtx_rings(np);
1575 free_ringdesc(np);
1576
1577 return 0;
1578 }
1579
1580 static void __devexit w840_remove1 (struct pci_dev *pdev)
1581 {
1582 struct net_device *dev = pci_get_drvdata(pdev);
1583
1584 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1585 if (dev) {
1586 unregister_netdev(dev);
1587 pci_release_regions(pdev);
1588 #ifndef USE_IO_OPS
1589 iounmap((char *)(dev->base_addr));
1590 #endif
1591 kfree(dev);
1592 }
1593
1594 pci_set_drvdata(pdev, NULL);
1595 }
1596
1597 #ifdef CONFIG_PM
1598
1599 /*
1600 * suspend/resume synchronization:
1601 * - open, close, do_ioctl:
1602 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1603 * - get_stats:
1604 * spin_lock_irq(np->lock), doesn't touch hw if not present
1605 * - hard_start_xmit:
1606 * netif_stop_queue + spin_unlock_wait(&dev->xmit_lock);
1607 * - tx_timeout:
1608 * netif_device_detach + spin_unlock_wait(&dev->xmit_lock);
1609 * - set_multicast_list
1610 * netif_device_detach + spin_unlock_wait(&dev->xmit_lock);
1611 * - interrupt handler
1612 * doesn't touch hw if not present, synchronize_irq waits for
1613 * running instances of the interrupt handler.
1614 *
1615 * Disabling hw requires clearing csr6 & IntrEnable.
1616 * update_csr6 & all function that write IntrEnable check netif_device_present
1617 * before settings any bits.
1618 *
1619 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1620 * device would cause an irq storm.
1621 */
1622 static int w840_suspend (struct pci_dev *pdev, u32 state)
1623 {
1624 struct net_device *dev = pci_get_drvdata (pdev);
1625 struct netdev_private *np = dev->priv;
1626 long ioaddr = dev->base_addr;
1627
1628 rtnl_lock();
1629 if (netif_running (dev)) {
1630 del_timer_sync(&np->timer);
1631
1632 spin_lock_irq(&np->lock);
1633 netif_device_detach(dev);
1634 update_csr6(dev, 0);
1635 writel(0, ioaddr + IntrEnable);
1636 netif_stop_queue(dev);
1637 spin_unlock_irq(&np->lock);
1638
1639 spin_unlock_wait(&dev->xmit_lock);
1640 synchronize_irq();
1641
1642 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1643
1644 /* no more hardware accesses behind this line. */
1645
1646 if (np->csr6) BUG();
1647 if (readl(ioaddr + IntrEnable)) BUG();
1648
1649 /* pci_power_off(pdev, -1); */
1650
1651 free_rxtx_rings(np);
1652 } else {
1653 netif_device_detach(dev);
1654 }
1655 rtnl_unlock();
1656 return 0;
1657 }
1658
1659
1660 static int w840_resume (struct pci_dev *pdev)
1661 {
1662 struct net_device *dev = pci_get_drvdata (pdev);
1663 struct netdev_private *np = dev->priv;
1664
1665 rtnl_lock();
1666 if (netif_device_present(dev))
1667 goto out; /* device not suspended */
1668 if (netif_running(dev)) {
1669 pci_enable_device(pdev);
1670 /* pci_power_on(pdev); */
1671
1672 spin_lock_irq(&np->lock);
1673 writel(1, dev->base_addr+PCIBusCfg);
1674 readl(dev->base_addr+PCIBusCfg);
1675 udelay(1);
1676 netif_device_attach(dev);
1677 init_rxtx_rings(dev);
1678 init_registers(dev);
1679 spin_unlock_irq(&np->lock);
1680
1681 netif_wake_queue(dev);
1682
1683 np->timer.expires = jiffies + 1*HZ;
1684 add_timer(&np->timer);
1685 } else {
1686 netif_device_attach(dev);
1687 }
1688 out:
1689 rtnl_unlock();
1690 return 0;
1691 }
1692 #endif
1693
1694 static struct pci_driver w840_driver = {
1695 name: DRV_NAME,
1696 id_table: w840_pci_tbl,
1697 probe: w840_probe1,
1698 remove: w840_remove1,
1699 #ifdef CONFIG_PM
1700 suspend: w840_suspend,
1701 resume: w840_resume,
1702 #endif
1703 };
1704
1705 static int __init w840_init(void)
1706 {
1707 /* when a module, this is printed whether or not devices are found in probe */
1708 #ifdef MODULE
1709 printk(version);
1710 #endif
1711 return pci_module_init(&w840_driver);
1712 }
1713
1714 static void __exit w840_exit(void)
1715 {
1716 pci_unregister_driver(&w840_driver);
1717 }
1718
1719 module_init(w840_init);
1720 module_exit(w840_exit);
1721