File: /usr/src/linux/arch/cris/drivers/ide.c
1 /* $Id: ide.c,v 1.19 2001/05/09 12:53:16 johana Exp $
2 *
3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
5 * Copyright (c) 2000, 2001 Axis Communications AB
6 *
7 * Authors: Bjorn Wesen (initial version)
8 * Mikael Starvik (pio setup stuff)
9 *
10 * $Log: ide.c,v $
11 * Revision 1.19 2001/05/09 12:53:16 johana
12 * Added #include <asm/dma.h>
13 *
14 * Revision 1.18 2001/05/09 12:37:00 johana
15 * Use DMA_NBR macros from dma.h.
16 *
17 * Revision 1.17 2001/04/23 13:36:30 matsfg
18 * Changed CONFIG_IDE_DELAY to CONFIG_ETRAX_IDE_DELAY
19 *
20 * Revision 1.16 2001/04/05 08:30:07 matsfg
21 * Corrected cse1 and csp0 reset.
22 *
23 * Revision 1.15 2001/04/04 14:34:06 bjornw
24 * Re-instated code that mysteriously disappeared during review updates.
25 *
26 * Revision 1.14 2001/04/04 13:45:12 matsfg
27 * Calls REG_SHADOW_SET for cse1 reset so only the resetbit is affected
28 *
29 * Revision 1.13 2001/04/04 13:26:40 matsfg
30 * memmapping is done in init.c
31 *
32 * Revision 1.12 2001/04/04 11:37:56 markusl
33 * Updated according to review remarks
34 *
35 * Revision 1.11 2001/03/29 12:49:14 matsfg
36 * Changed check for ata_tot_size from >= to >.
37 * Sets sw_len to 0 if size is exactly 65536.
38 *
39 * Revision 1.10 2001/03/16 09:39:30 matsfg
40 * Support for reset on port CSP0
41 *
42 * Revision 1.9 2001/03/01 13:11:18 bjornw
43 * 100 -> HZ
44 *
45 * Revision 1.8 2001/03/01 09:32:56 matsfg
46 * Moved IDE delay to a CONFIG-parameter instead
47 *
48 * Revision 1.7 2001/02/23 13:46:38 bjornw
49 * Spellling check
50 *
51 * Revision 1.6 2001/02/22 15:44:30 bjornw
52 * * Use ioremap when mapping the CSE1 memory-mapped reset-line for LX v2
53 * * sw_len for a 65536 descriptor is 0, not 65536
54 * * Express concern for G27 reset code
55 *
56 * Revision 1.5 2001/02/16 07:35:38 matsfg
57 * Now handles DMA request blocks between 64k and 128k by split into two descriptors.
58 *
59 * Revision 1.4 2001/01/10 21:14:32 bjornw
60 * Initialize hwif->ideproc, for the new way of handling ide_xxx_data
61 *
62 * Revision 1.3 2000/12/01 17:48:18 bjornw
63 * - atapi_output_bytes now uses DMA
64 * - dma_active check removed - the kernel does proper serializing and it had
65 * a race-condition anyway
66 * - ide_build_dmatable had a nameclash
67 * - re-added the RESET_DMA thingys because sometimes the interface can get
68 * stuck apparently
69 * - added ide_release_dma
70 *
71 * Revision 1.2 2000/11/29 17:31:29 bjornw
72 * 2.4 port
73 *
74 * - The "register addresses" stored in the hwif are now 32-bit fields that
75 * don't need to be shifted into correct positions in R_ATA_CTRL_DATA
76 * - PIO-mode detection temporarily disabled since ide-modes.c is not compiled
77 * - All DMA uses virt_to_phys conversions for DMA buffers and descriptor ptrs
78 * - Probably correct ide_dma_begin semantics in dmaproc now for ATAPI devices
79 * - Removed RESET_DMA when starting a new transfer - why was this necessary ?
80 * - Indentation fix
81 *
82 *
83 */
84
85 /* Regarding DMA:
86 *
87 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
88 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
89 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
90 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
91 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
92 */
93
94 #undef REALLY_SLOW_IO /* most systems can safely undef this */
95
96 #include <linux/config.h>
97 #include <linux/types.h>
98 #include <linux/kernel.h>
99 #include <linux/timer.h>
100 #include <linux/mm.h>
101 #include <linux/interrupt.h>
102 #include <linux/delay.h>
103 #include <linux/blkdev.h>
104 #include <linux/hdreg.h>
105 #include <linux/ide.h>
106 #include <linux/init.h>
107
108 #include <asm/io.h>
109 #include <asm/svinto.h>
110 #include <asm/dma.h>
111
112 /* number of Etrax DMA descriptors */
113 #define MAX_DMA_DESCRS 64
114
115 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
116 /* address where the memory-mapped IDE reset bit lives, if used */
117 static volatile unsigned long *reset_addr;
118 #endif
119
120 #define LOWDB(x)
121 #define D(x)
122
123 void OUT_BYTE(unsigned char data, ide_ioreg_t reg) {
124 LOWDB(printk("ob: data 0x%x, reg 0x%x\n", data, reg));
125 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag */
126 *R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */
127 while(!(*R_ATA_STATUS_DATA &
128 IO_MASK(R_ATA_STATUS_DATA, tr_rdy))); /* wait for transmitter ready */
129 }
130
131 unsigned char IN_BYTE(ide_ioreg_t reg) {
132 int status;
133 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag */
134 *R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */
135 while(!((status = *R_ATA_STATUS_DATA) &
136 IO_MASK(R_ATA_STATUS_DATA, dav))); /* wait for available */
137 LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg));
138 return (unsigned char)status; /* data was in the lower 16 bits in the status reg */
139 }
140
141 /* PIO timing (in R_ATA_CONFIG)
142 *
143 * _____________________________
144 * ADDRESS : ________/
145 *
146 * _______________
147 * DIOR : ____________/ \__________
148 *
149 * _______________
150 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
151 *
152 *
153 * DIOR is unbuffered while address and data is buffered.
154 * This creates two problems:
155 * 1. The DIOR pulse is to early (because it is unbuffered)
156 * 2. The rise time of DIOR is long
157 *
158 * There are at least three different plausible solutions
159 * 1. Use a pad capable of larger currents in Etrax
160 * 2. Use an external buffer
161 * 3. Make the strobe pulse longer
162 *
163 * Some of the strobe timings below are modified to compensate
164 * for this. This implies a slight performance decrease.
165 *
166 * THIS SHOULD NEVER BE CHANGED!
167 *
168 * TODO: Is this true for the latest LX boards still ?
169 */
170
171 #define ATA_DMA2_STROBE 4
172 #define ATA_DMA2_HOLD 0
173 #define ATA_DMA1_STROBE 4
174 #define ATA_DMA1_HOLD 1
175 #define ATA_DMA0_STROBE 12
176 #define ATA_DMA0_HOLD 9
177 #define ATA_PIO4_SETUP 1
178 #define ATA_PIO4_STROBE 5
179 #define ATA_PIO4_HOLD 0
180 #define ATA_PIO3_SETUP 1
181 #define ATA_PIO3_STROBE 5
182 #define ATA_PIO3_HOLD 1
183 #define ATA_PIO2_SETUP 1
184 #define ATA_PIO2_STROBE 6
185 #define ATA_PIO2_HOLD 2
186 #define ATA_PIO1_SETUP 2
187 #define ATA_PIO1_STROBE 11
188 #define ATA_PIO1_HOLD 4
189 #define ATA_PIO0_SETUP 4
190 #define ATA_PIO0_STROBE 19
191 #define ATA_PIO0_HOLD 4
192
193 static int e100_dmaproc (ide_dma_action_t func, ide_drive_t *drive);
194 static void e100_ideproc (ide_ide_action_t func, ide_drive_t *drive,
195 void *buffer, unsigned int length);
196
197 /*
198 * good_dma_drives() lists the model names (from "hdparm -i")
199 * of drives which do not support mword2 DMA but which are
200 * known to work fine with this interface under Linux.
201 */
202
203 const char *good_dma_drives[] = {"Micropolis 2112A",
204 "CONNER CTMA 4000",
205 "CONNER CTT8000-A",
206 NULL};
207
208 static void tune_e100_ide(ide_drive_t *drive, byte pio)
209 {
210 unsigned long flags;
211
212 pio = 4;
213 /* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */
214
215 save_flags(flags);
216 cli();
217
218 /* set pio mode! */
219
220 switch(pio) {
221 case 0:
222 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
223 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
224 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
225 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO0_SETUP ) |
226 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) |
227 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO0_HOLD ) );
228 break;
229 case 1:
230 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
231 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
232 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
233 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO1_SETUP ) |
234 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) |
235 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO1_HOLD ) );
236 break;
237 case 2:
238 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
239 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
240 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
241 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO2_SETUP ) |
242 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) |
243 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO2_HOLD ) );
244 break;
245 case 3:
246 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
247 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
248 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
249 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO3_SETUP ) |
250 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) |
251 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO3_HOLD ) );
252 break;
253 case 4:
254 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
255 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
256 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
257 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) |
258 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
259 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) );
260 break;
261 }
262 restore_flags(flags);
263 }
264
265 void __init
266 init_e100_ide (void)
267 {
268 volatile unsigned int dummy;
269 int h;
270
271 printk("ide: ETRAX 100LX built-in ATA DMA controller\n");
272
273 /* first fill in some stuff in the ide_hwifs fields */
274
275 for(h = 0; h < MAX_HWIFS; h++) {
276 ide_hwif_t *hwif = &ide_hwifs[h];
277 hwif->chipset = ide_etrax100;
278 hwif->tuneproc = &tune_e100_ide;
279 hwif->dmaproc = &e100_dmaproc;
280 hwif->ideproc = &e100_ideproc;
281 }
282 /* actually reset and configure the etrax100 ide/ata interface */
283
284 /* This is mystifying; why is not G27 SET anywhere ? It's just reset here twice. */
285
286 /* de-assert bus-reset */
287 #ifdef CONFIG_ETRAX_IDE_PB7_RESET
288 port_pb_dir_shadow = port_pb_dir_shadow |
289 IO_STATE(R_PORT_PB_DIR, dir7, output);
290 *R_PORT_PB_DIR = port_pb_dir_shadow;
291 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
292 #endif
293 #ifdef CONFIG_ETRAX_IDE_G27_RESET
294 *R_PORT_G_DATA = 0;
295 #endif
296
297 *R_ATA_CTRL_DATA = 0;
298 *R_ATA_TRANSFER_CNT = 0;
299 *R_ATA_CONFIG = 0;
300
301 genconfig_shadow = (genconfig_shadow &
302 ~IO_MASK(R_GEN_CONFIG, dma2) &
303 ~IO_MASK(R_GEN_CONFIG, dma3) &
304 ~IO_MASK(R_GEN_CONFIG, ata)) |
305 ( IO_STATE( R_GEN_CONFIG, dma3, ata ) |
306 IO_STATE( R_GEN_CONFIG, dma2, ata ) |
307 IO_STATE( R_GEN_CONFIG, ata, select ) );
308
309 *R_GEN_CONFIG = genconfig_shadow;
310
311 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
312 init_ioremap();
313 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0);
314 #endif
315
316 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
317 init_ioremap();
318 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0);
319 #endif
320
321 /* wait some */
322 udelay(25);
323
324 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
325 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1);
326 #endif
327 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
328 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1);
329 #endif
330 #ifdef CONFIG_ETRAX_IDE_G27_RESET
331 *R_PORT_G_DATA = 0; /* de-assert bus-reset */
332 #endif
333
334 /* make a dummy read to set the ata controller in a proper state */
335 dummy = *R_ATA_STATUS_DATA;
336
337 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
338 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
339 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
340 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) |
341 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
342 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) );
343
344 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
345 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
346
347 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
348
349 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
350 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
351 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
352 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
353
354 printk("ide: waiting %d seconds for drives to regain consciousness\n", CONFIG_ETRAX_IDE_DELAY);
355
356 h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ);
357 while(jiffies < h) ;
358
359 /* reset the dma channels we will use */
360
361 RESET_DMA(ATA_TX_DMA_NBR);
362 RESET_DMA(ATA_RX_DMA_NBR);
363 WAIT_DMA(ATA_TX_DMA_NBR);
364 WAIT_DMA(ATA_RX_DMA_NBR);
365
366 }
367
368 static etrax_dma_descr mydescr;
369
370 /*
371 * The following routines are mainly used by the ATAPI drivers.
372 *
373 * These routines will round up any request for an odd number of bytes,
374 * so if an odd bytecount is specified, be sure that there's at least one
375 * extra byte allocated for the buffer.
376 */
377 static void
378 e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
379 {
380 ide_ioreg_t data_reg = IDE_DATA_REG;
381
382 D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
383 data_reg, buffer, bytecount));
384
385 if(bytecount & 1) {
386 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
387 bytecount++; /* to round off */
388 }
389
390 /* make sure the DMA channel is available */
391 RESET_DMA(ATA_RX_DMA_NBR);
392 WAIT_DMA(ATA_RX_DMA_NBR);
393
394 /* setup DMA descriptor */
395
396 mydescr.sw_len = bytecount;
397 mydescr.ctrl = d_eol;
398 mydescr.buf = virt_to_phys(buffer);
399
400 /* start the dma channel */
401
402 *R_DMA_CH3_FIRST = virt_to_phys(&mydescr);
403 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
404
405 /* initiate a multi word dma read using PIO handshaking */
406
407 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
408
409 *R_ATA_CTRL_DATA = data_reg |
410 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
411 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
412 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
413 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
414 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
415
416 /* wait for completion */
417
418 LED_DISK_READ(1);
419 WAIT_DMA(ATA_RX_DMA_NBR);
420 LED_DISK_READ(0);
421
422 #if 0
423 /* old polled transfer code
424 * this should be moved into a new function that can do polled
425 * transfers if DMA is not available
426 */
427
428 /* initiate a multi word read */
429
430 *R_ATA_TRANSFER_CNT = wcount << 1;
431
432 *R_ATA_CTRL_DATA = data_reg |
433 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
434 IO_STATE(R_ATA_CTRL_DATA, src_dst, register) |
435 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
436 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
437 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
438
439 /* svinto has a latency until the busy bit actually is set */
440
441 nop(); nop();
442 nop(); nop();
443 nop(); nop();
444 nop(); nop();
445 nop(); nop();
446
447 /* unit should be busy during multi transfer */
448 while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) {
449 while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav)))
450 status = *R_ATA_STATUS_DATA;
451 *ptr++ = (unsigned short)(status & 0xffff);
452 }
453 #endif
454 }
455
456 static void
457 e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
458 {
459 ide_ioreg_t data_reg = IDE_DATA_REG;
460
461 D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
462 data_reg, buffer, bytecount));
463
464 if(bytecount & 1) {
465 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
466 bytecount++;
467 }
468
469 /* make sure the DMA channel is available */
470 RESET_DMA(ATA_TX_DMA_NBR);
471 WAIT_DMA(ATA_TX_DMA_NBR);
472
473 /* setup DMA descriptor */
474
475 mydescr.sw_len = bytecount;
476 mydescr.ctrl = d_eol;
477 mydescr.buf = virt_to_phys(buffer);
478
479 /* start the dma channel */
480
481 *R_DMA_CH2_FIRST = virt_to_phys(&mydescr);
482 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
483
484 /* initiate a multi word dma write using PIO handshaking */
485
486 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
487
488 *R_ATA_CTRL_DATA = data_reg |
489 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
490 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
491 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
492 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
493 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
494
495 /* wait for completion */
496
497 LED_DISK_WRITE(1);
498 WAIT_DMA(ATA_TX_DMA_NBR);
499 LED_DISK_WRITE(0);
500
501 #if 0
502 /* old polled write code - see comment in input_bytes */
503
504 /* wait for busy flag */
505 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
506
507 /* initiate a multi word write */
508
509 *R_ATA_TRANSFER_CNT = bytecount >> 1;
510
511 ctrl = data_reg |
512 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
513 IO_STATE(R_ATA_CTRL_DATA, src_dst, register) |
514 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
515 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
516 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
517
518 LED_DISK_WRITE(1);
519
520 /* Etrax will set busy = 1 until the multi pio transfer has finished
521 * and tr_rdy = 1 after each succesful word transfer.
522 * When the last byte has been transferred Etrax will first set tr_tdy = 1
523 * and then busy = 0 (not in the same cycle). If we read busy before it
524 * has been set to 0 we will think that we should transfer more bytes
525 * and then tr_rdy would be 0 forever. This is solved by checking busy
526 * in the inner loop.
527 */
528
529 do {
530 *R_ATA_CTRL_DATA = ctrl | *ptr++;
531 while(!(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy)) &&
532 (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)));
533 } while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
534
535 LED_DISK_WRITE(0);
536 #endif
537
538 }
539
540 /*
541 * This is used for most PIO data transfers *from* the IDE interface
542 */
543 static void
544 e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
545 {
546 e100_atapi_input_bytes(drive, buffer, wcount << 2);
547 }
548
549 /*
550 * This is used for most PIO data transfers *to* the IDE interface
551 */
552 static void
553 e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
554 {
555 e100_atapi_output_bytes(drive, buffer, wcount << 2);
556 }
557
558 /*
559 * The multiplexor for ide_xxxput_data and atapi calls
560 */
561 static void
562 e100_ideproc (ide_ide_action_t func, ide_drive_t *drive,
563 void *buffer, unsigned int length)
564 {
565 switch (func) {
566 case ideproc_ide_input_data:
567 e100_ide_input_data(drive, buffer, length);
568 break;
569 case ideproc_ide_output_data:
570 e100_ide_input_data(drive, buffer, length);
571 break;
572 case ideproc_atapi_input_bytes:
573 e100_atapi_input_bytes(drive, buffer, length);
574 break;
575 case ideproc_atapi_output_bytes:
576 e100_atapi_output_bytes(drive, buffer, length);
577 break;
578 default:
579 printk("e100_ideproc: unsupported func %d!\n", func);
580 break;
581 }
582 }
583
584 /* we only have one DMA channel on the chip for ATA, so we can keep these statically */
585 static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS];
586 static unsigned int ata_tot_size;
587
588 /*
589 * e100_ide_build_dmatable() prepares a dma request.
590 * Returns 0 if all went okay, returns 1 otherwise.
591 */
592 static int e100_ide_build_dmatable (ide_drive_t *drive)
593 {
594 struct request *rq = HWGROUP(drive)->rq;
595 struct buffer_head *bh = rq->bh;
596 unsigned long size, addr;
597 unsigned int count = 0;
598
599 ata_tot_size = 0;
600
601 do {
602 /*
603 * Determine addr and size of next buffer area. We assume that
604 * individual virtual buffers are always composed linearly in
605 * physical memory. For example, we assume that any 8kB buffer
606 * is always composed of two adjacent physical 4kB pages rather
607 * than two possibly non-adjacent physical 4kB pages.
608 */
609 if (bh == NULL) { /* paging and tape requests have (rq->bh == NULL) */
610 addr = virt_to_phys (rq->buffer);
611 size = rq->nr_sectors << 9;
612 } else {
613 /* group sequential buffers into one large buffer */
614 addr = virt_to_phys (bh->b_data);
615 size = bh->b_size;
616 while ((bh = bh->b_reqnext) != NULL) {
617 if ((addr + size) != virt_to_phys (bh->b_data))
618 break;
619 size += bh->b_size;
620 }
621 }
622
623 /* did we run out of descriptors? */
624
625 if(count >= MAX_DMA_DESCRS) {
626 printk("%s: too few DMA descriptors\n", drive->name);
627 return 1;
628 }
629
630 /* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more
631 than 65536 words per transfer, so in that case we need to either
632 1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with
633 the descriptors, or
634 2) simply do the request here, and get dma_intr to only ide_end_request on
635 those blocks that were actually set-up for transfer.
636 */
637
638 if(ata_tot_size + size > 131072) {
639 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, size);
640 return 1;
641 }
642
643 /* If size > 65536 it has to be splitted into new descriptors. Since we don't handle
644 size > 131072 only one split is necessary */
645
646 if(size > 65536) {
647 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
648 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */
649 ata_descrs[count].ctrl = 0;
650 ata_descrs[count].buf = addr;
651 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
652 count++;
653 ata_tot_size += 65536;
654 /* size and addr should refere to not handled data */
655 size -= 65536;
656 addr += 65536;
657 }
658 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
659 if(size == 65536) {
660 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */
661 }
662 else {
663 ata_descrs[count].sw_len = size;
664 }
665 ata_descrs[count].ctrl = 0;
666 ata_descrs[count].buf = addr;
667 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
668 count++;
669 ata_tot_size += size;
670
671 } while (bh != NULL);
672
673 if (count) {
674 /* set the end-of-list flag on the last descriptor */
675 ata_descrs[count - 1].ctrl |= d_eol;
676 /* return and say all is ok */
677 return 0;
678 }
679
680 printk("%s: empty DMA table?\n", drive->name);
681 return 1; /* let the PIO routines handle this weirdness */
682 }
683
684 static int config_drive_for_dma (ide_drive_t *drive)
685 {
686 const char **list;
687 struct hd_driveid *id = drive->id;
688
689 if (id && (id->capability & 1)) {
690 /* Enable DMA on any drive that supports mword2 DMA */
691 if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
692 drive->using_dma = 1;
693 return 0; /* DMA enabled */
694 }
695
696 /* Consult the list of known "good" drives */
697 list = good_dma_drives;
698 while (*list) {
699 if (!strcmp(*list++,id->model)) {
700 drive->using_dma = 1;
701 return 0; /* DMA enabled */
702 }
703 }
704 }
705 return 1; /* DMA not enabled */
706 }
707
708 /*
709 * etrax_dma_intr() is the handler for disk read/write DMA interrupts
710 */
711 static ide_startstop_t etrax_dma_intr (ide_drive_t *drive)
712 {
713 int i, dma_stat;
714 byte stat;
715
716 LED_DISK_READ(0);
717 LED_DISK_WRITE(0);
718
719 dma_stat = HWIF(drive)->dmaproc(ide_dma_end, drive);
720 stat = GET_STAT(); /* get drive status */
721 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
722 if (!dma_stat) {
723 struct request *rq;
724 rq = HWGROUP(drive)->rq;
725 for (i = rq->nr_sectors; i > 0;) {
726 i -= rq->current_nr_sectors;
727 ide_end_request(1, HWGROUP(drive));
728 }
729 return ide_stopped;
730 }
731 printk("%s: bad DMA status\n", drive->name);
732 }
733 return ide_error(drive, "dma_intr", stat);
734 }
735
736 /*
737 * e100_dmaproc() initiates/aborts DMA read/write operations on a drive.
738 *
739 * The caller is assumed to have selected the drive and programmed the drive's
740 * sector address using CHS or LBA. All that remains is to prepare for DMA
741 * and then issue the actual read/write DMA/PIO command to the drive.
742 *
743 * For ATAPI devices, we just prepare for DMA and return. The caller should
744 * then issue the packet command to the drive and call us again with
745 * ide_dma_begin afterwards.
746 *
747 * Returns 0 if all went well.
748 * Returns 1 if DMA read/write could not be started, in which case
749 * the caller should revert to PIO for the current request.
750 */
751
752 static int e100_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
753 {
754 static unsigned int reading; /* static to support ide_dma_begin semantics */
755 int atapi = 0;
756
757 D(printk("e100_dmaproc func %d\n", func));
758
759 switch (func) {
760 case ide_dma_verbose:
761 return 0;
762 case ide_dma_check:
763 return config_drive_for_dma (drive);
764 case ide_dma_off:
765 case ide_dma_off_quietly:
766 /* ok.. we don't really need to do anything I think. */
767 return 0;
768 case ide_dma_write:
769 reading = 0;
770 break;
771 case ide_dma_read:
772 reading = 1;
773 break;
774 case ide_dma_begin:
775 /* begin DMA, used by ATAPI devices which want to issue the
776 * appropriate IDE command themselves.
777 *
778 * they have already called ide_dma_read/write to set the
779 * static reading flag, now they call ide_dma_begin to do
780 * the real stuff. we tell our code below not to issue
781 * any IDE commands itself and jump into it.
782 */
783 atapi++;
784 goto dma_begin;
785 case ide_dma_end: /* returns 1 on error, 0 otherwise */
786 /* TODO: check if something went wrong with the DMA */
787 return 0;
788
789 default:
790 printk("e100_dmaproc: unsupported func %d\n", func);
791 return 1;
792 }
793
794 /* ATAPI-devices (not disks) first call ide_dma_read/write to set the direction
795 * then they call ide_dma_begin after they have issued the appropriate drive command
796 * themselves to actually start the chipset DMA. so we just return here if we're
797 * not a diskdrive.
798 */
799
800 if (drive->media != ide_disk)
801 return 0;
802
803 dma_begin:
804
805 if(reading) {
806
807 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
808 WAIT_DMA(ATA_RX_DMA_NBR);
809
810 /* set up the Etrax DMA descriptors */
811
812 if(e100_ide_build_dmatable (drive))
813 return 1;
814
815 if(!atapi) {
816 /* set the irq handler which will finish the request when DMA is done */
817
818 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);
819
820 /* issue cmd to drive */
821
822 OUT_BYTE(WIN_READDMA, IDE_COMMAND_REG);
823 }
824
825 /* begin DMA */
826
827 *R_DMA_CH3_FIRST = virt_to_phys(ata_descrs);
828 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
829
830 /* initiate a multi word dma read using DMA handshaking */
831
832 *R_ATA_TRANSFER_CNT =
833 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
834
835 *R_ATA_CTRL_DATA =
836 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
837 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
838 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
839 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) |
840 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
841 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
842
843 LED_DISK_READ(1);
844
845 D(printk("dma read of %d bytes.\n", ata_tot_size));
846
847 } else {
848 /* writing */
849
850 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
851 WAIT_DMA(ATA_TX_DMA_NBR);
852
853 /* set up the Etrax DMA descriptors */
854
855 if(e100_ide_build_dmatable (drive))
856 return 1;
857
858 if(!atapi) {
859 /* set the irq handler which will finish the request when DMA is done */
860
861 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);
862
863 /* issue cmd to drive */
864
865 OUT_BYTE(WIN_WRITEDMA, IDE_COMMAND_REG);
866 }
867
868 /* begin DMA */
869
870 *R_DMA_CH2_FIRST = virt_to_phys(ata_descrs);
871 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
872
873 /* initiate a multi word dma write using DMA handshaking */
874
875 *R_ATA_TRANSFER_CNT =
876 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
877
878 *R_ATA_CTRL_DATA =
879 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
880 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
881 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
882 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) |
883 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
884 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
885
886 LED_DISK_WRITE(1);
887
888 D(printk("dma write of %d bytes.\n", ata_tot_size));
889 }
890
891 /* DMA started successfully */
892 return 0;
893 }
894
895 /* ide.c calls this, but we don't need to do anything particular */
896
897 int ide_release_dma (ide_hwif_t *hwif)
898 {
899 return 1;
900 }
901