File: /usr/src/linux/drivers/net/yellowfin.c
1 /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2 /*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22
23
24 Linux kernel changelog:
25 -----------------------
26
27 LK1.1.1 (jgarzik): Port to 2.4 kernel
28
29 LK1.1.2 (jgarzik):
30 * Merge in becker version 1.05
31
32 LK1.1.3 (jgarzik):
33 * Various cleanups
34 * Update yellowfin_timer to correctly calculate duplex.
35 (suggested by Manfred Spraul)
36
37 LK1.1.4 (val@nmt.edu):
38 * Fix three endian-ness bugs
39 * Support dual function SYM53C885E ethernet chip
40
41 */
42
43 #define DRV_NAME "yellowfin"
44 #define DRV_VERSION "1.05+LK1.1.3"
45 #define DRV_RELDATE "May 10, 2001"
46
47 #define PFX DRV_NAME ": "
48
49 /* The user-configurable values.
50 These may be modified when a driver module is loaded.*/
51
52 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
53 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
54 static int max_interrupt_work = 20;
55 static int mtu;
56 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
57 /* System-wide count of bogus-rx frames. */
58 static int bogus_rx;
59 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
60 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
61 #elif YF_NEW /* A future perfect board :->. */
62 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
63 static int fifo_cfg = 0x0028;
64 #else
65 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
66 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
67 #endif
68
69 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
70 Setting to > 1514 effectively disables this feature. */
71 static int rx_copybreak;
72
73 /* Used to pass the media type, etc.
74 No media types are currently defined. These exist for driver
75 interoperability.
76 */
77 #define MAX_UNITS 8 /* More are supported, limit only on options */
78 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
79 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
80
81 /* Do ugly workaround for GX server chipset errata. */
82 static int gx_fix;
83
84 /* Operational parameters that are set at compile time. */
85
86 /* Keep the ring sizes a power of two for efficiency.
87 Making the Tx ring too long decreases the effectiveness of channel
88 bonding and packet priority.
89 There are no ill effects from too-large receive rings. */
90 #define TX_RING_SIZE 16
91 #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
92 #define RX_RING_SIZE 64
93 #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
94 #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
95 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
96
97 /* Operational parameters that usually are not changed. */
98 /* Time in jiffies before concluding the transmitter is hung. */
99 #define TX_TIMEOUT (2*HZ)
100 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
101
102 #define yellowfin_debug debug
103
104 #if !defined(__OPTIMIZE__)
105 #warning You must compile this file with the correct options!
106 #warning See the last lines of the source file.
107 #error You must compile this driver with "-O".
108 #endif
109
110 #include <linux/module.h>
111 #include <linux/kernel.h>
112 #include <linux/string.h>
113 #include <linux/timer.h>
114 #include <linux/errno.h>
115 #include <linux/ioport.h>
116 #include <linux/slab.h>
117 #include <linux/interrupt.h>
118 #include <linux/pci.h>
119 #include <linux/init.h>
120 #include <linux/mii.h>
121 #include <linux/netdevice.h>
122 #include <linux/etherdevice.h>
123 #include <linux/skbuff.h>
124 #include <linux/ethtool.h>
125 #include <asm/uaccess.h>
126 #include <asm/processor.h> /* Processor type for cache alignment. */
127 #include <asm/unaligned.h>
128 #include <asm/bitops.h>
129 #include <asm/io.h>
130
131 /* These identify the driver base version and may not be removed. */
132 static char version[] __devinitdata =
133 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
134 KERN_INFO " http://www.scyld.com/network/yellowfin.html\n"
135 KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
136
137 #ifndef USE_IO_OPS
138 #undef inb
139 #undef inw
140 #undef inl
141 #undef outb
142 #undef outw
143 #undef outl
144 #define inb readb
145 #define inw readw
146 #define inl readl
147 #define outb writeb
148 #define outw writew
149 #define outl writel
150 #endif /* !USE_IO_OPS */
151 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
152 MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
153 MODULE_PARM(max_interrupt_work, "i");
154 MODULE_PARM(mtu, "i");
155 MODULE_PARM(debug, "i");
156 MODULE_PARM(rx_copybreak, "i");
157 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
158 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
159 MODULE_PARM(gx_fix, "i");
160 MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
161 MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
162 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
163 MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
164 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
165 MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
166 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
167
168 /*
169 Theory of Operation
170
171 I. Board Compatibility
172
173 This device driver is designed for the Packet Engines "Yellowfin" Gigabit
174 Ethernet adapter. The only PCA currently supported is the G-NIC 64-bit
175 PCI card.
176
177 II. Board-specific settings
178
179 PCI bus devices are configured by the system at boot time, so no jumpers
180 need to be set on the board. The system BIOS preferably should assign the
181 PCI INTA signal to an otherwise unused system IRQ line.
182 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
183 interrupt lines.
184
185 III. Driver operation
186
187 IIIa. Ring buffers
188
189 The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
190 This is a descriptor list scheme similar to that used by the EEPro100 and
191 Tulip. This driver uses two statically allocated fixed-size descriptor lists
192 formed into rings by a branch from the final descriptor to the beginning of
193 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
194
195 The driver allocates full frame size skbuffs for the Rx ring buffers at
196 open() time and passes the skb->data field to the Yellowfin as receive data
197 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
198 a fresh skbuff is allocated and the frame is copied to the new skbuff.
199 When the incoming frame is larger, the skbuff is passed directly up the
200 protocol stack and replaced by a newly allocated skbuff.
201
202 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
203 using a full-sized skbuff for small frames vs. the copying costs of larger
204 frames. For small frames the copying cost is negligible (esp. considering
205 that we are pre-loading the cache with immediately useful header
206 information). For large frames the copying cost is non-trivial, and the
207 larger copy might flush the cache of useful data.
208
209 IIIC. Synchronization
210
211 The driver runs as two independent, single-threaded flows of control. One
212 is the send-packet routine, which enforces single-threaded use by the
213 dev->tbusy flag. The other thread is the interrupt handler, which is single
214 threaded by the hardware and other software.
215
216 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
217 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
218 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
219 the 'yp->tx_full' flag.
220
221 The interrupt handler has exclusive control over the Rx ring and records stats
222 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
223 empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
224 clears both the tx_full and tbusy flags.
225
226 IV. Notes
227
228 Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
229 Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
230 and an AlphaStation to verifty the Alpha port!
231
232 IVb. References
233
234 Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
235 Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
236 Data Manual v3.0
237 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
238 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
239
240 IVc. Errata
241
242 See Packet Engines confidential appendix (prototype chips only).
243 */
244
245
246
247 enum pci_id_flags_bits {
248 /* Set PCI command register bits before calling probe1(). */
249 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
250 /* Read and map the single following PCI BAR. */
251 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
252 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
253 PCI_UNUSED_IRQ=0x800,
254 };
255 enum capability_flags {
256 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
257 HasMACAddrBug=32, /* Only on early revs. */
258 };
259 /* The PCI I/O space extent. */
260 #define YELLOWFIN_SIZE 0x100
261 #ifdef USE_IO_OPS
262 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
263 #else
264 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
265 #endif
266
267 struct pci_id_info {
268 const char *name;
269 struct match_info {
270 int pci, pci_mask, subsystem, subsystem_mask;
271 int revision, revision_mask; /* Only 8 bits. */
272 } id;
273 enum pci_id_flags_bits pci_flags;
274 int io_size; /* Needed for I/O region check or ioremap(). */
275 int drv_flags; /* Driver use, intended as capability flags. */
276 };
277
278 static struct pci_id_info pci_id_tbl[] = {
279 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
280 PCI_IOTYPE, YELLOWFIN_SIZE,
281 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug},
282 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
283 PCI_IOTYPE, YELLOWFIN_SIZE, HasMII | IsGigabit | FullTxStatus },
284 {0,},
285 };
286
287 static struct pci_device_id yellowfin_pci_tbl[] __devinitdata = {
288 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
289 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
290 { 0, }
291 };
292 MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
293
294
295 /* Offsets to the Yellowfin registers. Various sizes and alignments. */
296 enum yellowfin_offsets {
297 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
298 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
299 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
300 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
301 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
302 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
303 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
304 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
305 MII_Status=0xAE,
306 RxDepth=0xB8, FlowCtrl=0xBC,
307 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
308 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
309 EEFeature=0xF5,
310 };
311
312 /* The Yellowfin Rx and Tx buffer descriptors.
313 Elements are written as 32 bit for endian portability. */
314 struct yellowfin_desc {
315 u32 dbdma_cmd;
316 u32 addr;
317 u32 branch_addr;
318 u32 result_status;
319 };
320
321 struct tx_status_words {
322 #ifdef __BIG_ENDIAN
323 u16 tx_errs;
324 u16 tx_cnt;
325 u16 paused;
326 u16 total_tx_cnt;
327 #else /* Little endian chips. */
328 u16 tx_cnt;
329 u16 tx_errs;
330 u16 total_tx_cnt;
331 u16 paused;
332 #endif /* __BIG_ENDIAN */
333 };
334
335 /* Bits in yellowfin_desc.cmd */
336 enum desc_cmd_bits {
337 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
338 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
339 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
340 BRANCH_IFTRUE=0x040000,
341 };
342
343 /* Bits in yellowfin_desc.status */
344 enum desc_status_bits { RX_EOP=0x0040, };
345
346 /* Bits in the interrupt status/mask registers. */
347 enum intr_status_bits {
348 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
349 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
350 IntrEarlyRx=0x100, IntrWakeup=0x200, };
351
352 #define PRIV_ALIGN 31 /* Required alignment mask */
353 #define MII_CNT 4
354 struct yellowfin_private {
355 /* Descriptor rings first for alignment.
356 Tx requires a second descriptor for status. */
357 struct yellowfin_desc *rx_ring;
358 struct yellowfin_desc *tx_ring;
359 struct sk_buff* rx_skbuff[RX_RING_SIZE];
360 struct sk_buff* tx_skbuff[TX_RING_SIZE];
361 dma_addr_t rx_ring_dma;
362 dma_addr_t tx_ring_dma;
363
364 struct tx_status_words *tx_status;
365 dma_addr_t tx_status_dma;
366
367 struct timer_list timer; /* Media selection timer. */
368 struct net_device_stats stats;
369 /* Frequently used and paired value: keep adjacent for cache effect. */
370 int chip_id, drv_flags;
371 struct pci_dev *pci_dev;
372 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
373 unsigned int rx_buf_sz; /* Based on MTU+slack. */
374 struct tx_status_words *tx_tail_desc;
375 unsigned int cur_tx, dirty_tx;
376 int tx_threshold;
377 unsigned int tx_full:1; /* The Tx queue is full. */
378 unsigned int full_duplex:1; /* Full-duplex operation requested. */
379 unsigned int duplex_lock:1;
380 unsigned int medialock:1; /* Do not sense media. */
381 unsigned int default_port:4; /* Last dev->if_port value. */
382 /* MII transceiver section. */
383 int mii_cnt; /* MII device addresses. */
384 u16 advertising; /* NWay media advertisement */
385 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
386 spinlock_t lock;
387 };
388
389 static int read_eeprom(long ioaddr, int location);
390 static int mdio_read(long ioaddr, int phy_id, int location);
391 static void mdio_write(long ioaddr, int phy_id, int location, int value);
392 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
393 static int yellowfin_open(struct net_device *dev);
394 static void yellowfin_timer(unsigned long data);
395 static void yellowfin_tx_timeout(struct net_device *dev);
396 static void yellowfin_init_ring(struct net_device *dev);
397 static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
398 static void yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
399 static int yellowfin_rx(struct net_device *dev);
400 static void yellowfin_error(struct net_device *dev, int intr_status);
401 static int yellowfin_close(struct net_device *dev);
402 static struct net_device_stats *yellowfin_get_stats(struct net_device *dev);
403 static void set_rx_mode(struct net_device *dev);
404
405
406 static int __devinit yellowfin_init_one(struct pci_dev *pdev,
407 const struct pci_device_id *ent)
408 {
409 struct net_device *dev;
410 struct yellowfin_private *np;
411 int irq;
412 int chip_idx = ent->driver_data;
413 static int find_cnt;
414 long ioaddr, real_ioaddr;
415 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
416 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
417 void *ring_space;
418 dma_addr_t ring_dma;
419
420 /* when built into the kernel, we only print version if device is found */
421 #ifndef MODULE
422 static int printed_version;
423 if (!printed_version++)
424 printk(version);
425 #endif
426
427 i = pci_enable_device(pdev);
428 if (i) return i;
429
430 dev = alloc_etherdev(sizeof(*np));
431 if (!dev) {
432 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
433 return -ENOMEM;
434 }
435 SET_MODULE_OWNER(dev);
436
437 np = dev->priv;
438
439 if (pci_request_regions(pdev, dev->name))
440 goto err_out_free_netdev;
441
442 pci_set_master (pdev);
443
444 #ifdef USE_IO_OPS
445 real_ioaddr = ioaddr = pci_resource_start (pdev, 0);
446 #else
447 real_ioaddr = ioaddr = pci_resource_start (pdev, 1);
448 ioaddr = (long) ioremap(ioaddr, YELLOWFIN_SIZE);
449 if (!ioaddr)
450 goto err_out_free_res;
451 #endif
452 irq = pdev->irq;
453
454 if (drv_flags & IsGigabit)
455 for (i = 0; i < 6; i++)
456 dev->dev_addr[i] = inb(ioaddr + StnAddr + i);
457 else {
458 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
459 for (i = 0; i < 6; i++)
460 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
461 }
462
463 /* Reset the chip. */
464 outl(0x80000000, ioaddr + DMACtrl);
465
466 dev->base_addr = ioaddr;
467 dev->irq = irq;
468
469 pci_set_drvdata(pdev, dev);
470 spin_lock_init(&np->lock);
471
472 np->pci_dev = pdev;
473 np->chip_id = chip_idx;
474 np->drv_flags = drv_flags;
475
476 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
477 if (!ring_space)
478 goto err_out_cleardev;
479 np->tx_ring = (struct yellowfin_desc *)ring_space;
480 np->tx_ring_dma = ring_dma;
481
482 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
483 if (!ring_space)
484 goto err_out_unmap_tx;
485 np->rx_ring = (struct yellowfin_desc *)ring_space;
486 np->rx_ring_dma = ring_dma;
487
488 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
489 if (!ring_space)
490 goto err_out_unmap_rx;
491 np->tx_status = (struct tx_status_words *)ring_space;
492 np->tx_status_dma = ring_dma;
493
494 if (dev->mem_start)
495 option = dev->mem_start;
496
497 /* The lower four bits are the media type. */
498 if (option > 0) {
499 if (option & 0x200)
500 np->full_duplex = 1;
501 np->default_port = option & 15;
502 if (np->default_port)
503 np->medialock = 1;
504 }
505 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
506 np->full_duplex = 1;
507
508 if (np->full_duplex)
509 np->duplex_lock = 1;
510
511 /* The Yellowfin-specific entries in the device structure. */
512 dev->open = &yellowfin_open;
513 dev->hard_start_xmit = &yellowfin_start_xmit;
514 dev->stop = &yellowfin_close;
515 dev->get_stats = &yellowfin_get_stats;
516 dev->set_multicast_list = &set_rx_mode;
517 dev->do_ioctl = &netdev_ioctl;
518 dev->tx_timeout = yellowfin_tx_timeout;
519 dev->watchdog_timeo = TX_TIMEOUT;
520
521 if (mtu)
522 dev->mtu = mtu;
523
524 i = register_netdev(dev);
525 if (i)
526 goto err_out_unmap_status;
527
528 printk(KERN_INFO "%s: %s type %8x at 0x%lx, ",
529 dev->name, pci_id_tbl[chip_idx].name, inl(ioaddr + ChipRev), ioaddr);
530 for (i = 0; i < 5; i++)
531 printk("%2.2x:", dev->dev_addr[i]);
532 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
533
534 if (np->drv_flags & HasMII) {
535 int phy, phy_idx = 0;
536 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
537 int mii_status = mdio_read(ioaddr, phy, 1);
538 if (mii_status != 0xffff && mii_status != 0x0000) {
539 np->phys[phy_idx++] = phy;
540 np->advertising = mdio_read(ioaddr, phy, 4);
541 printk(KERN_INFO "%s: MII PHY found at address %d, status "
542 "0x%4.4x advertising %4.4x.\n",
543 dev->name, phy, mii_status, np->advertising);
544 }
545 }
546 np->mii_cnt = phy_idx;
547 }
548
549 find_cnt++;
550
551 return 0;
552
553 err_out_unmap_status:
554 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
555 np->tx_status_dma);
556 err_out_unmap_rx:
557 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
558 err_out_unmap_tx:
559 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
560 err_out_cleardev:
561 pci_set_drvdata(pdev, NULL);
562 #ifndef USE_IO_OPS
563 iounmap((void *)ioaddr);
564 err_out_free_res:
565 #endif
566 pci_release_regions(pdev);
567 err_out_free_netdev:
568 kfree (dev);
569 return -ENODEV;
570 }
571
572 static int __devinit read_eeprom(long ioaddr, int location)
573 {
574 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
575
576 outb(location, ioaddr + EEAddr);
577 outb(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
578 while ((inb(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
579 ;
580 return inb(ioaddr + EERead);
581 }
582
583 /* MII Managemen Data I/O accesses.
584 These routines assume the MDIO controller is idle, and do not exit until
585 the command is finished. */
586
587 static int mdio_read(long ioaddr, int phy_id, int location)
588 {
589 int i;
590
591 outw((phy_id<<8) + location, ioaddr + MII_Addr);
592 outw(1, ioaddr + MII_Cmd);
593 for (i = 10000; i >= 0; i--)
594 if ((inw(ioaddr + MII_Status) & 1) == 0)
595 break;
596 return inw(ioaddr + MII_Rd_Data);
597 }
598
599 static void mdio_write(long ioaddr, int phy_id, int location, int value)
600 {
601 int i;
602
603 outw((phy_id<<8) + location, ioaddr + MII_Addr);
604 outw(value, ioaddr + MII_Wr_Data);
605
606 /* Wait for the command to finish. */
607 for (i = 10000; i >= 0; i--)
608 if ((inw(ioaddr + MII_Status) & 1) == 0)
609 break;
610 return;
611 }
612
613
614 static int yellowfin_open(struct net_device *dev)
615 {
616 struct yellowfin_private *yp = dev->priv;
617 long ioaddr = dev->base_addr;
618 int i;
619
620 /* Reset the chip. */
621 outl(0x80000000, ioaddr + DMACtrl);
622
623 i = request_irq(dev->irq, &yellowfin_interrupt, SA_SHIRQ, dev->name, dev);
624 if (i) return i;
625
626 if (yellowfin_debug > 1)
627 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
628 dev->name, dev->irq);
629
630 yellowfin_init_ring(dev);
631
632 outl(yp->rx_ring_dma, ioaddr + RxPtr);
633 outl(yp->tx_ring_dma, ioaddr + TxPtr);
634
635 for (i = 0; i < 6; i++)
636 outb(dev->dev_addr[i], ioaddr + StnAddr + i);
637
638 /* Set up various condition 'select' registers.
639 There are no options here. */
640 outl(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
641 outl(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
642 outl(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
643 outl(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
644 outl(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
645 outl(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
646
647 /* Initialize other registers: with so many this eventually this will
648 converted to an offset/value list. */
649 outl(dma_ctrl, ioaddr + DMACtrl);
650 outw(fifo_cfg, ioaddr + FIFOcfg);
651 /* Enable automatic generation of flow control frames, period 0xffff. */
652 outl(0x0030FFFF, ioaddr + FlowCtrl);
653
654 yp->tx_threshold = 32;
655 outl(yp->tx_threshold, ioaddr + TxThreshold);
656
657 if (dev->if_port == 0)
658 dev->if_port = yp->default_port;
659
660 netif_start_queue(dev);
661
662 /* Setting the Rx mode will start the Rx process. */
663 if (yp->drv_flags & IsGigabit) {
664 /* We are always in full-duplex mode with gigabit! */
665 yp->full_duplex = 1;
666 outw(0x01CF, ioaddr + Cnfg);
667 } else {
668 outw(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
669 outw(0x1018, ioaddr + FrameGap1);
670 outw(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
671 }
672 set_rx_mode(dev);
673
674 /* Enable interrupts by setting the interrupt mask. */
675 outw(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
676 outw(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
677 outl(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
678 outl(0x80008000, ioaddr + TxCtrl);
679
680 if (yellowfin_debug > 2) {
681 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
682 dev->name);
683 }
684
685 /* Set the timer to check for link beat. */
686 init_timer(&yp->timer);
687 yp->timer.expires = jiffies + 3*HZ;
688 yp->timer.data = (unsigned long)dev;
689 yp->timer.function = &yellowfin_timer; /* timer handler */
690 add_timer(&yp->timer);
691
692 return 0;
693 }
694
695 static void yellowfin_timer(unsigned long data)
696 {
697 struct net_device *dev = (struct net_device *)data;
698 struct yellowfin_private *yp = dev->priv;
699 long ioaddr = dev->base_addr;
700 int next_tick = 60*HZ;
701
702 if (yellowfin_debug > 3) {
703 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
704 dev->name, inw(ioaddr + IntrStatus));
705 }
706
707 if (yp->mii_cnt) {
708 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
709 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
710 int negotiated = lpa & yp->advertising;
711 if (yellowfin_debug > 1)
712 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
713 "link partner capability %4.4x.\n",
714 dev->name, yp->phys[0], bmsr, lpa);
715
716 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
717
718 outw(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
719
720 if (bmsr & BMSR_LSTATUS)
721 next_tick = 60*HZ;
722 else
723 next_tick = 3*HZ;
724 }
725
726 yp->timer.expires = jiffies + next_tick;
727 add_timer(&yp->timer);
728 }
729
730 static void yellowfin_tx_timeout(struct net_device *dev)
731 {
732 struct yellowfin_private *yp = dev->priv;
733 long ioaddr = dev->base_addr;
734
735 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
736 "status %4.4x, Rx status %4.4x, resetting...\n",
737 dev->name, yp->cur_tx, yp->dirty_tx,
738 inl(ioaddr + TxStatus), inl(ioaddr + RxStatus));
739
740 /* Note: these should be KERN_DEBUG. */
741 if (yellowfin_debug) {
742 int i;
743 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
744 for (i = 0; i < RX_RING_SIZE; i++)
745 printk(" %8.8x", yp->rx_ring[i].result_status);
746 printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring);
747 for (i = 0; i < TX_RING_SIZE; i++)
748 printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
749 yp->tx_ring[i].result_status);
750 printk("\n");
751 }
752
753 /* If the hardware is found to hang regularly, we will update the code
754 to reinitialize the chip here. */
755 dev->if_port = 0;
756
757 /* Wake the potentially-idle transmit channel. */
758 outl(0x10001000, dev->base_addr + TxCtrl);
759 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
760 netif_wake_queue (dev); /* Typical path */
761
762 dev->trans_start = jiffies;
763 yp->stats.tx_errors++;
764 }
765
766 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
767 static void yellowfin_init_ring(struct net_device *dev)
768 {
769 struct yellowfin_private *yp = dev->priv;
770 int i;
771
772 yp->tx_full = 0;
773 yp->cur_rx = yp->cur_tx = 0;
774 yp->dirty_tx = 0;
775
776 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
777
778 for (i = 0; i < RX_RING_SIZE; i++) {
779 yp->rx_ring[i].dbdma_cmd =
780 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
781 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
782 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
783 }
784
785 for (i = 0; i < RX_RING_SIZE; i++) {
786 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
787 yp->rx_skbuff[i] = skb;
788 if (skb == NULL)
789 break;
790 skb->dev = dev; /* Mark as being used by this device. */
791 skb_reserve(skb, 2); /* 16 byte align the IP header. */
792 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
793 skb->tail, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
794 }
795 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
796 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
797
798 #define NO_TXSTATS
799 #ifdef NO_TXSTATS
800 /* In this mode the Tx ring needs only a single descriptor. */
801 for (i = 0; i < TX_RING_SIZE; i++) {
802 yp->tx_skbuff[i] = 0;
803 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
804 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
805 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
806 }
807 /* Wrap ring */
808 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
809 #else
810 {
811 int j;
812
813 /* Tx ring needs a pair of descriptors, the second for the status. */
814 for (i = 0; i < TX_RING_SIZE; i++) {
815 j = 2*i;
816 yp->tx_skbuff[i] = 0;
817 /* Branch on Tx error. */
818 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
819 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
820 (j+1)*sizeof(struct yellowfin_desc);
821 j++;
822 if (yp->flags & FullTxStatus) {
823 yp->tx_ring[j].dbdma_cmd =
824 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
825 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
826 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
827 i*sizeof(struct tx_status_words);
828 } else {
829 /* Symbios chips write only tx_errs word. */
830 yp->tx_ring[j].dbdma_cmd =
831 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
832 yp->tx_ring[j].request_cnt = 2;
833 /* Om pade ummmmm... */
834 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
835 i*sizeof(struct tx_status_words) +
836 &(yp->tx_status[0].tx_errs) -
837 &(yp->tx_status[0]));
838 }
839 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
840 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
841 }
842 /* Wrap ring */
843 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
844 }
845 #endif
846 yp->tx_tail_desc = &yp->tx_status[0];
847 return;
848 }
849
850 static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
851 {
852 struct yellowfin_private *yp = dev->priv;
853 unsigned entry;
854
855 netif_stop_queue (dev);
856
857 /* Note: Ordering is important here, set the field with the
858 "ownership" bit last, and only then increment cur_tx. */
859
860 /* Calculate the next Tx descriptor entry. */
861 entry = yp->cur_tx % TX_RING_SIZE;
862
863 yp->tx_skbuff[entry] = skb;
864
865 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
866 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
867 /* Fix GX chipset errata. */
868 if (cacheline_end > 24 || cacheline_end == 0)
869 skb->len += 32 - cacheline_end + 1;
870 }
871 #ifdef NO_TXSTATS
872 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
873 skb->data, skb->len, PCI_DMA_TODEVICE));
874 yp->tx_ring[entry].result_status = 0;
875 if (entry >= TX_RING_SIZE-1) {
876 /* New stop command. */
877 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
878 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
879 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | skb->len);
880 } else {
881 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
882 yp->tx_ring[entry].dbdma_cmd =
883 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | skb->len);
884 }
885 yp->cur_tx++;
886 #else
887 yp->tx_ring[entry<<1].request_cnt = skb->len;
888 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
889 skb->data, skb->len, PCI_DMA_TODEVICE));
890 /* The input_last (status-write) command is constant, but we must
891 rewrite the subsequent 'stop' command. */
892
893 yp->cur_tx++;
894 {
895 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
896 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
897 }
898 /* Final step -- overwrite the old 'stop' command. */
899
900 yp->tx_ring[entry<<1].dbdma_cmd =
901 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
902 CMD_TX_PKT | BRANCH_IFTRUE) | skb->len);
903 #endif
904
905 /* Non-x86 Todo: explicitly flush cache lines here. */
906
907 /* Wake the potentially-idle transmit channel. */
908 outl(0x10001000, dev->base_addr + TxCtrl);
909
910 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
911 netif_start_queue (dev); /* Typical path */
912 else
913 yp->tx_full = 1;
914 dev->trans_start = jiffies;
915
916 if (yellowfin_debug > 4) {
917 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
918 dev->name, yp->cur_tx, entry);
919 }
920 return 0;
921 }
922
923 /* The interrupt handler does all of the Rx thread work and cleans up
924 after the Tx thread. */
925 static void yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
926 {
927 struct net_device *dev = dev_instance;
928 struct yellowfin_private *yp;
929 long ioaddr;
930 int boguscnt = max_interrupt_work;
931
932 #ifndef final_version /* Can never occur. */
933 if (dev == NULL) {
934 printk (KERN_ERR "yellowfin_interrupt(): irq %d for unknown device.\n", irq);
935 return;
936 }
937 #endif
938
939 ioaddr = dev->base_addr;
940 yp = dev->priv;
941
942 spin_lock (&yp->lock);
943
944 do {
945 u16 intr_status = inw(ioaddr + IntrClear);
946
947 if (yellowfin_debug > 4)
948 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
949 dev->name, intr_status);
950
951 if (intr_status == 0)
952 break;
953
954 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
955 yellowfin_rx(dev);
956 outl(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
957 }
958
959 #ifdef NO_TXSTATS
960 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
961 int entry = yp->dirty_tx % TX_RING_SIZE;
962 struct sk_buff *skb;
963
964 if (yp->tx_ring[entry].result_status == 0)
965 break;
966 skb = yp->tx_skbuff[entry];
967 yp->stats.tx_packets++;
968 yp->stats.tx_bytes += skb->len;
969 /* Free the original skb. */
970 pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr,
971 skb->len, PCI_DMA_TODEVICE);
972 dev_kfree_skb_irq(skb);
973 yp->tx_skbuff[entry] = 0;
974 }
975 if (yp->tx_full
976 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
977 /* The ring is no longer full, clear tbusy. */
978 yp->tx_full = 0;
979 netif_wake_queue(dev);
980 }
981 #else
982 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
983 unsigned dirty_tx = yp->dirty_tx;
984
985 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
986 dirty_tx++) {
987 /* Todo: optimize this. */
988 int entry = dirty_tx % TX_RING_SIZE;
989 u16 tx_errs = yp->tx_status[entry].tx_errs;
990 struct sk_buff *skb;
991
992 #ifndef final_version
993 if (yellowfin_debug > 5)
994 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
995 "%4.4x %4.4x %4.4x %4.4x.\n",
996 dev->name, entry,
997 yp->tx_status[entry].tx_cnt,
998 yp->tx_status[entry].tx_errs,
999 yp->tx_status[entry].total_tx_cnt,
1000 yp->tx_status[entry].paused);
1001 #endif
1002 if (tx_errs == 0)
1003 break; /* It still hasn't been Txed */
1004 skb = yp->tx_skbuff[entry];
1005 if (tx_errs & 0xF810) {
1006 /* There was an major error, log it. */
1007 #ifndef final_version
1008 if (yellowfin_debug > 1)
1009 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
1010 dev->name, tx_errs);
1011 #endif
1012 yp->stats.tx_errors++;
1013 if (tx_errs & 0xF800) yp->stats.tx_aborted_errors++;
1014 if (tx_errs & 0x0800) yp->stats.tx_carrier_errors++;
1015 if (tx_errs & 0x2000) yp->stats.tx_window_errors++;
1016 if (tx_errs & 0x8000) yp->stats.tx_fifo_errors++;
1017 #ifdef ETHER_STATS
1018 if (tx_errs & 0x1000) yp->stats.collisions16++;
1019 #endif
1020 } else {
1021 #ifndef final_version
1022 if (yellowfin_debug > 4)
1023 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
1024 dev->name, tx_errs);
1025 #endif
1026 #ifdef ETHER_STATS
1027 if (tx_errs & 0x0400) yp->stats.tx_deferred++;
1028 #endif
1029 yp->stats.tx_bytes += skb->len;
1030 yp->stats.collisions += tx_errs & 15;
1031 yp->stats.tx_packets++;
1032 }
1033 /* Free the original skb. */
1034 pci_unmap_single(yp->pci_dev,
1035 yp->tx_ring[entry<<1].addr, skb->len,
1036 PCI_DMA_TODEVICE);
1037 dev_kfree_skb_irq(skb);
1038 yp->tx_skbuff[entry] = 0;
1039 /* Mark status as empty. */
1040 yp->tx_status[entry].tx_errs = 0;
1041 }
1042
1043 #ifndef final_version
1044 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1045 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1046 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1047 dirty_tx += TX_RING_SIZE;
1048 }
1049 #endif
1050
1051 if (yp->tx_full
1052 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1053 /* The ring is no longer full, clear tbusy. */
1054 yp->tx_full = 0;
1055 netif_wake_queue(dev);
1056 }
1057
1058 yp->dirty_tx = dirty_tx;
1059 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1060 }
1061 #endif
1062
1063 /* Log errors and other uncommon events. */
1064 if (intr_status & 0x2ee) /* Abnormal error summary. */
1065 yellowfin_error(dev, intr_status);
1066
1067 if (--boguscnt < 0) {
1068 printk(KERN_WARNING "%s: Too much work at interrupt, "
1069 "status=0x%4.4x.\n",
1070 dev->name, intr_status);
1071 break;
1072 }
1073 } while (1);
1074
1075 if (yellowfin_debug > 3)
1076 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1077 dev->name, inw(ioaddr + IntrStatus));
1078
1079 spin_unlock (&yp->lock);
1080 return;
1081 }
1082
1083 /* This routine is logically part of the interrupt handler, but separated
1084 for clarity and better register allocation. */
1085 static int yellowfin_rx(struct net_device *dev)
1086 {
1087 struct yellowfin_private *yp = dev->priv;
1088 int entry = yp->cur_rx % RX_RING_SIZE;
1089 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1090
1091 if (yellowfin_debug > 4) {
1092 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1093 entry, yp->rx_ring[entry].result_status);
1094 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1095 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1096 yp->rx_ring[entry].result_status);
1097 }
1098
1099 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1100 while (1) {
1101 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1102 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1103 s16 frame_status;
1104 u16 desc_status;
1105 int data_size;
1106 u8 *buf_addr;
1107
1108 if(!desc->result_status)
1109 break;
1110 pci_dma_sync_single(yp->pci_dev, desc->addr,
1111 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1112 desc_status = le32_to_cpu(desc->result_status) >> 16;
1113 buf_addr = rx_skb->tail;
1114 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1115 le32_to_cpu(desc->result_status)) & 0xffff;
1116 frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2])));
1117 if (yellowfin_debug > 4)
1118 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1119 frame_status);
1120 if (--boguscnt < 0)
1121 break;
1122 if ( ! (desc_status & RX_EOP)) {
1123 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1124 " status %4.4x!\n", dev->name, desc_status);
1125 yp->stats.rx_length_errors++;
1126 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1127 /* There was a error. */
1128 if (yellowfin_debug > 3)
1129 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1130 frame_status);
1131 yp->stats.rx_errors++;
1132 if (frame_status & 0x0060) yp->stats.rx_length_errors++;
1133 if (frame_status & 0x0008) yp->stats.rx_frame_errors++;
1134 if (frame_status & 0x0010) yp->stats.rx_crc_errors++;
1135 if (frame_status < 0) yp->stats.rx_dropped++;
1136 } else if ( !(yp->drv_flags & IsGigabit) &&
1137 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1138 u8 status1 = buf_addr[data_size-2];
1139 u8 status2 = buf_addr[data_size-1];
1140 yp->stats.rx_errors++;
1141 if (status1 & 0xC0) yp->stats.rx_length_errors++;
1142 if (status2 & 0x03) yp->stats.rx_frame_errors++;
1143 if (status2 & 0x04) yp->stats.rx_crc_errors++;
1144 if (status2 & 0x80) yp->stats.rx_dropped++;
1145 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1146 } else if ((yp->flags & HasMACAddrBug) &&
1147 memcmp(le32_to_cpu(yp->rx_ring_dma +
1148 entry*sizeof(struct yellowfin_desc)),
1149 dev->dev_addr, 6) != 0 &&
1150 memcmp(le32_to_cpu(yp->rx_ring_dma +
1151 entry*sizeof(struct yellowfin_desc)),
1152 "\377\377\377\377\377\377", 6) != 0) {
1153 if (bogus_rx++ == 0)
1154 printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:"
1155 "%2.2x:%2.2x.\n",
1156 dev->name, buf_addr[0], buf_addr[1], buf_addr[2],
1157 buf_addr[3], buf_addr[4], buf_addr[5]);
1158 #endif
1159 } else {
1160 struct sk_buff *skb;
1161 int pkt_len = data_size -
1162 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1163 /* To verify: Yellowfin Length should omit the CRC! */
1164
1165 #ifndef final_version
1166 if (yellowfin_debug > 4)
1167 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1168 " of %d, bogus_cnt %d.\n",
1169 pkt_len, data_size, boguscnt);
1170 #endif
1171 /* Check if the packet is long enough to just pass up the skbuff
1172 without copying to a properly sized skbuff. */
1173 if (pkt_len > rx_copybreak) {
1174 skb_put(skb = rx_skb, pkt_len);
1175 pci_unmap_single(yp->pci_dev,
1176 yp->rx_ring[entry].addr,
1177 yp->rx_buf_sz,
1178 PCI_DMA_FROMDEVICE);
1179 yp->rx_skbuff[entry] = NULL;
1180 } else {
1181 skb = dev_alloc_skb(pkt_len + 2);
1182 if (skb == NULL)
1183 break;
1184 skb->dev = dev;
1185 skb_reserve(skb, 2); /* 16 byte align the IP header */
1186 #if HAS_IP_COPYSUM
1187 eth_copy_and_sum(skb, rx_skb->tail, pkt_len, 0);
1188 skb_put(skb, pkt_len);
1189 #else
1190 memcpy(skb_put(skb, pkt_len),
1191 rx_skb->tail, pkt_len);
1192 #endif
1193 }
1194 skb->protocol = eth_type_trans(skb, dev);
1195 netif_rx(skb);
1196 dev->last_rx = jiffies;
1197 yp->stats.rx_packets++;
1198 yp->stats.rx_bytes += pkt_len;
1199 }
1200 entry = (++yp->cur_rx) % RX_RING_SIZE;
1201 }
1202
1203 /* Refill the Rx ring buffers. */
1204 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1205 entry = yp->dirty_rx % RX_RING_SIZE;
1206 if (yp->rx_skbuff[entry] == NULL) {
1207 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1208 if (skb == NULL)
1209 break; /* Better luck next round. */
1210 yp->rx_skbuff[entry] = skb;
1211 skb->dev = dev; /* Mark as being used by this device. */
1212 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1213 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1214 skb->tail, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1215 }
1216 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1217 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1218 if (entry != 0)
1219 yp->rx_ring[entry - 1].dbdma_cmd =
1220 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1221 else
1222 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1223 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1224 | yp->rx_buf_sz);
1225 }
1226
1227 return 0;
1228 }
1229
1230 static void yellowfin_error(struct net_device *dev, int intr_status)
1231 {
1232 struct yellowfin_private *yp = dev->priv;
1233
1234 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1235 dev->name, intr_status);
1236 /* Hmmmmm, it's not clear what to do here. */
1237 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1238 yp->stats.tx_errors++;
1239 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1240 yp->stats.rx_errors++;
1241 }
1242
1243 static int yellowfin_close(struct net_device *dev)
1244 {
1245 long ioaddr = dev->base_addr;
1246 struct yellowfin_private *yp = dev->priv;
1247 int i;
1248
1249 netif_stop_queue (dev);
1250
1251 if (yellowfin_debug > 1) {
1252 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1253 "Rx %4.4x Int %2.2x.\n",
1254 dev->name, inw(ioaddr + TxStatus),
1255 inw(ioaddr + RxStatus), inw(ioaddr + IntrStatus));
1256 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1257 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1258 }
1259
1260 /* Disable interrupts by clearing the interrupt mask. */
1261 outw(0x0000, ioaddr + IntrEnb);
1262
1263 /* Stop the chip's Tx and Rx processes. */
1264 outl(0x80000000, ioaddr + RxCtrl);
1265 outl(0x80000000, ioaddr + TxCtrl);
1266
1267 del_timer(&yp->timer);
1268
1269 #if defined(__i386__)
1270 if (yellowfin_debug > 2) {
1271 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n", yp->tx_ring_dma);
1272 for (i = 0; i < TX_RING_SIZE*2; i++)
1273 printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1274 inl(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1275 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1276 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1277 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1278 for (i = 0; i < TX_RING_SIZE; i++)
1279 printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1280 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1281 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1282
1283 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n", yp->rx_ring_dma);
1284 for (i = 0; i < RX_RING_SIZE; i++) {
1285 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1286 inl(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1287 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1288 yp->rx_ring[i].result_status);
1289 if (yellowfin_debug > 6) {
1290 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1291 int j;
1292 for (j = 0; j < 0x50; j++)
1293 printk(" %4.4x",
1294 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1295 printk("\n");
1296 }
1297 }
1298 }
1299 }
1300 #endif /* __i386__ debugging only */
1301
1302 free_irq(dev->irq, dev);
1303
1304 /* Free all the skbuffs in the Rx queue. */
1305 for (i = 0; i < RX_RING_SIZE; i++) {
1306 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1307 yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1308 if (yp->rx_skbuff[i]) {
1309 dev_kfree_skb(yp->rx_skbuff[i]);
1310 }
1311 yp->rx_skbuff[i] = 0;
1312 }
1313 for (i = 0; i < TX_RING_SIZE; i++) {
1314 if (yp->tx_skbuff[i])
1315 dev_kfree_skb(yp->tx_skbuff[i]);
1316 yp->tx_skbuff[i] = 0;
1317 }
1318
1319 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1320 if (yellowfin_debug > 0) {
1321 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1322 dev->name, bogus_rx);
1323 }
1324 #endif
1325
1326 return 0;
1327 }
1328
1329 static struct net_device_stats *yellowfin_get_stats(struct net_device *dev)
1330 {
1331 struct yellowfin_private *yp = dev->priv;
1332 return &yp->stats;
1333 }
1334
1335 /* Set or clear the multicast filter for this adaptor. */
1336
1337 /* The little-endian AUTODIN32 ethernet CRC calculation.
1338 N.B. Do not use for bulk data, use a table-based routine instead.
1339 This is common code and should be moved to net/core/crc.c */
1340 static unsigned const ethernet_polynomial_le = 0xedb88320U;
1341
1342 static inline unsigned ether_crc_le(int length, unsigned char *data)
1343 {
1344 unsigned int crc = 0xffffffff; /* Initial value. */
1345 while(--length >= 0) {
1346 unsigned char current_octet = *data++;
1347 int bit;
1348 for (bit = 8; --bit >= 0; current_octet >>= 1) {
1349 if ((crc ^ current_octet) & 1) {
1350 crc >>= 1;
1351 crc ^= ethernet_polynomial_le;
1352 } else
1353 crc >>= 1;
1354 }
1355 }
1356 return crc;
1357 }
1358
1359
1360 static void set_rx_mode(struct net_device *dev)
1361 {
1362 struct yellowfin_private *yp = dev->priv;
1363 long ioaddr = dev->base_addr;
1364 u16 cfg_value = inw(ioaddr + Cnfg);
1365
1366 /* Stop the Rx process to change any value. */
1367 outw(cfg_value & ~0x1000, ioaddr + Cnfg);
1368 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1369 /* Unconditionally log net taps. */
1370 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1371 outw(0x000F, ioaddr + AddrMode);
1372 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1373 /* Too many to filter well, or accept all multicasts. */
1374 outw(0x000B, ioaddr + AddrMode);
1375 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1376 struct dev_mc_list *mclist;
1377 u16 hash_table[4];
1378 int i;
1379 memset(hash_table, 0, sizeof(hash_table));
1380 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1381 i++, mclist = mclist->next) {
1382 /* Due to a bug in the early chip versions, multiple filter
1383 slots must be set for each address. */
1384 if (yp->drv_flags & HasMulticastBug) {
1385 set_bit((ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f,
1386 hash_table);
1387 set_bit((ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f,
1388 hash_table);
1389 set_bit((ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f,
1390 hash_table);
1391 }
1392 set_bit((ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f,
1393 hash_table);
1394 }
1395 /* Copy the hash table to the chip. */
1396 for (i = 0; i < 4; i++)
1397 outw(hash_table[i], ioaddr + HashTbl + i*2);
1398 outw(0x0003, ioaddr + AddrMode);
1399 } else { /* Normal, unicast/broadcast-only mode. */
1400 outw(0x0001, ioaddr + AddrMode);
1401 }
1402 /* Restart the Rx process. */
1403 outw(cfg_value | 0x1000, ioaddr + Cnfg);
1404 }
1405
1406 static int netdev_ethtool_ioctl(struct net_device *dev, void *useraddr)
1407 {
1408 struct yellowfin_private *np = dev->priv;
1409 u32 ethcmd;
1410
1411 if (copy_from_user(ðcmd, useraddr, sizeof(ethcmd)))
1412 return -EFAULT;
1413
1414 switch (ethcmd) {
1415 case ETHTOOL_GDRVINFO: {
1416 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
1417 strcpy(info.driver, DRV_NAME);
1418 strcpy(info.version, DRV_VERSION);
1419 strcpy(info.bus_info, np->pci_dev->slot_name);
1420 if (copy_to_user(useraddr, &info, sizeof(info)))
1421 return -EFAULT;
1422 return 0;
1423 }
1424
1425 }
1426
1427 return -EOPNOTSUPP;
1428 }
1429
1430 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1431 {
1432 struct yellowfin_private *np = dev->priv;
1433 long ioaddr = dev->base_addr;
1434 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1435
1436 switch(cmd) {
1437 case SIOCETHTOOL:
1438 return netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
1439 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1440 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
1441 data->phy_id = np->phys[0] & 0x1f;
1442 /* Fall Through */
1443
1444 case SIOCGMIIREG: /* Read MII PHY register. */
1445 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
1446 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1447 return 0;
1448
1449 case SIOCSMIIREG: /* Write MII PHY register. */
1450 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
1451 if (!capable(CAP_NET_ADMIN))
1452 return -EPERM;
1453 if (data->phy_id == np->phys[0]) {
1454 u16 value = data->val_in;
1455 switch (data->reg_num) {
1456 case 0:
1457 /* Check for autonegotiation on or reset. */
1458 np->medialock = (value & 0x9000) ? 0 : 1;
1459 if (np->medialock)
1460 np->full_duplex = (value & 0x0100) ? 1 : 0;
1461 break;
1462 case 4: np->advertising = value; break;
1463 }
1464 /* Perhaps check_duplex(dev), depending on chip semantics. */
1465 }
1466 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1467 return 0;
1468 default:
1469 return -EOPNOTSUPP;
1470 }
1471 }
1472
1473
1474 static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1475 {
1476 struct net_device *dev = pci_get_drvdata(pdev);
1477 struct yellowfin_private *np;
1478
1479 if (!dev)
1480 BUG();
1481 np = dev->priv;
1482
1483 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1484 np->tx_status_dma);
1485 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1486 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1487 unregister_netdev (dev);
1488
1489 pci_release_regions (pdev);
1490
1491 #ifndef USE_IO_OPS
1492 iounmap ((void *) dev->base_addr);
1493 #endif
1494
1495 kfree (dev);
1496 pci_set_drvdata(pdev, NULL);
1497 }
1498
1499
1500 static struct pci_driver yellowfin_driver = {
1501 name: DRV_NAME,
1502 id_table: yellowfin_pci_tbl,
1503 probe: yellowfin_init_one,
1504 remove: yellowfin_remove_one,
1505 };
1506
1507
1508 static int __init yellowfin_init (void)
1509 {
1510 /* when a module, this is printed whether or not devices are found in probe */
1511 #ifdef MODULE
1512 printk(version);
1513 #endif
1514 return pci_module_init (&yellowfin_driver);
1515 }
1516
1517
1518 static void __exit yellowfin_cleanup (void)
1519 {
1520 pci_unregister_driver (&yellowfin_driver);
1521 }
1522
1523
1524 module_init(yellowfin_init);
1525 module_exit(yellowfin_cleanup);
1526
1527 /*
1528 * Local variables:
1529 * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1530 * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1531 * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"
1532 * c-indent-level: 4
1533 * c-basic-offset: 4
1534 * tab-width: 4
1535 * End:
1536 */
1537