File: /usr/src/linux/drivers/parport/parport_pc.c
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <Philip.Blundell@pobox.com>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 */
17
18 /* This driver should work with any hardware that is broadly compatible
19 * with that in the IBM PC. This applies to the majority of integrated
20 * I/O chipsets that are commonly available. The expected register
21 * layout is:
22 *
23 * base+0 data
24 * base+1 status
25 * base+2 control
26 *
27 * In addition, there are some optional registers:
28 *
29 * base+3 EPP address
30 * base+4 EPP data
31 * base+0x400 ECP config A
32 * base+0x401 ECP config B
33 * base+0x402 ECP control
34 *
35 * All registers are 8 bits wide and read/write. If your hardware differs
36 * only in register addresses (eg because your registers are on 32-bit
37 * word boundaries) then you can alter the constants in parport_pc.h to
38 * accomodate this.
39 *
40 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
41 * but rather will start at port->base_hi.
42 */
43
44 #include <linux/config.h>
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/pci.h>
55 #include <linux/sysctl.h>
56
57 #include <asm/io.h>
58 #include <asm/dma.h>
59 #include <asm/uaccess.h>
60
61 #include <linux/parport.h>
62 #include <linux/parport_pc.h>
63 #include <asm/parport.h>
64
65 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
66
67 /* ECR modes */
68 #define ECR_SPP 00
69 #define ECR_PS2 01
70 #define ECR_PPF 02
71 #define ECR_ECP 03
72 #define ECR_EPP 04
73 #define ECR_VND 05
74 #define ECR_TST 06
75 #define ECR_CNF 07
76
77 #undef DEBUG
78
79 #ifdef DEBUG
80 #define DPRINTK printk
81 #else
82 #define DPRINTK(stuff...)
83 #endif
84
85
86 #define NR_SUPERIOS 3
87 static struct superio_struct { /* For Super-IO chips autodetection */
88 int io;
89 int irq;
90 int dma;
91 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
92
93 static int user_specified __devinitdata = 0;
94 static int registered_parport;
95
96 /* frob_control, but for ECR */
97 static void frob_econtrol (struct parport *pb, unsigned char m,
98 unsigned char v)
99 {
100 unsigned char ectr = inb (ECONTROL (pb));
101 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
102 m, v, ectr, (ectr & ~m) ^ v);
103
104 outb ((ectr & ~m) ^ v, ECONTROL (pb));
105 }
106
107 #ifdef CONFIG_PARPORT_PC_FIFO
108 /* Safely change the mode bits in the ECR
109 Returns:
110 0 : Success
111 -EBUSY: Could not drain FIFO in some finite amount of time,
112 mode not changed!
113 */
114 static int change_mode(struct parport *p, int m)
115 {
116 const struct parport_pc_private *priv = p->physport->private_data;
117 int ecr = ECONTROL(p);
118 unsigned char oecr;
119 int mode;
120
121 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
122
123 if (!priv->ecr) {
124 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
125 return 0;
126 }
127
128 /* Bits <7:5> contain the mode. */
129 oecr = inb (ecr);
130 mode = (oecr >> 5) & 0x7;
131 if (mode == m) return 0;
132
133 if (mode >= 2 && !(priv->ctr & 0x20)) {
134 /* This mode resets the FIFO, so we may
135 * have to wait for it to drain first. */
136 long expire = jiffies + p->physport->cad->timeout;
137 int counter;
138 switch (mode) {
139 case ECR_PPF: /* Parallel Port FIFO mode */
140 case ECR_ECP: /* ECP Parallel Port mode */
141 /* Busy wait for 200us */
142 for (counter = 0; counter < 40; counter++) {
143 if (inb (ECONTROL (p)) & 0x01)
144 break;
145 if (signal_pending (current)) break;
146 udelay (5);
147 }
148
149 /* Poll slowly. */
150 while (!(inb (ECONTROL (p)) & 0x01)) {
151 if (time_after_eq (jiffies, expire))
152 /* The FIFO is stuck. */
153 return -EBUSY;
154 __set_current_state (TASK_INTERRUPTIBLE);
155 schedule_timeout ((HZ + 99) / 100);
156 if (signal_pending (current))
157 break;
158 }
159 }
160 }
161
162 if (mode >= 2 && m >= 2) {
163 /* We have to go through mode 001 */
164 oecr &= ~(7 << 5);
165 oecr |= ECR_PS2 << 5;
166 outb (oecr, ecr);
167 }
168
169 /* Set the mode. */
170 oecr &= ~(7 << 5);
171 oecr |= m << 5;
172 outb (oecr, ecr);
173 return 0;
174 }
175
176 #ifdef CONFIG_PARPORT_1284
177 /* Find FIFO lossage; FIFO is reset */
178 static int get_fifo_residue (struct parport *p)
179 {
180 int residue;
181 int cnfga;
182 const struct parport_pc_private *priv = p->physport->private_data;
183
184 /* Adjust for the contents of the FIFO. */
185 for (residue = priv->fifo_depth; ; residue--) {
186 if (inb (ECONTROL (p)) & 0x2)
187 /* Full up. */
188 break;
189
190 outb (0, FIFO (p));
191 }
192
193 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
194 residue);
195
196 /* Reset the FIFO. */
197 frob_econtrol (p, 0xe0, ECR_PS2 << 5);
198
199 /* Now change to config mode and clean up. FIXME */
200 frob_econtrol (p, 0xe0, ECR_CNF << 5);
201 cnfga = inb (CONFIGA (p));
202 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
203
204 if (!(cnfga & (1<<2))) {
205 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
206 residue++;
207 }
208
209 /* Don't care about partial PWords until support is added for
210 * PWord != 1 byte. */
211
212 /* Back to PS2 mode. */
213 frob_econtrol (p, 0xe0, ECR_PS2 << 5);
214
215 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
216 return residue;
217 }
218 #endif /* IEEE 1284 support */
219 #endif /* FIFO support */
220
221 /*
222 * Clear TIMEOUT BIT in EPP MODE
223 *
224 * This is also used in SPP detection.
225 */
226 static int clear_epp_timeout(struct parport *pb)
227 {
228 unsigned char r;
229
230 if (!(parport_pc_read_status(pb) & 0x01))
231 return 1;
232
233 /* To clear timeout some chips require double read */
234 parport_pc_read_status(pb);
235 r = parport_pc_read_status(pb);
236 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
237 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
238 r = parport_pc_read_status(pb);
239
240 return !(r & 0x01);
241 }
242
243 /*
244 * Access functions.
245 *
246 * Most of these aren't static because they may be used by the
247 * parport_xxx_yyy macros. extern __inline__ versions of several
248 * of these are in parport_pc.h.
249 */
250
251 static void parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
252 {
253 parport_generic_irq(irq, (struct parport *) dev_id, regs);
254 }
255
256 void parport_pc_write_data(struct parport *p, unsigned char d)
257 {
258 outb (d, DATA (p));
259 }
260
261 unsigned char parport_pc_read_data(struct parport *p)
262 {
263 return inb (DATA (p));
264 }
265
266 void parport_pc_write_control(struct parport *p, unsigned char d)
267 {
268 const unsigned char wm = (PARPORT_CONTROL_STROBE |
269 PARPORT_CONTROL_AUTOFD |
270 PARPORT_CONTROL_INIT |
271 PARPORT_CONTROL_SELECT);
272
273 /* Take this out when drivers have adapted to the newer interface. */
274 if (d & 0x20) {
275 printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
276 p->name, p->cad->name);
277 parport_pc_data_reverse (p);
278 }
279
280 __parport_pc_frob_control (p, wm, d & wm);
281 }
282
283 unsigned char parport_pc_read_control(struct parport *p)
284 {
285 const unsigned char wm = (PARPORT_CONTROL_STROBE |
286 PARPORT_CONTROL_AUTOFD |
287 PARPORT_CONTROL_INIT |
288 PARPORT_CONTROL_SELECT);
289 const struct parport_pc_private *priv = p->physport->private_data;
290 return priv->ctr & wm; /* Use soft copy */
291 }
292
293 unsigned char parport_pc_frob_control (struct parport *p, unsigned char mask,
294 unsigned char val)
295 {
296 const unsigned char wm = (PARPORT_CONTROL_STROBE |
297 PARPORT_CONTROL_AUTOFD |
298 PARPORT_CONTROL_INIT |
299 PARPORT_CONTROL_SELECT);
300
301 /* Take this out when drivers have adapted to the newer interface. */
302 if (mask & 0x20) {
303 printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
304 p->name, p->cad->name,
305 (val & 0x20) ? "reverse" : "forward");
306 if (val & 0x20)
307 parport_pc_data_reverse (p);
308 else
309 parport_pc_data_forward (p);
310 }
311
312 /* Restrict mask and val to control lines. */
313 mask &= wm;
314 val &= wm;
315
316 return __parport_pc_frob_control (p, mask, val);
317 }
318
319 unsigned char parport_pc_read_status(struct parport *p)
320 {
321 return inb (STATUS (p));
322 }
323
324 void parport_pc_disable_irq(struct parport *p)
325 {
326 __parport_pc_frob_control (p, 0x10, 0);
327 }
328
329 void parport_pc_enable_irq(struct parport *p)
330 {
331 __parport_pc_frob_control (p, 0x10, 0x10);
332 }
333
334 void parport_pc_data_forward (struct parport *p)
335 {
336 __parport_pc_frob_control (p, 0x20, 0);
337 }
338
339 void parport_pc_data_reverse (struct parport *p)
340 {
341 __parport_pc_frob_control (p, 0x20, 0x20);
342 }
343
344 void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
345 {
346 s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
347 s->u.pc.ecr = 0x24;
348 }
349
350 void parport_pc_save_state(struct parport *p, struct parport_state *s)
351 {
352 const struct parport_pc_private *priv = p->physport->private_data;
353 s->u.pc.ctr = priv->ctr;
354 if (priv->ecr)
355 s->u.pc.ecr = inb (ECONTROL (p));
356 }
357
358 void parport_pc_restore_state(struct parport *p, struct parport_state *s)
359 {
360 struct parport_pc_private *priv = p->physport->private_data;
361 outb (s->u.pc.ctr, CONTROL (p));
362 priv->ctr = s->u.pc.ctr;
363 if (priv->ecr)
364 outb (s->u.pc.ecr, ECONTROL (p));
365 }
366
367 #ifdef CONFIG_PARPORT_1284
368 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
369 size_t length, int flags)
370 {
371 size_t got = 0;
372
373 if (flags & PARPORT_W91284PIC) {
374 unsigned char status;
375 size_t left = length;
376
377 /* use knowledge about data lines..:
378 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
379 * pError is 1 if there are 16 bytes in the Warp's FIFO
380 */
381 status = inb (STATUS (port));
382
383 while (!(status & 0x08) && (got < length)) {
384 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
385 /* can grab 16 bytes from warp fifo */
386 if (!((long)buf & 0x03)) {
387 insl (EPPDATA (port), buf, 4);
388 } else {
389 insb (EPPDATA (port), buf, 16);
390 }
391 buf += 16;
392 got += 16;
393 left -= 16;
394 } else {
395 /* grab single byte from the warp fifo */
396 *((char *)buf)++ = inb (EPPDATA (port));
397 got++;
398 left--;
399 }
400 status = inb (STATUS (port));
401 if (status & 0x01) {
402 /* EPP timeout should never occur... */
403 printk (KERN_DEBUG "%s: EPP timeout occured while talking to "
404 "w91284pic (should not have done)\n", port->name);
405 clear_epp_timeout (port);
406 }
407 }
408 return got;
409 }
410 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
411 if (!(((long)buf | length) & 0x03)) {
412 insl (EPPDATA (port), buf, (length >> 2));
413 } else {
414 insb (EPPDATA (port), buf, length);
415 }
416 if (inb (STATUS (port)) & 0x01) {
417 clear_epp_timeout (port);
418 return -EIO;
419 }
420 return length;
421 }
422 for (; got < length; got++) {
423 *((char*)buf)++ = inb (EPPDATA(port));
424 if (inb (STATUS (port)) & 0x01) {
425 /* EPP timeout */
426 clear_epp_timeout (port);
427 break;
428 }
429 }
430
431 return got;
432 }
433
434 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
435 size_t length, int flags)
436 {
437 size_t written = 0;
438
439 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
440 if (!(((long)buf | length) & 0x03)) {
441 outsl (EPPDATA (port), buf, (length >> 2));
442 } else {
443 outsb (EPPDATA (port), buf, length);
444 }
445 if (inb (STATUS (port)) & 0x01) {
446 clear_epp_timeout (port);
447 return -EIO;
448 }
449 return length;
450 }
451 for (; written < length; written++) {
452 outb (*((char*)buf)++, EPPDATA(port));
453 if (inb (STATUS(port)) & 0x01) {
454 clear_epp_timeout (port);
455 break;
456 }
457 }
458
459 return written;
460 }
461
462 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
463 size_t length, int flags)
464 {
465 size_t got = 0;
466
467 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
468 insb (EPPADDR (port), buf, length);
469 if (inb (STATUS (port)) & 0x01) {
470 clear_epp_timeout (port);
471 return -EIO;
472 }
473 return length;
474 }
475 for (; got < length; got++) {
476 *((char*)buf)++ = inb (EPPADDR (port));
477 if (inb (STATUS (port)) & 0x01) {
478 clear_epp_timeout (port);
479 break;
480 }
481 }
482
483 return got;
484 }
485
486 static size_t parport_pc_epp_write_addr (struct parport *port,
487 const void *buf, size_t length,
488 int flags)
489 {
490 size_t written = 0;
491
492 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
493 outsb (EPPADDR (port), buf, length);
494 if (inb (STATUS (port)) & 0x01) {
495 clear_epp_timeout (port);
496 return -EIO;
497 }
498 return length;
499 }
500 for (; written < length; written++) {
501 outb (*((char*)buf)++, EPPADDR (port));
502 if (inb (STATUS (port)) & 0x01) {
503 clear_epp_timeout (port);
504 break;
505 }
506 }
507
508 return written;
509 }
510
511 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
512 size_t length, int flags)
513 {
514 size_t got;
515
516 frob_econtrol (port, 0xe0, ECR_EPP << 5);
517 parport_pc_data_reverse (port);
518 parport_pc_write_control (port, 0x4);
519 got = parport_pc_epp_read_data (port, buf, length, flags);
520 frob_econtrol (port, 0xe0, ECR_PS2 << 5);
521
522 return got;
523 }
524
525 static size_t parport_pc_ecpepp_write_data (struct parport *port,
526 const void *buf, size_t length,
527 int flags)
528 {
529 size_t written;
530
531 frob_econtrol (port, 0xe0, ECR_EPP << 5);
532 parport_pc_write_control (port, 0x4);
533 parport_pc_data_forward (port);
534 written = parport_pc_epp_write_data (port, buf, length, flags);
535 frob_econtrol (port, 0xe0, ECR_PS2 << 5);
536
537 return written;
538 }
539
540 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
541 size_t length, int flags)
542 {
543 size_t got;
544
545 frob_econtrol (port, 0xe0, ECR_EPP << 5);
546 parport_pc_data_reverse (port);
547 parport_pc_write_control (port, 0x4);
548 got = parport_pc_epp_read_addr (port, buf, length, flags);
549 frob_econtrol (port, 0xe0, ECR_PS2 << 5);
550
551 return got;
552 }
553
554 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
555 const void *buf, size_t length,
556 int flags)
557 {
558 size_t written;
559
560 frob_econtrol (port, 0xe0, ECR_EPP << 5);
561 parport_pc_write_control (port, 0x4);
562 parport_pc_data_forward (port);
563 written = parport_pc_epp_write_addr (port, buf, length, flags);
564 frob_econtrol (port, 0xe0, ECR_PS2 << 5);
565
566 return written;
567 }
568 #endif /* IEEE 1284 support */
569
570 #ifdef CONFIG_PARPORT_PC_FIFO
571 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
572 const void *buf, size_t length)
573 {
574 int ret = 0;
575 const unsigned char *bufp = buf;
576 size_t left = length;
577 long expire = jiffies + port->physport->cad->timeout;
578 const int fifo = FIFO (port);
579 int poll_for = 8; /* 80 usecs */
580 const struct parport_pc_private *priv = port->physport->private_data;
581 const int fifo_depth = priv->fifo_depth;
582
583 port = port->physport;
584
585 /* We don't want to be interrupted every character. */
586 parport_pc_disable_irq (port);
587 /* set nErrIntrEn and serviceIntr */
588 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
589
590 /* Forward mode. */
591 parport_pc_data_forward (port); /* Must be in PS2 mode */
592
593 while (left) {
594 unsigned char byte;
595 unsigned char ecrval = inb (ECONTROL (port));
596 int i = 0;
597
598 if (current->need_resched && time_before (jiffies, expire))
599 /* Can't yield the port. */
600 schedule ();
601
602 /* Anyone else waiting for the port? */
603 if (port->waithead) {
604 printk (KERN_DEBUG "Somebody wants the port\n");
605 break;
606 }
607
608 if (ecrval & 0x02) {
609 /* FIFO is full. Wait for interrupt. */
610
611 /* Clear serviceIntr */
612 outb (ecrval & ~(1<<2), ECONTROL (port));
613 false_alarm:
614 ret = parport_wait_event (port, HZ);
615 if (ret < 0) break;
616 ret = 0;
617 if (!time_before (jiffies, expire)) {
618 /* Timed out. */
619 printk (KERN_DEBUG "FIFO write timed out\n");
620 break;
621 }
622 ecrval = inb (ECONTROL (port));
623 if (!(ecrval & (1<<2))) {
624 if (current->need_resched &&
625 time_before (jiffies, expire))
626 schedule ();
627
628 goto false_alarm;
629 }
630
631 continue;
632 }
633
634 /* Can't fail now. */
635 expire = jiffies + port->cad->timeout;
636
637 poll:
638 if (signal_pending (current))
639 break;
640
641 if (ecrval & 0x01) {
642 /* FIFO is empty. Blast it full. */
643 const int n = left < fifo_depth ? left : fifo_depth;
644 outsb (fifo, bufp, n);
645 bufp += n;
646 left -= n;
647
648 /* Adjust the poll time. */
649 if (i < (poll_for - 2)) poll_for--;
650 continue;
651 } else if (i++ < poll_for) {
652 udelay (10);
653 ecrval = inb (ECONTROL (port));
654 goto poll;
655 }
656
657 /* Half-full (call me an optimist) */
658 byte = *bufp++;
659 outb (byte, fifo);
660 left--;
661 }
662
663 dump_parport_state ("leave fifo_write_block_dma", port);
664 return length - left;
665 }
666
667 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
668 const void *buf, size_t length)
669 {
670 int ret = 0;
671 unsigned long dmaflag;
672 size_t left = length;
673 const struct parport_pc_private *priv = port->physport->private_data;
674 dma_addr_t dma_addr, dma_handle;
675 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
676 unsigned long start = (unsigned long) buf;
677 unsigned long end = (unsigned long) buf + length - 1;
678
679 dump_parport_state ("enter fifo_write_block_dma", port);
680 if (end < MAX_DMA_ADDRESS) {
681 /* If it would cross a 64k boundary, cap it at the end. */
682 if ((start ^ end) & ~0xffffUL)
683 maxlen = 0x10000 - (start & 0xffff);
684
685 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
686 PCI_DMA_TODEVICE);
687 } else {
688 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
689 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
690 dma_addr = priv->dma_handle;
691 dma_handle = 0;
692 }
693
694 port = port->physport;
695
696 /* We don't want to be interrupted every character. */
697 parport_pc_disable_irq (port);
698 /* set nErrIntrEn and serviceIntr */
699 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
700
701 /* Forward mode. */
702 parport_pc_data_forward (port); /* Must be in PS2 mode */
703
704 while (left) {
705 long expire = jiffies + port->physport->cad->timeout;
706
707 size_t count = left;
708
709 if (count > maxlen)
710 count = maxlen;
711
712 if (!dma_handle) /* bounce buffer ! */
713 memcpy(priv->dma_buf, buf, count);
714
715 dmaflag = claim_dma_lock();
716 disable_dma(port->dma);
717 clear_dma_ff(port->dma);
718 set_dma_mode(port->dma, DMA_MODE_WRITE);
719 set_dma_addr(port->dma, dma_addr);
720 set_dma_count(port->dma, count);
721
722 /* Set DMA mode */
723 frob_econtrol (port, 1<<3, 1<<3);
724
725 /* Clear serviceIntr */
726 frob_econtrol (port, 1<<2, 0);
727
728 enable_dma(port->dma);
729 release_dma_lock(dmaflag);
730
731 /* assume DMA will be successful */
732 left -= count;
733 buf += count;
734 if (dma_handle) dma_addr += count;
735
736 /* Wait for interrupt. */
737 false_alarm:
738 ret = parport_wait_event (port, HZ);
739 if (ret < 0) break;
740 ret = 0;
741 if (!time_before (jiffies, expire)) {
742 /* Timed out. */
743 printk (KERN_DEBUG "DMA write timed out\n");
744 break;
745 }
746 /* Is serviceIntr set? */
747 if (!(inb (ECONTROL (port)) & (1<<2))) {
748 if (current->need_resched)
749 schedule ();
750
751 goto false_alarm;
752 }
753
754 dmaflag = claim_dma_lock();
755 disable_dma(port->dma);
756 clear_dma_ff(port->dma);
757 count = get_dma_residue(port->dma);
758 release_dma_lock(dmaflag);
759
760 if (current->need_resched)
761 /* Can't yield the port. */
762 schedule ();
763
764 /* Anyone else waiting for the port? */
765 if (port->waithead) {
766 printk (KERN_DEBUG "Somebody wants the port\n");
767 break;
768 }
769
770 /* update for possible DMA residue ! */
771 buf -= count;
772 left += count;
773 if (dma_handle) dma_addr -= count;
774 }
775
776 /* Maybe got here through break, so adjust for DMA residue! */
777 dmaflag = claim_dma_lock();
778 disable_dma(port->dma);
779 clear_dma_ff(port->dma);
780 left += get_dma_residue(port->dma);
781 release_dma_lock(dmaflag);
782
783 /* Turn off DMA mode */
784 frob_econtrol (port, 1<<3, 0);
785
786 if (dma_handle)
787 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
788
789 dump_parport_state ("leave fifo_write_block_dma", port);
790 return length - left;
791 }
792
793 /* Parallel Port FIFO mode (ECP chipsets) */
794 size_t parport_pc_compat_write_block_pio (struct parport *port,
795 const void *buf, size_t length,
796 int flags)
797 {
798 size_t written;
799 int r;
800
801 /* Special case: a timeout of zero means we cannot call schedule(). */
802 if (!port->physport->cad->timeout)
803 return parport_ieee1284_write_compat (port, buf,
804 length, flags);
805
806 /* Set up parallel port FIFO mode.*/
807 parport_pc_data_forward (port); /* Must be in PS2 mode */
808 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
809 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
810 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
811
812 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
813
814 /* Write the data to the FIFO. */
815 if (port->dma != PARPORT_DMA_NONE)
816 written = parport_pc_fifo_write_block_dma (port, buf, length);
817 else
818 written = parport_pc_fifo_write_block_pio (port, buf, length);
819
820 /* Finish up. */
821 if (change_mode (port, ECR_PS2) == -EBUSY) {
822 const struct parport_pc_private *priv =
823 port->physport->private_data;
824
825 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
826
827 /* Prevent further data transfer. */
828 frob_econtrol (port, 0xe0, ECR_TST << 5);
829
830 /* Adjust for the contents of the FIFO. */
831 for (written -= priv->fifo_depth; ; written++) {
832 if (inb (ECONTROL (port)) & 0x2) {
833 /* Full up. */
834 break;
835 }
836 outb (0, FIFO (port));
837 }
838
839 /* Reset the FIFO and return to PS2 mode. */
840 frob_econtrol (port, 0xe0, ECR_PS2 << 5);
841 }
842
843 r = parport_wait_peripheral (port,
844 PARPORT_STATUS_BUSY,
845 PARPORT_STATUS_BUSY);
846 if (r)
847 printk (KERN_DEBUG
848 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
849 port->name, r);
850
851 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
852
853 return written;
854 }
855
856 /* ECP */
857 #ifdef CONFIG_PARPORT_1284
858 size_t parport_pc_ecp_write_block_pio (struct parport *port,
859 const void *buf, size_t length,
860 int flags)
861 {
862 size_t written;
863 int r;
864
865 /* Special case: a timeout of zero means we cannot call schedule(). */
866 if (!port->physport->cad->timeout)
867 return parport_ieee1284_ecp_write_data (port, buf,
868 length, flags);
869
870 /* Switch to forward mode if necessary. */
871 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
872 /* Event 47: Set nInit high. */
873 parport_frob_control (port,
874 PARPORT_CONTROL_INIT
875 | PARPORT_CONTROL_AUTOFD,
876 PARPORT_CONTROL_INIT
877 | PARPORT_CONTROL_AUTOFD);
878
879 /* Event 49: PError goes high. */
880 r = parport_wait_peripheral (port,
881 PARPORT_STATUS_PAPEROUT,
882 PARPORT_STATUS_PAPEROUT);
883 if (r) {
884 printk (KERN_DEBUG "%s: PError timeout (%d) "
885 "in ecp_write_block_pio\n", port->name, r);
886 }
887 }
888
889 /* Set up ECP parallel port mode.*/
890 parport_pc_data_forward (port); /* Must be in PS2 mode */
891 parport_pc_frob_control (port,
892 PARPORT_CONTROL_STROBE |
893 PARPORT_CONTROL_AUTOFD,
894 0);
895 r = change_mode (port, ECR_ECP); /* ECP FIFO */
896 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
897 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
898
899 /* Write the data to the FIFO. */
900 if (port->dma != PARPORT_DMA_NONE)
901 written = parport_pc_fifo_write_block_dma (port, buf, length);
902 else
903 written = parport_pc_fifo_write_block_pio (port, buf, length);
904
905 /* Finish up. */
906 if (change_mode (port, ECR_PS2) == -EBUSY) {
907 const struct parport_pc_private *priv =
908 port->physport->private_data;
909
910 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
911
912 /* Prevent further data transfer. */
913 frob_econtrol (port, 0xe0, ECR_TST << 5);
914
915 /* Adjust for the contents of the FIFO. */
916 for (written -= priv->fifo_depth; ; written++) {
917 if (inb (ECONTROL (port)) & 0x2) {
918 /* Full up. */
919 break;
920 }
921 outb (0, FIFO (port));
922 }
923
924 /* Reset the FIFO and return to PS2 mode. */
925 frob_econtrol (port, 0xe0, ECR_PS2 << 5);
926
927 /* Host transfer recovery. */
928 parport_pc_data_reverse (port); /* Must be in PS2 mode */
929 udelay (5);
930 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
931 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
932 if (r)
933 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
934 "in ecp_write_block_pio\n", port->name, r);
935
936 parport_frob_control (port,
937 PARPORT_CONTROL_INIT,
938 PARPORT_CONTROL_INIT);
939 r = parport_wait_peripheral (port,
940 PARPORT_STATUS_PAPEROUT,
941 PARPORT_STATUS_PAPEROUT);
942 if (r)
943 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
944 "in ecp_write_block_pio\n", port->name, r);
945 }
946
947 r = parport_wait_peripheral (port,
948 PARPORT_STATUS_BUSY,
949 PARPORT_STATUS_BUSY);
950 if(r)
951 printk (KERN_DEBUG
952 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
953 port->name, r);
954
955 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
956
957 return written;
958 }
959
960 size_t parport_pc_ecp_read_block_pio (struct parport *port,
961 void *buf, size_t length, int flags)
962 {
963 size_t left = length;
964 size_t fifofull;
965 int r;
966 const int fifo = FIFO(port);
967 const struct parport_pc_private *priv = port->physport->private_data;
968 const int fifo_depth = priv->fifo_depth;
969 char *bufp = buf;
970
971 port = port->physport;
972 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
973 dump_parport_state ("enter fcn", port);
974
975 /* Special case: a timeout of zero means we cannot call schedule(). */
976 if (!port->cad->timeout)
977 return parport_ieee1284_ecp_read_data (port, buf,
978 length, flags);
979
980 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
981 /* If the peripheral is allowed to send RLE compressed
982 * data, it is possible for a byte to expand to 128
983 * bytes in the FIFO. */
984 fifofull = 128;
985 } else {
986 fifofull = fifo_depth;
987 }
988
989 /* If the caller wants less than a full FIFO's worth of data,
990 * go through software emulation. Otherwise we may have to throw
991 * away data. */
992 if (length < fifofull)
993 return parport_ieee1284_ecp_read_data (port, buf,
994 length, flags);
995
996 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
997 /* change to reverse-idle phase (must be in forward-idle) */
998
999 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
1000 parport_frob_control (port,
1001 PARPORT_CONTROL_AUTOFD
1002 | PARPORT_CONTROL_STROBE,
1003 PARPORT_CONTROL_AUTOFD);
1004 parport_pc_data_reverse (port); /* Must be in PS2 mode */
1005 udelay (5);
1006 /* Event 39: Set nInit low to initiate bus reversal */
1007 parport_frob_control (port,
1008 PARPORT_CONTROL_INIT,
1009 0);
1010 /* Event 40: Wait for nAckReverse (PError) to go low */
1011 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
1012 if (r) {
1013 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
1014 "in ecp_read_block_pio\n", port->name, r);
1015 return 0;
1016 }
1017 }
1018
1019 /* Set up ECP FIFO mode.*/
1020 /* parport_pc_frob_control (port,
1021 PARPORT_CONTROL_STROBE |
1022 PARPORT_CONTROL_AUTOFD,
1023 PARPORT_CONTROL_AUTOFD); */
1024 r = change_mode (port, ECR_ECP); /* ECP FIFO */
1025 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
1026
1027 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1028
1029 /* the first byte must be collected manually */
1030 dump_parport_state ("pre 43", port);
1031 /* Event 43: Wait for nAck to go low */
1032 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1033 if (r) {
1034 /* timed out while reading -- no data */
1035 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1036 goto out_no_data;
1037 }
1038 /* read byte */
1039 *bufp++ = inb (DATA (port));
1040 left--;
1041 dump_parport_state ("43-44", port);
1042 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1043 parport_pc_frob_control (port,
1044 PARPORT_CONTROL_AUTOFD,
1045 0);
1046 dump_parport_state ("pre 45", port);
1047 /* Event 45: Wait for nAck to go high */
1048 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1049 dump_parport_state ("post 45", port);
1050 r = 0;
1051 if (r) {
1052 /* timed out while waiting for peripheral to respond to ack */
1053 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1054
1055 /* keep hold of the byte we've got already */
1056 goto out_no_data;
1057 }
1058 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1059 parport_pc_frob_control (port,
1060 PARPORT_CONTROL_AUTOFD,
1061 PARPORT_CONTROL_AUTOFD);
1062
1063
1064 dump_parport_state ("rev idle", port);
1065 /* Do the transfer. */
1066 while (left > fifofull) {
1067 int ret;
1068 long int expire = jiffies + port->cad->timeout;
1069 unsigned char ecrval = inb (ECONTROL (port));
1070
1071 if (current->need_resched && time_before (jiffies, expire))
1072 /* Can't yield the port. */
1073 schedule ();
1074
1075 /* At this point, the FIFO may already be full. In
1076 * that case ECP is already holding back the
1077 * peripheral (assuming proper design) with a delayed
1078 * handshake. Work fast to avoid a peripheral
1079 * timeout. */
1080
1081 if (ecrval & 0x01) {
1082 /* FIFO is empty. Wait for interrupt. */
1083 dump_parport_state ("FIFO empty", port);
1084
1085 /* Anyone else waiting for the port? */
1086 if (port->waithead) {
1087 printk (KERN_DEBUG "Somebody wants the port\n");
1088 break;
1089 }
1090
1091 /* Clear serviceIntr */
1092 outb (ecrval & ~(1<<2), ECONTROL (port));
1093 false_alarm:
1094 dump_parport_state ("waiting", port);
1095 ret = parport_wait_event (port, HZ);
1096 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1097 if (ret < 0)
1098 break;
1099 ret = 0;
1100 if (!time_before (jiffies, expire)) {
1101 /* Timed out. */
1102 dump_parport_state ("timeout", port);
1103 printk (KERN_DEBUG "PIO read timed out\n");
1104 break;
1105 }
1106 ecrval = inb (ECONTROL (port));
1107 if (!(ecrval & (1<<2))) {
1108 if (current->need_resched &&
1109 time_before (jiffies, expire)) {
1110 schedule ();
1111 }
1112 goto false_alarm;
1113 }
1114
1115 /* Depending on how the FIFO threshold was
1116 * set, how long interrupt service took, and
1117 * how fast the peripheral is, we might be
1118 * lucky and have a just filled FIFO. */
1119 continue;
1120 }
1121
1122 if (ecrval & 0x02) {
1123 /* FIFO is full. */
1124 dump_parport_state ("FIFO full", port);
1125 insb (fifo, bufp, fifo_depth);
1126 bufp += fifo_depth;
1127 left -= fifo_depth;
1128 continue;
1129 }
1130
1131 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1132
1133 /* FIFO not filled. We will cycle this loop for a while
1134 * and either the peripheral will fill it faster,
1135 * tripping a fast empty with insb, or we empty it. */
1136 *bufp++ = inb (fifo);
1137 left--;
1138 }
1139
1140 /* scoop up anything left in the FIFO */
1141 while (left && !(inb (ECONTROL (port) & 0x01))) {
1142 *bufp++ = inb (fifo);
1143 left--;
1144 }
1145
1146 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1147 dump_parport_state ("rev idle2", port);
1148
1149 out_no_data:
1150
1151 /* Go to forward idle mode to shut the peripheral up (event 47). */
1152 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1153
1154 /* event 49: PError goes high */
1155 r = parport_wait_peripheral (port,
1156 PARPORT_STATUS_PAPEROUT,
1157 PARPORT_STATUS_PAPEROUT);
1158 if (r) {
1159 printk (KERN_DEBUG
1160 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1161 port->name, r);
1162 }
1163
1164 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1165
1166 /* Finish up. */
1167 {
1168 int lost = get_fifo_residue (port);
1169 if (lost)
1170 /* Shouldn't happen with compliant peripherals. */
1171 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1172 port->name, lost);
1173 }
1174
1175 dump_parport_state ("fwd idle", port);
1176 return length - left;
1177 }
1178
1179 #endif /* IEEE 1284 support */
1180 #endif /* Allowed to use FIFO/DMA */
1181
1182
1183 /*
1184 * ******************************************
1185 * INITIALISATION AND MODULE STUFF BELOW HERE
1186 * ******************************************
1187 */
1188
1189
1190 void parport_pc_inc_use_count(void)
1191 {
1192 #ifdef MODULE
1193 MOD_INC_USE_COUNT;
1194 #endif
1195 }
1196
1197 void parport_pc_dec_use_count(void)
1198 {
1199 #ifdef MODULE
1200 MOD_DEC_USE_COUNT;
1201 #endif
1202 }
1203
1204 struct parport_operations parport_pc_ops =
1205 {
1206 parport_pc_write_data,
1207 parport_pc_read_data,
1208
1209 parport_pc_write_control,
1210 parport_pc_read_control,
1211 parport_pc_frob_control,
1212
1213 parport_pc_read_status,
1214
1215 parport_pc_enable_irq,
1216 parport_pc_disable_irq,
1217
1218 parport_pc_data_forward,
1219 parport_pc_data_reverse,
1220
1221 parport_pc_init_state,
1222 parport_pc_save_state,
1223 parport_pc_restore_state,
1224
1225 parport_pc_inc_use_count,
1226 parport_pc_dec_use_count,
1227
1228 parport_ieee1284_epp_write_data,
1229 parport_ieee1284_epp_read_data,
1230 parport_ieee1284_epp_write_addr,
1231 parport_ieee1284_epp_read_addr,
1232
1233 parport_ieee1284_ecp_write_data,
1234 parport_ieee1284_ecp_read_data,
1235 parport_ieee1284_ecp_write_addr,
1236
1237 parport_ieee1284_write_compat,
1238 parport_ieee1284_read_nibble,
1239 parport_ieee1284_read_byte,
1240 };
1241
1242 #ifdef CONFIG_PARPORT_PC_SUPERIO
1243 /* Super-IO chipset detection, Winbond, SMSC */
1244 static void __devinit show_parconfig_smsc37c669(int io, int key)
1245 {
1246 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1247 char *modes[]={ "SPP and Bidirectional (PS/2)",
1248 "EPP and SPP",
1249 "ECP",
1250 "ECP and EPP"};
1251
1252 outb(key,io);
1253 outb(key,io);
1254 outb(1,io);
1255 cr1=inb(io+1);
1256 outb(4,io);
1257 cr4=inb(io+1);
1258 outb(0x0a,io);
1259 cra=inb(io+1);
1260 outb(0x23,io);
1261 cr23=inb(io+1);
1262 outb(0x26,io);
1263 cr26=inb(io+1);
1264 outb(0x27,io);
1265 cr27=inb(io+1);
1266 outb(0xaa,io);
1267
1268 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1269 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1270 cr1,cr4,cra,cr23,cr26,cr27);
1271
1272 /* The documentation calls DMA and IRQ-Lines by letters, so
1273 the board maker can/will wire them
1274 appropriately/randomly... G=reserved H=IDE-irq, */
1275 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1276 "fifo threshold=%d\n", cr23*4,
1277 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1278 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1279 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1280 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1281 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1282 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1283 (cr4 & 0x40) ? "1.7" : "1.9");
1284
1285 /* Heuristics ! BIOS setup for this mainboard device limits
1286 the choices to standard settings, i.e. io-address and IRQ
1287 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1288 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1289 if(cr23*4 >=0x100) { /* if active */
1290 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1291 i++;
1292 if(i==NR_SUPERIOS)
1293 printk(KERN_INFO "Super-IO: too many chips!\n");
1294 else {
1295 int d;
1296 switch (cr23*4) {
1297 case 0x3bc:
1298 superios[i].io = 0x3bc;
1299 superios[i].irq = 7;
1300 break;
1301 case 0x378:
1302 superios[i].io = 0x378;
1303 superios[i].irq = 7;
1304 break;
1305 case 0x278:
1306 superios[i].io = 0x278;
1307 superios[i].irq = 5;
1308 }
1309 d=(cr26 &0x0f);
1310 if((d==1) || (d==3))
1311 superios[i].dma= d;
1312 else
1313 superios[i].dma= PARPORT_DMA_NONE;
1314 }
1315 }
1316 }
1317
1318
1319 static void __devinit show_parconfig_winbond(int io, int key)
1320 {
1321 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1322 char *modes[]={ "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1323 "EPP-1.9 and SPP",
1324 "ECP",
1325 "ECP and EPP-1.9",
1326 "Standard (SPP)",
1327 "EPP-1.7 and SPP", /* 5 */
1328 "undefined!",
1329 "ECP and EPP-1.7"};
1330 char *irqtypes[]={"pulsed low, high-Z", "follows nACK"};
1331
1332 /* The registers are called compatible-PnP because the
1333 register layout is modelled after ISA-PnP, the access
1334 method is just another ... */
1335 outb(key,io);
1336 outb(key,io);
1337 outb(0x07,io); /* Register 7: Select Logical Device */
1338 outb(0x01,io+1); /* LD1 is Parallel Port */
1339 outb(0x30,io);
1340 cr30=inb(io+1);
1341 outb(0x60,io);
1342 cr60=inb(io+1);
1343 outb(0x61,io);
1344 cr61=inb(io+1);
1345 outb(0x70,io);
1346 cr70=inb(io+1);
1347 outb(0x74,io);
1348 cr74=inb(io+1);
1349 outb(0xf0,io);
1350 crf0=inb(io+1);
1351 outb(0xaa,io);
1352
1353 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1354 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1355 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1356 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1357 if ((cr74 & 0x07) > 3)
1358 printk("dma=none\n");
1359 else
1360 printk("dma=%d\n",cr74 & 0x07);
1361 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1362 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1363 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1364
1365 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1366 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1367 i++;
1368 if(i==NR_SUPERIOS)
1369 printk(KERN_INFO "Super-IO: too many chips!\n");
1370 else {
1371 superios[i].io = (cr60<<8)|cr61;
1372 superios[i].irq = cr70&0x0f;
1373 superios[i].dma = (((cr74 & 0x07) > 3) ?
1374 PARPORT_DMA_NONE : (cr74 & 0x07));
1375 }
1376 }
1377 }
1378
1379 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1380 {
1381 char *type=NULL;
1382 int id,progif=2;
1383
1384 if (devid == devrev)
1385 /* simple heuristics, we happened to read some
1386 non-winbond register */
1387 return;
1388
1389 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x "
1390 "oldid=%02x\n", efer,key,devid,devrev,oldid);
1391 id=(devid<<8) | devrev;
1392
1393 /* Values are from public data sheets pdf files, I can just
1394 confirm 83977TF is correct :-) */
1395 if (id == 0x9771) type="83977F/AF";
1396 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1397 else if (id == 0x9774) type="83977ATF";
1398 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1399 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1400 else if ((id & ~0x0f) == 0x5210) type="83627";
1401 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1402 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1403 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1404 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1405 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1406 else progif=0;
1407
1408 if(type==NULL)
1409 printk(KERN_INFO "Winbond unknown chip type\n");
1410 else
1411 printk(KERN_INFO "Winbond chip type %s\n",type);
1412
1413 if(progif==2)
1414 show_parconfig_winbond(efer,key);
1415 return;
1416 }
1417
1418 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1419 {
1420 char *type=NULL;
1421 void (*func)(int io, int key);
1422 int id;
1423
1424 if (devid == devrev)
1425 /* simple heuristics, we happened to read some
1426 non-smsc register */
1427 return;
1428
1429 func=NULL;
1430 printk(KERN_INFO "SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x\n",
1431 efer,key,devid,devrev);
1432 id=(devid<<8) | devrev;
1433
1434 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1435 else if (id==0x6582) type="37c665IR";
1436 else if (devid==0x65) type="37c665GT";
1437 else if (devid==0x66) type="37c666GT";
1438
1439 if(type==NULL)
1440 printk(KERN_INFO "SMSC unknown chip type\n");
1441 else
1442 printk(KERN_INFO "SMSC chip type %s\n",type);
1443
1444 if(func) (func)(efer,key);
1445 return;
1446 }
1447
1448
1449 static void __devinit winbond_check(int io, int key)
1450 {
1451 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1452
1453 /* First probe without key */
1454 outb(0x20,io);
1455 x_devid=inb(io+1);
1456 outb(0x21,io);
1457 x_devrev=inb(io+1);
1458 outb(0x09,io);
1459 x_oldid=inb(io+1);
1460
1461 outb(key,io);
1462 outb(key,io); /* Write Magic Sequence to EFER, extended
1463 funtion enable register */
1464 outb(0x20,io); /* Write EFIR, extended function index register */
1465 devid=inb(io+1); /* Read EFDR, extended function data register */
1466 outb(0x21,io);
1467 devrev=inb(io+1);
1468 outb(0x09,io);
1469 oldid=inb(io+1);
1470 outb(0xaa,io); /* Magic Seal */
1471
1472 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1473 return; /* protection against false positives */
1474
1475 decode_winbond(io,key,devid,devrev,oldid);
1476 }
1477
1478 static void __devinit winbond_check2(int io,int key)
1479 {
1480 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1481
1482 /* First probe without the key */
1483 outb(0x20,io+2);
1484 x_devid=inb(io+2);
1485 outb(0x21,io+1);
1486 x_devrev=inb(io+2);
1487 outb(0x09,io+1);
1488 x_oldid=inb(io+2);
1489
1490 outb(key,io); /* Write Magic Byte to EFER, extended
1491 funtion enable register */
1492 outb(0x20,io+2); /* Write EFIR, extended function index register */
1493 devid=inb(io+2); /* Read EFDR, extended function data register */
1494 outb(0x21,io+1);
1495 devrev=inb(io+2);
1496 outb(0x09,io+1);
1497 oldid=inb(io+2);
1498 outb(0xaa,io); /* Magic Seal */
1499
1500 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1501 return; /* protection against false positives */
1502
1503 decode_winbond(io,key,devid,devrev,oldid);
1504 }
1505
1506 static void __devinit smsc_check(int io, int key)
1507 {
1508 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1509
1510 /* First probe without the key */
1511 outb(0x0d,io);
1512 x_oldid=inb(io+1);
1513 outb(0x0e,io);
1514 x_oldrev=inb(io+1);
1515 outb(0x20,io);
1516 x_id=inb(io+1);
1517 outb(0x21,io);
1518 x_rev=inb(io+1);
1519
1520 outb(key,io);
1521 outb(key,io); /* Write Magic Sequence to EFER, extended
1522 funtion enable register */
1523 outb(0x0d,io); /* Write EFIR, extended function index register */
1524 oldid=inb(io+1); /* Read EFDR, extended function data register */
1525 outb(0x0e,io);
1526 oldrev=inb(io+1);
1527 outb(0x20,io);
1528 id=inb(io+1);
1529 outb(0x21,io);
1530 rev=inb(io+1);
1531 outb(0xaa,io); /* Magic Seal */
1532
1533 if ((x_id == id) && (x_oldrev == oldrev) &&
1534 (x_oldid == oldid) && (x_rev == rev))
1535 return; /* protection against false positives */
1536
1537 decode_smsc(io,key,oldid,oldrev);
1538 }
1539
1540
1541 static void __devinit detect_and_report_winbond (void)
1542 {
1543 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1544
1545 winbond_check(0x3f0,0x87);
1546 winbond_check(0x370,0x87);
1547 winbond_check(0x2e ,0x87);
1548 winbond_check(0x4e ,0x87);
1549 winbond_check(0x3f0,0x86);
1550 winbond_check2(0x250,0x88);
1551 winbond_check2(0x250,0x89);
1552 }
1553
1554 static void __devinit detect_and_report_smsc (void)
1555 {
1556 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1557 smsc_check(0x3f0,0x55);
1558 smsc_check(0x370,0x55);
1559 smsc_check(0x3f0,0x44);
1560 smsc_check(0x370,0x44);
1561 }
1562 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1563
1564 static int __devinit get_superio_dma (struct parport *p)
1565 {
1566 int i=0;
1567 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1568 i++;
1569 if (i!=NR_SUPERIOS)
1570 return superios[i].dma;
1571 return PARPORT_DMA_NONE;
1572 }
1573
1574 static int __devinit get_superio_irq (struct parport *p)
1575 {
1576 int i=0;
1577 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1578 i++;
1579 if (i!=NR_SUPERIOS)
1580 return superios[i].irq;
1581 return PARPORT_IRQ_NONE;
1582 }
1583
1584
1585 /* --- Mode detection ------------------------------------- */
1586
1587 /*
1588 * Checks for port existence, all ports support SPP MODE
1589 * Returns:
1590 * 0 : No parallel port at this adress
1591 * PARPORT_MODE_PCSPP : SPP port detected
1592 * (if the user specified an ioport himself,
1593 * this shall always be the case!)
1594 *
1595 */
1596 static int __devinit parport_SPP_supported(struct parport *pb)
1597 {
1598 unsigned char r, w;
1599
1600 /*
1601 * first clear an eventually pending EPP timeout
1602 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1603 * that does not even respond to SPP cycles if an EPP
1604 * timeout is pending
1605 */
1606 clear_epp_timeout(pb);
1607
1608 /* Do a simple read-write test to make sure the port exists. */
1609 w = 0xc;
1610 outb (w, CONTROL (pb));
1611
1612 /* Is there a control register that we can read from? Some
1613 * ports don't allow reads, so read_control just returns a
1614 * software copy. Some ports _do_ allow reads, so bypass the
1615 * software copy here. In addition, some bits aren't
1616 * writable. */
1617 r = inb (CONTROL (pb));
1618 if ((r & 0xf) == w) {
1619 w = 0xe;
1620 outb (w, CONTROL (pb));
1621 r = inb (CONTROL (pb));
1622 outb (0xc, CONTROL (pb));
1623 if ((r & 0xf) == w)
1624 return PARPORT_MODE_PCSPP;
1625 }
1626
1627 if (user_specified)
1628 /* That didn't work, but the user thinks there's a
1629 * port here. */
1630 printk (KERN_DEBUG "parport 0x%lx (WARNING): CTR: "
1631 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1632
1633 /* Try the data register. The data lines aren't tri-stated at
1634 * this stage, so we expect back what we wrote. */
1635 w = 0xaa;
1636 parport_pc_write_data (pb, w);
1637 r = parport_pc_read_data (pb);
1638 if (r == w) {
1639 w = 0x55;
1640 parport_pc_write_data (pb, w);
1641 r = parport_pc_read_data (pb);
1642 if (r == w)
1643 return PARPORT_MODE_PCSPP;
1644 }
1645
1646 if (user_specified) {
1647 /* Didn't work, but the user is convinced this is the
1648 * place. */
1649 printk (KERN_DEBUG "parport 0x%lx (WARNING): DATA: "
1650 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1651 printk (KERN_DEBUG "parport 0x%lx: You gave this address, "
1652 "but there is probably no parallel port there!\n",
1653 pb->base);
1654 }
1655
1656 /* It's possible that we can't read the control register or
1657 * the data register. In that case just believe the user. */
1658 if (user_specified)
1659 return PARPORT_MODE_PCSPP;
1660
1661 return 0;
1662 }
1663
1664 /* Check for ECR
1665 *
1666 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1667 * on these cards actually accesses the CTR.
1668 *
1669 * Modern cards don't do this but reading from ECR will return 0xff
1670 * regardless of what is written here if the card does NOT support
1671 * ECP.
1672 *
1673 * We first check to see if ECR is the same as CTR. If not, the low
1674 * two bits of ECR aren't writable, so we check by writing ECR and
1675 * reading it back to see if it's what we expect.
1676 */
1677 static int __devinit parport_ECR_present(struct parport *pb)
1678 {
1679 struct parport_pc_private *priv = pb->private_data;
1680 unsigned char r = 0xc;
1681
1682 outb (r, CONTROL (pb));
1683 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1684 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1685
1686 r = inb (CONTROL (pb));
1687 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1688 goto no_reg; /* Sure that no ECR register exists */
1689 }
1690
1691 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1692 goto no_reg;
1693
1694 outb (0x34, ECONTROL (pb));
1695 if (inb (ECONTROL (pb)) != 0x35)
1696 goto no_reg;
1697
1698 priv->ecr = 1;
1699 outb (0xc, CONTROL (pb));
1700
1701 /* Go to mode 000 */
1702 frob_econtrol (pb, 0xe0, ECR_SPP << 5);
1703
1704 return 1;
1705
1706 no_reg:
1707 outb (0xc, CONTROL (pb));
1708 return 0;
1709 }
1710
1711 #ifdef CONFIG_PARPORT_1284
1712 /* Detect PS/2 support.
1713 *
1714 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1715 * allows us to read data from the data lines. In theory we would get back
1716 * 0xff but any peripheral attached to the port may drag some or all of the
1717 * lines down to zero. So if we get back anything that isn't the contents
1718 * of the data register we deem PS/2 support to be present.
1719 *
1720 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1721 * drivers, but an external peripheral with sufficiently beefy drivers of
1722 * its own can overpower them and assert its own levels onto the bus, from
1723 * where they can then be read back as normal. Ports with this property
1724 * and the right type of device attached are likely to fail the SPP test,
1725 * (as they will appear to have stuck bits) and so the fact that they might
1726 * be misdetected here is rather academic.
1727 */
1728
1729 static int __devinit parport_PS2_supported(struct parport *pb)
1730 {
1731 int ok = 0;
1732
1733 clear_epp_timeout(pb);
1734
1735 /* try to tri-state the buffer */
1736 parport_pc_data_reverse (pb);
1737
1738 parport_pc_write_data(pb, 0x55);
1739 if (parport_pc_read_data(pb) != 0x55) ok++;
1740
1741 parport_pc_write_data(pb, 0xaa);
1742 if (parport_pc_read_data(pb) != 0xaa) ok++;
1743
1744 /* cancel input mode */
1745 parport_pc_data_forward (pb);
1746
1747 if (ok) {
1748 pb->modes |= PARPORT_MODE_TRISTATE;
1749 } else {
1750 struct parport_pc_private *priv = pb->private_data;
1751 priv->ctr_writable &= ~0x20;
1752 }
1753
1754 return ok;
1755 }
1756
1757 static int __devinit parport_ECP_supported(struct parport *pb)
1758 {
1759 int i;
1760 int config, configb;
1761 int pword;
1762 struct parport_pc_private *priv = pb->private_data;
1763 int intrline[]={0,7,9,10,11,14,15,5}; /* Translate ECP
1764 intrLine to ISA irq
1765 value */
1766
1767 /* If there is no ECR, we have no hope of supporting ECP. */
1768 if (!priv->ecr)
1769 return 0;
1770
1771 /* Find out FIFO depth */
1772 outb (ECR_SPP << 5, ECONTROL (pb)); /* Reset FIFO */
1773 outb (ECR_TST << 5, ECONTROL (pb)); /* TEST FIFO */
1774 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1775 outb (0xaa, FIFO (pb));
1776
1777 /*
1778 * Using LGS chipset it uses ECR register, but
1779 * it doesn't support ECP or FIFO MODE
1780 */
1781 if (i == 1024) {
1782 outb (ECR_SPP << 5, ECONTROL (pb));
1783 return 0;
1784 }
1785
1786 priv->fifo_depth = i;
1787 printk (KERN_INFO "0x%lx: FIFO is %d bytes\n", pb->base, i);
1788
1789 /* Find out writeIntrThreshold */
1790 frob_econtrol (pb, 1<<2, 1<<2);
1791 frob_econtrol (pb, 1<<2, 0);
1792 for (i = 1; i <= priv->fifo_depth; i++) {
1793 inb (FIFO (pb));
1794 udelay (50);
1795 if (inb (ECONTROL (pb)) & (1<<2))
1796 break;
1797 }
1798
1799 if (i <= priv->fifo_depth)
1800 printk (KERN_INFO "0x%lx: writeIntrThreshold is %d\n",
1801 pb->base, i);
1802 else
1803 /* Number of bytes we know we can write if we get an
1804 interrupt. */
1805 i = 0;
1806
1807 priv->writeIntrThreshold = i;
1808
1809 /* Find out readIntrThreshold */
1810 frob_econtrol (pb, 0xe0, ECR_PS2 << 5); /* Reset FIFO and enable PS2 */
1811 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1812 frob_econtrol (pb, 0xe0, ECR_TST << 5); /* Test FIFO */
1813 frob_econtrol (pb, 1<<2, 1<<2);
1814 frob_econtrol (pb, 1<<2, 0);
1815 for (i = 1; i <= priv->fifo_depth; i++) {
1816 outb (0xaa, FIFO (pb));
1817 if (inb (ECONTROL (pb)) & (1<<2))
1818 break;
1819 }
1820
1821 if (i <= priv->fifo_depth)
1822 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1823 pb->base, i);
1824 else
1825 /* Number of bytes we can read if we get an interrupt. */
1826 i = 0;
1827
1828 priv->readIntrThreshold = i;
1829
1830 outb (ECR_SPP << 5, ECONTROL (pb)); /* Reset FIFO */
1831 outb (0xf4, ECONTROL (pb)); /* Configuration mode */
1832 config = inb (CONFIGA (pb));
1833 pword = (config >> 4) & 0x7;
1834 switch (pword) {
1835 case 0:
1836 pword = 2;
1837 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1838 pb->base);
1839 break;
1840 case 2:
1841 pword = 4;
1842 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1843 pb->base);
1844 break;
1845 default:
1846 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1847 pb->base);
1848 /* Assume 1 */
1849 case 1:
1850 pword = 1;
1851 }
1852 priv->pword = pword;
1853 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1854
1855 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1856 config & 0x80 ? "Level" : "Pulses");
1857
1858 configb = inb (CONFIGB (pb));
1859 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1860 pb->base, config, configb);
1861 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1862 if ((configb >>3) & 0x07)
1863 printk("%d",intrline[(configb >>3) & 0x07]);
1864 else
1865 printk("<none or set by other means>");
1866 printk (" dma=");
1867 if( (configb & 0x03 ) == 0x00)
1868 printk("<none or set by other means>\n");
1869 else
1870 printk("%d\n",configb & 0x07);
1871
1872 /* Go back to mode 000 */
1873 frob_econtrol (pb, 0xe0, ECR_SPP << 5);
1874 pb->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
1875
1876 return 1;
1877 }
1878
1879 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1880 {
1881 const struct parport_pc_private *priv = pb->private_data;
1882 int result;
1883 unsigned char oecr;
1884
1885 if (!priv->ecr)
1886 return 0;
1887
1888 oecr = inb (ECONTROL (pb));
1889 outb (ECR_PS2 << 5, ECONTROL (pb));
1890
1891 result = parport_PS2_supported(pb);
1892
1893 outb (oecr, ECONTROL (pb));
1894 return result;
1895 }
1896
1897 /* EPP mode detection */
1898
1899 static int __devinit parport_EPP_supported(struct parport *pb)
1900 {
1901 const struct parport_pc_private *priv = pb->private_data;
1902
1903 /*
1904 * Theory:
1905 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1906 * when EPP is possible and is set high when an EPP timeout
1907 * occurs (EPP uses the HALT line to stop the CPU while it does
1908 * the byte transfer, an EPP timeout occurs if the attached
1909 * device fails to respond after 10 micro seconds).
1910 *
1911 * This bit is cleared by either reading it (National Semi)
1912 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1913 * This bit is always high in non EPP modes.
1914 */
1915
1916 /* If EPP timeout bit clear then EPP available */
1917 if (!clear_epp_timeout(pb)) {
1918 return 0; /* No way to clear timeout */
1919 }
1920
1921 /* Check for Intel bug. */
1922 if (priv->ecr) {
1923 unsigned char i;
1924 for (i = 0x00; i < 0x80; i += 0x20) {
1925 outb (i, ECONTROL (pb));
1926 if (clear_epp_timeout (pb)) {
1927 /* Phony EPP in ECP. */
1928 return 0;
1929 }
1930 }
1931 }
1932
1933 pb->modes |= PARPORT_MODE_EPP;
1934
1935 /* Set up access functions to use EPP hardware. */
1936 pb->ops->epp_read_data = parport_pc_epp_read_data;
1937 pb->ops->epp_write_data = parport_pc_epp_write_data;
1938 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1939 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1940
1941 return 1;
1942 }
1943
1944 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1945 {
1946 struct parport_pc_private *priv = pb->private_data;
1947 int result;
1948 unsigned char oecr;
1949
1950 if (!priv->ecr) {
1951 return 0;
1952 }
1953
1954 oecr = inb (ECONTROL (pb));
1955 /* Search for SMC style EPP+ECP mode */
1956 outb (0x80, ECONTROL (pb));
1957 outb (0x04, CONTROL (pb));
1958 result = parport_EPP_supported(pb);
1959
1960 outb (oecr, ECONTROL (pb));
1961
1962 if (result) {
1963 /* Set up access functions to use ECP+EPP hardware. */
1964 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1965 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1966 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1967 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1968 }
1969
1970 return result;
1971 }
1972
1973 #else /* No IEEE 1284 support */
1974
1975 /* Don't bother probing for modes we know we won't use. */
1976 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1977 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
1978 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1979 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1980 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
1981
1982 #endif /* No IEEE 1284 support */
1983
1984 /* --- IRQ detection -------------------------------------- */
1985
1986 /* Only if supports ECP mode */
1987 static int __devinit programmable_irq_support(struct parport *pb)
1988 {
1989 int irq, intrLine;
1990 unsigned char oecr = inb (ECONTROL (pb));
1991 static const int lookup[8] = {
1992 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1993 };
1994
1995 outb (ECR_CNF << 5, ECONTROL (pb)); /* Configuration MODE */
1996
1997 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
1998 irq = lookup[intrLine];
1999
2000 outb (oecr, ECONTROL (pb));
2001 return irq;
2002 }
2003
2004 static int __devinit irq_probe_ECP(struct parport *pb)
2005 {
2006 int i;
2007 unsigned long irqs;
2008
2009 sti();
2010 irqs = probe_irq_on();
2011
2012 outb (ECR_SPP << 5, ECONTROL (pb)); /* Reset FIFO */
2013 outb ((ECR_TST << 5) | 0x04, ECONTROL (pb));
2014 outb (ECR_TST << 5, ECONTROL (pb));
2015
2016 /* If Full FIFO sure that writeIntrThreshold is generated */
2017 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
2018 outb (0xaa, FIFO (pb));
2019
2020 pb->irq = probe_irq_off(irqs);
2021 outb (ECR_SPP << 5, ECONTROL (pb));
2022
2023 if (pb->irq <= 0)
2024 pb->irq = PARPORT_IRQ_NONE;
2025
2026 return pb->irq;
2027 }
2028
2029 /*
2030 * This detection seems that only works in National Semiconductors
2031 * This doesn't work in SMC, LGS, and Winbond
2032 */
2033 static int __devinit irq_probe_EPP(struct parport *pb)
2034 {
2035 #ifndef ADVANCED_DETECT
2036 return PARPORT_IRQ_NONE;
2037 #else
2038 int irqs;
2039 unsigned char oecr;
2040
2041 if (pb->modes & PARPORT_MODE_PCECR)
2042 oecr = inb (ECONTROL (pb));
2043
2044 sti();
2045 irqs = probe_irq_on();
2046
2047 if (pb->modes & PARPORT_MODE_PCECR)
2048 frob_econtrol (pb, 0x10, 0x10);
2049
2050 clear_epp_timeout(pb);
2051 parport_pc_frob_control (pb, 0x20, 0x20);
2052 parport_pc_frob_control (pb, 0x10, 0x10);
2053 clear_epp_timeout(pb);
2054
2055 /* Device isn't expecting an EPP read
2056 * and generates an IRQ.
2057 */
2058 parport_pc_read_epp(pb);
2059 udelay(20);
2060
2061 pb->irq = probe_irq_off (irqs);
2062 if (pb->modes & PARPORT_MODE_PCECR)
2063 outb (oecr, ECONTROL (pb));
2064 parport_pc_write_control(pb, 0xc);
2065
2066 if (pb->irq <= 0)
2067 pb->irq = PARPORT_IRQ_NONE;
2068
2069 return pb->irq;
2070 #endif /* Advanced detection */
2071 }
2072
2073 static int __devinit irq_probe_SPP(struct parport *pb)
2074 {
2075 /* Don't even try to do this. */
2076 return PARPORT_IRQ_NONE;
2077 }
2078
2079 /* We will attempt to share interrupt requests since other devices
2080 * such as sound cards and network cards seem to like using the
2081 * printer IRQs.
2082 *
2083 * When ECP is available we can autoprobe for IRQs.
2084 * NOTE: If we can autoprobe it, we can register the IRQ.
2085 */
2086 static int __devinit parport_irq_probe(struct parport *pb)
2087 {
2088 const struct parport_pc_private *priv = pb->private_data;
2089
2090 if (priv->ecr) {
2091 pb->irq = programmable_irq_support(pb);
2092 }
2093
2094 if (pb->modes & PARPORT_MODE_ECP) {
2095 pb->irq = irq_probe_ECP(pb);
2096 }
2097
2098 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2099 (pb->modes & PARPORT_MODE_EPP))
2100 pb->irq = irq_probe_EPP(pb);
2101
2102 clear_epp_timeout(pb);
2103
2104 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2105 pb->irq = irq_probe_EPP(pb);
2106
2107 clear_epp_timeout(pb);
2108
2109 if (pb->irq == PARPORT_IRQ_NONE)
2110 pb->irq = irq_probe_SPP(pb);
2111
2112 if (pb->irq == PARPORT_IRQ_NONE)
2113 pb->irq = get_superio_irq(pb);
2114
2115 return pb->irq;
2116 }
2117
2118 /* --- DMA detection -------------------------------------- */
2119
2120 /* Only if chipset conforms to ECP ISA Interface Standard */
2121 static int __devinit programmable_dma_support (struct parport *p)
2122 {
2123 unsigned char oecr = inb (ECONTROL (p));
2124 int dma;
2125
2126 frob_econtrol (p, 0xe0, ECR_CNF << 5);
2127
2128 dma = inb (CONFIGB(p)) & 0x07;
2129 /* 000: Indicates jumpered 8-bit DMA if read-only.
2130 100: Indicates jumpered 16-bit DMA if read-only. */
2131 if ((dma & 0x03) == 0)
2132 dma = PARPORT_DMA_NONE;
2133
2134 outb (oecr, ECONTROL (p));
2135 return dma;
2136 }
2137
2138 static int __devinit parport_dma_probe (struct parport *p)
2139 {
2140 const struct parport_pc_private *priv = p->private_data;
2141 if (priv->ecr)
2142 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2143 if (p->dma == PARPORT_DMA_NONE) {
2144 /* ask known Super-IO chips proper, although these
2145 claim ECP compatible, some don't report their DMA
2146 conforming to ECP standards */
2147 p->dma = get_superio_dma(p);
2148 }
2149
2150 return p->dma;
2151 }
2152
2153 /* --- Initialisation code -------------------------------- */
2154
2155 struct parport *parport_pc_probe_port (unsigned long int base,
2156 unsigned long int base_hi,
2157 int irq, int dma,
2158 struct pci_dev *dev)
2159 {
2160 struct parport_pc_private *priv;
2161 struct parport_operations *ops;
2162 struct parport tmp;
2163 struct parport *p = &tmp;
2164 int probedirq = PARPORT_IRQ_NONE;
2165 if (check_region(base, 3)) return NULL;
2166 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2167 if (!priv) {
2168 printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
2169 return NULL;
2170 }
2171 ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
2172 if (!ops) {
2173 printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
2174 base);
2175 kfree (priv);
2176 return NULL;
2177 }
2178 memcpy (ops, &parport_pc_ops, sizeof (struct parport_operations));
2179 priv->ctr = 0xc;
2180 priv->ctr_writable = 0xff;
2181 priv->ecr = 0;
2182 priv->fifo_depth = 0;
2183 priv->dma_buf = 0;
2184 priv->dma_handle = 0;
2185 priv->dev = dev;
2186 p->base = base;
2187 p->base_hi = base_hi;
2188 p->irq = irq;
2189 p->dma = dma;
2190 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2191 p->ops = ops;
2192 p->private_data = priv;
2193 p->physport = p;
2194 if (base_hi && !check_region(base_hi,3)) {
2195 parport_ECR_present(p);
2196 parport_ECP_supported(p);
2197 }
2198 if (base != 0x3bc) {
2199 if (!check_region(base+0x3, 5)) {
2200 if (!parport_EPP_supported(p))
2201 parport_ECPEPP_supported(p);
2202 }
2203 }
2204 if (!parport_SPP_supported (p)) {
2205 /* No port. */
2206 kfree (priv);
2207 return NULL;
2208 }
2209 if (priv->ecr)
2210 parport_ECPPS2_supported(p);
2211 else
2212 parport_PS2_supported (p);
2213
2214 if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
2215 PARPORT_DMA_NONE, ops))) {
2216 kfree (priv);
2217 kfree (ops);
2218 return NULL;
2219 }
2220
2221 p->base_hi = base_hi;
2222 p->modes = tmp.modes;
2223 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2224 p->private_data = priv;
2225
2226 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2227 if (p->base_hi && (p->modes & PARPORT_MODE_ECP))
2228 printk(" (0x%lx)", p->base_hi);
2229 p->irq = irq;
2230 p->dma = dma;
2231 if (p->irq == PARPORT_IRQ_AUTO) {
2232 p->irq = PARPORT_IRQ_NONE;
2233 parport_irq_probe(p);
2234 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2235 p->irq = PARPORT_IRQ_NONE;
2236 parport_irq_probe(p);
2237 probedirq = p->irq;
2238 p->irq = PARPORT_IRQ_NONE;
2239 }
2240 if (p->irq != PARPORT_IRQ_NONE) {
2241 printk(", irq %d", p->irq);
2242
2243 if (p->dma == PARPORT_DMA_AUTO) {
2244 p->dma = PARPORT_DMA_NONE;
2245 parport_dma_probe(p);
2246 }
2247 }
2248 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2249 is mandatory (see above) */
2250 p->dma = PARPORT_DMA_NONE;
2251
2252 #ifdef CONFIG_PARPORT_PC_FIFO
2253 if (p->dma != PARPORT_DMA_NOFIFO &&
2254 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2255 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2256 #ifdef CONFIG_PARPORT_1284
2257 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2258 /* currently broken, but working on it.. (FB) */
2259 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2260 #endif /* IEEE 1284 support */
2261 if (p->dma != PARPORT_DMA_NONE) {
2262 printk(", dma %d", p->dma);
2263 p->modes |= PARPORT_MODE_DMA;
2264 }
2265 else printk(", using FIFO");
2266 }
2267 else
2268 /* We can't use the DMA channel after all. */
2269 p->dma = PARPORT_DMA_NONE;
2270 #endif /* Allowed to use FIFO/DMA */
2271
2272 printk(" [");
2273 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2274 {
2275 int f = 0;
2276 printmode(PCSPP);
2277 printmode(TRISTATE);
2278 printmode(COMPAT)
2279 printmode(EPP);
2280 printmode(ECP);
2281 printmode(DMA);
2282 }
2283 #undef printmode
2284 #ifndef CONFIG_PARPORT_1284
2285 printk ("(,...)");
2286 #endif /* CONFIG_PARPORT_1284 */
2287 printk("]\n");
2288 if (probedirq != PARPORT_IRQ_NONE)
2289 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2290 parport_proc_register(p);
2291
2292 request_region (p->base, 3, p->name);
2293 if (p->size > 3)
2294 request_region (p->base + 3, p->size - 3, p->name);
2295 if (p->modes & PARPORT_MODE_ECP)
2296 request_region (p->base_hi, 3, p->name);
2297
2298 if (p->irq != PARPORT_IRQ_NONE) {
2299 if (request_irq (p->irq, parport_pc_interrupt,
2300 0, p->name, p)) {
2301 printk (KERN_WARNING "%s: irq %d in use, "
2302 "resorting to polled operation\n",
2303 p->name, p->irq);
2304 p->irq = PARPORT_IRQ_NONE;
2305 p->dma = PARPORT_DMA_NONE;
2306 }
2307
2308 #ifdef CONFIG_PARPORT_PC_FIFO
2309 if (p->dma != PARPORT_DMA_NONE) {
2310 if (request_dma (p->dma, p->name)) {
2311 printk (KERN_WARNING "%s: dma %d in use, "
2312 "resorting to PIO operation\n",
2313 p->name, p->dma);
2314 p->dma = PARPORT_DMA_NONE;
2315 } else {
2316 priv->dma_buf =
2317 pci_alloc_consistent(priv->dev,
2318 PAGE_SIZE,
2319 &priv->dma_handle);
2320 if (! priv->dma_buf) {
2321 printk (KERN_WARNING "%s: "
2322 "cannot get buffer for DMA, "
2323 "resorting to PIO operation\n",
2324 p->name);
2325 free_dma(p->dma);
2326 p->dma = PARPORT_DMA_NONE;
2327 }
2328 }
2329 }
2330 #endif /* CONFIG_PARPORT_PC_FIFO */
2331 }
2332
2333 /* Done probing. Now put the port into a sensible start-up state. */
2334 if (priv->ecr)
2335 /*
2336 * Put the ECP detected port in PS2 mode.
2337 * Do this also for ports that have ECR but don't do ECP.
2338 */
2339 outb (0x34, ECONTROL (p));
2340
2341 parport_pc_write_data(p, 0);
2342 parport_pc_data_forward (p);
2343
2344 /* Now that we've told the sharing engine about the port, and
2345 found out its characteristics, let the high-level drivers
2346 know about it. */
2347 parport_announce_port (p);
2348
2349 return p;
2350 }
2351
2352 void parport_pc_unregister_port (struct parport *p)
2353 {
2354 struct parport_pc_private *priv = p->private_data;
2355 struct parport_operations *ops = p->ops;
2356 if (p->dma != PARPORT_DMA_NONE)
2357 free_dma(p->dma);
2358 if (p->irq != PARPORT_IRQ_NONE)
2359 free_irq(p->irq, p);
2360 release_region(p->base, 3);
2361 if (p->size > 3)
2362 release_region(p->base + 3, p->size - 3);
2363 if (p->modes & PARPORT_MODE_ECP)
2364 release_region(p->base_hi, 3);
2365 parport_proc_unregister(p);
2366 if (priv->dma_buf)
2367 pci_free_consistent(priv->dev, PAGE_SIZE,
2368 priv->dma_buf,
2369 priv->dma_handle);
2370 kfree (p->private_data);
2371 parport_unregister_port(p);
2372 kfree (ops); /* hope no-one cached it */
2373 }
2374
2375 #ifdef CONFIG_PCI
2376 /* Via support maintained by Jeff Garzik <jgarzik@mandrakesoft.com> */
2377 static int __devinit sio_via_686a_probe (struct pci_dev *pdev, int autoirq,
2378 int autodma)
2379 {
2380 u8 tmp;
2381 int dma, irq;
2382 unsigned port1, port2, have_eppecp;
2383
2384 /*
2385 * unlock super i/o configuration, set 0x85_1
2386 */
2387 pci_read_config_byte (pdev, 0x85, &tmp);
2388 tmp |= (1 << 1);
2389 pci_write_config_byte (pdev, 0x85, tmp);
2390
2391 /*
2392 * Super I/O configuration, index port == 3f0h, data port == 3f1h
2393 */
2394
2395 /* 0xE2_1-0: Parallel Port Mode / Enable */
2396 outb (0xE2, 0x3F0);
2397 tmp = inb (0x3F1);
2398
2399 if ((tmp & 0x03) == 0x03) {
2400 printk (KERN_INFO "parport_pc: Via 686A parallel port disabled in BIOS\n");
2401 return 0;
2402 }
2403
2404 /* 0xE6: Parallel Port I/O Base Address, bits 9-2 */
2405 outb (0xE6, 0x3F0);
2406 port1 = inb (0x3F1) << 2;
2407
2408 switch (port1) {
2409 case 0x3bc: port2 = 0x7bc; break;
2410 case 0x378: port2 = 0x778; break;
2411 case 0x278: port2 = 0x678; break;
2412 default:
2413 printk (KERN_INFO "parport_pc: Weird Via 686A parport base 0x%X, ignoring\n",
2414 port1);
2415 return 0;
2416 }
2417
2418 /* 0xF0_5: EPP+ECP enable */
2419 outb (0xF0, 0x3F0);
2420 have_eppecp = (inb (0x3F1) & (1 << 5));
2421
2422 /*
2423 * lock super i/o configuration, clear 0x85_1
2424 */
2425 pci_read_config_byte (pdev, 0x85, &tmp);
2426 tmp &= ~(1 << 1);
2427 pci_write_config_byte (pdev, 0x85, tmp);
2428
2429 /*
2430 * Get DMA and IRQ from PCI->ISA bridge PCI config registers
2431 */
2432
2433 /* 0x50_3-2: PnP Routing for Parallel Port DRQ */
2434 pci_read_config_byte (pdev, 0x50, &tmp);
2435 dma = ((tmp >> 2) & 0x03);
2436
2437 /* 0x51_7-4: PnP Routing for Parallel Port IRQ */
2438 pci_read_config_byte (pdev, 0x51, &tmp);
2439 irq = ((tmp >> 4) & 0x0F);
2440
2441 /* filter bogus IRQs */
2442 switch (irq) {
2443 case 0:
2444 case 2:
2445 case 8:
2446 case 13:
2447 irq = PARPORT_IRQ_NONE;
2448 break;
2449
2450 default: /* do nothing */
2451 break;
2452 }
2453
2454 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2455 if (!have_eppecp)
2456 dma = PARPORT_DMA_NONE;
2457
2458 /* Let the user (or defaults) steer us away from interrupts and DMA */
2459 if (autoirq != PARPORT_IRQ_AUTO) {
2460 irq = PARPORT_IRQ_NONE;
2461 dma = PARPORT_DMA_NONE;
2462 }
2463 if (autodma != PARPORT_DMA_AUTO)
2464 dma = PARPORT_DMA_NONE;
2465
2466 /* finally, do the probe with values obtained */
2467 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2468 printk (KERN_INFO
2469 "parport_pc: Via 686A parallel port: io=0x%X", port1);
2470 if (irq != PARPORT_IRQ_NONE)
2471 printk (", irq=%d", irq);
2472 if (dma != PARPORT_DMA_NONE)
2473 printk (", dma=%d", dma);
2474 printk ("\n");
2475 return 1;
2476 }
2477
2478 printk (KERN_WARNING "parport_pc: Strange, can't probe Via 686A parallel port: io=0x%X, irq=%d, dma=%d\n",
2479 port1, irq, dma);
2480 return 0;
2481 }
2482
2483
2484 enum parport_pc_sio_types {
2485 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2486 last_sio
2487 };
2488
2489 /* each element directly indexed from enum list, above */
2490 static struct parport_pc_superio {
2491 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma);
2492 } parport_pc_superio_info[] __devinitdata = {
2493 { sio_via_686a_probe, },
2494 };
2495
2496
2497 enum parport_pc_pci_cards {
2498 siig_1s1p_10x_550 = last_sio,
2499 siig_1s1p_10x_650,
2500 siig_1s1p_10x_850,
2501 siig_1p_10x,
2502 siig_2p_10x,
2503 siig_2s1p_10x_550,
2504 siig_2s1p_10x_650,
2505 siig_2s1p_10x_850,
2506 siig_1p_20x,
2507 siig_2p_20x,
2508 siig_2p1s_20x_550,
2509 siig_2p1s_20x_650,
2510 siig_2p1s_20x_850,
2511 siig_1s1p_20x_550,
2512 siig_1s1p_20x_650,
2513 siig_1s1p_20x_850,
2514 siig_2s1p_20x_550,
2515 siig_2s1p_20x_650,
2516 siig_2s1p_20x_850,
2517 lava_parallel,
2518 lava_parallel_dual_a,
2519 lava_parallel_dual_b,
2520 boca_ioppar,
2521 plx_9050,
2522 afavlab_tk9902,
2523 timedia_4078a,
2524 timedia_4079h,
2525 timedia_4085h,
2526 timedia_4088a,
2527 timedia_4089a,
2528 timedia_4095a,
2529 timedia_4096a,
2530 timedia_4078u,
2531 timedia_4079a,
2532 timedia_4085u,
2533 timedia_4079r,
2534 timedia_4079s,
2535 timedia_4079d,
2536 timedia_4079e,
2537 timedia_4079f,
2538 timedia_9079a,
2539 timedia_9079b,
2540 timedia_9079c,
2541 timedia_4006a,
2542 timedia_4014,
2543 timedia_4008a,
2544 timedia_4018,
2545 timedia_9018a,
2546 syba_2p_epp,
2547 syba_1p_ecp,
2548 titan_010l,
2549 titan_1284p2,
2550 };
2551
2552
2553 /* each element directly indexed from enum list, above
2554 * (but offset by last_sio) */
2555 static struct parport_pc_pci {
2556 int numports;
2557 struct { /* BAR (base address registers) numbers in the config
2558 space header */
2559 int lo;
2560 int hi; /* -1 if not there, >6 for offset-method (max
2561 BAR is 6) */
2562 } addr[4];
2563 } cards[] __devinitdata = {
2564 /* siig_1s1p_10x_550 */ { 1, { { 3, 4 }, } },
2565 /* siig_1s1p_10x_650 */ { 1, { { 3, 4 }, } },
2566 /* siig_1s1p_10x_850 */ { 1, { { 3, 4 }, } },
2567 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2568 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2569 /* siig_2s1p_10x_550 */ { 1, { { 4, 5 }, } },
2570 /* siig_2s1p_10x_650 */ { 1, { { 4, 5 }, } },
2571 /* siig_2s1p_10x_850 */ { 1, { { 4, 5 }, } },
2572 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2573 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2574 /* siig_2p1s_20x_550 */ { 2, { { 1, 2 }, { 3, 4 }, } },
2575 /* siig_2p1s_20x_650 */ { 2, { { 1, 2 }, { 3, 4 }, } },
2576 /* siig_2p1s_20x_850 */ { 2, { { 1, 2 }, { 3, 4 }, } },
2577 /* siig_1s1p_20x_550 */ { 1, { { 1, 2 }, } },
2578 /* siig_1s1p_20x_650 */ { 1, { { 1, 2 }, } },
2579 /* siig_1s1p_20x_850 */ { 1, { { 1, 2 }, } },
2580 /* siig_2s1p_20x_550 */ { 1, { { 2, 3 }, } },
2581 /* siig_2s1p_20x_650 */ { 1, { { 2, 3 }, } },
2582 /* siig_2s1p_20x_850 */ { 1, { { 2, 3 }, } },
2583 /* lava_parallel */ { 1, { { 0, -1 }, } },
2584 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2585 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2586 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2587 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2588 /* afavlab_tk9902 */ { 1, { { 0, 1 }, } },
2589 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2590 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2591 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2592 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2593 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2594 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2595 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2596 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2597 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2598 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2599 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2600 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2601 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2602 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2603 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2604 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2605 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2606 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2607 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2608 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2609 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2610 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2611 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2612 /* SYBA uses fixed offsets in
2613 a 1K io window */
2614 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2615 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2616 /* titan_010l */ { 1, { { 3, -1 }, } },
2617 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2618 };
2619
2620 static struct pci_device_id parport_pc_pci_tbl[] __devinitdata = {
2621 /* Super-IO onboard chips */
2622 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2623
2624 /* PCI cards */
2625 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
2626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x_550 },
2627 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
2628 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x_650 },
2629 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
2630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x_850 },
2631 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2633 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2634 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2635 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
2636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x_550 },
2637 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
2638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x_650 },
2639 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
2640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x_850 },
2641 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2643 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2645 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
2646 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x_550 },
2647 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
2648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x_650 },
2649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
2650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x_850 },
2651 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
2652 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_550 },
2653 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
2654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x_650 },
2655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
2656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x_850 },
2657 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
2658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_550 },
2659 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
2660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_650 },
2661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
2662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x_850 },
2663 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2665 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2667 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2669 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2671 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2672 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2673 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_TK9902,
2674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, afavlab_tk9902 },
2675 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2676 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2677 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2678 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2679 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2680 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2681 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2682 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2683 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2684 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2685 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2686 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2687 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2688 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2689 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2690 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2691 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2692 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2693 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2694 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2695 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2696 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2697 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2698 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2699 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2701 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2703 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2705 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2706 { 0, } /* terminate list */
2707 };
2708 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2709
2710 static int __devinit parport_pc_pci_probe (struct pci_dev *dev,
2711 const struct pci_device_id *id)
2712 {
2713 int err, count, n, i = id->driver_data;
2714 if (i < last_sio)
2715 /* This is an onboard Super-IO and has already been probed */
2716 return 0;
2717
2718 /* This is a PCI card */
2719 i -= last_sio;
2720 count = 0;
2721 if ((err = pci_enable_device (dev)) != 0)
2722 return err;
2723
2724 for (n = 0; n < cards[i].numports; n++) {
2725 int lo = cards[i].addr[n].lo;
2726 int hi = cards[i].addr[n].hi;
2727 unsigned long io_lo, io_hi;
2728 io_lo = pci_resource_start (dev, lo);
2729 io_hi = 0;
2730 if ((hi >= 0) && (hi <= 6))
2731 io_hi = pci_resource_start (dev, hi);
2732 else if (hi > 6)
2733 io_lo += hi; /* Reinterpret the meaning of
2734 "hi" as an offset (see SYBA
2735 def.) */
2736 /* TODO: test if sharing interrupts works */
2737 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2738 "I/O at %#lx(%#lx)\n",
2739 parport_pc_pci_tbl[i + last_sio].vendor,
2740 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2741 if (parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2742 PARPORT_DMA_NONE, dev))
2743 count++;
2744 }
2745
2746 return count == 0 ? -ENODEV : 0;
2747 }
2748
2749 static struct pci_driver parport_pc_pci_driver = {
2750 name: "parport_pc",
2751 id_table: parport_pc_pci_tbl,
2752 probe: parport_pc_pci_probe,
2753 };
2754
2755 static int __init parport_pc_init_superio (int autoirq, int autodma)
2756 {
2757 const struct pci_device_id *id;
2758 struct pci_dev *pdev;
2759 int ret = 0;
2760
2761 pci_for_each_dev(pdev) {
2762 id = pci_match_device (parport_pc_pci_tbl, pdev);
2763 if (id == NULL || id->driver_data >= last_sio)
2764 continue;
2765
2766 if (parport_pc_superio_info[id->driver_data].probe
2767 (pdev, autoirq, autodma)) {
2768 ret++;
2769 }
2770 }
2771
2772 return ret; /* number of devices found */
2773 }
2774 #else
2775 static struct pci_driver parport_pc_pci_driver;
2776 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
2777 #endif /* CONFIG_PCI */
2778
2779 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
2780 static int __init __attribute__((unused))
2781 parport_pc_find_isa_ports (int autoirq, int autodma)
2782 {
2783 int count = 0;
2784
2785 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
2786 count++;
2787 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
2788 count++;
2789 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
2790 count++;
2791
2792 return count;
2793 }
2794
2795 /* This function is called by parport_pc_init if the user didn't
2796 * specify any ports to probe. Its job is to find some ports. Order
2797 * is important here -- we want ISA ports to be registered first,
2798 * followed by PCI cards (for least surprise), but before that we want
2799 * to do chipset-specific tests for some onboard ports that we know
2800 * about.
2801 *
2802 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
2803 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
2804 */
2805 static int __init parport_pc_find_ports (int autoirq, int autodma)
2806 {
2807 int count = 0, r;
2808
2809 #ifdef CONFIG_PARPORT_PC_SUPERIO
2810 detect_and_report_winbond ();
2811 detect_and_report_smsc ();
2812 #endif
2813
2814 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
2815 count += parport_pc_init_superio (autoirq, autodma);
2816
2817 /* ISA ports and whatever (see asm/parport.h). */
2818 count += parport_pc_find_nonpci_ports (autoirq, autodma);
2819
2820 r = pci_register_driver (&parport_pc_pci_driver);
2821 if (r >= 0) {
2822 registered_parport = 1;
2823 count += r;
2824 }
2825
2826 return count;
2827 }
2828
2829 int __init parport_pc_init (int *io, int *io_hi, int *irq, int *dma)
2830 {
2831 int count = 0, i = 0;
2832
2833 if (io && *io) {
2834 /* Only probe the ports we were given. */
2835 user_specified = 1;
2836 do {
2837 if ((*io_hi) == PARPORT_IOHI_AUTO)
2838 *io_hi = 0x400 + *io;
2839 if (parport_pc_probe_port(*(io++), *(io_hi++),
2840 *(irq++), *(dma++), NULL))
2841 count++;
2842 } while (*io && (++i < PARPORT_PC_MAX_PORTS));
2843 } else {
2844 count += parport_pc_find_ports (irq[0], dma[0]);
2845 }
2846
2847 return count;
2848 }
2849
2850 /* Exported symbols. */
2851 EXPORT_SYMBOL (parport_pc_probe_port);
2852 EXPORT_SYMBOL (parport_pc_unregister_port);
2853
2854 #ifdef MODULE
2855 static int io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
2856 static int io_hi[PARPORT_PC_MAX_PORTS+1] =
2857 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
2858 static int dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_AUTO };
2859 static int irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
2860 static const char *irq[PARPORT_PC_MAX_PORTS] = { NULL, };
2861 static const char *dma[PARPORT_PC_MAX_PORTS] = { NULL, };
2862
2863 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
2864 MODULE_DESCRIPTION("PC-style parallel port driver");
2865 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
2866 MODULE_PARM(io, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
2867 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
2868 MODULE_PARM(io_hi, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
2869 MODULE_PARM_DESC(irq, "IRQ line");
2870 MODULE_PARM(irq, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
2871 MODULE_PARM_DESC(dma, "DMA channel");
2872 MODULE_PARM(dma, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
2873
2874 int init_module(void)
2875 {
2876 /* Work out how many ports we have, then get parport_share to parse
2877 the irq values. */
2878 unsigned int i;
2879 int ret;
2880 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++);
2881 if (i) {
2882 if (parport_parse_irqs(i, irq, irqval)) return 1;
2883 if (parport_parse_dmas(i, dma, dmaval)) return 1;
2884 }
2885 else {
2886 /* The user can make us use any IRQs or DMAs we find. */
2887 int val;
2888
2889 if (irq[0] && !parport_parse_irqs (1, irq, &val))
2890 switch (val) {
2891 case PARPORT_IRQ_NONE:
2892 case PARPORT_IRQ_AUTO:
2893 irqval[0] = val;
2894 }
2895
2896 if (dma[0] && !parport_parse_dmas (1, dma, &val))
2897 switch (val) {
2898 case PARPORT_DMA_NONE:
2899 case PARPORT_DMA_AUTO:
2900 dmaval[0] = val;
2901 }
2902 }
2903
2904 ret = !parport_pc_init (io, io_hi, irqval, dmaval);
2905 if (ret && registered_parport)
2906 pci_unregister_driver (&parport_pc_pci_driver);
2907
2908 return ret;
2909 }
2910
2911 void cleanup_module(void)
2912 {
2913 /* We ought to keep track of which ports are actually ours. */
2914 struct parport *p = parport_enumerate(), *tmp;
2915
2916 if (!user_specified)
2917 pci_unregister_driver (&parport_pc_pci_driver);
2918
2919 while (p) {
2920 tmp = p->next;
2921 if (p->modes & PARPORT_MODE_PCSPP)
2922 parport_pc_unregister_port (p);
2923
2924 p = tmp;
2925 }
2926 }
2927 #endif
2928