File: /usr/src/linux/drivers/pci/pci.c
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@suse.cz>
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
22 #include <linux/pm.h>
23 #include <linux/kmod.h> /* for hotplug_path */
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26
27 #include <asm/page.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29
30 #undef DEBUG
31
32 #ifdef DEBUG
33 #define DBG(x...) printk(x)
34 #else
35 #define DBG(x...)
36 #endif
37
38 LIST_HEAD(pci_root_buses);
39 LIST_HEAD(pci_devices);
40
41 /**
42 * pci_find_slot - locate PCI device from a given PCI slot
43 * @bus: number of PCI bus on which desired PCI device resides
44 * @devfn: encodes number of PCI slot in which the desired PCI
45 * device resides and the logical device number within that slot
46 * in case of multi-function devices.
47 *
48 * Given a PCI bus and slot/function number, the desired PCI device
49 * is located in system global list of PCI devices. If the device
50 * is found, a pointer to its data structure is returned. If no
51 * device is found, %NULL is returned.
52 */
53 struct pci_dev *
54 pci_find_slot(unsigned int bus, unsigned int devfn)
55 {
56 struct pci_dev *dev;
57
58 pci_for_each_dev(dev) {
59 if (dev->bus->number == bus && dev->devfn == devfn)
60 return dev;
61 }
62 return NULL;
63 }
64
65 /**
66 * pci_find_subsys - begin or continue searching for a PCI device by vendor/subvendor/device/subdevice id
67 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
68 * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
69 * @ss_vendor: PCI subsystem vendor id to match, or %PCI_ANY_ID to match all vendor ids
70 * @ss_device: PCI subsystem device id to match, or %PCI_ANY_ID to match all device ids
71 * @from: Previous PCI device found in search, or %NULL for new search.
72 *
73 * Iterates through the list of known PCI devices. If a PCI device is
74 * found with a matching @vendor, @device, @ss_vendor and @ss_device, a pointer to its
75 * device structure is returned. Otherwise, %NULL is returned.
76 * A new search is initiated by passing %NULL to the @from argument.
77 * Otherwise if @from is not %NULL, searches continue from next device on the global list.
78 */
79 struct pci_dev *
80 pci_find_subsys(unsigned int vendor, unsigned int device,
81 unsigned int ss_vendor, unsigned int ss_device,
82 const struct pci_dev *from)
83 {
84 struct list_head *n = from ? from->global_list.next : pci_devices.next;
85
86 while (n != &pci_devices) {
87 struct pci_dev *dev = pci_dev_g(n);
88 if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
89 (device == PCI_ANY_ID || dev->device == device) &&
90 (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
91 (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
92 return dev;
93 n = n->next;
94 }
95 return NULL;
96 }
97
98
99 /**
100 * pci_find_device - begin or continue searching for a PCI device by vendor/device id
101 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
102 * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
103 * @from: Previous PCI device found in search, or %NULL for new search.
104 *
105 * Iterates through the list of known PCI devices. If a PCI device is
106 * found with a matching @vendor and @device, a pointer to its device structure is
107 * returned. Otherwise, %NULL is returned.
108 * A new search is initiated by passing %NULL to the @from argument.
109 * Otherwise if @from is not %NULL, searches continue from next device on the global list.
110 */
111 struct pci_dev *
112 pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
113 {
114 return pci_find_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
115 }
116
117
118 /**
119 * pci_find_class - begin or continue searching for a PCI device by class
120 * @class: search for a PCI device with this class designation
121 * @from: Previous PCI device found in search, or %NULL for new search.
122 *
123 * Iterates through the list of known PCI devices. If a PCI device is
124 * found with a matching @class, a pointer to its device structure is
125 * returned. Otherwise, %NULL is returned.
126 * A new search is initiated by passing %NULL to the @from argument.
127 * Otherwise if @from is not %NULL, searches continue from next device
128 * on the global list.
129 */
130 struct pci_dev *
131 pci_find_class(unsigned int class, const struct pci_dev *from)
132 {
133 struct list_head *n = from ? from->global_list.next : pci_devices.next;
134
135 while (n != &pci_devices) {
136 struct pci_dev *dev = pci_dev_g(n);
137 if (dev->class == class)
138 return dev;
139 n = n->next;
140 }
141 return NULL;
142 }
143
144 /**
145 * pci_find_capability - query for devices' capabilities
146 * @dev: PCI device to query
147 * @cap: capability code
148 *
149 * Tell if a device supports a given PCI capability.
150 * Returns the address of the requested capability structure within the
151 * device's PCI configuration space or 0 in case the device does not
152 * support it. Possible values for @cap:
153 *
154 * %PCI_CAP_ID_PM Power Management
155 *
156 * %PCI_CAP_ID_AGP Accelerated Graphics Port
157 *
158 * %PCI_CAP_ID_VPD Vital Product Data
159 *
160 * %PCI_CAP_ID_SLOTID Slot Identification
161 *
162 * %PCI_CAP_ID_MSI Message Signalled Interrupts
163 *
164 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
165 */
166 int
167 pci_find_capability(struct pci_dev *dev, int cap)
168 {
169 u16 status;
170 u8 pos, id;
171 int ttl = 48;
172
173 pci_read_config_word(dev, PCI_STATUS, &status);
174 if (!(status & PCI_STATUS_CAP_LIST))
175 return 0;
176 switch (dev->hdr_type) {
177 case PCI_HEADER_TYPE_NORMAL:
178 case PCI_HEADER_TYPE_BRIDGE:
179 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
180 break;
181 case PCI_HEADER_TYPE_CARDBUS:
182 pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos);
183 break;
184 default:
185 return 0;
186 }
187 while (ttl-- && pos >= 0x40) {
188 pos &= ~3;
189 pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
190 if (id == 0xff)
191 break;
192 if (id == cap)
193 return pos;
194 pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
195 }
196 return 0;
197 }
198
199
200 /**
201 * pci_find_parent_resource - return resource region of parent bus of given region
202 * @dev: PCI device structure contains resources to be searched
203 * @res: child resource record for which parent is sought
204 *
205 * For given resource region of given device, return the resource
206 * region of parent bus the given region is contained in or where
207 * it should be allocated from.
208 */
209 struct resource *
210 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
211 {
212 const struct pci_bus *bus = dev->bus;
213 int i;
214 struct resource *best = NULL;
215
216 for(i=0; i<4; i++) {
217 struct resource *r = bus->resource[i];
218 if (!r)
219 continue;
220 if (res->start && !(res->start >= r->start && res->end <= r->end))
221 continue; /* Not contained */
222 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
223 continue; /* Wrong type */
224 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
225 return r; /* Exact match */
226 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
227 best = r; /* Approximating prefetchable by non-prefetchable */
228 }
229 return best;
230 }
231
232 /**
233 * pci_set_power_state - Set the power state of a PCI device
234 * @dev: PCI device to be suspended
235 * @state: Power state we're entering
236 *
237 * Transition a device to a new power state, using the Power Management
238 * Capabilities in the device's config space.
239 *
240 * RETURN VALUE:
241 * -EINVAL if trying to enter a lower state than we're already in.
242 * 0 if we're already in the requested state.
243 * -EIO if device does not support PCI PM.
244 * 0 if we can successfully change the power state.
245 */
246
247 int
248 pci_set_power_state(struct pci_dev *dev, int state)
249 {
250 int pm;
251 u16 pmcsr;
252
253 /* bound the state we're entering */
254 if (state > 3) state = 3;
255
256 /* Validate current state:
257 * Can enter D0 from any state, but if we can only go deeper
258 * to sleep if we're already in a low power state
259 */
260 if (state > 0 && dev->current_state > state)
261 return -EINVAL;
262 else if (dev->current_state == state)
263 return 0; /* we're already there */
264
265 /* find PCI PM capability in list */
266 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
267
268 /* abort if the device doesn't support PM capabilities */
269 if (!pm) return -EIO;
270
271 /* check if this device supports the desired state */
272 if (state == 1 || state == 2) {
273 u16 pmc;
274 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
275 if (state == 1 && !(pmc & PCI_PM_CAP_D1)) return -EIO;
276 else if (state == 2 && !(pmc & PCI_PM_CAP_D2)) return -EIO;
277 }
278
279 /* If we're in D3, force entire word to 0.
280 * This doesn't affect PME_Status, disables PME_En, and
281 * sets PowerState to 0.
282 */
283 if (dev->current_state >= 3)
284 pmcsr = 0;
285 else {
286 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
287 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
288 pmcsr |= state;
289 }
290
291 /* enter specified state */
292 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
293
294 /* Mandatory power management transition delays */
295 /* see PCI PM 1.1 5.6.1 table 18 */
296 if(state == 3 || dev->current_state == 3)
297 {
298 set_current_state(TASK_UNINTERRUPTIBLE);
299 schedule_timeout(HZ/100);
300 }
301 else if(state == 2 || dev->current_state == 2)
302 udelay(200);
303 dev->current_state = state;
304
305 return 0;
306 }
307
308 /**
309 * pci_save_state - save the PCI configuration space of a device before suspending
310 * @dev: - PCI device that we're dealing with
311 * @buffer: - buffer to hold config space context
312 *
313 * @buffer must be large enough to hold the entire PCI 2.2 config space
314 * (>= 64 bytes).
315 */
316 int
317 pci_save_state(struct pci_dev *dev, u32 *buffer)
318 {
319 int i;
320 if (buffer) {
321 /* XXX: 100% dword access ok here? */
322 for (i = 0; i < 16; i++)
323 pci_read_config_dword(dev, i * 4,&buffer[i]);
324 }
325 return 0;
326 }
327
328 /**
329 * pci_restore_state - Restore the saved state of a PCI device
330 * @dev: - PCI device that we're dealing with
331 * @buffer: - saved PCI config space
332 *
333 */
334 int
335 pci_restore_state(struct pci_dev *dev, u32 *buffer)
336 {
337 int i;
338
339 if (buffer) {
340 for (i = 0; i < 16; i++)
341 pci_write_config_dword(dev,i * 4, buffer[i]);
342 }
343 /*
344 * otherwise, write the context information we know from bootup.
345 * This works around a problem where warm-booting from Windows
346 * combined with a D3(hot)->D0 transition causes PCI config
347 * header data to be forgotten.
348 */
349 else {
350 for (i = 0; i < 6; i ++)
351 pci_write_config_dword(dev,
352 PCI_BASE_ADDRESS_0 + (i * 4),
353 dev->resource[i].start);
354 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
355 }
356 return 0;
357 }
358
359 /**
360 * pci_enable_device - Initialize device before it's used by a driver.
361 * @dev: PCI device to be initialized
362 *
363 * Initialize device before it's used by a driver. Ask low-level code
364 * to enable I/O and memory. Wake up the device if it was suspended.
365 * Beware, this function can fail.
366 */
367 int
368 pci_enable_device(struct pci_dev *dev)
369 {
370 int err;
371
372 pci_set_power_state(dev, 0);
373 if ((err = pcibios_enable_device(dev)) < 0)
374 return err;
375 return 0;
376 }
377
378 /**
379 * pci_disable_device - Disable PCI device after use
380 * @dev: PCI device to be disabled
381 *
382 * Signal to the system that the PCI device is not in use by the system
383 * anymore. This only involves disabling PCI bus-mastering, if active.
384 */
385 void
386 pci_disable_device(struct pci_dev *dev)
387 {
388 u16 pci_command;
389
390 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
391 if (pci_command & PCI_COMMAND_MASTER) {
392 pci_command &= ~PCI_COMMAND_MASTER;
393 pci_write_config_word(dev, PCI_COMMAND, pci_command);
394 }
395 }
396
397 /**
398 * pci_enable_wake - enable device to generate PME# when suspended
399 * @dev: - PCI device to operate on
400 * @state: - Current state of device.
401 * @enable: - Flag to enable or disable generation
402 *
403 * Set the bits in the device's PM Capabilities to generate PME# when
404 * the system is suspended.
405 *
406 * -EIO is returned if device doesn't have PM Capabilities.
407 * -EINVAL is returned if device supports it, but can't generate wake events.
408 * 0 if operation is successful.
409 *
410 */
411 int pci_enable_wake(struct pci_dev *dev, u32 state, int enable)
412 {
413 int pm;
414 u16 value;
415
416 /* find PCI PM capability in list */
417 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
418
419 /* If device doesn't support PM Capabilities, but request is to disable
420 * wake events, it's a nop; otherwise fail */
421 if (!pm)
422 return enable ? -EIO : 0;
423
424 /* Check device's ability to generate PME# */
425 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
426
427 value &= PCI_PM_CAP_PME_MASK;
428 value >>= ffs(value); /* First bit of mask */
429
430 /* Check if it can generate PME# from requested state. */
431 if (!value || !(value & (1 << state)))
432 return enable ? -EINVAL : 0;
433
434 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
435
436 /* Clear PME_Status by writing 1 to it and enable PME# */
437 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
438
439 if (!enable)
440 value &= ~PCI_PM_CTRL_PME_ENABLE;
441
442 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
443
444 return 0;
445 }
446
447 int
448 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
449 {
450 u8 pin;
451
452 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
453 if (!pin)
454 return -1;
455 pin--;
456 while (dev->bus->self) {
457 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
458 dev = dev->bus->self;
459 }
460 *bridge = dev;
461 return pin;
462 }
463
464 /**
465 * pci_release_regions - Release reserved PCI I/O and memory resources
466 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
467 *
468 * Releases all PCI I/O and memory resources previously reserved by a
469 * successful call to pci_request_regions. Call this function only
470 * after all use of the PCI regions has ceased.
471 */
472 void pci_release_regions(struct pci_dev *pdev)
473 {
474 int i;
475
476 for (i = 0; i < 6; i++) {
477 if (pci_resource_len(pdev, i) == 0)
478 continue;
479
480 if (pci_resource_flags(pdev, i) & IORESOURCE_IO)
481 release_region(pci_resource_start(pdev, i),
482 pci_resource_len(pdev, i));
483
484 else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM)
485 release_mem_region(pci_resource_start(pdev, i),
486 pci_resource_len(pdev, i));
487 }
488 }
489
490 /**
491 * pci_request_regions - Reserved PCI I/O and memory resources
492 * @pdev: PCI device whose resources are to be reserved
493 * @res_name: Name to be associated with resource.
494 *
495 * Mark all PCI regions associated with PCI device @pdev as
496 * being reserved by owner @res_name. Do not access any
497 * address inside the PCI regions unless this call returns
498 * successfully.
499 *
500 * Returns 0 on success, or %EBUSY on error. A warning
501 * message is also printed on failure.
502 */
503 int pci_request_regions(struct pci_dev *pdev, char *res_name)
504 {
505 int i;
506
507 for (i = 0; i < 6; i++) {
508 if (pci_resource_len(pdev, i) == 0)
509 continue;
510
511 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
512 if (!request_region(pci_resource_start(pdev, i),
513 pci_resource_len(pdev, i), res_name))
514 goto err_out;
515 }
516
517 else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
518 if (!request_mem_region(pci_resource_start(pdev, i),
519 pci_resource_len(pdev, i), res_name))
520 goto err_out;
521 }
522 }
523
524 return 0;
525
526 err_out:
527 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
528 pci_resource_flags(pdev, i) & IORESOURCE_IO ? "I/O" : "mem",
529 i + 1, /* PCI BAR # */
530 pci_resource_len(pdev, i), pci_resource_start(pdev, i),
531 pdev->slot_name);
532 pci_release_regions(pdev);
533 return -EBUSY;
534 }
535
536
537 /*
538 * Registration of PCI drivers and handling of hot-pluggable devices.
539 */
540
541 static LIST_HEAD(pci_drivers);
542
543 /**
544 * pci_match_device - Tell if a PCI device structure has a matching PCI device id structure
545 * @ids: array of PCI device id structures to search in
546 * @dev: the PCI device structure to match against
547 *
548 * Used by a driver to check whether a PCI device present in the
549 * system is in its list of supported devices.Returns the matching
550 * pci_device_id structure or %NULL if there is no match.
551 */
552 const struct pci_device_id *
553 pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev)
554 {
555 while (ids->vendor || ids->subvendor || ids->class_mask) {
556 if ((ids->vendor == PCI_ANY_ID || ids->vendor == dev->vendor) &&
557 (ids->device == PCI_ANY_ID || ids->device == dev->device) &&
558 (ids->subvendor == PCI_ANY_ID || ids->subvendor == dev->subsystem_vendor) &&
559 (ids->subdevice == PCI_ANY_ID || ids->subdevice == dev->subsystem_device) &&
560 !((ids->class ^ dev->class) & ids->class_mask))
561 return ids;
562 ids++;
563 }
564 return NULL;
565 }
566
567 static int
568 pci_announce_device(struct pci_driver *drv, struct pci_dev *dev)
569 {
570 const struct pci_device_id *id;
571 int ret = 0;
572
573 if (drv->id_table) {
574 id = pci_match_device(drv->id_table, dev);
575 if (!id) {
576 ret = 0;
577 goto out;
578 }
579 } else
580 id = NULL;
581
582 dev_probe_lock();
583 if (drv->probe(dev, id) >= 0) {
584 dev->driver = drv;
585 ret = 1;
586 }
587 dev_probe_unlock();
588 out:
589 return ret;
590 }
591
592 /**
593 * pci_register_driver - register a new pci driver
594 * @drv: the driver structure to register
595 *
596 * Adds the driver structure to the list of registered drivers
597 * Returns the number of pci devices which were claimed by the driver
598 * during registration. The driver remains registered even if the
599 * return value is zero.
600 */
601 int
602 pci_register_driver(struct pci_driver *drv)
603 {
604 struct pci_dev *dev;
605 int count = 0;
606
607 list_add_tail(&drv->node, &pci_drivers);
608 pci_for_each_dev(dev) {
609 if (!pci_dev_driver(dev))
610 count += pci_announce_device(drv, dev);
611 }
612 return count;
613 }
614
615 /**
616 * pci_unregister_driver - unregister a pci driver
617 * @drv: the driver structure to unregister
618 *
619 * Deletes the driver structure from the list of registered PCI drivers,
620 * gives it a chance to clean up by calling its remove() function for
621 * each device it was responsible for, and marks those devices as
622 * driverless.
623 */
624
625 void
626 pci_unregister_driver(struct pci_driver *drv)
627 {
628 struct pci_dev *dev;
629
630 list_del(&drv->node);
631 pci_for_each_dev(dev) {
632 if (dev->driver == drv) {
633 if (drv->remove)
634 drv->remove(dev);
635 dev->driver = NULL;
636 }
637 }
638 }
639
640 #ifdef CONFIG_HOTPLUG
641
642 #ifndef FALSE
643 #define FALSE (0)
644 #define TRUE (!FALSE)
645 #endif
646
647 static void
648 run_sbin_hotplug(struct pci_dev *pdev, int insert)
649 {
650 int i;
651 char *argv[3], *envp[8];
652 char id[20], sub_id[24], bus_id[24], class_id[20];
653
654 if (!hotplug_path[0])
655 return;
656
657 sprintf(class_id, "PCI_CLASS=%04X", pdev->class);
658 sprintf(id, "PCI_ID=%04X:%04X", pdev->vendor, pdev->device);
659 sprintf(sub_id, "PCI_SUBSYS_ID=%04X:%04X", pdev->subsystem_vendor, pdev->subsystem_device);
660 sprintf(bus_id, "PCI_SLOT_NAME=%s", pdev->slot_name);
661
662 i = 0;
663 argv[i++] = hotplug_path;
664 argv[i++] = "pci";
665 argv[i] = 0;
666
667 i = 0;
668 /* minimal command environment */
669 envp[i++] = "HOME=/";
670 envp[i++] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin";
671
672 /* other stuff we want to pass to /sbin/hotplug */
673 envp[i++] = class_id;
674 envp[i++] = id;
675 envp[i++] = sub_id;
676 envp[i++] = bus_id;
677 if (insert)
678 envp[i++] = "ACTION=add";
679 else
680 envp[i++] = "ACTION=remove";
681 envp[i] = 0;
682
683 call_usermodehelper (argv [0], argv, envp);
684 }
685
686 /**
687 * pci_insert_device - insert a hotplug device
688 * @dev: the device to insert
689 * @bus: where to insert it
690 *
691 * Add a new device to the device lists and notify userspace (/sbin/hotplug).
692 */
693 void
694 pci_insert_device(struct pci_dev *dev, struct pci_bus *bus)
695 {
696 struct list_head *ln;
697
698 list_add_tail(&dev->bus_list, &bus->devices);
699 list_add_tail(&dev->global_list, &pci_devices);
700 #ifdef CONFIG_PROC_FS
701 pci_proc_attach_device(dev);
702 #endif
703 for(ln=pci_drivers.next; ln != &pci_drivers; ln=ln->next) {
704 struct pci_driver *drv = list_entry(ln, struct pci_driver, node);
705 if (drv->remove && pci_announce_device(drv, dev))
706 break;
707 }
708
709 /* notify userspace of new hotplug device */
710 run_sbin_hotplug(dev, TRUE);
711 }
712
713 static void
714 pci_free_resources(struct pci_dev *dev)
715 {
716 int i;
717
718 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
719 struct resource *res = dev->resource + i;
720 if (res->parent)
721 release_resource(res);
722 }
723 }
724
725 /**
726 * pci_remove_device - remove a hotplug device
727 * @dev: the device to remove
728 *
729 * Delete the device structure from the device lists and
730 * notify userspace (/sbin/hotplug).
731 */
732 void
733 pci_remove_device(struct pci_dev *dev)
734 {
735 if (dev->driver) {
736 if (dev->driver->remove)
737 dev->driver->remove(dev);
738 dev->driver = NULL;
739 }
740 list_del(&dev->bus_list);
741 list_del(&dev->global_list);
742 pci_free_resources(dev);
743 #ifdef CONFIG_PROC_FS
744 pci_proc_detach_device(dev);
745 #endif
746
747 /* notify userspace of hotplug device removal */
748 run_sbin_hotplug(dev, FALSE);
749 }
750
751 #endif
752
753 static struct pci_driver pci_compat_driver = {
754 name: "compat"
755 };
756
757 /**
758 * pci_dev_driver - get the pci_driver of a device
759 * @dev: the device to query
760 *
761 * Returns the appropriate pci_driver structure or %NULL if there is no
762 * registered driver for the device.
763 */
764 struct pci_driver *
765 pci_dev_driver(const struct pci_dev *dev)
766 {
767 if (dev->driver)
768 return dev->driver;
769 else {
770 int i;
771 for(i=0; i<=PCI_ROM_RESOURCE; i++)
772 if (dev->resource[i].flags & IORESOURCE_BUSY)
773 return &pci_compat_driver;
774 }
775 return NULL;
776 }
777
778
779 /*
780 * This interrupt-safe spinlock protects all accesses to PCI
781 * configuration space.
782 */
783
784 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
785
786 /*
787 * Wrappers for all PCI configuration access functions. They just check
788 * alignment, do locking and call the low-level functions pointed to
789 * by pci_dev->ops.
790 */
791
792 #define PCI_byte_BAD 0
793 #define PCI_word_BAD (pos & 1)
794 #define PCI_dword_BAD (pos & 3)
795
796 #define PCI_OP(rw,size,type) \
797 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
798 { \
799 int res; \
800 unsigned long flags; \
801 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
802 spin_lock_irqsave(&pci_lock, flags); \
803 res = dev->bus->ops->rw##_##size(dev, pos, value); \
804 spin_unlock_irqrestore(&pci_lock, flags); \
805 return res; \
806 }
807
808 PCI_OP(read, byte, u8 *)
809 PCI_OP(read, word, u16 *)
810 PCI_OP(read, dword, u32 *)
811 PCI_OP(write, byte, u8)
812 PCI_OP(write, word, u16)
813 PCI_OP(write, dword, u32)
814
815 /**
816 * pci_set_master - enables bus-mastering for device dev
817 * @dev: the PCI device to enable
818 *
819 * Enables bus-mastering on the device and calls pcibios_set_master()
820 * to do the needed arch specific settings.
821 */
822 void
823 pci_set_master(struct pci_dev *dev)
824 {
825 u16 cmd;
826
827 pci_read_config_word(dev, PCI_COMMAND, &cmd);
828 if (! (cmd & PCI_COMMAND_MASTER)) {
829 DBG("PCI: Enabling bus mastering for device %s\n", dev->slot_name);
830 cmd |= PCI_COMMAND_MASTER;
831 pci_write_config_word(dev, PCI_COMMAND, cmd);
832 }
833 pcibios_set_master(dev);
834 }
835
836 int
837 pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask)
838 {
839 if(! pci_dma_supported(dev, mask))
840 return -EIO;
841
842 dev->dma_mask = mask;
843
844 return 0;
845 }
846
847
848 /*
849 * Translate the low bits of the PCI base
850 * to the resource type
851 */
852 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
853 {
854 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
855 return IORESOURCE_IO;
856
857 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
858 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
859
860 return IORESOURCE_MEM;
861 }
862
863 /*
864 * Find the extent of a PCI decode..
865 */
866 static u32 pci_size(u32 base, unsigned long mask)
867 {
868 u32 size = mask & base; /* Find the significant bits */
869 size = size & ~(size-1); /* Get the lowest of them to find the decode size */
870 return size-1; /* extent = size - 1 */
871 }
872
873 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
874 {
875 unsigned int pos, reg, next;
876 u32 l, sz;
877 struct resource *res;
878
879 for(pos=0; pos<howmany; pos = next) {
880 next = pos+1;
881 res = &dev->resource[pos];
882 res->name = dev->name;
883 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
884 pci_read_config_dword(dev, reg, &l);
885 pci_write_config_dword(dev, reg, ~0);
886 pci_read_config_dword(dev, reg, &sz);
887 pci_write_config_dword(dev, reg, l);
888 if (!sz || sz == 0xffffffff)
889 continue;
890 if (l == 0xffffffff)
891 l = 0;
892 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
893 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
894 sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
895 } else {
896 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
897 sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
898 }
899 res->end = res->start + (unsigned long) sz;
900 res->flags |= (l & 0xf) | pci_calc_resource_flags(l);
901 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
902 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
903 pci_read_config_dword(dev, reg+4, &l);
904 next++;
905 #if BITS_PER_LONG == 64
906 res->start |= ((unsigned long) l) << 32;
907 res->end = res->start + sz;
908 pci_write_config_dword(dev, reg+4, ~0);
909 pci_read_config_dword(dev, reg+4, &sz);
910 pci_write_config_dword(dev, reg+4, l);
911 if (~sz)
912 res->end = res->start + 0xffffffff +
913 (((unsigned long) ~sz) << 32);
914 #else
915 if (l) {
916 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", dev->slot_name);
917 res->start = 0;
918 res->flags = 0;
919 continue;
920 }
921 #endif
922 }
923 }
924 if (rom) {
925 dev->rom_base_reg = rom;
926 res = &dev->resource[PCI_ROM_RESOURCE];
927 pci_read_config_dword(dev, rom, &l);
928 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
929 pci_read_config_dword(dev, rom, &sz);
930 pci_write_config_dword(dev, rom, l);
931 if (l == 0xffffffff)
932 l = 0;
933 if (sz && sz != 0xffffffff) {
934 res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
935 IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
936 res->start = l & PCI_ROM_ADDRESS_MASK;
937 sz = pci_size(sz, PCI_ROM_ADDRESS_MASK);
938 res->end = res->start + (unsigned long) sz;
939 }
940 res->name = dev->name;
941 }
942 }
943
944 void __init pci_read_bridge_bases(struct pci_bus *child)
945 {
946 struct pci_dev *dev = child->self;
947 u8 io_base_lo, io_limit_lo;
948 u16 mem_base_lo, mem_limit_lo;
949 unsigned long base, limit;
950 struct resource *res;
951 int i;
952
953 if (!dev) /* It's a host bus, nothing to read */
954 return;
955
956 for(i=0; i<3; i++)
957 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
958
959 res = child->resource[0];
960 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
961 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
962 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
963 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
964
965 if ((base & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
966 u16 io_base_hi, io_limit_hi;
967 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
968 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
969 base |= (io_base_hi << 16);
970 limit |= (io_limit_hi << 16);
971 }
972
973 if (base && base <= limit) {
974 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
975 res->start = base;
976 res->end = limit + 0xfff;
977 res->name = child->name;
978 } else {
979 /*
980 * Ugh. We don't know enough about this bridge. Just assume
981 * that it's entirely transparent.
982 */
983 printk(KERN_ERR "Unknown bridge resource %d: assuming transparent\n", 0);
984 child->resource[0] = child->parent->resource[0];
985 }
986
987 res = child->resource[1];
988 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
989 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
990 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
991 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
992 if (base && base <= limit) {
993 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
994 res->start = base;
995 res->end = limit + 0xfffff;
996 res->name = child->name;
997 } else {
998 /* See comment above. Same thing */
999 printk(KERN_ERR "Unknown bridge resource %d: assuming transparent\n", 1);
1000 child->resource[1] = child->parent->resource[1];
1001 }
1002
1003 res = child->resource[2];
1004 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
1005 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
1006 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
1007 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
1008
1009 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
1010 u32 mem_base_hi, mem_limit_hi;
1011 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
1012 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
1013 #if BITS_PER_LONG == 64
1014 base |= ((long) mem_base_hi) << 32;
1015 limit |= ((long) mem_limit_hi) << 32;
1016 #else
1017 if (mem_base_hi || mem_limit_hi) {
1018 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
1019 return;
1020 }
1021 #endif
1022 }
1023 if (base && base <= limit) {
1024 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
1025 res->start = base;
1026 res->end = limit + 0xfffff;
1027 res->name = child->name;
1028 } else {
1029 /* See comments above */
1030 printk(KERN_ERR "Unknown bridge resource %d: assuming transparent\n", 2);
1031 child->resource[2] = child->parent->resource[2];
1032 }
1033 }
1034
1035 static struct pci_bus * __init pci_alloc_bus(void)
1036 {
1037 struct pci_bus *b;
1038
1039 b = kmalloc(sizeof(*b), GFP_KERNEL);
1040 if (b) {
1041 memset(b, 0, sizeof(*b));
1042 INIT_LIST_HEAD(&b->children);
1043 INIT_LIST_HEAD(&b->devices);
1044 }
1045 return b;
1046 }
1047
1048 static struct pci_bus * __init pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
1049 {
1050 struct pci_bus *child;
1051 int i;
1052
1053 /*
1054 * Allocate a new bus, and inherit stuff from the parent..
1055 */
1056 child = pci_alloc_bus();
1057
1058 list_add_tail(&child->node, &parent->children);
1059 child->self = dev;
1060 dev->subordinate = child;
1061 child->parent = parent;
1062 child->ops = parent->ops;
1063 child->sysdata = parent->sysdata;
1064
1065 /*
1066 * Set up the primary, secondary and subordinate
1067 * bus numbers.
1068 */
1069 child->number = child->secondary = busnr;
1070 child->primary = parent->secondary;
1071 child->subordinate = 0xff;
1072
1073 /* Set up default resource pointers.. */
1074 for (i = 0; i < 4; i++)
1075 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
1076
1077 return child;
1078 }
1079
1080 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus);
1081
1082 /*
1083 * If it's a bridge, configure it and scan the bus behind it.
1084 * For CardBus bridges, we don't scan behind as the devices will
1085 * be handled by the bridge driver itself.
1086 *
1087 * We need to process bridges in two passes -- first we scan those
1088 * already configured by the BIOS and after we are done with all of
1089 * them, we proceed to assigning numbers to the remaining buses in
1090 * order to avoid overlaps between old and new bus numbers.
1091 */
1092 static int __init pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
1093 {
1094 unsigned int buses;
1095 unsigned short cr;
1096 struct pci_bus *child;
1097 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1098
1099 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1100 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", dev->slot_name, buses & 0xffffff, pass);
1101 if ((buses & 0xffff00) && !pcibios_assign_all_busses()) {
1102 /*
1103 * Bus already configured by firmware, process it in the first
1104 * pass and just note the configuration.
1105 */
1106 if (pass)
1107 return max;
1108 child = pci_add_new_bus(bus, dev, 0);
1109 child->primary = buses & 0xFF;
1110 child->secondary = (buses >> 8) & 0xFF;
1111 child->subordinate = (buses >> 16) & 0xFF;
1112 child->number = child->secondary;
1113 if (!is_cardbus) {
1114 unsigned int cmax = pci_do_scan_bus(child);
1115 if (cmax > max) max = cmax;
1116 } else {
1117 unsigned int cmax = child->subordinate;
1118 if (cmax > max) max = cmax;
1119 }
1120 } else {
1121 /*
1122 * We need to assign a number to this bus which we always
1123 * do in the second pass. We also keep all address decoders
1124 * on the bridge disabled during scanning. FIXME: Why?
1125 */
1126 if (!pass)
1127 return max;
1128 pci_read_config_word(dev, PCI_COMMAND, &cr);
1129 pci_write_config_word(dev, PCI_COMMAND, 0x0000);
1130 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1131
1132 child = pci_add_new_bus(bus, dev, ++max);
1133 buses = (buses & 0xff000000)
1134 | ((unsigned int)(child->primary) << 0)
1135 | ((unsigned int)(child->secondary) << 8)
1136 | ((unsigned int)(child->subordinate) << 16);
1137 /*
1138 * We need to blast all three values with a single write.
1139 */
1140 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1141 if (!is_cardbus) {
1142 /* Now we can scan all subordinate buses... */
1143 max = pci_do_scan_bus(child);
1144 } else {
1145 /*
1146 * For CardBus bridges, we leave 4 bus numbers
1147 * as cards with a PCI-to-PCI bridge can be
1148 * inserted later.
1149 */
1150 max += 3;
1151 }
1152 /*
1153 * Set the subordinate bus number to its real value.
1154 */
1155 child->subordinate = max;
1156 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1157 pci_write_config_word(dev, PCI_COMMAND, cr);
1158 }
1159 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
1160 return max;
1161 }
1162
1163 /*
1164 * Read interrupt line and base address registers.
1165 * The architecture-dependent code can tweak these, of course.
1166 */
1167 static void pci_read_irq(struct pci_dev *dev)
1168 {
1169 unsigned char irq;
1170
1171 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1172 if (irq)
1173 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1174 dev->irq = irq;
1175 }
1176
1177 /**
1178 * pci_setup_device - fill in class and map information of a device
1179 * @dev: the device structure to fill
1180 *
1181 * Initialize the device structure with information about the device's
1182 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1183 * Called at initialisation of the PCI subsystem and by CardBus services.
1184 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
1185 * or CardBus).
1186 */
1187 int pci_setup_device(struct pci_dev * dev)
1188 {
1189 u32 class;
1190
1191 sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
1192 sprintf(dev->name, "PCI device %04x:%04x", dev->vendor, dev->device);
1193
1194 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1195 class >>= 8; /* upper 3 bytes */
1196 dev->class = class;
1197 class >>= 8;
1198
1199 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
1200
1201 /* "Unknown power state" */
1202 dev->current_state = 4;
1203
1204 switch (dev->hdr_type) { /* header type */
1205 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1206 if (class == PCI_CLASS_BRIDGE_PCI)
1207 goto bad;
1208 pci_read_irq(dev);
1209 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1210 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1211 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1212 break;
1213
1214 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1215 if (class != PCI_CLASS_BRIDGE_PCI)
1216 goto bad;
1217 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1218 break;
1219
1220 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1221 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1222 goto bad;
1223 pci_read_irq(dev);
1224 pci_read_bases(dev, 1, 0);
1225 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1226 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1227 break;
1228
1229 default: /* unknown header */
1230 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
1231 dev->slot_name, dev->hdr_type);
1232 return -1;
1233
1234 bad:
1235 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
1236 dev->slot_name, class, dev->hdr_type);
1237 dev->class = PCI_CLASS_NOT_DEFINED;
1238 }
1239
1240 /* We found a fine healthy device, go go go... */
1241 return 0;
1242 }
1243
1244 /*
1245 * Read the config data for a PCI device, sanity-check it
1246 * and fill in the dev structure...
1247 */
1248 static struct pci_dev * __init pci_scan_device(struct pci_dev *temp)
1249 {
1250 struct pci_dev *dev;
1251 u32 l;
1252
1253 if (pci_read_config_dword(temp, PCI_VENDOR_ID, &l))
1254 return NULL;
1255
1256 /* some broken boards return 0 or ~0 if a slot is empty: */
1257 if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
1258 return NULL;
1259
1260 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1261 if (!dev)
1262 return NULL;
1263
1264 memcpy(dev, temp, sizeof(*dev));
1265 dev->vendor = l & 0xffff;
1266 dev->device = (l >> 16) & 0xffff;
1267
1268 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1269 set this higher, assuming the system even supports it. */
1270 dev->dma_mask = 0xffffffff;
1271 if (pci_setup_device(dev) < 0) {
1272 kfree(dev);
1273 dev = NULL;
1274 }
1275 return dev;
1276 }
1277
1278 struct pci_dev * __init pci_scan_slot(struct pci_dev *temp)
1279 {
1280 struct pci_bus *bus = temp->bus;
1281 struct pci_dev *dev;
1282 struct pci_dev *first_dev = NULL;
1283 int func = 0;
1284 int is_multi = 0;
1285 u8 hdr_type;
1286
1287 for (func = 0; func < 8; func++, temp->devfn++) {
1288 if (func && !is_multi) /* not a multi-function device */
1289 continue;
1290 if (pci_read_config_byte(temp, PCI_HEADER_TYPE, &hdr_type))
1291 continue;
1292 temp->hdr_type = hdr_type & 0x7f;
1293
1294 dev = pci_scan_device(temp);
1295 if (!dev)
1296 continue;
1297 pci_name_device(dev);
1298 if (!func) {
1299 is_multi = hdr_type & 0x80;
1300 first_dev = dev;
1301 }
1302
1303 /*
1304 * Link the device to both the global PCI device chain and
1305 * the per-bus list of devices.
1306 */
1307 list_add_tail(&dev->global_list, &pci_devices);
1308 list_add_tail(&dev->bus_list, &bus->devices);
1309
1310 /* Fix up broken headers */
1311 pci_fixup_device(PCI_FIXUP_HEADER, dev);
1312 }
1313 return first_dev;
1314 }
1315
1316 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus)
1317 {
1318 unsigned int devfn, max, pass;
1319 struct list_head *ln;
1320 struct pci_dev *dev, dev0;
1321
1322 DBG("Scanning bus %02x\n", bus->number);
1323 max = bus->secondary;
1324
1325 /* Create a device template */
1326 memset(&dev0, 0, sizeof(dev0));
1327 dev0.bus = bus;
1328 dev0.sysdata = bus->sysdata;
1329
1330 /* Go find them, Rover! */
1331 for (devfn = 0; devfn < 0x100; devfn += 8) {
1332 dev0.devfn = devfn;
1333 pci_scan_slot(&dev0);
1334 }
1335
1336 /*
1337 * After performing arch-dependent fixup of the bus, look behind
1338 * all PCI-to-PCI bridges on this bus.
1339 */
1340 DBG("Fixups for bus %02x\n", bus->number);
1341 pcibios_fixup_bus(bus);
1342 for (pass=0; pass < 2; pass++)
1343 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
1344 dev = pci_dev_b(ln);
1345 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1346 max = pci_scan_bridge(bus, dev, max, pass);
1347 }
1348
1349 /*
1350 * We've scanned the bus and so we know all about what's on
1351 * the other side of any bridges that may be on this bus plus
1352 * any devices.
1353 *
1354 * Return how far we've got finding sub-buses.
1355 */
1356 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
1357 return max;
1358 }
1359
1360 int __init pci_bus_exists(const struct list_head *list, int nr)
1361 {
1362 const struct list_head *l;
1363
1364 for(l=list->next; l != list; l = l->next) {
1365 const struct pci_bus *b = pci_bus_b(l);
1366 if (b->number == nr || pci_bus_exists(&b->children, nr))
1367 return 1;
1368 }
1369 return 0;
1370 }
1371
1372 struct pci_bus * __init pci_alloc_primary_bus(int bus)
1373 {
1374 struct pci_bus *b;
1375
1376 if (pci_bus_exists(&pci_root_buses, bus)) {
1377 /* If we already got to this bus through a different bridge, ignore it */
1378 DBG("PCI: Bus %02x already known\n", bus);
1379 return NULL;
1380 }
1381
1382 b = pci_alloc_bus();
1383 list_add_tail(&b->node, &pci_root_buses);
1384
1385 b->number = b->secondary = bus;
1386 b->resource[0] = &ioport_resource;
1387 b->resource[1] = &iomem_resource;
1388 return b;
1389 }
1390
1391 struct pci_bus * __init pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
1392 {
1393 struct pci_bus *b = pci_alloc_primary_bus(bus);
1394 if (b) {
1395 b->sysdata = sysdata;
1396 b->ops = ops;
1397 b->subordinate = pci_do_scan_bus(b);
1398 }
1399 return b;
1400 }
1401
1402 #ifdef CONFIG_PM
1403
1404 /*
1405 * PCI Power management..
1406 *
1407 * This needs to be done centralized, so that we power manage PCI
1408 * devices in the right order: we should not shut down PCI bridges
1409 * before we've shut down the devices behind them, and we should
1410 * not wake up devices before we've woken up the bridge to the
1411 * device.. Eh?
1412 *
1413 * We do not touch devices that don't have a driver that exports
1414 * a suspend/resume function. That is just too dangerous. If the default
1415 * PCI suspend/resume functions work for a device, the driver can
1416 * easily implement them (ie just have a suspend function that calls
1417 * the pci_set_power_state() function).
1418 */
1419
1420 static int pci_pm_save_state_device(struct pci_dev *dev, u32 state)
1421 {
1422 int error = 0;
1423 if (dev) {
1424 struct pci_driver *driver = dev->driver;
1425 if (driver && driver->save_state)
1426 error = driver->save_state(dev,state);
1427 }
1428 return error;
1429 }
1430
1431 static int pci_pm_suspend_device(struct pci_dev *dev, u32 state)
1432 {
1433 int error = 0;
1434 if (dev) {
1435 struct pci_driver *driver = dev->driver;
1436 if (driver && driver->suspend)
1437 error = driver->suspend(dev,state);
1438 }
1439 return error;
1440 }
1441
1442 static int pci_pm_resume_device(struct pci_dev *dev)
1443 {
1444 int error = 0;
1445 if (dev) {
1446 struct pci_driver *driver = dev->driver;
1447 if (driver && driver->resume)
1448 error = driver->resume(dev);
1449 }
1450 return error;
1451 }
1452
1453 static int pci_pm_save_state_bus(struct pci_bus *bus, u32 state)
1454 {
1455 struct list_head *list;
1456 int error = 0;
1457
1458 list_for_each(list, &bus->children) {
1459 error = pci_pm_save_state_bus(pci_bus_b(list),state);
1460 if (error) return error;
1461 }
1462 list_for_each(list, &bus->devices) {
1463 error = pci_pm_save_state_device(pci_dev_b(list),state);
1464 if (error) return error;
1465 }
1466 return 0;
1467 }
1468
1469 static int pci_pm_suspend_bus(struct pci_bus *bus, u32 state)
1470 {
1471 struct list_head *list;
1472
1473 /* Walk the bus children list */
1474 list_for_each(list, &bus->children)
1475 pci_pm_suspend_bus(pci_bus_b(list),state);
1476
1477 /* Walk the device children list */
1478 list_for_each(list, &bus->devices)
1479 pci_pm_suspend_device(pci_dev_b(list),state);
1480 return 0;
1481 }
1482
1483 static int pci_pm_resume_bus(struct pci_bus *bus)
1484 {
1485 struct list_head *list;
1486
1487 /* Walk the device children list */
1488 list_for_each(list, &bus->devices)
1489 pci_pm_resume_device(pci_dev_b(list));
1490
1491 /* And then walk the bus children */
1492 list_for_each(list, &bus->children)
1493 pci_pm_resume_bus(pci_bus_b(list));
1494 return 0;
1495 }
1496
1497 static int pci_pm_save_state(u32 state)
1498 {
1499 struct list_head *list;
1500 struct pci_bus *bus;
1501 int error = 0;
1502
1503 list_for_each(list, &pci_root_buses) {
1504 bus = pci_bus_b(list);
1505 error = pci_pm_save_state_bus(bus,state);
1506 if (!error)
1507 error = pci_pm_save_state_device(bus->self,state);
1508 }
1509 return error;
1510 }
1511
1512 static int pci_pm_suspend(u32 state)
1513 {
1514 struct list_head *list;
1515 struct pci_bus *bus;
1516
1517 list_for_each(list, &pci_root_buses) {
1518 bus = pci_bus_b(list);
1519 pci_pm_suspend_bus(bus,state);
1520 pci_pm_suspend_device(bus->self,state);
1521 }
1522 return 0;
1523 }
1524
1525 static int pci_pm_resume(void)
1526 {
1527 struct list_head *list;
1528 struct pci_bus *bus;
1529
1530 list_for_each(list, &pci_root_buses) {
1531 bus = pci_bus_b(list);
1532 pci_pm_resume_device(bus->self);
1533 pci_pm_resume_bus(bus);
1534 }
1535 return 0;
1536 }
1537
1538 static int
1539 pci_pm_callback(struct pm_dev *pm_device, pm_request_t rqst, void *data)
1540 {
1541 int error = 0;
1542
1543 switch (rqst) {
1544 case PM_SAVE_STATE:
1545 error = pci_pm_save_state((u32)data);
1546 break;
1547 case PM_SUSPEND:
1548 error = pci_pm_suspend((u32)data);
1549 break;
1550 case PM_RESUME:
1551 error = pci_pm_resume();
1552 break;
1553 default: break;
1554 }
1555 return error;
1556 }
1557
1558 #endif
1559
1560 /*
1561 * Pool allocator ... wraps the pci_alloc_consistent page allocator, so
1562 * small blocks are easily used by drivers for bus mastering controllers.
1563 * This should probably be sharing the guts of the slab allocator.
1564 */
1565
1566 struct pci_pool { /* the pool */
1567 struct list_head page_list;
1568 spinlock_t lock;
1569 size_t blocks_per_page;
1570 size_t size;
1571 int flags;
1572 struct pci_dev *dev;
1573 size_t allocation;
1574 char name [32];
1575 wait_queue_head_t waitq;
1576 };
1577
1578 struct pci_page { /* cacheable header for 'allocation' bytes */
1579 struct list_head page_list;
1580 void *vaddr;
1581 dma_addr_t dma;
1582 unsigned long bitmap [0];
1583 };
1584
1585 #define POOL_TIMEOUT_JIFFIES ((100 /* msec */ * HZ) / 1000)
1586 #define POOL_POISON_BYTE 0xa7
1587
1588 // #define CONFIG_PCIPOOL_DEBUG
1589
1590
1591 /**
1592 * pci_pool_create - Creates a pool of pci consistent memory blocks, for dma.
1593 * @name: name of pool, for diagnostics
1594 * @pdev: pci device that will be doing the DMA
1595 * @size: size of the blocks in this pool.
1596 * @align: alignment requirement for blocks; must be a power of two
1597 * @allocation: returned blocks won't cross this boundary (or zero)
1598 * @flags: SLAB_* flags (not all are supported).
1599 *
1600 * Returns a pci allocation pool with the requested characteristics, or
1601 * null if one can't be created. Given one of these pools, pci_pool_alloc()
1602 * may be used to allocate memory. Such memory will all have "consistent"
1603 * DMA mappings, accessible by the device and its driver without using
1604 * cache flushing primitives. The actual size of blocks allocated may be
1605 * larger than requested because of alignment.
1606 *
1607 * If allocation is nonzero, objects returned from pci_pool_alloc() won't
1608 * cross that size boundary. This is useful for devices which have
1609 * addressing restrictions on individual DMA transfers, such as not crossing
1610 * boundaries of 4KBytes.
1611 */
1612 struct pci_pool *
1613 pci_pool_create (const char *name, struct pci_dev *pdev,
1614 size_t size, size_t align, size_t allocation, int flags)
1615 {
1616 struct pci_pool *retval;
1617
1618 if (align == 0)
1619 align = 1;
1620 if (size == 0)
1621 return 0;
1622 else if (size < align)
1623 size = align;
1624 else if ((size % align) != 0) {
1625 size += align + 1;
1626 size &= ~(align - 1);
1627 }
1628
1629 if (allocation == 0) {
1630 if (PAGE_SIZE < size)
1631 allocation = size;
1632 else
1633 allocation = PAGE_SIZE;
1634 // FIXME: round up for less fragmentation
1635 } else if (allocation < size)
1636 return 0;
1637
1638 if (!(retval = kmalloc (sizeof *retval, flags)))
1639 return retval;
1640
1641 #ifdef CONFIG_PCIPOOL_DEBUG
1642 flags |= SLAB_POISON;
1643 #endif
1644
1645 strncpy (retval->name, name, sizeof retval->name);
1646 retval->name [sizeof retval->name - 1] = 0;
1647
1648 retval->dev = pdev;
1649 INIT_LIST_HEAD (&retval->page_list);
1650 spin_lock_init (&retval->lock);
1651 retval->size = size;
1652 retval->flags = flags;
1653 retval->allocation = allocation;
1654 retval->blocks_per_page = allocation / size;
1655 init_waitqueue_head (&retval->waitq);
1656
1657 #ifdef CONFIG_PCIPOOL_DEBUG
1658 printk (KERN_DEBUG "pcipool create %s/%s size %d, %d/page (%d alloc)\n",
1659 pdev ? pdev->slot_name : NULL, retval->name, size,
1660 retval->blocks_per_page, allocation);
1661 #endif
1662
1663 return retval;
1664 }
1665
1666
1667 static struct pci_page *
1668 pool_alloc_page (struct pci_pool *pool, int mem_flags)
1669 {
1670 struct pci_page *page;
1671 int mapsize;
1672
1673 mapsize = pool->blocks_per_page;
1674 mapsize = (mapsize + BITS_PER_LONG - 1) / BITS_PER_LONG;
1675 mapsize *= sizeof (long);
1676
1677 page = (struct pci_page *) kmalloc (mapsize + sizeof *page, mem_flags);
1678 if (!page)
1679 return 0;
1680 page->vaddr = pci_alloc_consistent (pool->dev,
1681 pool->allocation, &page->dma);
1682 if (page->vaddr) {
1683 memset (page->bitmap, 0xff, mapsize); // bit set == free
1684 if (pool->flags & SLAB_POISON)
1685 memset (page->vaddr, POOL_POISON_BYTE, pool->allocation);
1686 list_add (&page->page_list, &pool->page_list);
1687 } else {
1688 kfree (page);
1689 page = 0;
1690 }
1691 return page;
1692 }
1693
1694
1695 static inline int
1696 is_page_busy (int blocks, unsigned long *bitmap)
1697 {
1698 while (blocks > 0) {
1699 if (*bitmap++ != ~0UL)
1700 return 1;
1701 blocks -= BITS_PER_LONG;
1702 }
1703 return 0;
1704 }
1705
1706 static void
1707 pool_free_page (struct pci_pool *pool, struct pci_page *page)
1708 {
1709 dma_addr_t dma = page->dma;
1710
1711 if (pool->flags & SLAB_POISON)
1712 memset (page->vaddr, POOL_POISON_BYTE, pool->allocation);
1713 pci_free_consistent (pool->dev, pool->allocation, page->vaddr, dma);
1714 list_del (&page->page_list);
1715 kfree (page);
1716 }
1717
1718
1719 /**
1720 * pci_pool_destroy - destroys a pool of pci memory blocks.
1721 * @pool: pci pool that will be destroyed
1722 *
1723 * Caller guarantees that no more memory from the pool is in use,
1724 * and that nothing will try to use the pool after this call.
1725 */
1726 void
1727 pci_pool_destroy (struct pci_pool *pool)
1728 {
1729 unsigned long flags;
1730
1731 #ifdef CONFIG_PCIPOOL_DEBUG
1732 printk (KERN_DEBUG "pcipool destroy %s/%s\n",
1733 pool->dev ? pool->dev->slot_name : NULL,
1734 pool->name);
1735 #endif
1736
1737 spin_lock_irqsave (&pool->lock, flags);
1738 while (!list_empty (&pool->page_list)) {
1739 struct pci_page *page;
1740 page = list_entry (pool->page_list.next,
1741 struct pci_page, page_list);
1742 if (is_page_busy (pool->blocks_per_page, page->bitmap)) {
1743 printk (KERN_ERR "pci_pool_destroy %s/%s, %p busy\n",
1744 pool->dev ? pool->dev->slot_name : NULL,
1745 pool->name, page->vaddr);
1746 /* leak the still-in-use consistent memory */
1747 list_del (&page->page_list);
1748 kfree (page);
1749 } else
1750 pool_free_page (pool, page);
1751 }
1752 spin_unlock_irqrestore (&pool->lock, flags);
1753 kfree (pool);
1754 }
1755
1756
1757 /**
1758 * pci_pool_alloc - get a block of consistent memory
1759 * @pool: pci pool that will produce the block
1760 * @mem_flags: SLAB_KERNEL or SLAB_ATOMIC
1761 * @handle: pointer to dma address of block
1762 *
1763 * This returns the kernel virtual address of a currently unused block,
1764 * and reports its dma address through the handle.
1765 * If such a memory block can't be allocated, null is returned.
1766 */
1767 void *
1768 pci_pool_alloc (struct pci_pool *pool, int mem_flags, dma_addr_t *handle)
1769 {
1770 unsigned long flags;
1771 struct list_head *entry;
1772 struct pci_page *page;
1773 int map, block;
1774 size_t offset;
1775 void *retval;
1776
1777 restart:
1778 spin_lock_irqsave (&pool->lock, flags);
1779 list_for_each (entry, &pool->page_list) {
1780 int i;
1781 page = list_entry (entry, struct pci_page, page_list);
1782 /* only cachable accesses here ... */
1783 for (map = 0, i = 0;
1784 i < pool->blocks_per_page;
1785 i += BITS_PER_LONG, map++) {
1786 if (page->bitmap [map] == 0)
1787 continue;
1788 block = ffz (~ page->bitmap [map]);
1789 if ((i + block) < pool->blocks_per_page) {
1790 clear_bit (block, &page->bitmap [map]);
1791 offset = (BITS_PER_LONG * map) + block;
1792 offset *= pool->size;
1793 goto ready;
1794 }
1795 }
1796 }
1797 if (!(page = pool_alloc_page (pool, mem_flags))) {
1798 if (mem_flags == SLAB_KERNEL) {
1799 DECLARE_WAITQUEUE (wait, current);
1800
1801 current->state = TASK_INTERRUPTIBLE;
1802 add_wait_queue (&pool->waitq, &wait);
1803 spin_unlock_irqrestore (&pool->lock, flags);
1804
1805 schedule_timeout (POOL_TIMEOUT_JIFFIES);
1806
1807 current->state = TASK_RUNNING;
1808 remove_wait_queue (&pool->waitq, &wait);
1809 goto restart;
1810 }
1811 retval = 0;
1812 goto done;
1813 }
1814
1815 clear_bit (0, &page->bitmap [0]);
1816 offset = 0;
1817 ready:
1818 retval = offset + page->vaddr;
1819 *handle = offset + page->dma;
1820 done:
1821 spin_unlock_irqrestore (&pool->lock, flags);
1822 return retval;
1823 }
1824
1825
1826 static struct pci_page *
1827 pool_find_page (struct pci_pool *pool, dma_addr_t dma)
1828 {
1829 unsigned long flags;
1830 struct list_head *entry;
1831 struct pci_page *page;
1832
1833 spin_lock_irqsave (&pool->lock, flags);
1834 list_for_each (entry, &pool->page_list) {
1835 page = list_entry (entry, struct pci_page, page_list);
1836 if (dma < page->dma)
1837 continue;
1838 if (dma < (page->dma + pool->allocation))
1839 goto done;
1840 }
1841 page = 0;
1842 done:
1843 spin_unlock_irqrestore (&pool->lock, flags);
1844 return page;
1845 }
1846
1847
1848 /**
1849 * pci_pool_free - put block back into pci pool
1850 * @pool: the pci pool holding the block
1851 * @vaddr: virtual address of block
1852 * @dma: dma address of block
1853 *
1854 * Caller promises neither device nor driver will again touch this block
1855 * unless it is first re-allocated.
1856 */
1857 void
1858 pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t dma)
1859 {
1860 struct pci_page *page;
1861 unsigned long flags;
1862 int map, block;
1863
1864 if ((page = pool_find_page (pool, dma)) == 0) {
1865 printk (KERN_ERR "pci_pool_free %s/%s, %p/%x (bad dma)\n",
1866 pool->dev ? pool->dev->slot_name : NULL,
1867 pool->name, vaddr, dma);
1868 return;
1869 }
1870 #ifdef CONFIG_PCIPOOL_DEBUG
1871 if (((dma - page->dma) + (void *)page->vaddr) != vaddr) {
1872 printk (KERN_ERR "pci_pool_free %s/%s, %p (bad vaddr)/%x\n",
1873 pool->dev ? pool->dev->slot_name : NULL,
1874 pool->name, vaddr, dma);
1875 return;
1876 }
1877 #endif
1878
1879 block = dma - page->dma;
1880 block /= pool->size;
1881 map = block / BITS_PER_LONG;
1882 block %= BITS_PER_LONG;
1883
1884 #ifdef CONFIG_PCIPOOL_DEBUG
1885 if (page->bitmap [map] & (1UL << block)) {
1886 printk (KERN_ERR "pci_pool_free %s/%s, dma %x already free\n",
1887 pool->dev ? pool->dev->slot_name : NULL,
1888 pool->name, dma);
1889 return;
1890 }
1891 #endif
1892 if (pool->flags & SLAB_POISON)
1893 memset (vaddr, POOL_POISON_BYTE, pool->size);
1894
1895 spin_lock_irqsave (&pool->lock, flags);
1896 set_bit (block, &page->bitmap [map]);
1897 if (waitqueue_active (&pool->waitq))
1898 wake_up (&pool->waitq);
1899 /*
1900 * Resist a temptation to do
1901 * if (!is_page_busy(bpp, page->bitmap)) pool_free_page(pool, page);
1902 * it is not interrupt safe. Better have empty pages hang around.
1903 */
1904 spin_unlock_irqrestore (&pool->lock, flags);
1905 }
1906
1907
1908 void __init pci_init(void)
1909 {
1910 struct pci_dev *dev;
1911
1912 pcibios_init();
1913
1914 pci_for_each_dev(dev) {
1915 pci_fixup_device(PCI_FIXUP_FINAL, dev);
1916 }
1917
1918 #ifdef CONFIG_PM
1919 pm_register(PM_PCI_DEV, 0, pci_pm_callback);
1920 #endif
1921 }
1922
1923 static int __init pci_setup(char *str)
1924 {
1925 while (str) {
1926 char *k = strchr(str, ',');
1927 if (k)
1928 *k++ = 0;
1929 if (*str && (str = pcibios_setup(str)) && *str) {
1930 /* PCI layer options should be handled here */
1931 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
1932 }
1933 str = k;
1934 }
1935 return 1;
1936 }
1937
1938 __setup("pci=", pci_setup);
1939
1940 EXPORT_SYMBOL(pci_read_config_byte);
1941 EXPORT_SYMBOL(pci_read_config_word);
1942 EXPORT_SYMBOL(pci_read_config_dword);
1943 EXPORT_SYMBOL(pci_write_config_byte);
1944 EXPORT_SYMBOL(pci_write_config_word);
1945 EXPORT_SYMBOL(pci_write_config_dword);
1946 EXPORT_SYMBOL(pci_devices);
1947 EXPORT_SYMBOL(pci_root_buses);
1948 EXPORT_SYMBOL(pci_enable_device);
1949 EXPORT_SYMBOL(pci_disable_device);
1950 EXPORT_SYMBOL(pci_find_capability);
1951 EXPORT_SYMBOL(pci_release_regions);
1952 EXPORT_SYMBOL(pci_request_regions);
1953 EXPORT_SYMBOL(pci_find_class);
1954 EXPORT_SYMBOL(pci_find_device);
1955 EXPORT_SYMBOL(pci_find_slot);
1956 EXPORT_SYMBOL(pci_find_subsys);
1957 EXPORT_SYMBOL(pci_set_master);
1958 EXPORT_SYMBOL(pci_set_dma_mask);
1959 EXPORT_SYMBOL(pci_assign_resource);
1960 EXPORT_SYMBOL(pci_register_driver);
1961 EXPORT_SYMBOL(pci_unregister_driver);
1962 EXPORT_SYMBOL(pci_dev_driver);
1963 EXPORT_SYMBOL(pci_match_device);
1964 EXPORT_SYMBOL(pci_find_parent_resource);
1965
1966 #ifdef CONFIG_HOTPLUG
1967 EXPORT_SYMBOL(pci_setup_device);
1968 EXPORT_SYMBOL(pci_insert_device);
1969 EXPORT_SYMBOL(pci_remove_device);
1970 #endif
1971
1972 EXPORT_SYMBOL(pci_set_power_state);
1973 EXPORT_SYMBOL(pci_save_state);
1974 EXPORT_SYMBOL(pci_restore_state);
1975 EXPORT_SYMBOL(pci_enable_wake);
1976
1977 /* Obsolete functions */
1978
1979 EXPORT_SYMBOL(pcibios_present);
1980 EXPORT_SYMBOL(pcibios_read_config_byte);
1981 EXPORT_SYMBOL(pcibios_read_config_word);
1982 EXPORT_SYMBOL(pcibios_read_config_dword);
1983 EXPORT_SYMBOL(pcibios_write_config_byte);
1984 EXPORT_SYMBOL(pcibios_write_config_word);
1985 EXPORT_SYMBOL(pcibios_write_config_dword);
1986 EXPORT_SYMBOL(pcibios_find_class);
1987 EXPORT_SYMBOL(pcibios_find_device);
1988
1989 /* Quirk info */
1990
1991 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1992 EXPORT_SYMBOL(pci_pci_problems);
1993
1994 /* Pool allocator */
1995
1996 EXPORT_SYMBOL (pci_pool_create);
1997 EXPORT_SYMBOL (pci_pool_destroy);
1998 EXPORT_SYMBOL (pci_pool_alloc);
1999 EXPORT_SYMBOL (pci_pool_free);
2000
2001