File: /usr/src/linux/drivers/sbus/audio/cs4231.h
1 /* $Id: cs4231.h,v 1.13 1999/09/21 14:37:27 davem Exp $
2 * drivers/sbus/audio/cs4231.h
3 *
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@noc.rutgers.edu)
5 * Copyright (C) 1997 Derrick J. Brashear (shadow@dementia.org)
6 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
7 */
8
9 #ifndef _CS4231_H_
10 #define _CS4231_H_
11
12 #include <linux/types.h>
13
14 /* According to the CS4231A data provided on CS web site and sun's includes */
15 #define IAR 0x00UL /* Index Address Register */
16 #define IDR 0x04UL /* Index Data Register */
17 #define STAT 0x08UL /* Status Register */
18 #define PIOD 0x0cUL /* PIO Data Register */
19 #define APCCSR 0x10UL /* APC DMA CSR */
20 #define APCCVA 0x20UL /* APC Capture DMA Address */
21 #define APCCC 0x24UL /* APC Capture Count */
22 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
23 #define APCCNC 0x2cUL /* APC Capture Next Count */
24 #define APCPVA 0x30UL /* APC Play DMA Address */
25 #define APCPC 0x34UL /* APC Play Count */
26 #define APCPNVA 0x38UL /* APC Play DMA Next Address */
27 #define APCPNC 0x3cUL /* APC Play Next Count */
28
29 /* EBUS DMA Registers */
30 #define EBDMA_CSR 0x00UL /* Control/Status */
31 #define EBDMA_ADDR 0x04UL /* DMA Address */
32 #define EBDMA_COUNT 0x08UL /* DMA Count */
33
34 /* Our structure for each chip */
35 struct cs4231_chip {
36 unsigned long regs;
37 unsigned long eb2c;
38 unsigned long eb2p;
39 struct audio_info perchip_info;
40 unsigned int playlen, reclen;
41 int irq, irq2, nirqs;
42 unsigned long regs_size;
43
44 /* Keep track of various info */
45 volatile unsigned int status;
46
47 /* Current buffer that the driver is playing. */
48 volatile __u8 * output_ptr;
49 volatile __u32 output_size;
50 volatile __u32 output_dma_handle, output_next_dma_handle;
51 volatile __u32 output_dma_size, output_next_dma_size;
52
53 /* Current record buffer. */
54 volatile __u8 * input_ptr;
55 volatile __u32 input_size;
56 volatile __u32 input_dma_handle, input_next_dma_handle;
57 volatile __u32 input_dma_size, input_next_dma_size;
58
59 /* Number of buffers in the pipe. */
60 volatile __u32 playing_count;
61 volatile __u32 recording_count;
62 };
63
64 #ifdef EB4231_SUPPORT
65 #define CS4231_READ32(__C, __REG) \
66 (((__C)->status & CS_STATUS_IS_EBUS) ? \
67 readl((__REG)) : \
68 sbus_readl((__REG)))
69 #define CS4231_READ8(__C, __REG) \
70 (((__C)->status & CS_STATUS_IS_EBUS) ? \
71 readb((__REG)) : \
72 sbus_readb((__REG)))
73 #define CS4231_WRITE32(__C, __REG, __VAL) \
74 (((__C)->status & CS_STATUS_IS_EBUS) ? \
75 writel((__VAL), (__REG)) : \
76 sbus_writel((__VAL), (__REG)))
77 #define CS4231_WRITE8(__C, __REG, __VAL) \
78 (((__C)->status & CS_STATUS_IS_EBUS) ? \
79 writeb((__VAL), (__REG)) : \
80 sbus_writeb((__VAL), (__REG)))
81 #else
82 /* We can assume all is SBUS in this case. */
83 #define CS4231_READ32(__C, __REG) sbus_readl((__REG))
84 #define CS4231_READ8(__C, __REG) sbus_readb((__REG))
85 #define CS4231_WRITE32(__C, __REG, __VAL) sbus_writel((__VAL), (__REG))
86 #define CS4231_WRITE8(__C, __REG, __VAL) sbus_writeb((__VAL), (__REG))
87 #endif
88
89 /* Local status bits */
90 #define CS_STATUS_NEED_INIT 0x01
91 #define CS_STATUS_INIT_ON_CLOSE 0x02
92 #define CS_STATUS_REV_A 0x04
93 #define CS_STATUS_INTS_ON 0x08
94 #define CS_STATUS_IS_ULTRA 0x10
95 #define CS_STATUS_IS_EBUS 0x20
96
97 #define CS_TIMEOUT 9000000
98
99 #define GAIN_SET(var, gain) ((var & ~(0x3f)) | gain)
100 #define RECGAIN_SET(var, gain) ((var & ~(0x1f)) | gain)
101
102 /* bits 0-3 set address of register accessed by idr register */
103 /* bit 4 allows access to idr registers 16-31 in mode 2 only */
104 /* bit 5 if set causes dma transfers to cease if the int bit of status set */
105 #define IAR_AUTOCAL_BEGIN 0x40 /* MCE */
106 #define IAR_NOT_READY 0x80 /* INIT */
107
108 #define IAR_AUTOCAL_END ~(IAR_AUTOCAL_BEGIN) /* MCD */
109
110 /* Registers 1-15 modes 1 and 2. Registers 16-31 mode 2 only */
111 /* Registers assumed to be same in both modes unless noted */
112
113 /* 0 - Left Input Control */
114 /* 1 - Right Input Control */
115 #define MIC_ENABLE(var) ((var & 0x2f) | 0x80)
116 #define LINE_ENABLE(var) (var & 0x2f)
117 #define CDROM_ENABLE(var) ((var & 0x2f) | 0x40)
118 #define OUTPUTLOOP_ENABLE(var) ((var & 0x2f) | 0xC0)
119 #define INPUTCR_AUX1 0x40
120
121 /* 2 - Left Aux 1 Input Control */
122 /* 3 - Right Aux 1 Input Control */
123 /* 4 - Left Aux 2 Input Control */
124 /* 5 - Right Aux 2 Input Control */
125
126 /* 6 - Left Output Control */
127 /* 7 - Right Output Control */
128 #define OUTCR_MUTE 0x80
129 #define OUTCR_UNMUTE ~0x80
130
131 /* 8 - Playback Data Format (Mode 2) */
132 #define CHANGE_DFR(var, val) ((var & ~(0xF)) | val)
133 #define CHANGE_ENCODING(var, val) ((var & ~(0xe0)) | val)
134 #define DEFAULT_DATA_FMAT CS4231_DFR_ULAW
135 #define CS4231_DFR_5512 0x01
136 #define CS4231_DFR_6615 0x0f
137 #define CS4231_DFR_8000 0x00
138 #define CS4231_DFR_9600 0x0e
139 #define CS4231_DFR_11025 0x03
140 #define CS4231_DFR_16000 0x02
141 #define CS4231_DFR_18900 0x05
142 #define CS4231_DFR_22050 0x07
143 #define CS4231_DFR_27429 0x04
144 #define CS4231_DFR_32000 0x06
145 #define CS4231_DFR_33075 0x0d
146 #define CS4231_DFR_37800 0x09
147 #define CS4231_DFR_44100 0x0b
148 #define CS4231_DFR_48000 0x0c
149 #define CS4231_DFR_LINEAR8 0x00
150 #define CS4231_DFR_ULAW 0x20
151 #define CS4231_DFR_LINEARLE 0x40
152 #define CS4231_DFR_ALAW 0x60
153 #define CS4231_DFR_ADPCM 0xa0 /* N/A in mode 1 */
154 #define CS4231_DFR_LINEARBE 0xc0 /* N/A in mode 1 */
155 #define CS4231_STEREO_ON(val) (val | 0x10)
156 #define CS4231_MONO_ON(val) (val & ~0x10)
157
158 /* 9 - Interface Config. Register */
159 #define PEN_ENABLE (0x01) /* Playback Enable */
160 #define PEN_DISABLE (~0x01)
161 #define CEN_ENABLE (0x02) /* Capture Enable */
162 #define CEN_DISABLE (~0x02)
163 #define SDC_ENABLE (0x04) /* Turn on single DMA Channel mode */
164 #define ACAL_CONV 0x08 /* Turn on converter autocal */
165 #define ACAL_DISABLE (~0x08)
166 #define ACAL_DAC 0x10 /* Turn on DAC autocal */
167 #define ACAL_FULL (ACAL_DAC|ACAL_CONV) /* Turn on full autocal */
168 #define PPIO 0x20 /* do playback via PIO rather than DMA */
169 #define CPIO 0x40 /* do capture via PIO rather than DMA */
170 #define ICR_AUTOCAL_INIT 0x01
171
172 /* 10 - Pin Control Register */
173 #define INTR_ON 0x82
174 #define INTR_OFF 0x80
175 #define PINCR_LINE_MUTE 0x40
176 #define PINCR_HDPH_MUTE 0x80
177
178 /* 11 - Test/Initialization */
179 #define DRQ_STAT 0x10
180 #define AUTOCAL_IN_PROGRESS 0x20
181
182 /* 12 - Misc Information */
183 #define MISC_IR_MODE2 0x40
184
185 /* 13 - Loopback Control */
186 #define LOOPB_ON 0x01
187 #define LOOPB_OFF 0x00
188
189 /* 14 - shared play/capture upper (mode 1) */
190 /* 15 - shared play/capture lower (mode 1) */
191
192 /* 14 - Playback Upper (mode 2) */
193 /* 15 - Playback Lower (mode 2) */
194
195 /* The rest are mode 2 only */
196
197 /* 16 - Alternate Feature 1 Enable */
198 #define DAC_ZERO 0x01
199 #define PLAY_MCE 0x10
200 #define CAPTURE_MCE 0x20
201 #define TIMER_ENABLE 0x40
202 #define OLB_ENABLE 0x80 /* go to 2.88 vpp analog output */
203
204 /* 17 - Alternate Feature 2 Enable */
205 #define HPF_ON 0x01 /* High Pass Filter */
206 #define XTALE_ON 0x02 /* Enable both crystals */
207 #define APAR_OFF 0x04 /* ADPCM playback accum reset */
208
209 /* 18 - Left Line Input Gain */
210 /* 19 - Right Line Input Gain */
211
212 /* 20 - Timer High */
213 /* 21 - Timer Low */
214
215 /* 22 - unused */
216
217 /* 23 - Alt. Fea. Ena 3 */
218 #define ACF 0x01
219
220 /* 24 - Alternate Feature Status */
221 #define CS_PU 0x01 /* Underrun */
222 #define CS_PO 0x02 /* Overrun */
223 #define CS_CU 0x04 /* Underrun */
224 #define CS_CO 0x08 /* Overrun */
225 #define CS_PI 0x10
226 #define CS_CI 0x20
227 #define CS_TI 0x40
228
229 /* 25 - Version */
230 #define CS4231A 0x20
231 #define CS4231CDE 0x80
232
233 /* 26 - Mono I/O Control */
234 #define CHANGE_MONO_GAIN(val) ((val & ~(0xFF)) | val)
235 #define MONO_IOCR_BYPASS 0x20
236 #define MONO_IOCR_MUTE 0x40
237 #define MONO_IOCR_INMUTE 0x80
238
239 /* 27 - Unused */
240
241 /* 28 - Capture Data Format */
242 /* see register 8 */
243
244 /* 29 - Unused */
245
246 /* 30 - Capture Upper */
247 /* 31 - Capture Lower */
248
249 /* Following are APC CSR register definitions for the Sparc */
250
251 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
252 #define APC_PLAY_INT 0x400000 /* Playback interrupt */
253 #define APC_CAPT_INT 0x200000 /* Capture interrupt */
254 #define APC_GENL_INT 0x100000 /* General interrupt */
255 #define APC_XINT_ENA 0x80000 /* General ext int. enable */
256 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
257 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
258 #define APC_XINT_GENL 0x10000 /* Error ext intr */
259 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
260 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
261 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
262 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
263 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
264 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
265 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
266 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
267 #define APC_PPAUSE 0x80 /* Pause the play DMA */
268 #define APC_CPAUSE 0x40 /* Pause the capture DMA */
269 #define APC_CDC_RESET 0x20 /* CODEC RESET */
270 #define APC_PDMA_READY 0x08 /* Play DMA Go */
271 #define APC_CDMA_READY 0x04 /* Capture DMA Go */
272 #define APC_CHIP_RESET 0x01 /* Reset the chip */
273
274 #define APC_INIT_SETUP (APC_CDMA_READY | APC_PDMA_READY | APC_XINT_ENA | \
275 APC_XINT_PLAY | APC_XINT_GENL | APC_INT_PENDING | \
276 APC_PLAY_INT | APC_CAPT_INT | APC_GENL_INT)
277
278 #define APC_PLAY_SETUP (APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA | \
279 APC_XINT_PLAY | APC_XINT_EMPT | APC_XINT_GENL | \
280 APC_XINT_PENA | APC_PDMA_READY)
281
282 #define APC_CAPT_SETUP (APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA | \
283 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL | \
284 APC_CDMA_READY)
285
286 /* Following are EB2 CSR register definitions for the Sparc */
287
288 /* asm/ebus.h has the base settings */
289
290 #define EB2_PLAY_SETUP (EBUS_DCSR_BURST_SZ_8 | EBUS_DCSR_INT_EN | EBUS_DCSR_EN_DMA | \
291 EBUS_DCSR_EN_CNT | EBUS_DCSR_TC)
292 #define EB2_CAPT_SETUP (EBUS_DCSR_BURST_SZ_8 | EBUS_DCSR_INT_EN | EBUS_DCSR_EN_DMA| \
293 EBUS_DCSR_EN_CNT | EBUS_DCSR_TC | EBUS_DCSR_WRITE)
294
295 #define CS4231_MIN_ATEN (0)
296 #define CS4231_MAX_ATEN (31)
297 #define CS4231_MAX_DEV_ATEN (63)
298
299 #define CS4231_MON_MIN_ATEN (0)
300 #define CS4231_MON_MAX_ATEN (63)
301
302 #define CS4231_DEFAULT_PLAYGAIN (132)
303 #define CS4231_DEFAULT_RECGAIN (126)
304
305 #define CS4231_MIN_GAIN (0)
306 #define CS4231_MAX_GAIN (15)
307
308 #define CS4231_PRECISION (8) /* # of bits/sample */
309 #define CS4231_CHANNELS (1) /* channels/sample */
310
311 #define CS4231_RATE (8000) /* default sample rate */
312
313 #endif /* _CS4231_H_ */
314