File: /usr/src/linux/drivers/sbus/audio/dbri.c
1 /* $Id: dbri.c,v 1.26 2001/05/21 01:25:22 davem Exp $
2 * drivers/sbus/audio/dbri.c
3 *
4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
5 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
6 *
7 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
8 * on Sun SPARCstation 10, 20, LX and Voyager models.
9 *
10 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
11 * data time multiplexer with ISDN support (aka T7259)
12 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
13 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
14 * Documentation:
15 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
16 * Sparc Technology Business (courtesy of Sun Support)
17 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
18 * available from the Lucent (formarly AT&T microelectronics) home
19 * page.
20 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
21 * Interfaces: CHI, Audio In & Out, 2 bits parallel
22 * Documentation: from the Crystal Semiconductor home page.
23 *
24 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
25 * memory and a serial device (long pipes, nr 0-15) or between two serial
26 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
27 * device (short pipes).
28 * A timeslot defines the bit-offset and nr of bits read from a serial device.
29 * The timeslots are linked to 6 circular lists, one for each direction for
30 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
31 * (the second one is a monitor/tee pipe, valid only for serial input).
32 *
33 * The mmcodec is connected via the CHI bus and needs the data & some
34 * parameters (volume, balance, output selection) timemultiplexed in 8 byte
35 * chunks. It also has a control mode, which serves for audio format setting.
36 *
37 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
38 * the same CHI bus, so I thought perhaps it is possible to use the onboard
39 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
40 * audio devices. But the SUN HW group decided against it, at least on my
41 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
42 * connected.
43 */
44
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/sched.h>
48 #include <linux/errno.h>
49 #include <linux/interrupt.h>
50 #include <linux/slab.h>
51 #include <linux/version.h>
52 #include <linux/delay.h>
53 #include <asm/openprom.h>
54 #include <asm/oplib.h>
55 #include <asm/system.h>
56 #include <asm/irq.h>
57 #include <asm/io.h>
58 #include <asm/sbus.h>
59 #include <asm/pgtable.h>
60
61 #include <asm/audioio.h>
62 #include "dbri.h"
63
64 #if defined(DBRI_ISDN)
65 #include "../../isdn/hisax/hisax.h"
66 #include "../../isdn/hisax/isdnl1.h"
67 #include "../../isdn/hisax/foreign.h"
68 #endif
69
70 #define DBRI_DEBUG
71
72 #ifdef DBRI_DEBUG
73
74 #define dprintk(a, x) if(dbri_debug & a) printk x
75 #define D_GEN (1<<0)
76 #define D_INT (1<<1)
77 #define D_CMD (1<<2)
78 #define D_MM (1<<3)
79 #define D_USR (1<<4)
80 #define D_DESC (1<<5)
81
82 static int dbri_debug = 0;
83 MODULE_PARM(dbri_debug, "i");
84
85 static int dbri_trace = 0;
86 MODULE_PARM(dbri_trace, "i");
87 #define tprintk(x) if(dbri_trace) printk x
88
89 static char *cmds[] = {
90 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
91 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
92 };
93
94 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value)
95
96 #else
97
98 #define dprintk(a, x)
99 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value)
100
101 #endif /* DBRI_DEBUG */
102
103
104
105 #define MAX_DRIVERS 2 /* Increase this if need more than 2 DBRI's */
106
107 static struct sparcaudio_driver drivers[MAX_DRIVERS];
108 static int num_drivers = 0;
109
110
111 /*
112 ****************************************************************************
113 ************** DBRI initialization and command synchronization *************
114 ****************************************************************************
115
116 Commands are sent to the DBRI by building a list of them in memory,
117 then writing the address of the first list item to DBRI register 8.
118 The list is terminated with a WAIT command, which can generate a
119 CPU interrupt if required.
120
121 Since the DBRI can run in parallel with the CPU, several means of
122 synchronization present themselves. The original scheme (Rudolf's)
123 was to set a flag when we "cmdlock"ed the DBRI, clear the flag when
124 an interrupt signaled completion, and wait on a wait_queue if a routine
125 attempted to cmdlock while the flag was set. The problems arose when
126 we tried to cmdlock from inside an interrupt handler, which might
127 cause scheduling in an interrupt (if we waited), etc, etc
128
129 A more sophisticated scheme might involve a circular command buffer
130 or an array of command buffers. A routine could fill one with
131 commands and link it onto a list. When a interrupt signaled
132 completion of the current command buffer, look on the list for
133 the next one.
134
135 I've decided to implement something much simpler - after each command,
136 the CPU waits for the DBRI to finish the command by polling the P bit
137 in DBRI register 0. I've tried to implement this in such a way
138 that might make implementing a more sophisticated scheme easier.
139
140 Every time a routine wants to write commands to the DBRI, it must
141 first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
142 in return. After the commands have been writen, dbri_cmdsend() is
143 called with the final pointer value.
144
145 Something a little more clever is required if this code is ever run
146 on an SMP machine.
147
148 */
149
150 static int dbri_locked = 0;
151
152 static volatile s32 *dbri_cmdlock(struct dbri *dbri)
153 {
154 if (dbri_locked)
155 printk("DBRI: Command buffer locked! (bug in driver)\n");
156
157 dbri_locked++;
158 return &dbri->dma->cmd[0];
159 }
160
161 static void dbri_process_interrupt_buffer(struct dbri *);
162
163 static void dbri_cmdsend(struct dbri *dbri, volatile s32 *cmd)
164 {
165 int MAXLOOPS = 1000000;
166 int maxloops = MAXLOOPS;
167 unsigned long flags;
168 volatile s32 *ptr;
169
170 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
171 dprintk(D_CMD, ("DBRI cmd: %lx:%08x\n",
172 (unsigned long) ptr, *ptr));
173 }
174
175 save_and_cli(flags);
176
177 dbri_locked--;
178 if (dbri_locked != 0) {
179 printk("DBRI: Command buffer improperly locked! (bug in driver)\n");
180 } else if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS-1) {
181 printk("DBRI: Command buffer overflow! (bug in driver)\n");
182 } else {
183 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
184 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
185 dbri->wait_seen = 0;
186 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
187 while ((--maxloops) > 0 &&
188 (sbus_readl(dbri->regs + REG0) & D_P))
189 barrier();
190 if (maxloops == 0) {
191 printk("DBRI: Chip never completed command buffer\n");
192 } else {
193 while ((--maxloops) > 0 && (! dbri->wait_seen))
194 dbri_process_interrupt_buffer(dbri);
195 if (maxloops == 0) {
196 printk("DBRI: Chip never acked WAIT\n");
197 } else {
198 dprintk(D_INT, ("DBRI: Chip completed command "
199 "buffer (%d)\n",
200 MAXLOOPS - maxloops));
201 }
202 }
203 }
204
205 restore_flags(flags);
206 }
207
208 static void dbri_reset(struct dbri *dbri)
209 {
210 int i;
211
212 dprintk(D_GEN, ("DBRI: reset 0:%x 2:%x 8:%x 9:%x\n",
213 sbus_readl(dbri->regs + REG0),
214 sbus_readl(dbri->regs + REG2),
215 sbus_readl(dbri->regs + REG8),
216 sbus_readl(dbri->regs + REG9)));
217
218 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
219 for(i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
220 udelay(10);
221 }
222
223 static void dbri_detach(struct dbri *dbri)
224 {
225 dbri_reset(dbri);
226 free_irq(dbri->irq, dbri);
227 sbus_iounmap(dbri->regs, dbri->regs_size);
228 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
229 (void *)dbri->dma, dbri->dma_dvma);
230 kfree(dbri);
231 }
232
233 static void dbri_initialize(struct dbri *dbri)
234 {
235 volatile s32 *cmd;
236 u32 dma_addr, tmp;
237 int n;
238
239 dbri_reset(dbri);
240
241 dprintk(D_GEN, ("DBRI: init: cmd: %p, int: %p\n",
242 &dbri->dma->cmd[0], &dbri->dma->intr[0]));
243
244 /*
245 * Initialize the interrupt ringbuffer.
246 */
247 for(n = 0; n < DBRI_NO_INTS-1; n++) {
248 dma_addr = dbri->dma_dvma;
249 dma_addr += dbri_dma_off(intr, ((n+1) & DBRI_INT_BLK));
250 dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
251 }
252 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
253 dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
254 dbri->dbri_irqp = 1;
255
256 /* We should query the openprom to see what burst sizes this
257 * SBus supports. For now, just disable all SBus bursts */
258 tmp = sbus_readl(dbri->regs + REG0);
259 tmp &= ~(D_G | D_S | D_E);
260 sbus_writel(tmp, dbri->regs + REG0);
261
262 /*
263 * Set up the interrupt queue
264 */
265 cmd = dbri_cmdlock(dbri);
266 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
267 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
268 *(cmd++) = dma_addr;
269
270 dbri_cmdsend(dbri, cmd);
271 }
272
273
274 /*
275 ****************************************************************************
276 *************************** DBRI interrupt handler *************************
277 ****************************************************************************
278
279 The DBRI communicates with the CPU mainly via a circular interrupt
280 buffer. When an interrupt is signaled, the CPU walks through the
281 buffer and calls dbri_process_one_interrupt() for each interrupt word.
282 Complicated interrupts are handled by dedicated functions (which
283 appear first in this file). Any pending interrupts can be serviced by
284 calling dbri_process_interrupt_buffer(), which works even if the CPU's
285 interrupts are disabled. This function is used by dbri_cmdsend()
286 to make sure we're synced up with the chip after each command sequence,
287 even if we're running cli'ed.
288
289 */
290
291
292 /*
293 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
294 * So we have to reverse the bits. Note: not all bit lengths are supported
295 */
296 static __u32 reverse_bytes(__u32 b, int len)
297 {
298 switch(len) {
299 case 32:
300 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
301 case 16:
302 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
303 case 8:
304 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
305 case 4:
306 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
307 case 2:
308 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
309 case 1:
310 case 0:
311 break;
312 default:
313 printk("DBRI reverse_bytes: unsupported length\n");
314 };
315
316 return b;
317 }
318
319 /* transmission_complete_intr()
320 *
321 * Called by main interrupt handler when DBRI signals transmission complete
322 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
323 *
324 * Walks through the pipe's list of transmit buffer descriptors, releasing
325 * each one's DMA buffer (if present), flagging the descriptor available,
326 * and signaling its callback routine (if present), before proceeding
327 * to the next one. Stops when the first descriptor is found without
328 * TBC (Transmit Buffer Complete) set, or we've run through them all.
329 */
330
331 static void transmission_complete_intr(struct dbri *dbri, int pipe)
332 {
333 int td;
334 int status;
335 void *buffer;
336 void (*callback)(void *, int);
337 void *callback_arg;
338
339 td = dbri->pipes[pipe].desc;
340
341 while (td >= 0) {
342 if (td >= DBRI_NO_DESCS) {
343 printk("DBRI: invalid td on pipe %d\n", pipe);
344 return;
345 }
346
347 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
348
349 if (! (status & DBRI_TD_TBC)) {
350 break;
351 }
352
353 dprintk(D_INT, ("DBRI: TD %d, status 0x%02x\n", td, status));
354
355 buffer = dbri->descs[td].buffer;
356 if (buffer)
357 sbus_unmap_single(dbri->sdev,
358 dbri->descs[td].buffer_dvma,
359 dbri->descs[td].len,
360 SBUS_DMA_TODEVICE);
361
362 callback = dbri->descs[td].output_callback;
363 callback_arg = dbri->descs[td].output_callback_arg;
364
365 dbri->descs[td].inuse = 0;
366
367 td = dbri->descs[td].next;
368 dbri->pipes[pipe].desc = td;
369
370 if (callback != NULL)
371 callback(callback_arg, status & 0xe);
372 }
373 }
374
375 static void reception_complete_intr(struct dbri *dbri, int pipe)
376 {
377 int rd = dbri->pipes[pipe].desc;
378 s32 status;
379 void *buffer;
380 void (*callback)(void *, int, unsigned int);
381
382 if (rd < 0 || rd >= DBRI_NO_DESCS) {
383 printk("DBRI: invalid rd on pipe %d\n", pipe);
384 return;
385 }
386
387 dbri->descs[rd].inuse = 0;
388 dbri->pipes[pipe].desc = dbri->descs[rd].next;
389 status = dbri->dma->desc[rd].word1;
390
391 buffer = dbri->descs[rd].buffer;
392 if (buffer)
393 sbus_unmap_single(dbri->sdev,
394 dbri->descs[rd].buffer_dvma,
395 dbri->descs[rd].len,
396 SBUS_DMA_FROMDEVICE);
397
398 callback = dbri->descs[rd].input_callback;
399 if (callback != NULL)
400 callback(dbri->descs[rd].input_callback_arg,
401 DBRI_RD_STATUS(status),
402 DBRI_RD_CNT(status)-2);
403
404 dprintk(D_INT, ("DBRI: Recv RD %d, status 0x%02x, len %d\n",
405 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)));
406 }
407
408 static void dbri_process_one_interrupt(struct dbri *dbri, int x)
409 {
410 int val = D_INTR_GETVAL(x);
411 int channel = D_INTR_GETCHAN(x);
412 int command = D_INTR_GETCMD(x);
413 int code = D_INTR_GETCODE(x);
414 int rval = D_INTR_GETRVAL(x);
415
416 if (channel == D_INTR_CMD) {
417 dprintk(D_INT,("DBRI: INTR: Command: %-5s Value:%d\n",
418 cmds[command], val));
419 } else {
420 dprintk(D_INT,("DBRI: INTR: Chan:%d Code:%d Val:%#x\n",
421 channel, code, rval));
422 }
423
424 if (channel == D_INTR_CMD && command == D_WAIT)
425 dbri->wait_seen++;
426
427 if (code == D_INTR_SBRI) {
428 /* SBRI - BRI status change */
429 const int liu_states[] = {1, 0, 8, 3, 4, 5, 6, 7};
430
431 dbri->liu_state = liu_states[val & 0x7];
432 if (dbri->liu_callback)
433 dbri->liu_callback(dbri->liu_callback_arg);
434 }
435
436 if (code == D_INTR_BRDY)
437 reception_complete_intr(dbri, channel);
438
439 if (code == D_INTR_XCMP)
440 transmission_complete_intr(dbri, channel);
441
442 if (code == D_INTR_UNDR) {
443 /* UNDR - Transmission underrun
444 * resend SDP command with clear pipe bit (C) set
445 */
446 volatile s32 *cmd;
447 int pipe = channel;
448 int td = dbri->pipes[pipe].desc;
449
450 dbri->dma->desc[td].word4 = 0;
451
452 cmd = dbri_cmdlock(dbri);
453 *(cmd++) = DBRI_CMD(D_SDP, 0,
454 dbri->pipes[pipe].sdp
455 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
456 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
457 dbri_cmdsend(dbri, cmd);
458 }
459
460 if (code == D_INTR_FXDT) {
461 /* FXDT - Fixed data change */
462 if (dbri->pipes[channel].sdp & D_SDP_MSB)
463 val = reverse_bytes(val, dbri->pipes[channel].length);
464
465 if (dbri->pipes[channel].recv_fixed_ptr)
466 *(dbri->pipes[channel].recv_fixed_ptr) = val;
467 }
468 }
469
470 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
471 * buffer until it finds a zero word (indicating nothing more to do
472 * right now). Non-zero words require processing and are handed off
473 * to dbri_process_one_interrupt AFTER advancing the pointer. This
474 * order is important since we might recurse back into this function
475 * and need to make sure the pointer has been advanced first.
476 */
477 static void dbri_process_interrupt_buffer(struct dbri *dbri)
478 {
479 s32 x;
480
481 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
482 dbri->dma->intr[dbri->dbri_irqp] = 0;
483 dbri->dbri_irqp++;
484 if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK))
485 dbri->dbri_irqp = 1;
486 else if ((dbri->dbri_irqp & (DBRI_INT_BLK-1)) == 0)
487 dbri->dbri_irqp++;
488
489 tprintk(("dbri->dbri_irqp == %d\n", dbri->dbri_irqp));
490 dbri_process_one_interrupt(dbri, x);
491 }
492 }
493
494 static void dbri_intr(int irq, void *opaque, struct pt_regs *regs)
495 {
496 struct dbri *dbri = (struct dbri *) opaque;
497 int x;
498
499 /*
500 * Read it, so the interrupt goes away.
501 */
502 x = sbus_readl(dbri->regs + REG1);
503
504 dprintk(D_INT, ("DBRI: Interrupt! (reg1=0x%08x)\n", x));
505
506 if (x & (D_MRR|D_MLE|D_LBG|D_MBE)) {
507 u32 tmp;
508
509 if(x & D_MRR) printk("DBRI: Multiple Error Ack on SBus\n");
510 if(x & D_MLE) printk("DBRI: Multiple Late Error on SBus\n");
511 if(x & D_LBG) printk("DBRI: Lost Bus Grant on SBus\n");
512 if(x & D_MBE) printk("DBRI: Burst Error on SBus\n");
513
514 /* Some of these SBus errors cause the chip's SBus circuitry
515 * to be disabled, so just re-enable and try to keep going.
516 *
517 * The only one I've seen is MRR, which will be triggered
518 * if you let a transmit pipe underrun, then try to CDP it.
519 *
520 * If these things persist, we should probably reset
521 * and re-init the chip.
522 */
523 tmp = sbus_readl(dbri->regs + REG0);
524 tmp &= ~(D_D);
525 sbus_writel(tmp, dbri->regs + REG0);
526 }
527
528 #if 0
529 if (!(x & D_IR)) /* Not for us */
530 return;
531 #endif
532
533 dbri_process_interrupt_buffer(dbri);
534 }
535
536
537 /*
538 ****************************************************************************
539 ************************** DBRI data pipe management ***********************
540 ****************************************************************************
541
542 While DBRI control functions use the command and interrupt buffers, the
543 main data path takes the form of data pipes, which can be short (command
544 and interrupt driven), or long (attached to DMA buffers). These functions
545 provide a rudimentary means of setting up and managing the DBRI's pipes,
546 but the calling functions have to make sure they respect the pipes' linked
547 list ordering, among other things. The transmit and receive functions
548 here interface closely with the transmit and receive interrupt code.
549
550 */
551 static int pipe_active(struct dbri *dbri, int pipe)
552 {
553 return (dbri->pipes[pipe].desc != -1);
554 }
555
556
557 /* reset_pipe(dbri, pipe)
558 *
559 * Called on an in-use pipe to clear anything being transmitted or received
560 */
561 static void reset_pipe(struct dbri *dbri, int pipe)
562 {
563 int sdp;
564 int desc;
565 volatile int *cmd;
566
567 if (pipe < 0 || pipe > 31) {
568 printk("DBRI: reset_pipe called with illegal pipe number\n");
569 return;
570 }
571
572 sdp = dbri->pipes[pipe].sdp;
573 if (sdp == 0) {
574 printk("DBRI: reset_pipe called on uninitialized pipe\n");
575 return;
576 }
577
578 cmd = dbri_cmdlock(dbri);
579 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
580 *(cmd++) = 0;
581 dbri_cmdsend(dbri, cmd);
582
583 desc = dbri->pipes[pipe].desc;
584 while (desc != -1) {
585 void *buffer = dbri->descs[desc].buffer;
586 void (*output_callback) (void *, int)
587 = dbri->descs[desc].output_callback;
588 void *output_callback_arg
589 = dbri->descs[desc].output_callback_arg;
590 void (*input_callback) (void *, int, unsigned int)
591 = dbri->descs[desc].input_callback;
592 void *input_callback_arg
593 = dbri->descs[desc].input_callback_arg;
594
595 if (buffer)
596 sbus_unmap_single(dbri->sdev,
597 dbri->descs[desc].buffer_dvma,
598 dbri->descs[desc].len,
599 output_callback != NULL ? SBUS_DMA_TODEVICE
600 : SBUS_DMA_FROMDEVICE);
601
602 dbri->descs[desc].inuse = 0;
603 desc = dbri->descs[desc].next;
604
605 if (output_callback)
606 output_callback(output_callback_arg, -1);
607
608 if (input_callback)
609 input_callback(input_callback_arg, -1, 0);
610 }
611
612 dbri->pipes[pipe].desc = -1;
613 }
614
615 static void setup_pipe(struct dbri *dbri, int pipe, int sdp)
616 {
617 if (pipe < 0 || pipe > 31) {
618 printk("DBRI: setup_pipe called with illegal pipe number\n");
619 return;
620 }
621
622 if ((sdp & 0xf800) != sdp) {
623 printk("DBRI: setup_pipe called with strange SDP value\n");
624 /* sdp &= 0xf800; */
625 }
626
627 /* If this is a fixed receive pipe, arrange for an interrupt
628 * every time its data changes
629 */
630 if (D_SDP_MODE(sdp) == D_SDP_FIXED && ! (sdp & D_SDP_TO_SER))
631 sdp |= D_SDP_CHANGE;
632
633 sdp |= D_PIPE(pipe);
634 dbri->pipes[pipe].sdp = sdp;
635 dbri->pipes[pipe].desc = -1;
636
637 reset_pipe(dbri, pipe);
638 }
639
640 static void link_time_slot(struct dbri *dbri, int pipe,
641 enum in_or_out direction, int basepipe,
642 int length, int cycle)
643 {
644 volatile s32 *cmd;
645 int val;
646 int prevpipe;
647 int nextpipe;
648
649 if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
650 printk("DBRI: link_time_slot called with illegal pipe number\n");
651 return;
652 }
653
654 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
655 printk("DBRI: link_time_slot called on uninitialized pipe\n");
656 return;
657 }
658
659 /* Deal with CHI special case:
660 * "If transmission on edges 0 or 1 is desired, then cycle n
661 * (where n = # of bit times per frame...) must be used."
662 * - DBRI data sheet, page 11
663 */
664 if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
665 cycle = dbri->chi_bpf;
666
667 if (basepipe == pipe) {
668 prevpipe = pipe;
669 nextpipe = pipe;
670 } else {
671 /* We're not initializing a new linked list (basepipe != pipe),
672 * so run through the linked list and find where this pipe
673 * should be sloted in, based on its cycle. CHI confuses
674 * things a bit, since it has a single anchor for both its
675 * transmit and receive lists.
676 */
677 if (basepipe == 16) {
678 if (direction == PIPEinput) {
679 prevpipe = dbri->chi_in_pipe;
680 } else {
681 prevpipe = dbri->chi_out_pipe;
682 }
683 } else {
684 prevpipe = basepipe;
685 }
686
687 nextpipe = dbri->pipes[prevpipe].nextpipe;
688
689 while (dbri->pipes[nextpipe].cycle < cycle
690 && dbri->pipes[nextpipe].nextpipe != basepipe) {
691 prevpipe = nextpipe;
692 nextpipe = dbri->pipes[nextpipe].nextpipe;
693 }
694 }
695
696 if (prevpipe == 16) {
697 if (direction == PIPEinput) {
698 dbri->chi_in_pipe = pipe;
699 } else {
700 dbri->chi_out_pipe = pipe;
701 }
702 } else {
703 dbri->pipes[prevpipe].nextpipe = pipe;
704 }
705
706 dbri->pipes[pipe].nextpipe = nextpipe;
707 dbri->pipes[pipe].cycle = cycle;
708 dbri->pipes[pipe].length = length;
709
710 cmd = dbri_cmdlock(dbri);
711
712 if (direction == PIPEinput) {
713 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
714 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
715 *(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
716 *(cmd++) = 0;
717 } else {
718 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
719 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
720 *(cmd++) = 0;
721 *(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
722 }
723
724 dbri_cmdsend(dbri, cmd);
725 }
726
727 /* I don't use this function, so it's basically untested. */
728 static void unlink_time_slot(struct dbri *dbri, int pipe,
729 enum in_or_out direction, int prevpipe,
730 int nextpipe)
731 {
732 volatile s32 *cmd;
733 int val;
734
735 if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
736 printk("DBRI: unlink_time_slot called with illegal pipe number\n");
737 return;
738 }
739
740 cmd = dbri_cmdlock(dbri);
741
742 if (direction == PIPEinput) {
743 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
744 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
745 *(cmd++) = D_TS_NEXT(nextpipe);
746 *(cmd++) = 0;
747 } else {
748 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
749 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
750 *(cmd++) = 0;
751 *(cmd++) = D_TS_NEXT(nextpipe);
752 }
753
754 dbri_cmdsend(dbri, cmd);
755 }
756
757 /* xmit_fixed() / recv_fixed()
758 *
759 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
760 * expected to change much, and which we don't need to buffer.
761 * The DBRI only interrupts us when the data changes (receive pipes),
762 * or only changes the data when this function is called (transmit pipes).
763 * Only short pipes (numbers 16-31) can be used in fixed data mode.
764 *
765 * These function operate on a 32-bit field, no matter how large
766 * the actual time slot is. The interrupt handler takes care of bit
767 * ordering and alignment. An 8-bit time slot will always end up
768 * in the low-order 8 bits, filled either MSB-first or LSB-first,
769 * depending on the settings passed to setup_pipe()
770 */
771 static void xmit_fixed(struct dbri *dbri, int pipe, unsigned int data)
772 {
773 volatile s32 *cmd;
774
775 if (pipe < 16 || pipe > 31) {
776 printk("DBRI: xmit_fixed: Illegal pipe number\n");
777 return;
778 }
779
780 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
781 printk("DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
782 return;
783 }
784
785 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
786 printk("DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
787 return;
788 }
789
790 if (! (dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
791 printk("DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
792 return;
793 }
794
795 /* DBRI short pipes always transmit LSB first */
796
797 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
798 data = reverse_bytes(data, dbri->pipes[pipe].length);
799
800 cmd = dbri_cmdlock(dbri);
801
802 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
803 *(cmd++) = data;
804
805 dbri_cmdsend(dbri, cmd);
806 }
807
808 static void recv_fixed(struct dbri *dbri, int pipe, volatile __u32 *ptr)
809 {
810 if (pipe < 16 || pipe > 31) {
811 printk("DBRI: recv_fixed called with illegal pipe number\n");
812 return;
813 }
814
815 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
816 printk("DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
817 return;
818 }
819
820 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
821 printk("DBRI: recv_fixed called on transmit pipe %d\n", pipe);
822 return;
823 }
824
825 dbri->pipes[pipe].recv_fixed_ptr = ptr;
826 }
827
828
829 /* xmit_on_pipe() / recv_on_pipe()
830 *
831 * Transmit/receive data on a "long" pipe - i.e, one associated
832 * with a DMA buffer.
833 *
834 * Only pipe numbers 0-15 can be used in this mode.
835 *
836 * Both functions take pointer/len arguments pointing to a data buffer,
837 * and both provide callback functions (may be NULL) to notify higher
838 * level code when transmission/reception is complete.
839 *
840 * Both work by building chains of descriptors which identify the
841 * data buffers. Buffers too large for a single descriptor will
842 * be spread across multiple descriptors.
843 */
844 static void xmit_on_pipe(struct dbri *dbri, int pipe,
845 void * buffer, unsigned int len,
846 void (*callback)(void *, int), void * callback_arg)
847 {
848 volatile s32 *cmd;
849 unsigned long flags;
850 int td = 0;
851 int first_td = -1;
852 int last_td = -1;
853 __u32 dvma_buffer, dvma_buffer_base;
854
855 if (pipe < 0 || pipe > 15) {
856 printk("DBRI: xmit_on_pipe: Illegal pipe number\n");
857 return;
858 }
859
860 if (dbri->pipes[pipe].sdp == 0) {
861 printk("DBRI: xmit_on_pipe: Uninitialized pipe %d\n", pipe);
862 return;
863 }
864
865 if (! (dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
866 printk("DBRI: xmit_on_pipe: Called on receive pipe %d\n",
867 pipe);
868 return;
869 }
870
871 dvma_buffer_base = dvma_buffer = sbus_map_single(dbri->sdev, buffer, len,
872 SBUS_DMA_TODEVICE);
873 while (len > 0) {
874 int mylen;
875
876 for (; td < DBRI_NO_DESCS; td ++) {
877 if (! dbri->descs[td].inuse)
878 break;
879 }
880 if (td == DBRI_NO_DESCS) {
881 printk("DBRI: xmit_on_pipe: No descriptors\n");
882 break;
883 }
884
885 if (len > ((1 << 13) - 1)) {
886 mylen = (1 << 13) - 1;
887 } else {
888 mylen = len;
889 }
890
891 dbri->descs[td].inuse = 1;
892 dbri->descs[td].next = -1;
893 dbri->descs[td].buffer = NULL;
894 dbri->descs[td].output_callback = NULL;
895 dbri->descs[td].input_callback = NULL;
896
897 dbri->dma->desc[td].word1 = DBRI_TD_CNT(mylen);
898 dbri->dma->desc[td].ba = dvma_buffer;
899 dbri->dma->desc[td].nda = 0;
900 dbri->dma->desc[td].word4 = 0;
901
902 if (first_td == -1) {
903 first_td = td;
904 } else {
905 dbri->descs[last_td].next = td;
906 dbri->dma->desc[last_td].nda =
907 dbri->dma_dvma + dbri_dma_off(desc, td);
908 }
909
910 last_td = td;
911 dvma_buffer += mylen;
912 len -= mylen;
913 }
914
915 if (first_td == -1 || last_td == -1) {
916 sbus_unmap_single(dbri->sdev, dvma_buffer_base,
917 dvma_buffer - dvma_buffer_base + len,
918 SBUS_DMA_TODEVICE);
919 return;
920 }
921
922 dbri->dma->desc[last_td].word1 |= DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
923
924 dbri->descs[last_td].buffer = buffer;
925 dbri->descs[last_td].buffer_dvma = dvma_buffer_base;
926 dbri->descs[last_td].len = dvma_buffer - dvma_buffer_base + len;
927 dbri->descs[last_td].output_callback = callback;
928 dbri->descs[last_td].output_callback_arg = callback_arg;
929
930 for (td=first_td; td != -1; td = dbri->descs[td].next) {
931 dprintk(D_DESC, ("DBRI TD %d: %08x %08x %08x %08x\n",
932 td,
933 dbri->dma->desc[td].word1,
934 dbri->dma->desc[td].ba,
935 dbri->dma->desc[td].nda,
936 dbri->dma->desc[td].word4));
937 }
938
939 save_and_cli(flags);
940
941 if (pipe_active(dbri, pipe)) {
942 /* Pipe is already active - find last TD in use
943 * and link our first TD onto its end. Then issue
944 * a CDP command to let the DBRI know there's more data.
945 */
946 last_td = dbri->pipes[pipe].desc;
947 while (dbri->descs[last_td].next != -1)
948 last_td = dbri->descs[last_td].next;
949
950 dbri->descs[last_td].next = first_td;
951 dbri->dma->desc[last_td].nda =
952 dbri->dma_dvma + dbri_dma_off(desc, first_td);
953
954 cmd = dbri_cmdlock(dbri);
955 *(cmd++) = DBRI_CMD(D_CDP, 0, pipe);
956 dbri_cmdsend(dbri,cmd);
957 } else {
958 /* Pipe isn't active - issue an SDP command to start
959 * our chain of TDs running.
960 */
961 dbri->pipes[pipe].desc = first_td;
962 cmd = dbri_cmdlock(dbri);
963 *(cmd++) = DBRI_CMD(D_SDP, 0,
964 dbri->pipes[pipe].sdp
965 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
966 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
967 dbri_cmdsend(dbri, cmd);
968 }
969
970 restore_flags(flags);
971 }
972
973 static void recv_on_pipe(struct dbri *dbri, int pipe,
974 void * buffer, unsigned int len,
975 void (*callback)(void *, int, unsigned int),
976 void * callback_arg)
977 {
978 volatile s32 *cmd;
979 int first_rd = -1;
980 int last_rd = -1;
981 int rd;
982 __u32 bus_buffer, bus_buffer_base;
983
984 if (pipe < 0 || pipe > 15) {
985 printk("DBRI: recv_on_pipe: Illegal pipe number\n");
986 return;
987 }
988
989 if (dbri->pipes[pipe].sdp == 0) {
990 printk("DBRI: recv_on_pipe: Uninitialized pipe %d\n", pipe);
991 return;
992 }
993
994 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
995 printk("DBRI: recv_on_pipe: Called on transmit pipe %d\n",
996 pipe);
997 return;
998 }
999
1000 /* XXX Fix this XXX
1001 * Should be able to queue multiple buffers to receive on a pipe
1002 */
1003 if (dbri->pipes[pipe].desc != -1) {
1004 printk("DBRI: recv_on_pipe: Called on active pipe %d\n", pipe);
1005 return;
1006 }
1007
1008 /* Make sure buffer size is multiple of four */
1009 len &= ~3;
1010
1011 bus_buffer_base = bus_buffer = sbus_map_single(dbri->sdev, buffer, len,
1012 SBUS_DMA_FROMDEVICE);
1013
1014 while (len > 0) {
1015 int rd, mylen;
1016
1017 if (len > ((1 << 13) - 4)) {
1018 mylen = (1 << 13) - 4;
1019 } else {
1020 mylen = len;
1021 }
1022
1023 for (rd = 0; rd < DBRI_NO_DESCS; rd ++) {
1024 if (! dbri->descs[rd].inuse)
1025 break;
1026 }
1027 if (rd == DBRI_NO_DESCS) {
1028 printk("DBRI recv_on_pipe: No descriptors\n");
1029 break;
1030 }
1031
1032 dbri->dma->desc[rd].word1 = 0;
1033 dbri->dma->desc[rd].ba = bus_buffer;
1034 dbri->dma->desc[rd].nda = 0;
1035 dbri->dma->desc[rd].word4 = DBRI_RD_B | DBRI_RD_BCNT(mylen);
1036
1037 dbri->descs[rd].buffer = NULL;
1038 dbri->descs[rd].len = 0;
1039 dbri->descs[rd].input_callback = NULL;
1040 dbri->descs[rd].output_callback = NULL;
1041 dbri->descs[rd].next = -1;
1042 dbri->descs[rd].inuse = 1;
1043
1044 if (first_rd == -1) first_rd = rd;
1045 if (last_rd != -1) {
1046 dbri->dma->desc[last_rd].nda =
1047 dbri->dma_dvma + dbri_dma_off(desc, rd);
1048 dbri->descs[last_rd].next = rd;
1049 }
1050 last_rd = rd;
1051
1052 bus_buffer += mylen;
1053 len -= mylen;
1054 }
1055
1056 if (last_rd == -1 || first_rd == -1) {
1057 sbus_unmap_single(dbri->sdev, bus_buffer_base,
1058 bus_buffer - bus_buffer_base + len,
1059 SBUS_DMA_FROMDEVICE);
1060 return;
1061 }
1062
1063 for (rd=first_rd; rd != -1; rd = dbri->descs[rd].next) {
1064 dprintk(D_DESC, ("DBRI RD %d: %08x %08x %08x %08x\n",
1065 rd,
1066 dbri->dma->desc[rd].word1,
1067 dbri->dma->desc[rd].ba,
1068 dbri->dma->desc[rd].nda,
1069 dbri->dma->desc[rd].word4));
1070 }
1071
1072 dbri->descs[last_rd].buffer = buffer;
1073 dbri->descs[last_rd].buffer_dvma = bus_buffer_base;
1074 dbri->descs[last_rd].len = bus_buffer - bus_buffer_base + len;
1075 dbri->descs[last_rd].input_callback = callback;
1076 dbri->descs[last_rd].input_callback_arg = callback_arg;
1077
1078 dbri->pipes[pipe].desc = first_rd;
1079
1080 cmd = dbri_cmdlock(dbri);
1081
1082 *(cmd++) = DBRI_CMD(D_SDP, 0, dbri->pipes[pipe].sdp | D_SDP_P | D_SDP_C);
1083 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_rd);
1084
1085 dbri_cmdsend(dbri, cmd);
1086 }
1087
1088
1089 /*
1090 ****************************************************************************
1091 ************************** DBRI - CHI interface ****************************
1092 ****************************************************************************
1093
1094 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1095 multiplexed serial interface which the DBRI can operate in either master
1096 (give clock/frame sync) or slave (take clock/frame sync) mode.
1097
1098 */
1099
1100 enum master_or_slave { CHImaster, CHIslave };
1101
1102 static void reset_chi(struct dbri *dbri, enum master_or_slave master_or_slave,
1103 int bits_per_frame)
1104 {
1105 volatile s32 *cmd;
1106 int val;
1107 static int chi_initialized = 0;
1108
1109 if (!chi_initialized) {
1110
1111 cmd = dbri_cmdlock(dbri);
1112
1113 /* Set CHI Anchor: Pipe 16 */
1114
1115 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
1116 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1117 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1118 *(cmd++) = 0;
1119
1120 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
1121 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1122 *(cmd++) = 0;
1123 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1124
1125 dbri->pipes[16].sdp = 1;
1126 dbri->pipes[16].nextpipe = 16;
1127 dbri->chi_in_pipe = 16;
1128 dbri->chi_out_pipe = 16;
1129
1130 #if 0
1131 chi_initialized ++;
1132 #endif
1133 } else {
1134 int pipe;
1135
1136 for (pipe = dbri->chi_in_pipe;
1137 pipe != 16;
1138 pipe = dbri->pipes[pipe].nextpipe) {
1139 unlink_time_slot(dbri, pipe, PIPEinput,
1140 16, dbri->pipes[pipe].nextpipe);
1141 }
1142 for (pipe = dbri->chi_out_pipe;
1143 pipe != 16;
1144 pipe = dbri->pipes[pipe].nextpipe) {
1145 unlink_time_slot(dbri, pipe, PIPEoutput,
1146 16, dbri->pipes[pipe].nextpipe);
1147 }
1148
1149 dbri->chi_in_pipe = 16;
1150 dbri->chi_out_pipe = 16;
1151
1152 cmd = dbri_cmdlock(dbri);
1153 }
1154
1155 if (master_or_slave == CHIslave) {
1156 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1157 *
1158 * CHICM = 0 (slave mode, 8 kHz frame rate)
1159 * IR = give immediate CHI status interrupt
1160 * EN = give CHI status interrupt upon change
1161 */
1162 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1163 } else {
1164 /* Setup DBRI for CHI Master - generate clock, FS
1165 *
1166 * BPF = bits per 8 kHz frame
1167 * 12.288 MHz / CHICM_divisor = clock rate
1168 * FD = 1 - drive CHIFS on rising edge of CHICK
1169 */
1170 int clockrate = bits_per_frame * 8;
1171 int divisor = 12288 / clockrate;
1172
1173 if (divisor > 255 || divisor * clockrate != 12288)
1174 printk("DBRI: illegal bits_per_frame in setup_chi\n");
1175
1176 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1177 | D_CHI_BPF(bits_per_frame));
1178 }
1179
1180 dbri->chi_bpf = bits_per_frame;
1181
1182 /* CHI Data Mode
1183 *
1184 * RCE = 0 - receive on falling edge of CHICK
1185 * XCE = 1 - transmit on rising edge of CHICK
1186 * XEN = 1 - enable transmitter
1187 * REN = 1 - enable receiver
1188 */
1189
1190 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1191 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE|D_CDM_XEN|D_CDM_REN);
1192
1193 dbri_cmdsend(dbri, cmd);
1194 }
1195
1196 /*
1197 ****************************************************************************
1198 *********************** CS4215 audio codec management **********************
1199 ****************************************************************************
1200
1201 In the standard SPARC audio configuration, the CS4215 codec is attached
1202 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1203
1204 */
1205 static void mmcodec_default(struct cs4215 *mm)
1206 {
1207 /*
1208 * No action, memory resetting only.
1209 *
1210 * Data Time Slot 5-8
1211 * Speaker,Line and Headphone enable. Gain set to the half.
1212 * Input is mike.
1213 */
1214 mm->data[0] = CS4215_LO(0x20) | CS4215_HE|CS4215_LE;
1215 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1216 mm->data[2] = CS4215_LG( 0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1217 mm->data[3] = CS4215_RG( 0x8) | CS4215_MA(0xf);
1218
1219 /*
1220 * Control Time Slot 1-4
1221 * 0: Default I/O voltage scale
1222 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1223 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1224 * 3: Tests disabled
1225 */
1226 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1227 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1228 mm->ctrl[2] = CS4215_XCLK |
1229 CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1230 mm->ctrl[3] = 0;
1231 }
1232
1233 static void mmcodec_setup_pipes(struct dbri *dbri)
1234 {
1235 /*
1236 * Data mode:
1237 * Pipe 4: Send timeslots 1-4 (audio data)
1238 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1239 * Pipe 6: Receive timeslots 1-4 (audio data)
1240 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1241 * interrupt, and the rest of the data (slot 5 and 8) is
1242 * not relevant for us (only for doublechecking).
1243 *
1244 * Control mode:
1245 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1246 * Pipe 18: Receive timeslot 1 (clb).
1247 * Pipe 19: Receive timeslot 7 (version).
1248 */
1249
1250 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1251 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1252 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1253 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1254
1255 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1256 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1257 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1258
1259 dbri->mm.status = 0;
1260
1261 recv_fixed(dbri, 18, & dbri->mm.status);
1262 recv_fixed(dbri, 19, & dbri->mm.version);
1263 }
1264
1265 static void mmcodec_setgain(struct dbri *dbri, int muted)
1266 {
1267 if (muted || dbri->perchip_info.output_muted) {
1268 dbri->mm.data[0] = 63;
1269 dbri->mm.data[1] = 63;
1270 } else {
1271 int left_gain = (dbri->perchip_info.play.gain / 4) % 64;
1272 int right_gain = (dbri->perchip_info.play.gain / 4) % 64;
1273 int outport = dbri->perchip_info.play.port;
1274
1275 if (dbri->perchip_info.play.balance < AUDIO_MID_BALANCE) {
1276 right_gain *= dbri->perchip_info.play.balance;
1277 right_gain /= AUDIO_MID_BALANCE;
1278 } else {
1279 left_gain *= AUDIO_RIGHT_BALANCE
1280 - dbri->perchip_info.play.balance;
1281 left_gain /= AUDIO_MID_BALANCE;
1282 }
1283
1284 dprintk(D_MM, ("DBRI: Setting codec gain left: %d right: %d\n",
1285 left_gain, right_gain));
1286
1287 dbri->mm.data[0] = (63 - left_gain);
1288 if (outport & AUDIO_HEADPHONE) dbri->mm.data[0] |= CS4215_HE;
1289 if (outport & AUDIO_LINE_OUT) dbri->mm.data[0] |= CS4215_LE;
1290 dbri->mm.data[1] = (63 - right_gain);
1291 if (outport & AUDIO_SPEAKER) dbri->mm.data[1] |= CS4215_SE;
1292 }
1293
1294 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1295 }
1296
1297 static void mmcodec_init_data(struct dbri *dbri)
1298 {
1299 int data_width;
1300 u32 tmp;
1301
1302 /*
1303 * Data mode:
1304 * Pipe 4: Send timeslots 1-4 (audio data)
1305 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1306 * Pipe 6: Receive timeslots 1-4 (audio data)
1307 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1308 * interrupt, and the rest of the data (slot 5 and 8) is
1309 * not relevant for us (only for doublechecking).
1310 *
1311 * Just like in control mode, the time slots are all offset by eight
1312 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1313 * even if it's the CHI master. Don't ask me...
1314 */
1315 tmp = sbus_readl(dbri->regs + REG0);
1316 tmp &= ~(D_C); /* Disable CHI */
1317 sbus_writel(tmp, dbri->regs + REG0);
1318
1319 /* Switch CS4215 to data mode - set PIO3 to 1 */
1320 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1321 (dbri->mm.onboard ? D_PIO0 : D_PIO2),
1322 dbri->regs + REG2);
1323
1324 reset_chi(dbri, CHIslave, 128);
1325
1326 /* Note: this next doesn't work for 8-bit stereo, because the two
1327 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1328 * (See CS4215 datasheet Fig 15)
1329 *
1330 * DBRI non-contiguous mode would be required to make this work.
1331 */
1332
1333 data_width = dbri->perchip_info.play.channels
1334 * dbri->perchip_info.play.precision;
1335
1336 link_time_slot(dbri, 20, PIPEoutput, 16,
1337 32, dbri->mm.offset + 32);
1338 link_time_slot(dbri, 4, PIPEoutput, 16,
1339 data_width, dbri->mm.offset);
1340 link_time_slot(dbri, 6, PIPEinput, 16,
1341 data_width, dbri->mm.offset);
1342 link_time_slot(dbri, 21, PIPEinput, 16,
1343 16, dbri->mm.offset + 40);
1344
1345 mmcodec_setgain(dbri, 0);
1346
1347 tmp = sbus_readl(dbri->regs + REG0);
1348 tmp |= D_C; /* Enable CHI */
1349 sbus_writel(tmp, dbri->regs + REG0);
1350 }
1351
1352 /*
1353 * Send the control information (i.e. audio format)
1354 */
1355 static int mmcodec_setctrl(struct dbri *dbri)
1356 {
1357 int i, val;
1358 u32 tmp;
1359
1360 /* XXX - let the CPU do something useful during these delays */
1361
1362 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1363 * to make sure this takes. This avoids clicking noises.
1364 */
1365
1366 mmcodec_setgain(dbri, 1);
1367 udelay(125);
1368
1369 /*
1370 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1371 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1372 */
1373 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1374 sbus_writel(val, dbri->regs + REG2);
1375 udelay(34);
1376
1377 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1378 * operate as CHI master, supplying clocking and frame synchronization.
1379 *
1380 * In Data mode, however, the CS4215 must be CHI master to insure
1381 * that its data stream is synchronous with its codec.
1382 *
1383 * The upshot of all this? We start by putting the DBRI into master
1384 * mode, program the CS4215 in Control mode, then switch the CS4215
1385 * into Data mode and put the DBRI into slave mode. Various timing
1386 * requirements must be observed along the way.
1387 *
1388 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1389 * others?), the addressing of the CS4215's time slots is
1390 * offset by eight bits, so we add eight to all the "cycle"
1391 * values in the Define Time Slot (DTS) commands. This is
1392 * done in hardware by a TI 248 that delays the DBRI->4215
1393 * frame sync signal by eight clock cycles. Anybody know why?
1394 */
1395 tmp = sbus_readl(dbri->regs + REG0);
1396 tmp &= ~D_C; /* Disable CHI */
1397 sbus_writel(tmp, dbri->regs + REG0);
1398
1399 reset_chi(dbri, CHImaster, 128);
1400
1401 /*
1402 * Control mode:
1403 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1404 * Pipe 18: Receive timeslot 1 (clb).
1405 * Pipe 19: Receive timeslot 7 (version).
1406 */
1407
1408 link_time_slot(dbri, 17, PIPEoutput, 16,
1409 32, dbri->mm.offset);
1410 link_time_slot(dbri, 18, PIPEinput, 16,
1411 8, dbri->mm.offset);
1412 link_time_slot(dbri, 19, PIPEinput, 16,
1413 8, dbri->mm.offset + 48);
1414
1415 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1416
1417 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1418 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1419
1420 tmp = sbus_readl(dbri->regs + REG0);
1421 tmp |= D_C; /* Enable CHI */
1422 sbus_writel(tmp, dbri->regs + REG0);
1423
1424 i = 64;
1425 while (((dbri->mm.status & 0xe4) != 0x20) && --i)
1426 udelay(125);
1427 if (i == 0) {
1428 dprintk(D_MM, ("DBRI: CS4215 didn't respond to CLB (0x%02x)\n",
1429 dbri->mm.status));
1430 return -1;
1431 }
1432
1433 /* Terminate CS4215 control mode - data sheet says
1434 * "Set CLB=1 and send two more frames of valid control info"
1435 */
1436 dbri->mm.ctrl[0] |= CS4215_CLB;
1437 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1438
1439 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1440 udelay(250);
1441
1442 mmcodec_setgain(dbri, 0);
1443
1444 return 0;
1445 }
1446
1447 static int mmcodec_init(struct sparcaudio_driver *drv)
1448 {
1449 struct dbri *dbri = (struct dbri *) drv->private;
1450 u32 reg2 = sbus_readl(dbri->regs + REG2);
1451
1452 /* Look for the cs4215 chips */
1453 if(reg2 & D_PIO2) {
1454 dprintk(D_MM, ("DBRI: Onboard CS4215 detected\n"));
1455 dbri->mm.onboard = 1;
1456 }
1457 if(reg2 & D_PIO0) {
1458 dprintk(D_MM, ("DBRI: Speakerbox detected\n"));
1459 dbri->mm.onboard = 0;
1460 }
1461
1462
1463 /* Using the Speakerbox, if both are attached. */
1464 if((reg2 & D_PIO2) && (reg2 & D_PIO0)) {
1465 printk("DBRI: Using speakerbox / ignoring onboard mmcodec.\n");
1466 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1467 dbri->mm.onboard = 0;
1468 }
1469
1470 if(!(reg2 & (D_PIO0|D_PIO2))) {
1471 printk("DBRI: no mmcodec found.\n");
1472 return -EIO;
1473 }
1474
1475
1476 mmcodec_setup_pipes(dbri);
1477
1478 mmcodec_default(&dbri->mm);
1479
1480 dbri->mm.version = 0xff;
1481 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1482 if (mmcodec_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1483 dprintk(D_MM, ("DBRI: CS4215 failed probe at offset %d\n",
1484 dbri->mm.offset));
1485 return -EIO;
1486 }
1487
1488 dprintk(D_MM, ("DBRI: Found CS4215 at offset %d\n", dbri->mm.offset));
1489
1490 dbri->perchip_info.play.channels = 1;
1491 dbri->perchip_info.play.precision = 8;
1492 dbri->perchip_info.play.gain = (AUDIO_MAX_GAIN * 7 / 10); /* 70% */
1493 dbri->perchip_info.play.balance = AUDIO_MID_BALANCE;
1494 dbri->perchip_info.play.port = dbri->perchip_info.play.avail_ports =
1495 AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
1496 dbri->perchip_info.record.port = AUDIO_MICROPHONE;
1497 dbri->perchip_info.record.avail_ports =
1498 AUDIO_MICROPHONE | AUDIO_LINE_IN;
1499
1500 mmcodec_init_data(dbri);
1501
1502 return 0;
1503 }
1504
1505
1506 /*
1507 ****************************************************************************
1508 ******************** Interface with sparcaudio midlevel ********************
1509 ****************************************************************************
1510
1511 The sparcaudio midlevel is contained in the file audio.c. It interfaces
1512 to the user process and performs buffering, intercepts SunOS-style ioctl's,
1513 etc. It interfaces to a abstract audio device via a struct sparcaudio_driver.
1514 This code presents such an interface for the DBRI with an attached CS4215.
1515 All our routines are defined, and then comes our struct sparcaudio_driver.
1516
1517 */
1518
1519 /******************* sparcaudio midlevel - audio output *******************/
1520 static void dbri_audio_output_callback(void * callback_arg, int status)
1521 {
1522 struct sparcaudio_driver *drv = callback_arg;
1523
1524 if (status != -1)
1525 sparcaudio_output_done(drv, 1);
1526 }
1527
1528 static void dbri_start_output(struct sparcaudio_driver *drv,
1529 __u8 * buffer, unsigned long count)
1530 {
1531 struct dbri *dbri = (struct dbri *) drv->private;
1532
1533 dprintk(D_USR, ("DBRI: start audio output buf=%p/%ld\n",
1534 buffer, count));
1535
1536 /* Pipe 4 is audio transmit */
1537 xmit_on_pipe(dbri, 4, buffer, count,
1538 &dbri_audio_output_callback, drv);
1539
1540 #if 0
1541 /* Notify midlevel that we're a DMA-capable driver that
1542 * can accept another buffer immediately. We should probably
1543 * check that we've got enough resources (i.e, descriptors)
1544 * available before doing this, but the default midlevel
1545 * settings only buffer 64KB, which we can handle with 16
1546 * of our DBRI_NO_DESCS (64) descriptors.
1547 *
1548 * This code is #ifdef'ed out because it's caused me more
1549 * problems than it solved. It'd be nice to provide the
1550 * DBRI with a chain of buffers, but the midlevel code is
1551 * so tricky that I really don't want to deal with it.
1552 */
1553
1554 sparcaudio_output_done(drv, 2);
1555 #endif
1556 }
1557
1558 static void dbri_stop_output(struct sparcaudio_driver *drv)
1559 {
1560 struct dbri *dbri = (struct dbri *) drv->private;
1561
1562 reset_pipe(dbri, 4);
1563 }
1564
1565 /******************* sparcaudio midlevel - audio input ********************/
1566
1567 static void dbri_audio_input_callback(void * callback_arg, int status,
1568 unsigned int len)
1569 {
1570 struct sparcaudio_driver * drv =
1571 (struct sparcaudio_driver *) callback_arg;
1572
1573 if (status != -1)
1574 sparcaudio_input_done(drv, 3);
1575 }
1576
1577 static void dbri_start_input(struct sparcaudio_driver *drv,
1578 __u8 * buffer, unsigned long len)
1579 {
1580 struct dbri *dbri = (struct dbri *) drv->private;
1581
1582 /* Pipe 6 is audio receive */
1583 recv_on_pipe(dbri, 6, buffer, len,
1584 &dbri_audio_input_callback, (void *)drv);
1585 dprintk(D_USR, ("DBRI: start audio input buf=%p/%ld\n",
1586 buffer, len));
1587 }
1588
1589 static void dbri_stop_input(struct sparcaudio_driver *drv)
1590 {
1591 struct dbri *dbri = (struct dbri *) drv->private;
1592
1593 reset_pipe(dbri, 6);
1594 }
1595
1596 /******************* sparcaudio midlevel - volume & balance ***************/
1597
1598 static int dbri_set_output_volume(struct sparcaudio_driver *drv, int volume)
1599 {
1600 struct dbri *dbri = (struct dbri *) drv->private;
1601
1602 dbri->perchip_info.play.gain = volume;
1603 mmcodec_setgain(dbri, 0);
1604
1605 return 0;
1606 }
1607
1608 static int dbri_get_output_volume(struct sparcaudio_driver *drv)
1609 {
1610 struct dbri *dbri = (struct dbri *) drv->private;
1611
1612 return dbri->perchip_info.play.gain;
1613 }
1614
1615 static int dbri_set_input_volume(struct sparcaudio_driver *drv, int volume)
1616 {
1617 return 0;
1618 }
1619
1620 static int dbri_get_input_volume(struct sparcaudio_driver *drv)
1621 {
1622 return 0;
1623 }
1624
1625 static int dbri_set_monitor_volume(struct sparcaudio_driver *drv, int volume)
1626 {
1627 return 0;
1628 }
1629
1630 static int dbri_get_monitor_volume(struct sparcaudio_driver *drv)
1631 {
1632 return 0;
1633 }
1634
1635 static int dbri_set_output_balance(struct sparcaudio_driver *drv, int balance)
1636 {
1637 struct dbri *dbri = (struct dbri *) drv->private;
1638
1639 dbri->perchip_info.play.balance = balance;
1640 mmcodec_setgain(dbri, 0);
1641
1642 return 0;
1643 }
1644
1645 static int dbri_get_output_balance(struct sparcaudio_driver *drv)
1646 {
1647 struct dbri *dbri = (struct dbri *) drv->private;
1648
1649 return dbri->perchip_info.play.balance;
1650 }
1651
1652 static int dbri_set_input_balance(struct sparcaudio_driver *drv, int balance)
1653 {
1654 return 0;
1655 }
1656
1657 static int dbri_get_input_balance(struct sparcaudio_driver *drv)
1658 {
1659 return 0;
1660 }
1661
1662 static int dbri_set_output_muted(struct sparcaudio_driver *drv, int mute)
1663 {
1664 struct dbri *dbri = (struct dbri *) drv->private;
1665
1666 dbri->perchip_info.output_muted = mute;
1667
1668 return 0;
1669 }
1670
1671 static int dbri_get_output_muted(struct sparcaudio_driver *drv)
1672 {
1673 struct dbri *dbri = (struct dbri *) drv->private;
1674
1675 return dbri->perchip_info.output_muted;
1676 }
1677
1678 /******************* sparcaudio midlevel - encoding format ****************/
1679
1680 static int dbri_set_output_channels(struct sparcaudio_driver *drv, int chan)
1681 {
1682 struct dbri *dbri = (struct dbri *) drv->private;
1683
1684 switch (chan) {
1685 case 0:
1686 return 0;
1687 case 1:
1688 dbri->mm.ctrl[1] &= ~CS4215_DFR_STEREO;
1689 break;
1690 case 2:
1691 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1692 break;
1693 default:
1694 return -1;
1695 }
1696
1697 dbri->perchip_info.play.channels = chan;
1698 mmcodec_setctrl(dbri);
1699 mmcodec_init_data(dbri);
1700 return 0;
1701 }
1702
1703 static int dbri_get_output_channels(struct sparcaudio_driver *drv)
1704 {
1705 struct dbri *dbri = (struct dbri *) drv->private;
1706
1707 return dbri->perchip_info.play.channels;
1708 }
1709
1710 static int dbri_set_input_channels(struct sparcaudio_driver *drv, int chan)
1711 {
1712 return dbri_set_output_channels(drv, chan);
1713 }
1714
1715 static int dbri_get_input_channels(struct sparcaudio_driver *drv)
1716 {
1717 return dbri_get_output_channels(drv);
1718 }
1719
1720 static int dbri_set_output_precision(struct sparcaudio_driver *drv, int prec)
1721 {
1722 return 0;
1723 }
1724
1725 static int dbri_get_output_precision(struct sparcaudio_driver *drv)
1726 {
1727 struct dbri *dbri = (struct dbri *) drv->private;
1728
1729 return dbri->perchip_info.play.precision;
1730 }
1731
1732 static int dbri_set_input_precision(struct sparcaudio_driver *drv, int prec)
1733 {
1734 return 0;
1735 }
1736
1737 static int dbri_get_input_precision(struct sparcaudio_driver *drv)
1738 {
1739 struct dbri *dbri = (struct dbri *) drv->private;
1740
1741 return dbri->perchip_info.play.precision;
1742 }
1743
1744 static int dbri_set_output_encoding(struct sparcaudio_driver *drv, int enc)
1745 {
1746 struct dbri *dbri = (struct dbri *) drv->private;
1747
1748 /* For ULAW and ALAW, audio.c enforces precision = 8,
1749 * for LINEAR, precision must be 16
1750 */
1751
1752 switch (enc) {
1753 case AUDIO_ENCODING_NONE:
1754 return 0;
1755 case AUDIO_ENCODING_ULAW:
1756 dbri->mm.ctrl[1] &= ~3;
1757 dbri->mm.ctrl[1] |= CS4215_DFR_ULAW;
1758 dbri->perchip_info.play.encoding = enc;
1759 dbri->perchip_info.play.precision = 8;
1760 break;
1761 case AUDIO_ENCODING_ALAW:
1762 dbri->mm.ctrl[1] &= ~3;
1763 dbri->mm.ctrl[1] |= CS4215_DFR_ALAW;
1764 dbri->perchip_info.play.encoding = enc;
1765 dbri->perchip_info.play.precision = 8;
1766 break;
1767 case AUDIO_ENCODING_LINEAR:
1768 dbri->mm.ctrl[1] &= ~3;
1769 dbri->mm.ctrl[1] |= CS4215_DFR_LINEAR16;
1770 dbri->perchip_info.play.encoding = enc;
1771 dbri->perchip_info.play.precision = 16;
1772 break;
1773 default:
1774 return -1;
1775 };
1776
1777 mmcodec_setctrl(dbri);
1778 mmcodec_init_data(dbri);
1779 return 0;
1780 }
1781
1782 static int dbri_get_output_encoding(struct sparcaudio_driver *drv)
1783 {
1784 struct dbri *dbri = (struct dbri *) drv->private;
1785
1786 return dbri->perchip_info.play.encoding;
1787 }
1788
1789 static int dbri_set_input_encoding(struct sparcaudio_driver *drv, int enc)
1790 {
1791 return dbri_set_output_encoding(drv, enc);
1792 }
1793
1794 static int dbri_get_input_encoding(struct sparcaudio_driver *drv)
1795 {
1796 return dbri_get_output_encoding(drv);
1797 }
1798
1799 static int dbri_set_output_rate(struct sparcaudio_driver *drv, int rate)
1800 {
1801 struct dbri *dbri = (struct dbri *) drv->private;
1802 int i;
1803
1804 if (rate == 0)
1805 return 0;
1806
1807 for (i=0; CS4215_FREQ[i].freq; i++) {
1808 if (CS4215_FREQ[i].freq == rate)
1809 break;
1810 }
1811
1812 if (CS4215_FREQ[i].freq == 0)
1813 return -1;
1814
1815 dbri->mm.ctrl[1] &= ~ 0x38;
1816 dbri->mm.ctrl[1] |= CS4215_FREQ[i].csval;
1817 dbri->mm.ctrl[2] &= ~ 0x70;
1818 dbri->mm.ctrl[2] |= CS4215_FREQ[i].xtal;
1819
1820 dbri->perchip_info.play.sample_rate = rate;
1821
1822 mmcodec_setctrl(dbri);
1823 mmcodec_init_data(dbri);
1824 return 0;
1825 }
1826
1827 static int dbri_get_output_rate(struct sparcaudio_driver *drv)
1828 {
1829 struct dbri *dbri = (struct dbri *) drv->private;
1830
1831 return dbri->perchip_info.play.sample_rate;
1832 }
1833
1834 static int dbri_set_input_rate(struct sparcaudio_driver *drv, int rate)
1835 {
1836 return dbri_set_output_rate(drv, rate);
1837 }
1838
1839 static int dbri_get_input_rate(struct sparcaudio_driver *drv)
1840 {
1841 return dbri_get_output_rate(drv);
1842 }
1843
1844 /******************* sparcaudio midlevel - ports ***********************/
1845
1846 static int dbri_set_output_port(struct sparcaudio_driver *drv, int port)
1847 {
1848 struct dbri *dbri = (struct dbri *) drv->private;
1849
1850 port &= dbri->perchip_info.play.avail_ports;
1851 dbri->perchip_info.play.port = port;
1852 mmcodec_setgain(dbri, 0);
1853
1854 return 0;
1855 }
1856
1857 static int dbri_get_output_port(struct sparcaudio_driver *drv)
1858 {
1859 struct dbri *dbri = (struct dbri *) drv->private;
1860
1861 return dbri->perchip_info.play.port;
1862 }
1863
1864 static int dbri_set_input_port(struct sparcaudio_driver *drv, int port)
1865 {
1866 struct dbri *dbri = (struct dbri *) drv->private;
1867
1868 port &= dbri->perchip_info.record.avail_ports;
1869 dbri->perchip_info.record.port = port;
1870 mmcodec_setgain(dbri, 0);
1871
1872 return 0;
1873 }
1874
1875 static int dbri_get_input_port(struct sparcaudio_driver *drv)
1876 {
1877 struct dbri *dbri = (struct dbri *) drv->private;
1878
1879 return dbri->perchip_info.record.port;
1880 }
1881
1882 static int dbri_get_output_ports(struct sparcaudio_driver *drv)
1883 {
1884 struct dbri *dbri = (struct dbri *) drv->private;
1885
1886 return dbri->perchip_info.play.avail_ports;
1887 }
1888
1889 static int dbri_get_input_ports(struct sparcaudio_driver *drv)
1890 {
1891 struct dbri *dbri = (struct dbri *) drv->private;
1892
1893 return dbri->perchip_info.record.avail_ports;
1894 }
1895
1896 /******************* sparcaudio midlevel - driver ID ********************/
1897
1898 static void dbri_audio_getdev(struct sparcaudio_driver *drv,
1899 audio_device_t *audinfo)
1900 {
1901 struct dbri *dbri = (struct dbri *) drv->private;
1902
1903 strncpy(audinfo->name, "SUNW,DBRI", sizeof(audinfo->name) - 1);
1904
1905 audinfo->version[0] = dbri->dbri_version;
1906 audinfo->version[1] = '\0';
1907
1908 strncpy(audinfo->config, "onboard1", sizeof(audinfo->config) - 1);
1909 }
1910
1911 static int dbri_sunaudio_getdev_sunos(struct sparcaudio_driver *drv)
1912 {
1913 return AUDIO_DEV_CODEC;
1914 }
1915
1916 /******************* sparcaudio midlevel - open & close ******************/
1917
1918 static int dbri_open(struct inode * inode, struct file * file,
1919 struct sparcaudio_driver *drv)
1920 {
1921 MOD_INC_USE_COUNT;
1922
1923 return 0;
1924 }
1925
1926 static void dbri_release(struct inode * inode, struct file * file,
1927 struct sparcaudio_driver *drv)
1928 {
1929 MOD_DEC_USE_COUNT;
1930 }
1931
1932 static int dbri_ioctl(struct inode * inode, struct file * file,
1933 unsigned int x, unsigned long y,
1934 struct sparcaudio_driver *drv)
1935 {
1936 return -EINVAL;
1937 }
1938
1939 /*********** sparcaudio midlevel - struct sparcaudio_driver ************/
1940
1941 static struct sparcaudio_operations dbri_ops = {
1942 dbri_open,
1943 dbri_release,
1944 dbri_ioctl,
1945 dbri_start_output,
1946 dbri_stop_output,
1947 dbri_start_input,
1948 dbri_stop_input,
1949 dbri_audio_getdev,
1950 dbri_set_output_volume,
1951 dbri_get_output_volume,
1952 dbri_set_input_volume,
1953 dbri_get_input_volume,
1954 dbri_set_monitor_volume,
1955 dbri_get_monitor_volume,
1956 dbri_set_output_balance,
1957 dbri_get_output_balance,
1958 dbri_set_input_balance,
1959 dbri_get_input_balance,
1960 dbri_set_output_channels,
1961 dbri_get_output_channels,
1962 dbri_set_input_channels,
1963 dbri_get_input_channels,
1964 dbri_set_output_precision,
1965 dbri_get_output_precision,
1966 dbri_set_input_precision,
1967 dbri_get_input_precision,
1968 dbri_set_output_port,
1969 dbri_get_output_port,
1970 dbri_set_input_port,
1971 dbri_get_input_port,
1972 dbri_set_output_encoding,
1973 dbri_get_output_encoding,
1974 dbri_set_input_encoding,
1975 dbri_get_input_encoding,
1976 dbri_set_output_rate,
1977 dbri_get_output_rate,
1978 dbri_set_input_rate,
1979 dbri_get_input_rate,
1980 dbri_sunaudio_getdev_sunos,
1981 dbri_get_output_ports,
1982 dbri_get_input_ports,
1983 dbri_set_output_muted,
1984 dbri_get_output_muted,
1985 };
1986
1987
1988 /*
1989 ****************************************************************************
1990 ************************** ISDN (Hisax) Interface **************************
1991 ****************************************************************************
1992 */
1993 void dbri_isdn_init(struct dbri *dbri)
1994 {
1995 /* Pipe 0: Receive D channel
1996 * Pipe 8: Receive B1 channel
1997 * Pipe 9: Receive B2 channel
1998 * Pipe 1: Transmit D channel
1999 * Pipe 10: Transmit B1 channel
2000 * Pipe 11: Transmit B2 channel
2001 */
2002
2003 setup_pipe(dbri, 0, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
2004 setup_pipe(dbri, 8, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
2005 setup_pipe(dbri, 9, D_SDP_HDLC | D_SDP_FROM_SER | D_SDP_LSB);
2006
2007 setup_pipe(dbri, 1, D_SDP_HDLC_D | D_SDP_TO_SER | D_SDP_LSB);
2008 setup_pipe(dbri,10, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
2009 setup_pipe(dbri,11, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
2010
2011 link_time_slot(dbri, 0, PIPEinput, 0, 2, 17);
2012 link_time_slot(dbri, 8, PIPEinput, 0, 8, 0);
2013 link_time_slot(dbri, 9, PIPEinput, 8, 8, 8);
2014
2015 link_time_slot(dbri, 1, PIPEoutput, 1, 2, 17);
2016 link_time_slot(dbri, 10, PIPEoutput, 1, 8, 0);
2017 link_time_slot(dbri, 11, PIPEoutput, 10, 8, 8);
2018 }
2019
2020 int dbri_get_irqnum(int dev)
2021 {
2022 struct dbri *dbri;
2023
2024 if (dev >= num_drivers)
2025 return(0);
2026
2027 dbri = (struct dbri *) drivers[dev].private;
2028
2029 tprintk(("dbri_get_irqnum()\n"));
2030
2031 /* On the sparc, the cpu's irq number is only part of the "irq" */
2032 return (dbri->irq & NR_IRQS);
2033 }
2034
2035 int dbri_get_liu_state(int dev)
2036 {
2037 struct dbri *dbri;
2038
2039 if (dev >= num_drivers)
2040 return(0);
2041
2042 dbri = (struct dbri *) drivers[dev].private;
2043
2044 tprintk(("dbri_get_liu_state() returns %d\n", dbri->liu_state));
2045
2046 return dbri->liu_state;
2047 }
2048
2049 void dbri_liu_activate(int dev, int priority);
2050
2051 void dbri_liu_init(int dev, void (*callback)(void *), void *callback_arg)
2052 {
2053 struct dbri *dbri;
2054
2055 if (dev >= num_drivers)
2056 return;
2057
2058 dbri = (struct dbri *) drivers[dev].private;
2059
2060 tprintk(("dbri_liu_init()\n"));
2061
2062 /* Set callback for LIU state change */
2063 dbri->liu_callback = callback;
2064 dbri->liu_callback_arg = callback_arg;
2065
2066 dbri_isdn_init(dbri);
2067 dbri_liu_activate(dev, 0);
2068 }
2069
2070 void dbri_liu_activate(int dev, int priority)
2071 {
2072 struct dbri *dbri;
2073 int val;
2074 volatile s32 *cmd;
2075
2076 if (dev >= num_drivers)
2077 return;
2078
2079 dbri = (struct dbri *) drivers[dev].private;
2080
2081 tprintk(("dbri_liu_activate()\n"));
2082
2083 if (dbri->liu_state <= 3) {
2084 u32 tmp;
2085
2086 cmd = dbri_cmdlock(dbri);
2087
2088 /* Turn on the ISDN TE interface and request activation */
2089 val = D_NT_IRM_IMM | D_NT_IRM_EN | D_NT_ACT;
2090 #ifdef LOOPBACK_D
2091 val |= D_NT_LLB(4);
2092 #endif
2093 *(cmd++) = DBRI_CMD(D_TE, 0, val);
2094
2095 dbri_cmdsend(dbri, cmd);
2096
2097 /* Activate the interface */
2098 tmp = sbus_readl(dbri->regs + REG0);
2099 tmp |= D_T;
2100 sbus_writel(tmp, dbri->regs + REG0);
2101 }
2102 }
2103
2104 void dbri_liu_deactivate(int dev)
2105 {
2106 struct dbri *dbri;
2107 #if 0
2108 u32 tmp;
2109 #endif
2110
2111 if (dev >= num_drivers)
2112 return;
2113
2114 dbri = (struct dbri *) drivers[dev].private;
2115
2116 tprintk(("dbri_liu_deactivate()\n"));
2117
2118 #if 0
2119 /* Turn off the ISDN TE interface */
2120 tmp = sbus_readl(dbri->regs + REG0);
2121 tmp &= ~D_T;
2122 sbus_writel(tmp, dbri->regs + REG0);
2123
2124 dbri->liu_state = 0;
2125 #endif
2126 }
2127
2128 void dbri_dxmit(int dev, __u8 *buffer, unsigned int count,
2129 void (*callback)(void *, int), void *callback_arg)
2130 {
2131 struct dbri *dbri;
2132
2133 if (dev >= num_drivers)
2134 return;
2135
2136 dbri = (struct dbri *) drivers[dev].private;
2137
2138 /* Pipe 1 is D channel transmit */
2139 xmit_on_pipe(dbri, 1, buffer, count, callback, callback_arg);
2140 }
2141
2142 void dbri_drecv(int dev, __u8 *buffer, unsigned int size,
2143 void (*callback)(void *, int, unsigned int),
2144 void *callback_arg)
2145 {
2146 struct dbri *dbri;
2147
2148 if (dev >= num_drivers)
2149 return;
2150
2151 dbri = (struct dbri *) drivers[dev].private;
2152
2153 /* Pipe 0 is D channel receive */
2154 recv_on_pipe(dbri, 0, buffer, size, callback, callback_arg);
2155 }
2156
2157 int dbri_bopen(int dev, unsigned int chan,
2158 int hdlcmode, u_char xmit_idle_char)
2159 {
2160 struct dbri *dbri;
2161
2162 if (dev >= num_drivers || chan > 1)
2163 return -1;
2164
2165 dbri = (struct dbri *) drivers[dev].private;
2166
2167 if (hdlcmode) {
2168 /* return -1; */
2169
2170 /* Pipe 8/9: receive B1/B2 channel */
2171 setup_pipe(dbri, 8+chan, D_SDP_HDLC | D_SDP_FROM_SER|D_SDP_LSB);
2172
2173 /* Pipe 10/11: transmit B1/B2 channel */
2174 setup_pipe(dbri,10+chan, D_SDP_HDLC | D_SDP_TO_SER | D_SDP_LSB);
2175 } else { /* !hdlcmode means transparent */
2176 /* Pipe 8/9: receive B1/B2 channel */
2177 setup_pipe(dbri, 8+chan, D_SDP_MEM | D_SDP_FROM_SER|D_SDP_LSB);
2178
2179 /* Pipe 10/11: transmit B1/B2 channel */
2180 setup_pipe(dbri,10+chan, D_SDP_MEM | D_SDP_TO_SER | D_SDP_LSB);
2181 }
2182 return 0;
2183 }
2184
2185 void dbri_bclose(int dev, unsigned int chan)
2186 {
2187 struct dbri *dbri;
2188
2189 if (dev >= num_drivers || chan > 1)
2190 return;
2191
2192 dbri = (struct dbri *) drivers[dev].private;
2193
2194 reset_pipe(dbri, 8+chan);
2195 reset_pipe(dbri, 10+chan);
2196 }
2197
2198 void dbri_bxmit(int dev, unsigned int chan,
2199 __u8 *buffer, unsigned long count,
2200 void (*callback)(void *, int),
2201 void *callback_arg)
2202 {
2203 struct dbri *dbri;
2204
2205 if (dev >= num_drivers || chan > 1)
2206 return;
2207
2208 dbri = (struct dbri *) drivers[dev].private;
2209
2210 /* Pipe 10/11 is B1/B2 channel transmit */
2211 xmit_on_pipe(dbri, 10+chan, buffer, count, callback, callback_arg);
2212 }
2213
2214 void dbri_brecv(int dev, unsigned int chan,
2215 __u8 *buffer, unsigned long size,
2216 void (*callback)(void *, int, unsigned int),
2217 void *callback_arg)
2218 {
2219 struct dbri *dbri;
2220
2221 if (dev >= num_drivers || chan > 1)
2222 return;
2223
2224 dbri = (struct dbri *) drivers[dev].private;
2225
2226 /* Pipe 8/9 is B1/B2 channel receive */
2227 recv_on_pipe(dbri, 8+chan, buffer, size, callback, callback_arg);
2228 }
2229
2230 #if defined(DBRI_ISDN)
2231 struct foreign_interface dbri_foreign_interface = {
2232 dbri_get_irqnum,
2233 dbri_get_liu_state,
2234 dbri_liu_init,
2235 dbri_liu_activate,
2236 dbri_liu_deactivate,
2237 dbri_dxmit,
2238 dbri_drecv,
2239 dbri_bopen,
2240 dbri_bclose,
2241 dbri_bxmit,
2242 dbri_brecv
2243 };
2244 EXPORT_SYMBOL(dbri_foreign_interface);
2245 #endif
2246
2247 /*
2248 ****************************************************************************
2249 **************************** Initialization ********************************
2250 ****************************************************************************
2251 */
2252
2253 static int dbri_attach(struct sparcaudio_driver *drv,
2254 struct sbus_dev *sdev)
2255 {
2256 struct dbri *dbri;
2257 struct linux_prom_irqs irq;
2258 int err;
2259
2260 if (sdev->prom_name[9] < 'e') {
2261 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2262 sdev->prom_name[9]);
2263 return -EIO;
2264 }
2265
2266 drv->ops = &dbri_ops;
2267 drv->private = kmalloc(sizeof(struct dbri), GFP_KERNEL);
2268 if (drv->private == NULL)
2269 return -ENOMEM;
2270
2271 dbri = (struct dbri *) drv->private;
2272 memset(dbri, 0, sizeof(*dbri));
2273
2274 dbri->dma = sbus_alloc_consistent(sdev,
2275 sizeof(struct dbri_dma),
2276 &dbri->dma_dvma);
2277
2278 memset((void *) dbri->dma, 0, sizeof(struct dbri_dma));
2279
2280 dprintk(D_GEN, ("DBRI: DMA Cmd Block 0x%p (0x%08x)\n",
2281 dbri->dma, dbri->dma_dvma));
2282
2283 dbri->dbri_version = sdev->prom_name[9];
2284 dbri->sdev = sdev;
2285
2286 /* Map the registers into memory. */
2287 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2288 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2289 sdev->reg_addrs[0].reg_size,
2290 "DBRI Registers");
2291 if (!dbri->regs) {
2292 printk(KERN_ERR "DBRI: could not allocate registers\n");
2293 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2294 (void *)dbri->dma, dbri->dma_dvma);
2295 kfree(drv->private);
2296 return -EIO;
2297 }
2298
2299 prom_getproperty(sdev->prom_node, "intr", (char *)&irq, sizeof(irq));
2300 dbri->irq = irq.pri;
2301
2302 err = request_irq(dbri->irq, dbri_intr, SA_SHIRQ,
2303 "DBRI audio/ISDN", dbri);
2304 if (err) {
2305 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2306 sbus_iounmap(dbri->regs, dbri->regs_size);
2307 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2308 (void *)dbri->dma, dbri->dma_dvma);
2309 kfree(drv->private);
2310 return err;
2311 }
2312
2313 dbri_initialize(dbri);
2314 err = mmcodec_init(drv);
2315 if(err) {
2316 dbri_detach(dbri);
2317 return err;
2318 }
2319
2320 /* Register ourselves with the midlevel audio driver. */
2321 err = register_sparcaudio_driver(drv,1);
2322 if (err) {
2323 printk(KERN_ERR "DBRI: unable to register audio\n");
2324 dbri_detach(dbri);
2325 return err;
2326 }
2327
2328 dbri->perchip_info.play.active = dbri->perchip_info.play.pause = 0;
2329 dbri->perchip_info.record.active = dbri->perchip_info.record.pause = 0;
2330
2331 printk(KERN_INFO "audio%d at 0x%lx (irq %d) is DBRI(%c)+CS4215(%d)\n",
2332 num_drivers, dbri->regs,
2333 dbri->irq, dbri->dbri_version, dbri->mm.version);
2334
2335 return 0;
2336 }
2337
2338 /* Probe for the dbri chip and then attach the driver. */
2339 static int __init dbri_init(void)
2340 {
2341 struct sbus_bus *sbus;
2342 struct sbus_dev *sdev;
2343
2344 num_drivers = 0;
2345
2346 /* Probe each SBUS for the DBRI chip(s). */
2347 for_all_sbusdev(sdev, sbus) {
2348 /*
2349 * The version is coded in the last character
2350 */
2351 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2352 dprintk(D_GEN, ("DBRI: Found %s in SBUS slot %d\n",
2353 sdev->prom_name, sdev->slot));
2354 if (num_drivers >= MAX_DRIVERS) {
2355 printk("DBRI: Ignoring slot %d\n", sdev->slot);
2356 continue;
2357 }
2358
2359 if (dbri_attach(&drivers[num_drivers], sdev) == 0)
2360 num_drivers++;
2361 }
2362 }
2363
2364 return (num_drivers > 0) ? 0 : -EIO;
2365 }
2366
2367 static void __exit dbri_exit(void)
2368 {
2369 register int i;
2370
2371 for (i = 0; i < num_drivers; i++) {
2372 dbri_detach((struct dbri *) drivers[i].private);
2373 unregister_sparcaudio_driver(& drivers[i], 1);
2374 num_drivers--;
2375 }
2376 }
2377
2378 module_init(dbri_init);
2379 module_exit(dbri_exit);
2380 /*
2381 * Overrides for Emacs so that we follow Linus's tabbing style.
2382 * Emacs will notice this stuff at the end of the file and automatically
2383 * adjust the settings for this buffer only. This must remain at the end
2384 * of the file.
2385 * ---------------------------------------------------------------------------
2386 * Local Variables:
2387 * c-indent-level: 8
2388 * c-brace-imaginary-offset: 0
2389 * c-brace-offset: -8
2390 * c-argdecl-indent: 8
2391 * c-label-offset: -8
2392 * c-continued-statement-offset: 8
2393 * c-continued-brace-offset: 0
2394 * indent-tabs-mode: nil
2395 * tab-width: 8
2396 * End:
2397 */
2398