File: /usr/src/linux/drivers/sbus/char/bpp.c
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/version.h>
16 #include <linux/fs.h>
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/timer.h>
22 #include <linux/ioport.h>
23 #include <linux/major.h>
24 #include <linux/devfs_fs_kernel.h>
25
26 #include <asm/uaccess.h>
27 #include <asm/io.h>
28
29 #if defined(__i386__)
30 # include <asm/system.h>
31 # include <asm/segment.h>
32 #endif
33
34 #if defined(__sparc__)
35 # include <linux/init.h>
36 # include <linux/delay.h> /* udelay() */
37
38 # include <asm/oplib.h> /* OpenProm Library */
39 # include <asm/sbus.h>
40 #endif
41
42 #include <asm/bpp.h>
43
44 #define BPP_PROBE_CODE 0x55
45 #define BPP_DELAY 100
46
47 static const unsigned BPP_MAJOR = LP_MAJOR;
48 static const char* dev_name = "bpp";
49
50 /* When switching from compatibility to a mode where I can read, try
51 the following mode first. */
52
53 /* const unsigned char DEFAULT_ECP = 0x10; */
54 static const unsigned char DEFAULT_ECP = 0x30;
55 static const unsigned char DEFAULT_NIBBLE = 0x00;
56
57 /*
58 * These are 1284 time constraints, in units of jiffies.
59 */
60
61 static const unsigned long TIME_PSetup = 1;
62 static const unsigned long TIME_PResponse = 6;
63 static const unsigned long TIME_IDLE_LIMIT = 2000;
64
65 /*
66 * One instance per supported subdevice...
67 */
68 # define BPP_NO 3
69
70 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
71
72 struct inst {
73 unsigned present : 1; /* True if the hardware exists */
74 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
75 unsigned opened : 1; /* True if the device is opened already */
76 unsigned run_flag : 1; /* True if waiting for a repeate byte */
77
78 unsigned char direction; /* 0 --> out, 0x20 --> IN */
79 unsigned char pp_state; /* State of host controlled pins. */
80 enum IEEE_Mode mode;
81
82 unsigned char run_length;
83 unsigned char repeat_byte;
84
85 /* These members manage timeouts for programmed delays */
86 wait_queue_head_t wait_queue;
87 struct timer_list timer_list;
88 };
89
90 static struct inst instances[BPP_NO];
91
92 #if defined(__i386__)
93
94 const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
95
96 /*
97 * These are for data access.
98 * Control lines accesses are hidden in set_bits() and get_bits().
99 * The exeption is the probe procedure, which is system-dependent.
100 */
101 #define bpp_outb_p(data, base) outb_p((data), (base))
102 #define bpp_inb(base) inb(base)
103 #define bpp_inb_p(base) inb_p(base)
104
105 /*
106 * This method takes the pin values mask and sets the hardware pins to
107 * the requested value: 1 == high voltage, 0 == low voltage. This
108 * burries the annoying PC bit inversion and preserves the direction
109 * flag.
110 */
111 static void set_pins(unsigned short pins, unsigned minor)
112 {
113 unsigned char bits = instances[minor].direction; /* == 0x20 */
114
115 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
116 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
117 if ( pins & BPP_PP_nInit) bits |= 4;
118 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
119
120 instances[minor].pp_state = bits;
121
122 outb_p(bits, base_addrs[minor]+2);
123 }
124
125 static unsigned short get_pins(unsigned minor)
126 {
127 unsigned short bits = 0;
128
129 unsigned value = instances[minor].pp_state;
130 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
131 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
132 if (value & 0x04) bits |= BPP_PP_nInit;
133 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
134
135 value = inb_p(base_addrs[minor]+1);
136 if (value & 0x08) bits |= BPP_GP_nFault;
137 if (value & 0x10) bits |= BPP_GP_Select;
138 if (value & 0x20) bits |= BPP_GP_PError;
139 if (value & 0x40) bits |= BPP_GP_nAck;
140 if (! (value & 0x80)) bits |= BPP_GP_Busy;
141
142 return bits;
143 }
144
145 #endif /* __i386__ */
146
147 #if defined(__sparc__)
148
149 /*
150 * Register block
151 */
152 /* DMA registers */
153 #define BPP_CSR 0x00
154 #define BPP_ADDR 0x04
155 #define BPP_BCNT 0x08
156 #define BPP_TST_CSR 0x0C
157 /* Parallel Port registers */
158 #define BPP_HCR 0x10
159 #define BPP_OCR 0x12
160 #define BPP_DR 0x14
161 #define BPP_TCR 0x15
162 #define BPP_OR 0x16
163 #define BPP_IR 0x17
164 #define BPP_ICR 0x18
165 #define BPP_SIZE 0x1A
166
167 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
168 #define P_DEV_ID_MASK 0xf0000000 /* R */
169 #define P_DEV_ID_ZEBRA 0x40000000
170 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
171 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
172 #define P_A_LOADED 0x04000000 /* R */
173 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
174 #define P_EN_NEXT 0x01000000 /* RW */
175 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
176 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
177 of P-FIFO on loading of P_ADDR*/
178 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
179 #define P_BURST_8 0x00000000
180 #define P_BURST_4 0x00040000
181 #define P_BURST_1 0x00080000 /* "No burst" write */
182 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
183 P_EN_NEXT=1 */
184 #define P_EN_CNT 0x00002000 /* RW */
185 #define P_EN_DMA 0x00000200 /* RW */
186 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
187 #define P_RESET 0x00000080 /* RW */
188 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
189 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
190 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
191 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
192 #define P_ERR_PEND 0x00000002 /* R */
193 #define P_INT_PEND 0x00000001 /* R */
194
195 /* BPP_HCR. Time is in increments of SBus clock. */
196 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
197 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
198 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
199
200 /* BPP_OCR. */
201 #define P_OCR_MEM_CLR 0x8000
202 #define P_OCR_DATA_SRC 0x4000 /* ) */
203 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
204 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
205 #define P_OCR_ACK_DSEL 0x0800 /* ) */
206 #define P_OCR_EN_DIAG 0x0400
207 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
208 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
209 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
210 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
211 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
212 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
213
214 /* BPP_TCR */
215 #define P_TCR_DIR 0x08
216 #define P_TCR_BUSY 0x04
217 #define P_TCR_ACK 0x02
218 #define P_TCR_DS 0x01 /* Strobe */
219
220 /* BPP_OR */
221 #define P_OR_V3 0x20 /* ) */
222 #define P_OR_V2 0x10 /* ) on Zebra only */
223 #define P_OR_V1 0x08 /* ) */
224 #define P_OR_INIT 0x04
225 #define P_OR_AFXN 0x02 /* Auto Feed */
226 #define P_OR_SLCT_IN 0x01
227
228 /* BPP_IR */
229 #define P_IR_PE 0x04
230 #define P_IR_SLCT 0x02
231 #define P_IR_ERR 0x01
232
233 /* BPP_ICR */
234 #define P_DS_IRQ 0x8000 /* RW1 */
235 #define P_ACK_IRQ 0x4000 /* RW1 */
236 #define P_BUSY_IRQ 0x2000 /* RW1 */
237 #define P_PE_IRQ 0x1000 /* RW1 */
238 #define P_SLCT_IRQ 0x0800 /* RW1 */
239 #define P_ERR_IRQ 0x0400 /* RW1 */
240 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
241 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
242 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
243 #define P_BUSY_IRQ_EN 0x0040 /* RW */
244 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
245 #define P_PE_IRQ_EN 0x0010 /* RW */
246 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
247 #define P_SLCT_IRQ_EN 0x0004 /* RW */
248 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
249 #define P_ERR_IRQ_EN 0x0001 /* RW */
250
251 unsigned long base_addrs[BPP_NO];
252
253 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
254 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
255 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
256
257 static void set_pins(unsigned short pins, unsigned minor)
258 {
259 unsigned long base = base_addrs[minor];
260 unsigned char bits_tcr = 0, bits_or = 0;
261
262 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
263 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
264
265 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
266 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
267 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
268
269 sbus_writeb(bits_or, base + BPP_OR);
270 sbus_writeb(bits_tcr, base + BPP_TCR);
271 }
272
273 /*
274 * i386 people read output pins from a software image.
275 * We may get them back from hardware.
276 * Again, inversion of pins must he buried here.
277 */
278 static unsigned short get_pins(unsigned minor)
279 {
280 unsigned long base = base_addrs[minor];
281 unsigned short bits = 0;
282 unsigned value_tcr = sbus_readb(base + BPP_TCR);
283 unsigned value_ir = sbus_readb(base + BPP_IR);
284 unsigned value_or = sbus_readb(base + BPP_OR);
285
286 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
287 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
288 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
289 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
290
291 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
292 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
293 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
294 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
295 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
296
297 return bits;
298 }
299
300 #endif /* __sparc__ */
301
302 static void bpp_wake_up(unsigned long val)
303 { wake_up(&instances[val].wait_queue); }
304
305 static void snooze(unsigned long snooze_time, unsigned minor)
306 {
307 instances[minor].timer_list.expires = jiffies + snooze_time + 1;
308 instances[minor].timer_list.data = minor;
309 add_timer(&instances[minor].timer_list);
310 sleep_on (&instances[minor].wait_queue);
311 }
312
313 static int wait_for(unsigned short set, unsigned short clr,
314 unsigned long delay, unsigned minor)
315 {
316 unsigned short pins = get_pins(minor);
317
318 unsigned long extime = 0;
319
320 /*
321 * Try a real fast scan for the first jiffy, in case the device
322 * responds real good. The first while loop guesses an expire
323 * time accounting for possible wraparound of jiffies.
324 */
325 while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
326 while ( (time_before(jiffies, extime))
327 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
328 pins = get_pins(minor);
329 }
330
331 delay -= 1;
332
333 /*
334 * If my delay expired or the pins are still not where I want
335 * them, then resort to using the timer and greatly reduce my
336 * sample rate. If the peripheral is going to be slow, this will
337 * give the CPU up to some more worthy process.
338 */
339 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
340
341 snooze(1, minor);
342 pins = get_pins(minor);
343 delay -= 1;
344 }
345
346 if (delay == 0) return -1;
347 else return pins;
348 }
349
350 /*
351 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
352 * errno means something broke, and I do not yet know how to fix it.
353 */
354 static int negotiate(unsigned char mode, unsigned minor)
355 {
356 int rc;
357 unsigned short pins = get_pins(minor);
358 if (pins & BPP_PP_nSelectIn) return -EIO;
359
360
361 /* Event 0: Write the mode to the data lines */
362 bpp_outb_p(mode, base_addrs[minor]);
363
364 snooze(TIME_PSetup, minor);
365
366 /* Event 1: Strobe the mode code into the peripheral */
367 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
368
369 /* Wait for Event 2: Peripheral responds as a 1284 device. */
370 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
371 BPP_GP_nAck,
372 TIME_PResponse,
373 minor);
374
375 if (rc == -1) return -ETIMEDOUT;
376
377 /* Event 3: latch extensibility request */
378 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
379
380 /* ... quick nap while peripheral ponders the byte i'm sending...*/
381 snooze(1, minor);
382
383 /* Event 4: restore strobe, to ACK peripheral's response. */
384 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
385
386 /* Wait for Event 6: Peripheral latches response bits */
387 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
388 if (rc == -1) return -EIO;
389
390 /* A 1284 device cannot refuse nibble mode */
391 if (mode == DEFAULT_NIBBLE) return 0;
392
393 if (pins & BPP_GP_Select) return 0;
394
395 return -EPROTONOSUPPORT;
396 }
397
398 static int terminate(unsigned minor)
399 {
400 int rc;
401
402 /* Event 22: Request termination of 1284 mode */
403 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
404
405 /* Wait for Events 23 and 24: ACK termination request. */
406 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
407 BPP_GP_nAck,
408 TIME_PSetup+TIME_PResponse,
409 minor);
410
411 instances[minor].direction = 0;
412 instances[minor].mode = COMPATIBILITY;
413
414 if (rc == -1) {
415 return -EIO;
416 }
417
418 /* Event 25: Handshake by lowering nAutoFd */
419 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
420
421 /* Event 26: Peripheral wiggles lines... */
422
423 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
424 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
425 if (rc == -1) {
426 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
427 return -EIO;
428 }
429
430 /* Event 28: Finish phase by raising nAutoFd */
431 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
432
433 return 0;
434 }
435
436 static spinlock_t bpp_open_lock = SPIN_LOCK_UNLOCKED;
437
438 /*
439 * Allow only one process to open the device at a time.
440 */
441 static int bpp_open(struct inode *inode, struct file *f)
442 {
443 unsigned minor = MINOR(inode->i_rdev);
444 int ret;
445
446 spin_lock(&bpp_open_lock);
447 ret = 0;
448 if (minor >= BPP_NO) {
449 ret = -ENODEV;
450 } else {
451 if (! instances[minor].present) {
452 ret = -ENODEV;
453 } else {
454 if (instances[minor].opened)
455 ret = -EBUSY;
456 else
457 instances[minor].opened = 1;
458 }
459 }
460 spin_unlock(&bpp_open_lock);
461
462 return ret;
463 }
464
465 /*
466 * When the process closes the device, this method is called to clean
467 * up and reset the hardware. Always leave the device in compatibility
468 * mode as this is a reasonable place to clean up from messes made by
469 * ioctls, or other mayhem.
470 */
471 static int bpp_release(struct inode *inode, struct file *f)
472 {
473 unsigned minor = MINOR(inode->i_rdev);
474
475 spin_lock(&bpp_open_lock);
476 instances[minor].opened = 0;
477
478 if (instances[minor].mode != COMPATIBILITY)
479 terminate(minor);
480
481 spin_unlock(&bpp_open_lock);
482
483 return 0;
484 }
485
486 static long read_nibble(unsigned minor, char *c, unsigned long cnt)
487 {
488 unsigned long remaining = cnt;
489 long rc;
490
491 while (remaining > 0) {
492 unsigned char byte = 0;
493 int pins;
494
495 /* Event 7: request nibble */
496 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
497
498 /* Wait for event 9: Peripher strobes first nibble */
499 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
500 if (pins == -1) return -ETIMEDOUT;
501
502 /* Event 10: I handshake nibble */
503 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
504 if (pins & BPP_GP_nFault) byte |= 0x01;
505 if (pins & BPP_GP_Select) byte |= 0x02;
506 if (pins & BPP_GP_PError) byte |= 0x04;
507 if (pins & BPP_GP_Busy) byte |= 0x08;
508
509 /* Wait for event 11: Peripheral handshakes nibble */
510 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
511
512 /* Event 7: request nibble */
513 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
514
515 /* Wait for event 9: Peripher strobes first nibble */
516 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
517 if (rc == -1) return -ETIMEDOUT;
518
519 /* Event 10: I handshake nibble */
520 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
521 if (pins & BPP_GP_nFault) byte |= 0x10;
522 if (pins & BPP_GP_Select) byte |= 0x20;
523 if (pins & BPP_GP_PError) byte |= 0x40;
524 if (pins & BPP_GP_Busy) byte |= 0x80;
525
526 if (put_user(byte, c))
527 return -EFAULT;
528 c += 1;
529 remaining -= 1;
530
531 /* Wait for event 11: Peripheral handshakes nibble */
532 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
533 if (rc == -1) return -EIO;
534 }
535
536 return cnt - remaining;
537 }
538
539 static long read_ecp(unsigned minor, char *c, unsigned long cnt)
540 {
541 unsigned long remaining;
542 long rc;
543
544 /* Turn ECP mode from forward to reverse if needed. */
545 if (! instances[minor].direction) {
546 unsigned short pins = get_pins(minor);
547
548 /* Event 38: Turn the bus around */
549 instances[minor].direction = 0x20;
550 pins &= ~BPP_PP_nAutoFd;
551 set_pins(pins, minor);
552
553 /* Event 39: Set pins for reverse mode. */
554 snooze(TIME_PSetup, minor);
555 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
556
557 /* Wait for event 40: Peripheral ready to be strobed */
558 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
559 if (rc == -1) return -ETIMEDOUT;
560 }
561
562 remaining = cnt;
563
564 while (remaining > 0) {
565
566 /* If there is a run length for a repeated byte, repeat */
567 /* that byte a few times. */
568 if (instances[minor].run_length && !instances[minor].run_flag) {
569
570 char buffer[128];
571 unsigned idx;
572 unsigned repeat = remaining < instances[minor].run_length
573 ? remaining
574 : instances[minor].run_length;
575
576 for (idx = 0 ; idx < repeat ; idx += 1)
577 buffer[idx] = instances[minor].repeat_byte;
578
579 if (copy_to_user(c, buffer, repeat))
580 return -EFAULT;
581 remaining -= repeat;
582 c += repeat;
583 instances[minor].run_length -= repeat;
584 }
585
586 if (remaining == 0) break;
587
588
589 /* Wait for Event 43: Data active on the bus. */
590 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
591 if (rc == -1) break;
592
593 if (rc & BPP_GP_Busy) {
594 /* OK, this is data. read it in. */
595 unsigned char byte = bpp_inb(base_addrs[minor]);
596 if (put_user(byte, c))
597 return -EFAULT;
598 c += 1;
599 remaining -= 1;
600
601 if (instances[minor].run_flag) {
602 instances[minor].repeat_byte = byte;
603 instances[minor].run_flag = 0;
604 }
605
606 } else {
607 unsigned char byte = bpp_inb(base_addrs[minor]);
608 if (byte & 0x80) {
609 printk("bpp%d: "
610 "Ignoring ECP channel %u from device.\n",
611 minor, byte & 0x7f);
612 } else {
613 instances[minor].run_length = byte;
614 instances[minor].run_flag = 1;
615 }
616 }
617
618 /* Event 44: I got it. */
619 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
620
621 /* Wait for event 45: peripheral handshake */
622 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
623 if (rc == -1) return -ETIMEDOUT;
624
625 /* Event 46: Finish handshake */
626 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
627
628 }
629
630
631 return cnt - remaining;
632 }
633
634 static ssize_t bpp_read(struct file *f, char *c, size_t cnt, loff_t * ppos)
635 {
636 long rc;
637 const unsigned minor = MINOR(f->f_dentry->d_inode->i_rdev);
638 if (minor >= BPP_NO) return -ENODEV;
639 if (!instances[minor].present) return -ENODEV;
640
641 switch (instances[minor].mode) {
642
643 default:
644 if (instances[minor].mode != COMPATIBILITY)
645 terminate(minor);
646
647 if (instances[minor].enhanced) {
648 /* For now, do all reads with ECP-RLE mode */
649 unsigned short pins;
650
651 rc = negotiate(DEFAULT_ECP, minor);
652 if (rc < 0) break;
653
654 instances[minor].mode = ECP_RLE;
655
656 /* Event 30: set nAutoFd low to setup for ECP mode */
657 pins = get_pins(minor);
658 pins &= ~BPP_PP_nAutoFd;
659 set_pins(pins, minor);
660
661 /* Wait for Event 31: peripheral ready */
662 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
663 if (rc == -1) return -ETIMEDOUT;
664
665 rc = read_ecp(minor, c, cnt);
666
667 } else {
668 rc = negotiate(DEFAULT_NIBBLE, minor);
669 if (rc < 0) break;
670
671 instances[minor].mode = NIBBLE;
672
673 rc = read_nibble(minor, c, cnt);
674 }
675 break;
676
677 case NIBBLE:
678 rc = read_nibble(minor, c, cnt);
679 break;
680
681 case ECP:
682 case ECP_RLE:
683 rc = read_ecp(minor, c, cnt);
684 break;
685
686 }
687
688
689 return rc;
690 }
691
692 /*
693 * Compatibility mode handshaking is a matter of writing data,
694 * strobing it, and waiting for the printer to stop being busy.
695 */
696 static long write_compat(unsigned minor, const char *c, unsigned long cnt)
697 {
698 long rc;
699 unsigned short pins = get_pins(minor);
700
701 unsigned long remaining = cnt;
702
703
704 while (remaining > 0) {
705 unsigned char byte;
706
707 if (get_user(byte, c))
708 return -EFAULT;
709 c += 1;
710
711 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
712 if (rc == -1) return -ETIMEDOUT;
713
714 bpp_outb_p(byte, base_addrs[minor]);
715 remaining -= 1;
716 /* snooze(1, minor); */
717
718 pins &= ~BPP_PP_nStrobe;
719 set_pins(pins, minor);
720
721 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
722
723 pins |= BPP_PP_nStrobe;
724 set_pins(pins, minor);
725 }
726
727 return cnt - remaining;
728 }
729
730 /*
731 * Write data using ECP mode. Watch out that the port may be set up
732 * for reading. If so, turn the port around.
733 */
734 static long write_ecp(unsigned minor, const char *c, unsigned long cnt)
735 {
736 unsigned short pins = get_pins(minor);
737 unsigned long remaining = cnt;
738
739 if (instances[minor].direction) {
740 int rc;
741
742 /* Event 47 Request bus be turned around */
743 pins |= BPP_PP_nInit;
744 set_pins(pins, minor);
745
746 /* Wait for Event 49: Peripheral relinquished bus */
747 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
748
749 pins |= BPP_PP_nAutoFd;
750 instances[minor].direction = 0;
751 set_pins(pins, minor);
752 }
753
754 while (remaining > 0) {
755 unsigned char byte;
756 int rc;
757
758 if (get_user(byte, c))
759 return -EFAULT;
760
761 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
762 if (rc == -1) return -ETIMEDOUT;
763
764 c += 1;
765
766 bpp_outb_p(byte, base_addrs[minor]);
767
768 pins &= ~BPP_PP_nStrobe;
769 set_pins(pins, minor);
770
771 pins |= BPP_PP_nStrobe;
772 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
773 if (rc == -1) return -EIO;
774
775 set_pins(pins, minor);
776 }
777
778 return cnt - remaining;
779 }
780
781 /*
782 * Write to the peripheral. Be sensitive of the current mode. If I'm
783 * in a mode that can be turned around (ECP) then just do
784 * that. Otherwise, terminate and do my writing in compat mode. This
785 * is the safest course as any device can handle it.
786 */
787 static ssize_t bpp_write(struct file *f, const char *c, size_t cnt, loff_t * ppos)
788 {
789 long errno = 0;
790 const unsigned minor = MINOR(f->f_dentry->d_inode->i_rdev);
791 if (minor >= BPP_NO) return -ENODEV;
792 if (!instances[minor].present) return -ENODEV;
793
794 switch (instances[minor].mode) {
795
796 case ECP:
797 case ECP_RLE:
798 errno = write_ecp(minor, c, cnt);
799 break;
800 case COMPATIBILITY:
801 errno = write_compat(minor, c, cnt);
802 break;
803 default:
804 terminate(minor);
805 errno = write_compat(minor, c, cnt);
806 }
807
808 return errno;
809 }
810
811 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
812 unsigned long arg)
813 {
814 int errno = 0;
815
816 unsigned minor = MINOR(inode->i_rdev);
817 if (minor >= BPP_NO) return -ENODEV;
818 if (!instances[minor].present) return -ENODEV;
819
820
821 switch (cmd) {
822
823 case BPP_PUT_PINS:
824 set_pins(arg, minor);
825 break;
826
827 case BPP_GET_PINS:
828 errno = get_pins(minor);
829 break;
830
831 case BPP_PUT_DATA:
832 bpp_outb_p(arg, base_addrs[minor]);
833 break;
834
835 case BPP_GET_DATA:
836 errno = bpp_inb_p(base_addrs[minor]);
837 break;
838
839 case BPP_SET_INPUT:
840 if (arg)
841 if (instances[minor].enhanced) {
842 unsigned short bits = get_pins(minor);
843 instances[minor].direction = 0x20;
844 set_pins(bits, minor);
845 } else {
846 errno = -ENOTTY;
847 }
848 else {
849 unsigned short bits = get_pins(minor);
850 instances[minor].direction = 0x00;
851 set_pins(bits, minor);
852 }
853 break;
854
855 default:
856 errno = -EINVAL;
857 }
858
859 return errno;
860 }
861
862 static struct file_operations bpp_fops = {
863 owner: THIS_MODULE,
864 read: bpp_read,
865 write: bpp_write,
866 ioctl: bpp_ioctl,
867 open: bpp_open,
868 release: bpp_release,
869 };
870
871 #if defined(__i386__)
872
873 #define collectLptPorts() {}
874
875 static void probeLptPort(unsigned idx)
876 {
877 unsigned int testvalue;
878 const unsigned short lpAddr = base_addrs[idx];
879
880 instances[idx].present = 0;
881 instances[idx].enhanced = 0;
882 instances[idx].direction = 0;
883 instances[idx].mode = COMPATIBILITY;
884 instances[idx].wait_queue = 0;
885 instances[idx].run_length = 0;
886 instances[idx].run_flag = 0;
887 init_timer(&instances[idx].timer_list);
888 instances[idx].timer_list.function = bpp_wake_up;
889 if (check_region(lpAddr,3)) return;
890
891 /*
892 * First, make sure the instance exists. Do this by writing to
893 * the data latch and reading the value back. If the port *is*
894 * present, test to see if it supports extended-mode
895 * operation. This will be required for IEEE1284 reverse
896 * transfers.
897 */
898
899 outb_p(BPP_PROBE_CODE, lpAddr);
900 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
901 ;
902 testvalue = inb_p(lpAddr);
903 if (testvalue == BPP_PROBE_CODE) {
904 unsigned save;
905 instances[idx].present = 1;
906
907 request_region(lpAddr,3, dev_name);
908 save = inb_p(lpAddr+2);
909 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
910 ;
911 outb_p(save|0x20, lpAddr+2);
912 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
913 ;
914 outb_p(~BPP_PROBE_CODE, lpAddr);
915 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
916 ;
917 testvalue = inb_p(lpAddr);
918 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
919 instances[idx].enhanced = 0;
920 else
921 instances[idx].enhanced = 1;
922 outb_p(save, lpAddr+2);
923 }
924
925 /*
926 * Leave the port in compat idle mode.
927 */
928 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
929
930 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
931 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
932 }
933
934 static inline void freeLptPort(int idx)
935 {
936 release_region(base_addrs[idx], 3);
937 }
938
939 #endif
940
941 #if defined(__sparc__)
942
943 static unsigned long map_bpp(struct sbus_dev *dev, int idx)
944 {
945 return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
946 }
947
948 static int collectLptPorts(void)
949 {
950 struct sbus_bus *bus;
951 struct sbus_dev *dev;
952 int count;
953
954 count = 0;
955 for_all_sbusdev(dev, bus) {
956 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
957 if (count >= BPP_NO) {
958 printk(KERN_NOTICE
959 "bpp: More than %d bpp ports,"
960 " rest is ignored\n", BPP_NO);
961 return count;
962 }
963 base_addrs[count] = map_bpp(dev, count);
964 count++;
965 }
966 }
967 return count;
968 }
969
970 static void probeLptPort(unsigned idx)
971 {
972 unsigned long rp = base_addrs[idx];
973 __u32 csr;
974 char *brand;
975
976 instances[idx].present = 0;
977 instances[idx].enhanced = 0;
978 instances[idx].direction = 0;
979 instances[idx].mode = COMPATIBILITY;
980 init_waitqueue_head(&instances[idx].wait_queue);
981 instances[idx].run_length = 0;
982 instances[idx].run_flag = 0;
983 init_timer(&instances[idx].timer_list);
984 instances[idx].timer_list.function = bpp_wake_up;
985
986 if (rp == 0) return;
987
988 instances[idx].present = 1;
989 instances[idx].enhanced = 1; /* Sure */
990
991 csr = sbus_readl(rp + BPP_CSR);
992 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
993 udelay(20);
994 csr = sbus_readl(rp + BPP_CSR);
995 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
996 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
997 }
998 }
999 printk("bpp%d: reset with 0x%08x ..", idx, csr);
1000 sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
1001 udelay(500);
1002 sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
1003 csr = sbus_readl(rp + BPP_CSR);
1004 printk(" done with csr=0x%08x ocr=0x%04x\n",
1005 csr, sbus_readw(rp + BPP_OCR));
1006
1007 switch (csr & P_DEV_ID_MASK) {
1008 case P_DEV_ID_ZEBRA:
1009 brand = "Zebra";
1010 break;
1011 case P_DEV_ID_L64854:
1012 brand = "DMA2";
1013 break;
1014 default:
1015 brand = "Unknown";
1016 }
1017 printk("bpp%d: %s at 0x%lx\n", idx, brand, rp);
1018
1019 /*
1020 * Leave the port in compat idle mode.
1021 */
1022 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1023
1024 return;
1025 }
1026
1027 static inline void freeLptPort(int idx)
1028 {
1029 sbus_iounmap(base_addrs[idx], BPP_SIZE);
1030 }
1031
1032 #endif
1033
1034 static devfs_handle_t devfs_handle;
1035
1036 static int __init bpp_init(void)
1037 {
1038 int rc;
1039 unsigned idx;
1040
1041 rc = collectLptPorts();
1042 if (rc == 0)
1043 return -ENODEV;
1044
1045 rc = devfs_register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1046 if (rc < 0)
1047 return rc;
1048
1049 for (idx = 0; idx < BPP_NO; idx += 1) {
1050 instances[idx].opened = 0;
1051 probeLptPort(idx);
1052 }
1053 devfs_handle = devfs_mk_dir (NULL, "bpp", NULL);
1054 devfs_register_series (devfs_handle, "%u", BPP_NO, DEVFS_FL_DEFAULT,
1055 BPP_MAJOR, 0, S_IFCHR | S_IRUSR | S_IWUSR,
1056 &bpp_fops, NULL);
1057
1058 return 0;
1059 }
1060
1061 static void __exit bpp_cleanup(void)
1062 {
1063 unsigned idx;
1064
1065 devfs_unregister (devfs_handle);
1066 devfs_unregister_chrdev(BPP_MAJOR, dev_name);
1067
1068 for (idx = 0 ; idx < BPP_NO ; idx += 1) {
1069 if (instances[idx].present)
1070 freeLptPort(idx);
1071 }
1072 }
1073
1074 module_init(bpp_init);
1075 module_exit(bpp_cleanup);
1076