File: /usr/src/linux/drivers/scsi/FlashPoint.c
1 /*
2
3 FlashPoint.c -- FlashPoint SCCB Manager for Linux
4
5 This file contains the FlashPoint SCCB Manager from BusLogic's FlashPoint
6 Driver Developer's Kit, with minor modifications by Leonard N. Zubkoff for
7 Linux compatibility. It was provided by BusLogic in the form of 16 separate
8 source files, which would have unnecessarily cluttered the scsi directory, so
9 the individual files have been combined into this single file.
10
11 Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
12
13 This file is available under both the GNU General Public License
14 and a BSD-style copyright; see LICENSE.FlashPoint for details.
15
16 */
17
18
19 #include <linux/config.h>
20
21
22 #ifndef CONFIG_SCSI_OMIT_FLASHPOINT
23
24
25 #define UNIX
26 #define FW_TYPE _SCCB_MGR_
27 #define MAX_CARDS 8
28 #undef BUSTYPE_PCI
29
30
31 #define OS_InPortByte(port) inb(port)
32 #define OS_InPortWord(port) inw(port)
33 #define OS_InPortLong(port) inl(port)
34 #define OS_OutPortByte(port, value) outb(value, port)
35 #define OS_OutPortWord(port, value) outw(value, port)
36 #define OS_OutPortLong(port, value) outl(value, port)
37 #define OS_Lock(x)
38 #define OS_UnLock(x)
39
40
41 /*
42 Define name replacements for compatibility with the Linux BusLogic Driver.
43 */
44
45 #define SccbMgr_sense_adapter FlashPoint_ProbeHostAdapter
46 #define SccbMgr_config_adapter FlashPoint_HardwareResetHostAdapter
47 #define SccbMgr_unload_card FlashPoint_ReleaseHostAdapter
48 #define SccbMgr_start_sccb FlashPoint_StartCCB
49 #define SccbMgr_abort_sccb FlashPoint_AbortCCB
50 #define SccbMgr_my_int FlashPoint_InterruptPending
51 #define SccbMgr_isr FlashPoint_HandleInterrupt
52
53
54 /*
55 Define name replacements to avoid kernel namespace pollution.
56 */
57
58 #define BL_Card FPT_BL_Card
59 #define BusMasterInit FPT_BusMasterInit
60 #define CalcCrc16 FPT_CalcCrc16
61 #define CalcLrc FPT_CalcLrc
62 #define ChkIfChipInitialized FPT_ChkIfChipInitialized
63 #define DiagBusMaster FPT_DiagBusMaster
64 #define DiagEEPROM FPT_DiagEEPROM
65 #define DiagXbow FPT_DiagXbow
66 #define GetTarLun FPT_GetTarLun
67 #define RNVRamData FPT_RNVRamData
68 #define RdStack FPT_RdStack
69 #define SccbMgrTableInitAll FPT_SccbMgrTableInitAll
70 #define SccbMgrTableInitCard FPT_SccbMgrTableInitCard
71 #define SccbMgrTableInitTarget FPT_SccbMgrTableInitTarget
72 #define SccbMgr_bad_isr FPT_SccbMgr_bad_isr
73 #define SccbMgr_scsi_reset FPT_SccbMgr_scsi_reset
74 #define SccbMgr_timer_expired FPT_SccbMgr_timer_expired
75 #define SendMsg FPT_SendMsg
76 #define Wait FPT_Wait
77 #define Wait1Second FPT_Wait1Second
78 #define WrStack FPT_WrStack
79 #define XbowInit FPT_XbowInit
80 #define autoCmdCmplt FPT_autoCmdCmplt
81 #define autoLoadDefaultMap FPT_autoLoadDefaultMap
82 #define busMstrDataXferStart FPT_busMstrDataXferStart
83 #define busMstrSGDataXferStart FPT_busMstrSGDataXferStart
84 #define busMstrTimeOut FPT_busMstrTimeOut
85 #define dataXferProcessor FPT_dataXferProcessor
86 #define default_intena FPT_default_intena
87 #define hostDataXferAbort FPT_hostDataXferAbort
88 #define hostDataXferRestart FPT_hostDataXferRestart
89 #define inisci FPT_inisci
90 #define mbCards FPT_mbCards
91 #define nvRamInfo FPT_nvRamInfo
92 #define phaseBusFree FPT_phaseBusFree
93 #define phaseChkFifo FPT_phaseChkFifo
94 #define phaseCommand FPT_phaseCommand
95 #define phaseDataIn FPT_phaseDataIn
96 #define phaseDataOut FPT_phaseDataOut
97 #define phaseDecode FPT_phaseDecode
98 #define phaseIllegal FPT_phaseIllegal
99 #define phaseMsgIn FPT_phaseMsgIn
100 #define phaseMsgOut FPT_phaseMsgOut
101 #define phaseStatus FPT_phaseStatus
102 #define queueAddSccb FPT_queueAddSccb
103 #define queueCmdComplete FPT_queueCmdComplete
104 #define queueDisconnect FPT_queueDisconnect
105 #define queueFindSccb FPT_queueFindSccb
106 #define queueFlushSccb FPT_queueFlushSccb
107 #define queueFlushTargSccb FPT_queueFlushTargSccb
108 #define queueSearchSelect FPT_queueSearchSelect
109 #define queueSelectFail FPT_queueSelectFail
110 #define s_PhaseTbl FPT_s_PhaseTbl
111 #define scamHAString FPT_scamHAString
112 #define scamInfo FPT_scamInfo
113 #define scarb FPT_scarb
114 #define scasid FPT_scasid
115 #define scbusf FPT_scbusf
116 #define sccbMgrTbl FPT_sccbMgrTbl
117 #define schkdd FPT_schkdd
118 #define scini FPT_scini
119 #define sciso FPT_sciso
120 #define scmachid FPT_scmachid
121 #define scsavdi FPT_scsavdi
122 #define scsel FPT_scsel
123 #define scsell FPT_scsell
124 #define scsendi FPT_scsendi
125 #define scvalq FPT_scvalq
126 #define scwirod FPT_scwirod
127 #define scwiros FPT_scwiros
128 #define scwtsel FPT_scwtsel
129 #define scxferc FPT_scxferc
130 #define sdecm FPT_sdecm
131 #define sfm FPT_sfm
132 #define shandem FPT_shandem
133 #define sinits FPT_sinits
134 #define sisyncn FPT_sisyncn
135 #define sisyncr FPT_sisyncr
136 #define siwidn FPT_siwidn
137 #define siwidr FPT_siwidr
138 #define sres FPT_sres
139 #define sresb FPT_sresb
140 #define ssel FPT_ssel
141 #define ssenss FPT_ssenss
142 #define sssyncv FPT_sssyncv
143 #define stsyncn FPT_stsyncn
144 #define stwidn FPT_stwidn
145 #define sxfrp FPT_sxfrp
146 #define utilEERead FPT_utilEERead
147 #define utilEEReadOrg FPT_utilEEReadOrg
148 #define utilEESendCmdAddr FPT_utilEESendCmdAddr
149 #define utilEEWrite FPT_utilEEWrite
150 #define utilEEWriteOnOff FPT_utilEEWriteOnOff
151 #define utilUpdateResidual FPT_utilUpdateResidual
152
153
154 /*----------------------------------------------------------------------
155 *
156 *
157 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
158 *
159 * This file is available under both the GNU General Public License
160 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
161 *
162 * $Workfile: globals.h $
163 *
164 * Description: Common shared global defines.
165 *
166 * $Date: 1996/09/04 01:26:13 $
167 *
168 * $Revision: 1.11 $
169 *
170 *----------------------------------------------------------------------*/
171 #ifndef __GLOBALS_H__
172 #define __GLOBALS_H__
173
174 #define _UCB_MGR_ 1
175 #define _SCCB_MGR_ 2
176
177 /*#include <osflags.h>*/
178
179 #define MAX_CDBLEN 12
180
181 #define SCAM_LEV_2 1
182
183 #define CRCMASK 0xA001
184
185 /* In your osflags.h file, please ENSURE that only ONE OS FLAG
186 is on at a time !!! Also, please make sure you turn set the
187 variable FW_TYPE to either _UCB_MGR_ or _SCCB_MGR_ !!! */
188
189 #if defined(DOS) || defined(WIN95_16) || defined(OS2) || defined(OTHER_16)
190 #define COMPILER_16_BIT 1
191 #elif defined(NETWARE) || defined(NT) || defined(WIN95_32) || defined(UNIX) || defined(OTHER_32) || defined(SOLARIS_REAL_MODE)
192 #define COMPILER_32_BIT 1
193 #endif
194
195
196 #define BL_VENDOR_ID 0x104B
197 #define FP_DEVICE_ID 0x8130
198 #define MM_DEVICE_ID 0x1040
199
200
201 #ifndef FALSE
202 #define FALSE 0
203 #endif
204 #ifndef TRUE
205 #define TRUE (!(FALSE))
206 #endif
207
208 #ifndef NULL
209 #define NULL 0
210 #endif
211
212 #define FAILURE 0xFFFFFFFFL
213
214
215 typedef unsigned char UCHAR;
216 typedef unsigned short USHORT;
217 typedef unsigned int UINT;
218 typedef unsigned long ULONG;
219 typedef unsigned char * PUCHAR;
220 typedef unsigned short* PUSHORT;
221 typedef unsigned long * PULONG;
222 typedef void * PVOID;
223
224
225 #if defined(COMPILER_16_BIT)
226 typedef unsigned char far * uchar_ptr;
227 typedef unsigned short far * ushort_ptr;
228 typedef unsigned long far * ulong_ptr;
229 #endif /* 16_BIT_COMPILER */
230
231 #if defined(COMPILER_32_BIT)
232 typedef unsigned char * uchar_ptr;
233 typedef unsigned short * ushort_ptr;
234 typedef unsigned long * ulong_ptr;
235 #endif /* 32_BIT_COMPILER */
236
237
238 /* NEW TYPE DEFINITIONS (shared with Mylex North)
239
240 ** Use following type defines to avoid confusion in 16 and 32-bit
241 ** environments. Avoid using 'int' as it denotes 16 bits in 16-bit
242 ** environment and 32 in 32-bit environments.
243
244 */
245
246 #define s08bits char
247 #define s16bits short
248 #define s32bits long
249
250 #define u08bits unsigned s08bits
251 #define u16bits unsigned s16bits
252 #define u32bits unsigned s32bits
253
254 #if defined(COMPILER_16_BIT)
255
256 typedef u08bits far * pu08bits;
257 typedef u16bits far * pu16bits;
258 typedef u32bits far * pu32bits;
259
260 #endif /* COMPILER_16_BIT */
261
262 #if defined(COMPILER_32_BIT)
263
264 typedef u08bits * pu08bits;
265 typedef u16bits * pu16bits;
266 typedef u32bits * pu32bits;
267
268 #endif /* COMPILER_32_BIT */
269
270
271 #define BIT(x) ((UCHAR)(1<<(x))) /* single-bit mask in bit position x */
272 #define BITW(x) ((USHORT)(1<<(x))) /* single-bit mask in bit position x */
273
274
275
276 #if defined(DOS)
277 /*#include <dos.h>*/
278 #undef inportb /* undefine for Borland Lib */
279 #undef inport /* they may have define I/O function in LIB */
280 #undef outportb
281 #undef outport
282
283 #define OS_InPortByte(ioport) inportb(ioport)
284 #define OS_InPortWord(ioport) inport(ioport)
285 #define OS_InPortLong(ioport) inportq(ioport, val)
286 #define OS_OutPortByte(ioport, val) outportb(ioport, val)
287 #define OS_OutPortWord(ioport, val) outport(ioport, val)
288 #define OS_OutPortLong(ioport) outportq(ioport, val)
289 #endif /* DOS */
290
291 #if defined(NETWARE) || defined(OTHER_32) || defined(OTHER_16)
292 extern u08bits OS_InPortByte(u32bits ioport);
293 extern u16bits OS_InPortWord(u32bits ioport);
294 extern u32bits OS_InPortLong(u32bits ioport);
295
296 extern OS_InPortByteBuffer(u32bits ioport, pu08bits buffer, u32bits count);
297 extern OS_InPortWordBuffer(u32bits ioport, pu16bits buffer, u32bits count);
298 extern OS_OutPortByte(u32bits ioport, u08bits val);
299 extern OS_OutPortWord(u32bits ioport, u16bits val);
300 extern OS_OutPortLong(u32bits ioport, u32bits val);
301 extern OS_OutPortByteBuffer(u32bits ioport, pu08bits buffer, u32bits count);
302 extern OS_OutPortWordBuffer(u32bits ioport, pu16bits buffer, u32bits count);
303 #endif /* NETWARE || OTHER_32 || OTHER_16 */
304
305 #if defined (NT) || defined(WIN95_32) || defined(WIN95_16)
306 #if defined(NT)
307
308 extern __declspec(dllimport) u08bits ScsiPortReadPortUchar(pu08bits ioport);
309 extern __declspec(dllimport) u16bits ScsiPortReadPortUshort(pu16bits ioport);
310 extern __declspec(dllimport) u32bits ScsiPortReadPortUlong(pu32bits ioport);
311 extern __declspec(dllimport) void ScsiPortWritePortUchar(pu08bits ioport, u08bits val);
312 extern __declspec(dllimport) void ScsiPortWritePortUshort(pu16bits port, u16bits val);
313 extern __declspec(dllimport) void ScsiPortWritePortUlong(pu32bits port, u32bits val);
314
315 #else
316
317 extern u08bits ScsiPortReadPortUchar(pu08bits ioport);
318 extern u16bits ScsiPortReadPortUshort(pu16bits ioport);
319 extern u32bits ScsiPortReadPortUlong(pu32bits ioport);
320 extern void ScsiPortWritePortUchar(pu08bits ioport, u08bits val);
321 extern void ScsiPortWritePortUshort(pu16bits port, u16bits val);
322 extern void ScsiPortWritePortUlong(pu32bits port, u32bits val);
323 #endif
324
325
326 #define OS_InPortByte(ioport) ScsiPortReadPortUchar((pu08bits) ioport)
327 #define OS_InPortWord(ioport) ScsiPortReadPortUshort((pu16bits) ioport)
328 #define OS_InPortLong(ioport) ScsiPortReadPortUlong((pu32bits) ioport)
329
330 #define OS_OutPortByte(ioport, val) ScsiPortWritePortUchar((pu08bits) ioport, (u08bits) val)
331 #define OS_OutPortWord(ioport, val) ScsiPortWritePortUshort((pu16bits) ioport, (u16bits) val)
332 #define OS_OutPortLong(ioport, val) ScsiPortWritePortUlong((pu32bits) ioport, (u32bits) val)
333 #define OS_OutPortByteBuffer(ioport, buffer, count) \
334 ScsiPortWritePortBufferUchar((pu08bits)&port, (pu08bits) buffer, (u32bits) count)
335 #define OS_OutPortWordBuffer(ioport, buffer, count) \
336 ScsiPortWritePortBufferUshort((pu16bits)&port, (pu16bits) buffer, (u32bits) count)
337
338 #define OS_Lock(x)
339 #define OS_UnLock(x)
340 #endif /* NT || WIN95_32 || WIN95_16 */
341
342 #if defined (UNIX) && !defined(OS_InPortByte)
343 #define OS_InPortByte(ioport) inb((u16bits)ioport)
344 #define OS_InPortWord(ioport) inw((u16bits)ioport)
345 #define OS_InPortLong(ioport) inl((u16bits)ioport)
346 #define OS_OutPortByte(ioport,val) outb((u16bits)ioport, (u08bits)val)
347 #define OS_OutPortWord(ioport,val) outw((u16bits)ioport, (u16bits)val)
348 #define OS_OutPortLong(ioport,val) outl((u16bits)ioport, (u32bits)val)
349
350 #define OS_Lock(x)
351 #define OS_UnLock(x)
352 #endif /* UNIX */
353
354
355 #if defined(OS2)
356 extern u08bits inb(u32bits ioport);
357 extern u16bits inw(u32bits ioport);
358 extern void outb(u32bits ioport, u08bits val);
359 extern void outw(u32bits ioport, u16bits val);
360
361 #define OS_InPortByte(ioport) inb(ioport)
362 #define OS_InPortWord(ioport) inw(ioport)
363 #define OS_OutPortByte(ioport, val) outb(ioport, val)
364 #define OS_OutPortWord(ioport, val) outw(ioport, val)
365 extern u32bits OS_InPortLong(u32bits ioport);
366 extern void OS_OutPortLong(u32bits ioport, u32bits val);
367
368 #define OS_Lock(x)
369 #define OS_UnLock(x)
370 #endif /* OS2 */
371
372 #if defined(SOLARIS_REAL_MODE)
373
374 extern unsigned char inb(unsigned long ioport);
375 extern unsigned short inw(unsigned long ioport);
376
377 #define OS_InPortByte(ioport) inb(ioport)
378 #define OS_InPortWord(ioport) inw(ioport)
379
380 extern void OS_OutPortByte(unsigned long ioport, unsigned char val);
381 extern void OS_OutPortWord(unsigned long ioport, unsigned short val);
382 extern unsigned long OS_InPortLong(unsigned long ioport);
383 extern void OS_OutPortLong(unsigned long ioport, unsigned long val);
384
385 #define OS_Lock(x)
386 #define OS_UnLock(x)
387
388 #endif /* SOLARIS_REAL_MODE */
389
390 #endif /* __GLOBALS_H__ */
391
392 /*----------------------------------------------------------------------
393 *
394 *
395 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
396 *
397 * This file is available under both the GNU General Public License
398 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
399 *
400 * $Workfile: sccbmgr.h $
401 *
402 * Description: Common shared SCCB Interface defines and SCCB
403 * Manager specifics defines.
404 *
405 * $Date: 1996/10/24 23:09:33 $
406 *
407 * $Revision: 1.14 $
408 *
409 *----------------------------------------------------------------------*/
410
411 #ifndef __SCCB_H__
412 #define __SCCB_H__
413
414 /*#include <osflags.h>*/
415 /*#include <globals.h>*/
416
417 #if defined(BUGBUG)
418 #define debug_size 32
419 #endif
420
421 #if defined(DOS)
422
423 typedef struct _SCCB near *PSCCB;
424 #if (FW_TYPE == _SCCB_MGR_)
425 typedef void (*CALL_BK_FN)(PSCCB);
426 #endif
427
428 #elif defined(OS2)
429
430 typedef struct _SCCB far *PSCCB;
431 #if (FW_TYPE == _SCCB_MGR_)
432 typedef void (far *CALL_BK_FN)(PSCCB);
433 #endif
434
435 #else
436
437 typedef struct _SCCB *PSCCB;
438 #if (FW_TYPE == _SCCB_MGR_)
439 typedef void (*CALL_BK_FN)(PSCCB);
440 #endif
441
442 #endif
443
444
445 typedef struct SCCBMgr_info {
446 ULONG si_baseaddr;
447 UCHAR si_present;
448 UCHAR si_intvect;
449 UCHAR si_id;
450 UCHAR si_lun;
451 USHORT si_fw_revision;
452 USHORT si_per_targ_init_sync;
453 USHORT si_per_targ_fast_nego;
454 USHORT si_per_targ_ultra_nego;
455 USHORT si_per_targ_no_disc;
456 USHORT si_per_targ_wide_nego;
457 USHORT si_flags;
458 UCHAR si_card_family;
459 UCHAR si_bustype;
460 UCHAR si_card_model[3];
461 UCHAR si_relative_cardnum;
462 UCHAR si_reserved[4];
463 ULONG si_OS_reserved;
464 UCHAR si_XlatInfo[4];
465 ULONG si_reserved2[5];
466 ULONG si_secondary_range;
467 } SCCBMGR_INFO;
468
469 #if defined(DOS)
470 typedef SCCBMGR_INFO * PSCCBMGR_INFO;
471 #else
472 #if defined (COMPILER_16_BIT)
473 typedef SCCBMGR_INFO far * PSCCBMGR_INFO;
474 #else
475 typedef SCCBMGR_INFO * PSCCBMGR_INFO;
476 #endif
477 #endif // defined(DOS)
478
479
480
481
482 #if (FW_TYPE==_SCCB_MGR_)
483 #define SCSI_PARITY_ENA 0x0001
484 #define LOW_BYTE_TERM 0x0010
485 #define HIGH_BYTE_TERM 0x0020
486 #define BUSTYPE_PCI 0x3
487 #endif
488
489 #define SUPPORT_16TAR_32LUN 0x0002
490 #define SOFT_RESET 0x0004
491 #define EXTENDED_TRANSLATION 0x0008
492 #define POST_ALL_UNDERRRUNS 0x0040
493 #define FLAG_SCAM_ENABLED 0x0080
494 #define FLAG_SCAM_LEVEL2 0x0100
495
496
497
498
499 #define HARPOON_FAMILY 0x02
500
501
502 #define ISA_BUS_CARD 0x01
503 #define EISA_BUS_CARD 0x02
504 #define PCI_BUS_CARD 0x03
505 #define VESA_BUS_CARD 0x04
506
507 /* SCCB struc used for both SCCB and UCB manager compiles!
508 * The UCB Manager treats the SCCB as it's 'native hardware structure'
509 */
510
511
512 #pragma pack(1)
513 typedef struct _SCCB {
514 UCHAR OperationCode;
515 UCHAR ControlByte;
516 UCHAR CdbLength;
517 UCHAR RequestSenseLength;
518 ULONG DataLength;
519 ULONG DataPointer;
520 UCHAR CcbRes[2];
521 UCHAR HostStatus;
522 UCHAR TargetStatus;
523 UCHAR TargID;
524 UCHAR Lun;
525 UCHAR Cdb[12];
526 UCHAR CcbRes1;
527 UCHAR Reserved1;
528 ULONG Reserved2;
529 ULONG SensePointer;
530
531
532 CALL_BK_FN SccbCallback; /* VOID (*SccbCallback)(); */
533 ULONG SccbIOPort; /* Identifies board base port */
534 UCHAR SccbStatus;
535 UCHAR SCCBRes2;
536 USHORT SccbOSFlags;
537
538
539 ULONG Sccb_XferCnt; /* actual transfer count */
540 ULONG Sccb_ATC;
541 ULONG SccbVirtDataPtr; /* virtual addr for OS/2 */
542 ULONG Sccb_res1;
543 USHORT Sccb_MGRFlags;
544 USHORT Sccb_sgseg;
545 UCHAR Sccb_scsimsg; /* identify msg for selection */
546 UCHAR Sccb_tag;
547 UCHAR Sccb_scsistat;
548 UCHAR Sccb_idmsg; /* image of last msg in */
549 PSCCB Sccb_forwardlink;
550 PSCCB Sccb_backlink;
551 ULONG Sccb_savedATC;
552 UCHAR Save_Cdb[6];
553 UCHAR Save_CdbLen;
554 UCHAR Sccb_XferState;
555 ULONG Sccb_SGoffset;
556 #if (FW_TYPE == _UCB_MGR_)
557 PUCB Sccb_ucb_ptr;
558 #endif
559 } SCCB;
560
561 #define SCCB_SIZE sizeof(SCCB)
562
563 #pragma pack()
564
565
566
567 #define SCSI_INITIATOR_COMMAND 0x00
568 #define TARGET_MODE_COMMAND 0x01
569 #define SCATTER_GATHER_COMMAND 0x02
570 #define RESIDUAL_COMMAND 0x03
571 #define RESIDUAL_SG_COMMAND 0x04
572 #define RESET_COMMAND 0x81
573
574
575 #define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */
576 #define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */
577 #define TAG_Q_MASK 0xE0
578 #define SCCB_DATA_XFER_OUT 0x10 /* Write */
579 #define SCCB_DATA_XFER_IN 0x08 /* Read */
580
581
582 #define FOURTEEN_BYTES 0x00 /* Request Sense Buffer size */
583 #define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */
584
585
586 #define BUS_FREE_ST 0
587 #define SELECT_ST 1
588 #define SELECT_BDR_ST 2 /* Select w\ Bus Device Reset */
589 #define SELECT_SN_ST 3 /* Select w\ Sync Nego */
590 #define SELECT_WN_ST 4 /* Select w\ Wide Data Nego */
591 #define SELECT_Q_ST 5 /* Select w\ Tagged Q'ing */
592 #define COMMAND_ST 6
593 #define DATA_OUT_ST 7
594 #define DATA_IN_ST 8
595 #define DISCONNECT_ST 9
596 #define STATUS_ST 10
597 #define ABORT_ST 11
598 #define MESSAGE_ST 12
599
600
601 #define F_HOST_XFER_DIR 0x01
602 #define F_ALL_XFERRED 0x02
603 #define F_SG_XFER 0x04
604 #define F_AUTO_SENSE 0x08
605 #define F_ODD_BALL_CNT 0x10
606 #define F_NO_DATA_YET 0x80
607
608
609 #define F_STATUSLOADED 0x01
610 #define F_MSGLOADED 0x02
611 #define F_DEV_SELECTED 0x04
612
613
614 #define SCCB_COMPLETE 0x00 /* SCCB completed without error */
615 #define SCCB_DATA_UNDER_RUN 0x0C
616 #define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */
617 #define SCCB_DATA_OVER_RUN 0x12
618 #define SCCB_UNEXPECTED_BUS_FREE 0x13 /* Target dropped SCSI BSY */
619 #define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */
620
621 #define SCCB_INVALID_OP_CODE 0x16 /* SCCB invalid operation code */
622 #define SCCB_INVALID_SCCB 0x1A /* Invalid SCCB - bad parameter */
623 #define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */
624 #define SCCB_BM_ERR 0x30 /* BusMaster error. */
625 #define SCCB_PARITY_ERR 0x34 /* SCSI parity error */
626
627
628
629 #if (FW_TYPE==_UCB_MGR_)
630 #define HBA_AUTO_SENSE_FAIL 0x1B
631 #define HBA_TQ_REJECTED 0x1C
632 #define HBA_UNSUPPORTED_MSG 0x1D
633 #define HBA_HW_ERROR 0x20
634 #define HBA_ATN_NOT_RESPONDED 0x21
635 #define HBA_SCSI_RESET_BY_ADAPTER 0x22
636 #define HBA_SCSI_RESET_BY_TARGET 0x23
637 #define HBA_WRONG_CONNECTION 0x24
638 #define HBA_BUS_DEVICE_RESET 0x25
639 #define HBA_ABORT_QUEUE 0x26
640
641 #else // these are not defined in BUDI/UCB
642
643 #define SCCB_INVALID_DIRECTION 0x18 /* Invalid target direction */
644 #define SCCB_DUPLICATE_SCCB 0x19 /* Duplicate SCCB */
645 #define SCCB_SCSI_RST 0x35 /* SCSI RESET detected. */
646
647 #endif // (FW_TYPE==_UCB_MGR_)
648
649
650 #define SCCB_IN_PROCESS 0x00
651 #define SCCB_SUCCESS 0x01
652 #define SCCB_ABORT 0x02
653 #define SCCB_NOT_FOUND 0x03
654 #define SCCB_ERROR 0x04
655 #define SCCB_INVALID 0x05
656
657 #define SCCB_SIZE sizeof(SCCB)
658
659
660
661
662 #if (FW_TYPE == _UCB_MGR_)
663 void SccbMgr_start_sccb(CARD_HANDLE pCurrCard, PUCB p_ucb);
664 s32bits SccbMgr_abort_sccb(CARD_HANDLE pCurrCard, PUCB p_ucb);
665 u08bits SccbMgr_my_int(CARD_HANDLE pCurrCard);
666 s32bits SccbMgr_isr(CARD_HANDLE pCurrCard);
667 void SccbMgr_scsi_reset(CARD_HANDLE pCurrCard);
668 void SccbMgr_timer_expired(CARD_HANDLE pCurrCard);
669 void SccbMgr_unload_card(CARD_HANDLE pCurrCard);
670 void SccbMgr_restore_foreign_state(CARD_HANDLE pCurrCard);
671 void SccbMgr_restore_native_state(CARD_HANDLE pCurrCard);
672 void SccbMgr_save_foreign_state(PADAPTER_INFO pAdapterInfo);
673
674 #endif
675
676
677 #if (FW_TYPE == _SCCB_MGR_)
678
679 #if defined (DOS)
680 int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo);
681 USHORT SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo);
682 void SccbMgr_start_sccb(USHORT pCurrCard, PSCCB p_SCCB);
683 int SccbMgr_abort_sccb(USHORT pCurrCard, PSCCB p_SCCB);
684 UCHAR SccbMgr_my_int(USHORT pCurrCard);
685 int SccbMgr_isr(USHORT pCurrCard);
686 void SccbMgr_scsi_reset(USHORT pCurrCard);
687 void SccbMgr_timer_expired(USHORT pCurrCard);
688 USHORT SccbMgr_status(USHORT pCurrCard);
689 void SccbMgr_unload_card(USHORT pCurrCard);
690
691 #else //non-DOS
692
693 int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo);
694 ULONG SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo);
695 void SccbMgr_start_sccb(ULONG pCurrCard, PSCCB p_SCCB);
696 int SccbMgr_abort_sccb(ULONG pCurrCard, PSCCB p_SCCB);
697 UCHAR SccbMgr_my_int(ULONG pCurrCard);
698 int SccbMgr_isr(ULONG pCurrCard);
699 void SccbMgr_scsi_reset(ULONG pCurrCard);
700 void SccbMgr_enable_int(ULONG pCurrCard);
701 void SccbMgr_disable_int(ULONG pCurrCard);
702 void SccbMgr_timer_expired(ULONG pCurrCard);
703 void SccbMgr_unload_card(ULONG pCurrCard);
704
705 #endif
706 #endif // (FW_TYPE == _SCCB_MGR_)
707
708 #endif /* __SCCB_H__ */
709
710 /*----------------------------------------------------------------------
711 *
712 *
713 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
714 *
715 * This file is available under both the GNU General Public License
716 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
717 *
718 * $Workfile: blx30.h $
719 *
720 * Description: This module contains SCCB/UCB Manager implementation
721 * specific stuff.
722 *
723 * $Date: 1996/11/13 18:34:22 $
724 *
725 * $Revision: 1.10 $
726 *
727 *----------------------------------------------------------------------*/
728
729
730 #ifndef __blx30_H__
731 #define __blx30_H__
732
733 /*#include <globals.h>*/
734
735 #define ORION_FW_REV 3110
736
737
738
739
740 #define HARP_REVD 1
741
742
743 #if defined(DOS)
744 #define QUEUE_DEPTH 8+1 /*1 for Normal disconnect 0 for Q'ing. */
745 #else
746 #define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */
747 #endif // defined(DOS)
748
749 #define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */
750
751 #define WIDE_SCSI 1
752
753 #if defined(WIDE_SCSI)
754 #if defined(DOS)
755 #define MAX_SCSI_TAR 16
756 #define MAX_LUN 8
757 #define LUN_MASK 0x07
758 #else
759 #define MAX_SCSI_TAR 16
760 #define MAX_LUN 32
761 #define LUN_MASK 0x1f
762
763 #endif
764 #else
765 #define MAX_SCSI_TAR 8
766 #define MAX_LUN 8
767 #define LUN_MASK 0x07
768 #endif
769
770 #if defined(HARP_REVA)
771 #define SG_BUF_CNT 15 /*Number of prefetched elements. */
772 #else
773 #define SG_BUF_CNT 16 /*Number of prefetched elements. */
774 #endif
775
776 #define SG_ELEMENT_SIZE 8 /*Eight byte per element. */
777 #define SG_LOCAL_MASK 0x00000000L
778 #define SG_ELEMENT_MASK 0xFFFFFFFFL
779
780
781 #if (FW_TYPE == _UCB_MGR_)
782 #define OPC_DECODE_NORMAL 0x0f7f
783 #endif // _UCB_MGR_
784
785
786
787 #if defined(DOS)
788
789 /*#include <dos.h>*/
790 #define RD_HARPOON(ioport) (OS_InPortByte(ioport))
791 #define RDW_HARPOON(ioport) (OS_InPortWord(ioport))
792 #define WR_HARPOON(ioport,val) (OS_OutPortByte(ioport,val))
793 #define WRW_HARPOON(ioport,val) (OS_OutPortWord(ioport,val))
794
795 #define RD_HARP32(port,offset,data) asm{db 66h; \
796 push ax; \
797 mov dx,port; \
798 add dx, offset; \
799 db 66h; \
800 in ax,dx; \
801 db 66h; \
802 mov word ptr data,ax;\
803 db 66h; \
804 pop ax}
805
806 #define WR_HARP32(port,offset,data) asm{db 66h; \
807 push ax; \
808 mov dx,port; \
809 add dx, offset; \
810 db 66h; \
811 mov ax,word ptr data;\
812 db 66h; \
813 out dx,ax; \
814 db 66h; \
815 pop ax}
816 #endif /* DOS */
817
818 #if defined(NETWARE) || defined(OTHER_32) || defined(OTHER_16)
819 #define RD_HARPOON(ioport) OS_InPortByte((unsigned long)ioport)
820 #define RDW_HARPOON(ioport) OS_InPortWord((unsigned long)ioport)
821 #define RD_HARP32(ioport,offset,data) (data = OS_InPortLong(ioport + offset))
822 #define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
823 #define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
824 #define WR_HARP32(ioport,offset,data) OS_OutPortLong((ioport + offset), data)
825 #endif /* NETWARE || OTHER_32 || OTHER_16 */
826
827 #if defined(NT) || defined(WIN95_32) || defined(WIN95_16)
828 #define RD_HARPOON(ioport) OS_InPortByte((ULONG)ioport)
829 #define RDW_HARPOON(ioport) OS_InPortWord((ULONG)ioport)
830 #define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((ULONG)(ioport + offset)))
831 #define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
832 #define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
833 #define WR_HARP32(ioport,offset,data) OS_OutPortLong((ULONG)(ioport + offset), data)
834 #endif /* NT || WIN95_32 || WIN95_16 */
835
836 #if defined (UNIX)
837 #define RD_HARPOON(ioport) OS_InPortByte((u32bits)ioport)
838 #define RDW_HARPOON(ioport) OS_InPortWord((u32bits)ioport)
839 #define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((u32bits)(ioport + offset)))
840 #define WR_HARPOON(ioport,val) OS_OutPortByte((u32bits)ioport,(u08bits) val)
841 #define WRW_HARPOON(ioport,val) OS_OutPortWord((u32bits)ioport,(u16bits)val)
842 #define WR_HARP32(ioport,offset,data) OS_OutPortLong((u32bits)(ioport + offset), data)
843 #endif /* UNIX */
844
845 #if defined(OS2)
846 #define RD_HARPOON(ioport) OS_InPortByte((unsigned long)ioport)
847 #define RDW_HARPOON(ioport) OS_InPortWord((unsigned long)ioport)
848 #define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((ULONG)(ioport + offset)))
849 #define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
850 #define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
851 #define WR_HARP32(ioport,offset,data) OS_OutPortLong(((ULONG)(ioport + offset)), data)
852 #endif /* OS2 */
853
854 #if defined(SOLARIS_REAL_MODE)
855
856 #define RD_HARPOON(ioport) OS_InPortByte((unsigned long)ioport)
857 #define RDW_HARPOON(ioport) OS_InPortWord((unsigned long)ioport)
858 #define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((ULONG)(ioport + offset)))
859 #define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
860 #define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
861 #define WR_HARP32(ioport,offset,data) OS_OutPortLong((ULONG)(ioport + offset), (ULONG)data)
862
863 #endif /* SOLARIS_REAL_MODE */
864
865 #endif /* __BLX30_H__ */
866
867
868 /*----------------------------------------------------------------------
869 *
870 *
871 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
872 *
873 * This file is available under both the GNU General Public License
874 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
875 *
876 * $Workfile: target.h $
877 *
878 * Description: Definitions for Target related structures
879 *
880 * $Date: 1996/12/11 22:06:20 $
881 *
882 * $Revision: 1.9 $
883 *
884 *----------------------------------------------------------------------*/
885
886 #ifndef __TARGET__
887 #define __TARGET__
888
889 /*#include <globals.h>*/
890 /*#include <blx30.h>*/
891
892
893 #define TAR_SYNC_MASK (BIT(7)+BIT(6))
894 #define SYNC_UNKNOWN 0x00
895 #define SYNC_TRYING BIT(6)
896 #define SYNC_SUPPORTED (BIT(7)+BIT(6))
897
898 #define TAR_WIDE_MASK (BIT(5)+BIT(4))
899 #define WIDE_DISABLED 0x00
900 #define WIDE_ENABLED BIT(4)
901 #define WIDE_NEGOCIATED BIT(5)
902
903 #define TAR_TAG_Q_MASK (BIT(3)+BIT(2))
904 #define TAG_Q_UNKNOWN 0x00
905 #define TAG_Q_TRYING BIT(2)
906 #define TAG_Q_REJECT BIT(3)
907 #define TAG_Q_SUPPORTED (BIT(3)+BIT(2))
908
909 #define TAR_ALLOW_DISC BIT(0)
910
911
912 #define EE_SYNC_MASK (BIT(0)+BIT(1))
913 #define EE_SYNC_ASYNC 0x00
914 #define EE_SYNC_5MB BIT(0)
915 #define EE_SYNC_10MB BIT(1)
916 #define EE_SYNC_20MB (BIT(0)+BIT(1))
917
918 #define EE_ALLOW_DISC BIT(6)
919 #define EE_WIDE_SCSI BIT(7)
920
921
922 #if defined(DOS)
923 typedef struct SCCBMgr_tar_info near *PSCCBMgr_tar_info;
924
925 #elif defined(OS2)
926 typedef struct SCCBMgr_tar_info far *PSCCBMgr_tar_info;
927
928 #else
929 typedef struct SCCBMgr_tar_info *PSCCBMgr_tar_info;
930
931 #endif
932
933
934 typedef struct SCCBMgr_tar_info {
935
936 PSCCB TarSelQ_Head;
937 PSCCB TarSelQ_Tail;
938 UCHAR TarLUN_CA; /*Contingent Allgiance */
939 UCHAR TarTagQ_Cnt;
940 UCHAR TarSelQ_Cnt;
941 UCHAR TarStatus;
942 UCHAR TarEEValue;
943 UCHAR TarSyncCtrl;
944 UCHAR TarReserved[2]; /* for alignment */
945 UCHAR LunDiscQ_Idx[MAX_LUN];
946 UCHAR TarLUNBusy[MAX_LUN];
947 } SCCBMGR_TAR_INFO;
948
949 typedef struct NVRAMInfo {
950 UCHAR niModel; /* Model No. of card */
951 UCHAR niCardNo; /* Card no. */
952 #if defined(DOS)
953 USHORT niBaseAddr; /* Port Address of card */
954 #else
955 ULONG niBaseAddr; /* Port Address of card */
956 #endif
957 UCHAR niSysConf; /* Adapter Configuration byte - Byte 16 of eeprom map */
958 UCHAR niScsiConf; /* SCSI Configuration byte - Byte 17 of eeprom map */
959 UCHAR niScamConf; /* SCAM Configuration byte - Byte 20 of eeprom map */
960 UCHAR niAdapId; /* Host Adapter ID - Byte 24 of eerpom map */
961 UCHAR niSyncTbl[MAX_SCSI_TAR / 2]; /* Sync/Wide byte of targets */
962 UCHAR niScamTbl[MAX_SCSI_TAR][4]; /* Compressed Scam name string of Targets */
963 }NVRAMINFO;
964
965 #if defined(DOS)
966 typedef NVRAMINFO near *PNVRamInfo;
967 #elif defined (OS2)
968 typedef NVRAMINFO far *PNVRamInfo;
969 #else
970 typedef NVRAMINFO *PNVRamInfo;
971 #endif
972
973 #define MODEL_LT 1
974 #define MODEL_DL 2
975 #define MODEL_LW 3
976 #define MODEL_DW 4
977
978
979 typedef struct SCCBcard {
980 PSCCB currentSCCB;
981 #if (FW_TYPE==_SCCB_MGR_)
982 PSCCBMGR_INFO cardInfo;
983 #else
984 PADAPTER_INFO cardInfo;
985 #endif
986
987 #if defined(DOS)
988 USHORT ioPort;
989 #else
990 ULONG ioPort;
991 #endif
992
993 USHORT cmdCounter;
994 UCHAR discQCount;
995 UCHAR tagQ_Lst;
996 UCHAR cardIndex;
997 UCHAR scanIndex;
998 UCHAR globalFlags;
999 UCHAR ourId;
1000 PNVRamInfo pNvRamInfo;
1001 PSCCB discQ_Tbl[QUEUE_DEPTH];
1002
1003 }SCCBCARD;
1004
1005 #if defined(DOS)
1006 typedef struct SCCBcard near *PSCCBcard;
1007 #elif defined (OS2)
1008 typedef struct SCCBcard far *PSCCBcard;
1009 #else
1010 typedef struct SCCBcard *PSCCBcard;
1011 #endif
1012
1013
1014 #define F_TAG_STARTED 0x01
1015 #define F_CONLUN_IO 0x02
1016 #define F_DO_RENEGO 0x04
1017 #define F_NO_FILTER 0x08
1018 #define F_GREEN_PC 0x10
1019 #define F_HOST_XFER_ACT 0x20
1020 #define F_NEW_SCCB_CMD 0x40
1021 #define F_UPDATE_EEPROM 0x80
1022
1023
1024 #define ID_STRING_LENGTH 32
1025 #define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */
1026
1027 #define TYPE_CODE1 00 /*No ID yet */
1028
1029 #define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */
1030
1031 #define ASSIGN_ID 0x00
1032 #define SET_P_FLAG 0x01
1033 #define CFG_CMPLT 0x03
1034 #define DOM_MSTR 0x0F
1035 #define SYNC_PTRN 0x1F
1036
1037 #define ID_0_7 0x18
1038 #define ID_8_F 0x11
1039 #define ID_10_17 0x12
1040 #define ID_18_1F 0x0B
1041 #define MISC_CODE 0x14
1042 #define CLR_P_FLAG 0x18
1043 #define LOCATE_ON 0x12
1044 #define LOCATE_OFF 0x0B
1045
1046 #define LVL_1_MST 0x00
1047 #define LVL_2_MST 0x40
1048 #define DOM_LVL_2 0xC0
1049
1050
1051 #define INIT_SELTD 0x01
1052 #define LEVEL2_TAR 0x02
1053
1054
1055 enum scam_id_st { ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,
1056 ID13,ID14,ID15,ID_UNUSED,ID_UNASSIGNED,ID_ASSIGNED,LEGACY,
1057 CLR_PRIORITY,NO_ID_AVAIL };
1058
1059 typedef struct SCCBscam_info {
1060
1061 UCHAR id_string[ID_STRING_LENGTH];
1062 enum scam_id_st state;
1063
1064 } SCCBSCAM_INFO, *PSCCBSCAM_INFO;
1065
1066 #endif
1067 /*----------------------------------------------------------------------
1068 *
1069 *
1070 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
1071 *
1072 * This file is available under both the GNU General Public License
1073 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
1074 *
1075 * $Workfile: scsi2.h $
1076 *
1077 * Description: Register definitions for HARPOON ASIC.
1078 *
1079 * $Date: 1996/11/13 18:32:57 $
1080 *
1081 * $Revision: 1.4 $
1082 *
1083 *----------------------------------------------------------------------*/
1084
1085 #ifndef __SCSI_H__
1086 #define __SCSI_H__
1087
1088
1089
1090 #define SCSI_TEST_UNIT_READY 0x00
1091 #define SCSI_REZERO_UNIT 0x01
1092 #define SCSI_REQUEST_SENSE 0x03
1093 #define SCSI_FORMAT_UNIT 0x04
1094 #define SCSI_REASSIGN 0x07
1095 #define SCSI_READ 0x08
1096 #define SCSI_WRITE 0x0A
1097 #define SCSI_SEEK 0x0B
1098 #define SCSI_INQUIRY 0x12
1099 #define SCSI_MODE_SELECT 0x15
1100 #define SCSI_RESERVE_UNIT 0x16
1101 #define SCSI_RELEASE_UNIT 0x17
1102 #define SCSI_MODE_SENSE 0x1A
1103 #define SCSI_START_STOP_UNIT 0x1B
1104 #define SCSI_SEND_DIAGNOSTIC 0x1D
1105 #define SCSI_READ_CAPACITY 0x25
1106 #define SCSI_READ_EXTENDED 0x28
1107 #define SCSI_WRITE_EXTENDED 0x2A
1108 #define SCSI_SEEK_EXTENDED 0x2B
1109 #define SCSI_WRITE_AND_VERIFY 0x2E
1110 #define SCSI_VERIFY 0x2F
1111 #define SCSI_READ_DEFECT_DATA 0x37
1112 #define SCSI_WRITE_BUFFER 0x3B
1113 #define SCSI_READ_BUFFER 0x3C
1114 #define SCSI_RECV_DIAGNOSTIC 0x1C
1115 #define SCSI_READ_LONG 0x3E
1116 #define SCSI_WRITE_LONG 0x3F
1117 #define SCSI_LAST_SCSI_CMND SCSI_WRITE_LONG
1118 #define SCSI_INVALID_CMND 0xFF
1119
1120
1121
1122 #define SSGOOD 0x00
1123 #define SSCHECK 0x02
1124 #define SSCOND_MET 0x04
1125 #define SSBUSY 0x08
1126 #define SSRESERVATION_CONFLICT 0x18
1127 #define SSCMD_TERM 0x22
1128 #define SSQ_FULL 0x28
1129
1130
1131 #define SKNO_SEN 0x00
1132 #define SKRECOV_ERR 0x01
1133 #define SKNOT_RDY 0x02
1134 #define SKMED_ERR 0x03
1135 #define SKHW_ERR 0x04
1136 #define SKILL_REQ 0x05
1137 #define SKUNIT_ATTN 0x06
1138 #define SKDATA_PROTECT 0x07
1139 #define SKBLNK_CHK 0x08
1140 #define SKCPY_ABORT 0x0A
1141 #define SKABORT_CMD 0x0B
1142 #define SKEQUAL 0x0C
1143 #define SKVOL_OVF 0x0D
1144 #define SKMIS_CMP 0x0E
1145
1146
1147 #define SMCMD_COMP 0x00
1148 #define SMEXT 0x01
1149 #define SMSAVE_DATA_PTR 0x02
1150 #define SMREST_DATA_PTR 0x03
1151 #define SMDISC 0x04
1152 #define SMINIT_DETEC_ERR 0x05
1153 #define SMABORT 0x06
1154 #define SMREJECT 0x07
1155 #define SMNO_OP 0x08
1156 #define SMPARITY 0x09
1157 #define SMDEV_RESET 0x0C
1158 #define SMABORT_TAG 0x0D
1159 #define SMINIT_RECOVERY 0x0F
1160 #define SMREL_RECOVERY 0x10
1161
1162 #define SMIDENT 0x80
1163 #define DISC_PRIV 0x40
1164
1165
1166 #define SMSYNC 0x01
1167 #define SM10MBS 0x19 /* 100ns */
1168 #define SM5MBS 0x32 /* 200ns */
1169 #define SMOFFSET 0x0F /* Maxoffset value */
1170 #define SMWDTR 0x03
1171 #define SM8BIT 0x00
1172 #define SM16BIT 0x01
1173 #define SM32BIT 0x02
1174 #define SMIGNORWR 0x23 /* Ignore Wide Residue */
1175
1176
1177 #define ARBITRATION_DELAY 0x01 /* 2.4us using a 40Mhz clock */
1178 #define BUS_SETTLE_DELAY 0x01 /* 400ns */
1179 #define BUS_CLEAR_DELAY 0x01 /* 800ns */
1180
1181
1182
1183 #define SPHASE_TO 0x0A /* 10 second timeout waiting for */
1184 #define SCMD_TO 0x0F /* Overall command timeout */
1185
1186
1187
1188 #define SIX_BYTE_CMD 0x06
1189 #define TEN_BYTE_CMD 0x0A
1190 #define TWELVE_BYTE_CMD 0x0C
1191
1192 #define ASYNC 0x00
1193 #define PERI25NS 0x06 /* 25/4ns to next clock for xbow. */
1194 #define SYNC10MBS 0x19
1195 #define SYNC5MBS 0x32
1196 #define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */
1197
1198 #endif
1199 /*----------------------------------------------------------------------
1200 *
1201 *
1202 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
1203 *
1204 * This file is available under both the GNU General Public License
1205 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
1206 *
1207 * $Workfile: eeprom.h $
1208 *
1209 * Description: Definitions for EEPROM related structures
1210 *
1211 * $Date: 1996/11/13 18:28:39 $
1212 *
1213 * $Revision: 1.4 $
1214 *
1215 *----------------------------------------------------------------------*/
1216
1217 #ifndef __EEPROM__
1218 #define __EEPROM__
1219
1220 /*#include <globals.h>*/
1221
1222 #define EEPROM_WD_CNT 256
1223
1224 #define EEPROM_CHECK_SUM 0
1225 #define FW_SIGNATURE 2
1226 #define MODEL_NUMB_0 4
1227 #define MODEL_NUMB_1 5
1228 #define MODEL_NUMB_2 6
1229 #define MODEL_NUMB_3 7
1230 #define MODEL_NUMB_4 8
1231 #define MODEL_NUMB_5 9
1232 #define IO_BASE_ADDR 10
1233 #define IRQ_NUMBER 12
1234 #define PCI_INT_PIN 13
1235 #define BUS_DELAY 14 /*On time in byte 14 off delay in 15 */
1236 #define SYSTEM_CONFIG 16
1237 #define SCSI_CONFIG 17
1238 #define BIOS_CONFIG 18
1239 #define SPIN_UP_DELAY 19
1240 #define SCAM_CONFIG 20
1241 #define ADAPTER_SCSI_ID 24
1242
1243
1244 #define IGNORE_B_SCAN 32
1245 #define SEND_START_ENA 34
1246 #define DEVICE_ENABLE 36
1247
1248 #define SYNC_RATE_TBL 38
1249 #define SYNC_RATE_TBL01 38
1250 #define SYNC_RATE_TBL23 40
1251 #define SYNC_RATE_TBL45 42
1252 #define SYNC_RATE_TBL67 44
1253 #define SYNC_RATE_TBL89 46
1254 #define SYNC_RATE_TBLab 48
1255 #define SYNC_RATE_TBLcd 50
1256 #define SYNC_RATE_TBLef 52
1257
1258
1259
1260 #define EE_SCAMBASE 256
1261
1262
1263
1264 #define DOM_MASTER (BIT(0) + BIT(1))
1265 #define SCAM_ENABLED BIT(2)
1266 #define SCAM_LEVEL2 BIT(3)
1267
1268
1269 #define RENEGO_ENA BITW(10)
1270 #define CONNIO_ENA BITW(11)
1271 #define GREEN_PC_ENA BITW(12)
1272
1273
1274 #define AUTO_RATE_00 00
1275 #define AUTO_RATE_05 01
1276 #define AUTO_RATE_10 02
1277 #define AUTO_RATE_20 03
1278
1279 #define WIDE_NEGO_BIT BIT(7)
1280 #define DISC_ENABLE_BIT BIT(6)
1281
1282
1283 #endif
1284 /*----------------------------------------------------------------------
1285 *
1286 *
1287 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
1288 *
1289 * This file is available under both the GNU General Public License
1290 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
1291 *
1292 * $Workfile: harpoon.h $
1293 *
1294 * Description: Register definitions for HARPOON ASIC.
1295 *
1296 * $Date: 1997/07/09 21:44:36 $
1297 *
1298 * $Revision: 1.9 $
1299 *
1300 *----------------------------------------------------------------------*/
1301
1302
1303 /*#include <globals.h>*/
1304
1305 #ifndef __HARPOON__
1306 #define __HARPOON__
1307
1308
1309 #define hp_vendor_id_0 0x00 /* LSB */
1310 #define ORION_VEND_0 0x4B
1311
1312 #define hp_vendor_id_1 0x01 /* MSB */
1313 #define ORION_VEND_1 0x10
1314
1315 #define hp_device_id_0 0x02 /* LSB */
1316 #define ORION_DEV_0 0x30
1317
1318 #define hp_device_id_1 0x03 /* MSB */
1319 #define ORION_DEV_1 0x81
1320
1321 /* Sub Vendor ID and Sub Device ID only available in
1322 Harpoon Version 2 and higher */
1323
1324 #define hp_sub_vendor_id_0 0x04 /* LSB */
1325 #define hp_sub_vendor_id_1 0x05 /* MSB */
1326 #define hp_sub_device_id_0 0x06 /* LSB */
1327 #define hp_sub_device_id_1 0x07 /* MSB */
1328
1329
1330 #define hp_dual_addr_lo 0x08
1331 #define hp_dual_addr_lmi 0x09
1332 #define hp_dual_addr_hmi 0x0A
1333 #define hp_dual_addr_hi 0x0B
1334
1335 #define hp_semaphore 0x0C
1336 #define SCCB_MGR_ACTIVE BIT(0)
1337 #define TICKLE_ME BIT(1)
1338 #define SCCB_MGR_PRESENT BIT(3)
1339 #define BIOS_IN_USE BIT(4)
1340
1341 #define hp_user_defined_D 0x0D
1342
1343 #define hp_reserved_E 0x0E
1344
1345 #define hp_sys_ctrl 0x0F
1346
1347 #define STOP_CLK BIT(0) /*Turn off BusMaster Clock */
1348 #define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */
1349 #define HALT_MACH BIT(3) /*Halt State Machine */
1350 #define HARD_ABORT BIT(4) /*Hard Abort */
1351 #define DIAG_MODE BIT(5) /*Diagnostic Mode */
1352
1353 #define BM_ABORT_TMOUT 0x50 /*Halt State machine time out */
1354
1355 #define hp_sys_cfg 0x10
1356
1357 #define DONT_RST_FIFO BIT(7) /*Don't reset FIFO */
1358
1359
1360 #define hp_host_ctrl0 0x11
1361
1362 #define DUAL_ADDR_MODE BIT(0) /*Enable 64-bit addresses */
1363 #define IO_MEM_SPACE BIT(1) /*I/O Memory Space */
1364 #define RESOURCE_LOCK BIT(2) /*Enable Resource Lock */
1365 #define IGNOR_ACCESS_ERR BIT(3) /*Ignore Access Error */
1366 #define HOST_INT_EDGE BIT(4) /*Host interrupt level/edge mode sel */
1367 #define SIX_CLOCKS BIT(5) /*6 Clocks between Strobe */
1368 #define DMA_EVEN_PARITY BIT(6) /*Enable DMA Enen Parity */
1369
1370 /*
1371 #define BURST_MODE BIT(0)
1372 */
1373
1374 #define hp_reserved_12 0x12
1375
1376 #define hp_host_blk_cnt 0x13
1377
1378 #define XFER_BLK1 0x00 /* 0 0 0 1 byte per block*/
1379 #define XFER_BLK2 0x01 /* 0 0 1 2 byte per block*/
1380 #define XFER_BLK4 0x02 /* 0 1 0 4 byte per block*/
1381 #define XFER_BLK8 0x03 /* 0 1 1 8 byte per block*/
1382 #define XFER_BLK16 0x04 /* 1 0 0 16 byte per block*/
1383 #define XFER_BLK32 0x05 /* 1 0 1 32 byte per block*/
1384 #define XFER_BLK64 0x06 /* 1 1 0 64 byte per block*/
1385
1386 #define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes*/
1387
1388
1389 #define hp_reserved_14 0x14
1390 #define hp_reserved_15 0x15
1391 #define hp_reserved_16 0x16
1392
1393 #define hp_int_mask 0x17
1394
1395 #define INT_CMD_COMPL BIT(0) /* DMA command complete */
1396 #define INT_EXT_STATUS BIT(1) /* Extended Status Set */
1397 #define INT_SCSI BIT(2) /* Scsi block interrupt */
1398 #define INT_FIFO_RDY BIT(4) /* FIFO data ready */
1399
1400
1401 #define hp_xfer_cnt_lo 0x18
1402 #define hp_xfer_cnt_mi 0x19
1403 #define hp_xfer_cnt_hi 0x1A
1404 #define hp_xfer_cmd 0x1B
1405
1406 #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */
1407 #define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */
1408 #define XFER_HOST_MPU 0x02 /* 0 1 0 Transfer Host -> MPU */
1409 #define XFER_MPU_HOST 0x03 /* 0 1 1 Transfer MPU -> Host */
1410 #define XFER_DMA_MPU 0x04 /* 1 0 0 Transfer DMA -> MPU */
1411 #define XFER_MPU_DMA 0x05 /* 1 0 1 Transfer MPU -> DMA */
1412 #define SET_SEMAPHORE 0x06 /* 1 1 0 Set Semaphore */
1413 #define XFER_NOP 0x07 /* 1 1 1 Transfer NOP */
1414 #define XFER_MB_MPU 0x06 /* 1 1 0 Transfer MB -> MPU */
1415 #define XFER_MB_DMA 0x07 /* 1 1 1 Transfer MB -> DMA */
1416
1417
1418 #define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */
1419 #define XFER_HOST_8BIT 0x08 /* 0 1 8 BIT Transfer Size */
1420 #define XFER_HOST_16BIT 0x10 /* 1 0 16 BIT Transfer Size */
1421 #define XFER_HOST_32BIT 0x18 /* 1 1 32 BIT Transfer Size */
1422
1423 #define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */
1424 #define XFER_DMA_16BIT 0x40 /* 1 0 16 BIT Transfer Size */
1425
1426 #define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */
1427
1428 #define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT))
1429 #define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT))
1430 #define WIDE_HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_16BIT))
1431 #define WIDE_HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_16BIT))
1432
1433 #define hp_host_addr_lo 0x1C
1434 #define hp_host_addr_lmi 0x1D
1435 #define hp_host_addr_hmi 0x1E
1436 #define hp_host_addr_hi 0x1F
1437
1438 #define hp_pio_data 0x20
1439 #define hp_reserved_21 0x21
1440 #define hp_ee_ctrl 0x22
1441
1442 #define EXT_ARB_ACK BIT(7)
1443 #define SCSI_TERM_ENA_H BIT(6) /* SCSI high byte terminator */
1444 #define SEE_MS BIT(5)
1445 #define SEE_CS BIT(3)
1446 #define SEE_CLK BIT(2)
1447 #define SEE_DO BIT(1)
1448 #define SEE_DI BIT(0)
1449
1450 #define EE_READ 0x06
1451 #define EE_WRITE 0x05
1452 #define EWEN 0x04
1453 #define EWEN_ADDR 0x03C0
1454 #define EWDS 0x04
1455 #define EWDS_ADDR 0x0000
1456
1457 #define hp_brdctl 0x23
1458
1459 #define DAT_7 BIT(7)
1460 #define DAT_6 BIT(6)
1461 #define DAT_5 BIT(5)
1462 #define BRD_STB BIT(4)
1463 #define BRD_CS BIT(3)
1464 #define BRD_WR BIT(2)
1465
1466 #define hp_reserved_24 0x24
1467 #define hp_reserved_25 0x25
1468
1469
1470
1471
1472 #define hp_bm_ctrl 0x26
1473
1474 #define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */
1475 #define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */
1476 #define BM_XFER_MIN_8 BIT(2) /*Enable bus master transfer of 9 */
1477 #define BIOS_ENA BIT(3) /*Enable BIOS/FLASH Enable */
1478 #define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */
1479 #define FAST_SINGLE BIT(6) /*?? */
1480
1481 #define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L)
1482
1483 #define hp_reserved_27 0x27
1484
1485 #define hp_sg_addr 0x28
1486 #define hp_page_ctrl 0x29
1487
1488 #define SCATTER_EN BIT(0)
1489 #define SGRAM_ARAM BIT(1)
1490 #define BIOS_SHADOW BIT(2)
1491 #define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */
1492 #define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */
1493
1494 #define hp_reserved_2A 0x2A
1495 #define hp_pci_cmd_cfg 0x2B
1496
1497 #define IO_SPACE_ENA BIT(0) /*enable I/O space */
1498 #define MEM_SPACE_ENA BIT(1) /*enable memory space */
1499 #define BUS_MSTR_ENA BIT(2) /*enable bus master operation */
1500 #define MEM_WI_ENA BIT(4) /*enable Write and Invalidate */
1501 #define PAR_ERR_RESP BIT(6) /*enable parity error responce. */
1502
1503 #define hp_reserved_2C 0x2C
1504
1505 #define hp_pci_stat_cfg 0x2D
1506
1507 #define DATA_PARITY_ERR BIT(0)
1508 #define REC_TARGET_ABORT BIT(4) /*received Target abort */
1509 #define REC_MASTER_ABORT BIT(5) /*received Master abort */
1510 #define SIG_SYSTEM_ERR BIT(6)
1511 #define DETECTED_PAR_ERR BIT(7)
1512
1513 #define hp_reserved_2E 0x2E
1514
1515 #define hp_sys_status 0x2F
1516
1517 #define SLV_DATA_RDY BIT(0) /*Slave data ready */
1518 #define XFER_CNT_ZERO BIT(1) /*Transfer counter = 0 */
1519 #define BM_FIFO_EMPTY BIT(2) /*FIFO empty */
1520 #define BM_FIFO_FULL BIT(3) /*FIFO full */
1521 #define HOST_OP_DONE BIT(4) /*host operation done */
1522 #define DMA_OP_DONE BIT(5) /*DMA operation done */
1523 #define SLV_OP_DONE BIT(6) /*Slave operation done */
1524 #define PWR_ON_FLAG BIT(7) /*Power on flag */
1525
1526 #define hp_reserved_30 0x30
1527
1528 #define hp_host_status0 0x31
1529
1530 #define HOST_TERM BIT(5) /*Host Terminal Count */
1531 #define HOST_TRSHLD BIT(6) /*Host Threshold */
1532 #define CONNECTED_2_HOST BIT(7) /*Connected to Host */
1533
1534 #define hp_reserved_32 0x32
1535
1536 #define hp_rev_num 0x33
1537
1538 #define REV_A_CONST 0x0E
1539 #define REV_B_CONST 0x0E
1540
1541 #define hp_stack_data 0x34
1542 #define hp_stack_addr 0x35
1543
1544 #define hp_ext_status 0x36
1545
1546 #define BM_FORCE_OFF BIT(0) /*Bus Master is forced to get off */
1547 #define PCI_TGT_ABORT BIT(0) /*PCI bus master transaction aborted */
1548 #define PCI_DEV_TMOUT BIT(1) /*PCI Device Time out */
1549 #define FIFO_TC_NOT_ZERO BIT(2) /*FIFO or transfer counter not zero */
1550 #define CHIP_RST_OCCUR BIT(3) /*Chip reset occurs */
1551 #define CMD_ABORTED BIT(4) /*Command aborted */
1552 #define BM_PARITY_ERR BIT(5) /*parity error on data received */
1553 #define PIO_OVERRUN BIT(6) /*Slave data overrun */
1554 #define BM_CMD_BUSY BIT(7) /*Bus master transfer command busy */
1555 #define BAD_EXT_STATUS (BM_FORCE_OFF | PCI_DEV_TMOUT | CMD_ABORTED | \
1556 BM_PARITY_ERR | PIO_OVERRUN)
1557
1558 #define hp_int_status 0x37
1559
1560 #define BM_CMD_CMPL BIT(0) /*Bus Master command complete */
1561 #define EXT_STATUS_ON BIT(1) /*Extended status is valid */
1562 #define SCSI_INTERRUPT BIT(2) /*Global indication of a SCSI int. */
1563 #define BM_FIFO_RDY BIT(4)
1564 #define INT_ASSERTED BIT(5) /* */
1565 #define SRAM_BUSY BIT(6) /*Scatter/Gather RAM busy */
1566 #define CMD_REG_BUSY BIT(7)
1567
1568
1569 #define hp_fifo_cnt 0x38
1570 #define hp_curr_host_cnt 0x39
1571 #define hp_reserved_3A 0x3A
1572 #define hp_fifo_in_addr 0x3B
1573
1574 #define hp_fifo_out_addr 0x3C
1575 #define hp_reserved_3D 0x3D
1576 #define hp_reserved_3E 0x3E
1577 #define hp_reserved_3F 0x3F
1578
1579
1580
1581 extern USHORT default_intena;
1582
1583 #define hp_intena 0x40
1584
1585 #define RESET BITW(7)
1586 #define PROG_HLT BITW(6)
1587 #define PARITY BITW(5)
1588 #define FIFO BITW(4)
1589 #define SEL BITW(3)
1590 #define SCAM_SEL BITW(2)
1591 #define RSEL BITW(1)
1592 #define TIMEOUT BITW(0)
1593 #define BUS_FREE BITW(15)
1594 #define XFER_CNT_0 BITW(14)
1595 #define PHASE BITW(13)
1596 #define IUNKWN BITW(12)
1597 #define ICMD_COMP BITW(11)
1598 #define ITICKLE BITW(10)
1599 #define IDO_STRT BITW(9)
1600 #define ITAR_DISC BITW(8)
1601 #define AUTO_INT (BITW(12)+BITW(11)+BITW(10)+BITW(9)+BITW(8))
1602 #define CLR_ALL_INT 0xFFFF
1603 #define CLR_ALL_INT_1 0xFF00
1604
1605 #define hp_intstat 0x42
1606
1607 #define hp_scsisig 0x44
1608
1609 #define SCSI_SEL BIT(7)
1610 #define SCSI_BSY BIT(6)
1611 #define SCSI_REQ BIT(5)
1612 #define SCSI_ACK BIT(4)
1613 #define SCSI_ATN BIT(3)
1614 #define SCSI_CD BIT(2)
1615 #define SCSI_MSG BIT(1)
1616 #define SCSI_IOBIT BIT(0)
1617
1618 #define S_SCSI_PHZ (BIT(2)+BIT(1)+BIT(0))
1619 #define S_CMD_PH (BIT(2) )
1620 #define S_MSGO_PH (BIT(2)+BIT(1) )
1621 #define S_STAT_PH (BIT(2) +BIT(0))
1622 #define S_MSGI_PH (BIT(2)+BIT(1)+BIT(0))
1623 #define S_DATAI_PH ( BIT(0))
1624 #define S_DATAO_PH 0x00
1625 #define S_ILL_PH ( BIT(1) )
1626
1627 #define hp_scsictrl_0 0x45
1628
1629 #define NO_ARB BIT(7)
1630 #define SEL_TAR BIT(6)
1631 #define ENA_ATN BIT(4)
1632 #define ENA_RESEL BIT(2)
1633 #define SCSI_RST BIT(1)
1634 #define ENA_SCAM_SEL BIT(0)
1635
1636
1637
1638 #define hp_portctrl_0 0x46
1639
1640 #define SCSI_PORT BIT(7)
1641 #define SCSI_INBIT BIT(6)
1642 #define DMA_PORT BIT(5)
1643 #define DMA_RD BIT(4)
1644 #define HOST_PORT BIT(3)
1645 #define HOST_WRT BIT(2)
1646 #define SCSI_BUS_EN BIT(1)
1647 #define START_TO BIT(0)
1648
1649 #define hp_scsireset 0x47
1650
1651 #define SCSI_TAR BIT(7)
1652 #define SCSI_INI BIT(6)
1653 #define SCAM_EN BIT(5)
1654 #define ACK_HOLD BIT(4)
1655 #define DMA_RESET BIT(3)
1656 #define HPSCSI_RESET BIT(2)
1657 #define PROG_RESET BIT(1)
1658 #define FIFO_CLR BIT(0)
1659
1660 #define hp_xfercnt_0 0x48
1661 #define hp_xfercnt_1 0x49
1662 #define hp_xfercnt_2 0x4A
1663 #define hp_xfercnt_3 0x4B
1664
1665 #define hp_fifodata_0 0x4C
1666 #define hp_fifodata_1 0x4D
1667 #define hp_addstat 0x4E
1668
1669 #define SCAM_TIMER BIT(7)
1670 #define AUTO_RUNNING BIT(6)
1671 #define FAST_SYNC BIT(5)
1672 #define SCSI_MODE8 BIT(3)
1673 #define SCSI_PAR_ERR BIT(0)
1674
1675 #define hp_prgmcnt_0 0x4F
1676
1677 #define AUTO_PC_MASK 0x3F
1678
1679 #define hp_selfid_0 0x50
1680 #define hp_selfid_1 0x51
1681 #define hp_arb_id 0x52
1682
1683 #define ARB_ID (BIT(3) + BIT(2) + BIT(1) + BIT(0))
1684
1685 #define hp_select_id 0x53
1686
1687 #define RESEL_ID (BIT(7) + BIT(6) + BIT(5) + BIT(4))
1688 #define SELECT_ID (BIT(3) + BIT(2) + BIT(1) + BIT(0))
1689
1690 #define hp_synctarg_base 0x54
1691 #define hp_synctarg_12 0x54
1692 #define hp_synctarg_13 0x55
1693 #define hp_synctarg_14 0x56
1694 #define hp_synctarg_15 0x57
1695
1696 #define hp_synctarg_8 0x58
1697 #define hp_synctarg_9 0x59
1698 #define hp_synctarg_10 0x5A
1699 #define hp_synctarg_11 0x5B
1700
1701 #define hp_synctarg_4 0x5C
1702 #define hp_synctarg_5 0x5D
1703 #define hp_synctarg_6 0x5E
1704 #define hp_synctarg_7 0x5F
1705
1706 #define hp_synctarg_0 0x60
1707 #define hp_synctarg_1 0x61
1708 #define hp_synctarg_2 0x62
1709 #define hp_synctarg_3 0x63
1710
1711 #define RATE_20MB 0x00
1712 #define RATE_10MB ( BIT(5))
1713 #define RATE_6_6MB ( BIT(6) )
1714 #define RATE_5MB ( BIT(6)+BIT(5))
1715 #define RATE_4MB (BIT(7) )
1716 #define RATE_3_33MB (BIT(7) +BIT(5))
1717 #define RATE_2_85MB (BIT(7)+BIT(6) )
1718 #define RATE_2_5MB (BIT(7)+BIT(5)+BIT(6))
1719 #define NEXT_CLK BIT(5)
1720 #define SLOWEST_SYNC (BIT(7)+BIT(6)+BIT(5))
1721 #define NARROW_SCSI BIT(4)
1722 #define SYNC_OFFSET (BIT(3) + BIT(2) + BIT(1) + BIT(0))
1723 #define DEFAULT_ASYNC 0x00
1724 #define DEFAULT_OFFSET 0x0F
1725
1726 #define hp_autostart_0 0x64
1727 #define hp_autostart_1 0x65
1728 #define hp_autostart_2 0x66
1729 #define hp_autostart_3 0x67
1730
1731
1732
1733 #define DISABLE 0x00
1734 #define AUTO_IMMED BIT(5)
1735 #define SELECT BIT(6)
1736 #define RESELECT (BIT(6)+BIT(5))
1737 #define BUSFREE BIT(7)
1738 #define XFER_0 (BIT(7)+BIT(5))
1739 #define END_DATA (BIT(7)+BIT(6))
1740 #define MSG_PHZ (BIT(7)+BIT(6)+BIT(5))
1741
1742 #define hp_gp_reg_0 0x68
1743 #define hp_gp_reg_1 0x69
1744 #define hp_gp_reg_2 0x6A
1745 #define hp_gp_reg_3 0x6B
1746
1747 #define hp_seltimeout 0x6C
1748
1749
1750 #define TO_2ms 0x54 /* 2.0503ms */
1751 #define TO_4ms 0x67 /* 3.9959ms */
1752
1753 #define TO_5ms 0x03 /* 4.9152ms */
1754 #define TO_10ms 0x07 /* 11.xxxms */
1755 #define TO_250ms 0x99 /* 250.68ms */
1756 #define TO_290ms 0xB1 /* 289.99ms */
1757 #define TO_350ms 0xD6 /* 350.62ms */
1758 #define TO_417ms 0xFF /* 417.79ms */
1759
1760 #define hp_clkctrl_0 0x6D
1761
1762 #define PWR_DWN BIT(6)
1763 #define ACTdeassert BIT(4)
1764 #define ATNonErr BIT(3)
1765 #define CLK_30MHZ BIT(1)
1766 #define CLK_40MHZ (BIT(1) + BIT(0))
1767 #define CLK_50MHZ BIT(2)
1768
1769 #define CLKCTRL_DEFAULT (ACTdeassert | CLK_40MHZ)
1770
1771 #define hp_fiforead 0x6E
1772 #define hp_fifowrite 0x6F
1773
1774 #define hp_offsetctr 0x70
1775 #define hp_xferstat 0x71
1776
1777 #define FIFO_FULL BIT(7)
1778 #define FIFO_EMPTY BIT(6)
1779 #define FIFO_MASK 0x3F /* Mask for the FIFO count value. */
1780 #define FIFO_LEN 0x20
1781
1782 #define hp_portctrl_1 0x72
1783
1784 #define EVEN_HOST_P BIT(5)
1785 #define INVT_SCSI BIT(4)
1786 #define CHK_SCSI_P BIT(3)
1787 #define HOST_MODE8 BIT(0)
1788 #define HOST_MODE16 0x00
1789
1790 #define hp_xfer_pad 0x73
1791
1792 #define ID_UNLOCK BIT(3)
1793 #define XFER_PAD BIT(2)
1794
1795 #define hp_scsidata_0 0x74
1796 #define hp_scsidata_1 0x75
1797 #define hp_timer_0 0x76
1798 #define hp_timer_1 0x77
1799
1800 #define hp_reserved_78 0x78
1801 #define hp_reserved_79 0x79
1802 #define hp_reserved_7A 0x7A
1803 #define hp_reserved_7B 0x7B
1804
1805 #define hp_reserved_7C 0x7C
1806 #define hp_reserved_7D 0x7D
1807 #define hp_reserved_7E 0x7E
1808 #define hp_reserved_7F 0x7F
1809
1810 #define hp_aramBase 0x80
1811 #define BIOS_DATA_OFFSET 0x60
1812 #define BIOS_RELATIVE_CARD 0x64
1813
1814
1815
1816
1817 #define AUTO_LEN 0x80
1818 #define AR0 0x00
1819 #define AR1 BITW(8)
1820 #define AR2 BITW(9)
1821 #define AR3 (BITW(9) + BITW(8))
1822 #define SDATA BITW(10)
1823
1824 #define NOP_OP 0x00 /* Nop command */
1825
1826 #define CRD_OP BITW(11) /* Cmp Reg. w/ Data */
1827
1828 #define CRR_OP BITW(12) /* Cmp Reg. w. Reg. */
1829
1830 #define CBE_OP (BITW(14)+BITW(12)+BITW(11)) /* Cmp SCSI cmd class & Branch EQ */
1831
1832 #define CBN_OP (BITW(14)+BITW(13)) /* Cmp SCSI cmd class & Branch NOT EQ */
1833
1834 #define CPE_OP (BITW(14)+BITW(11)) /* Cmp SCSI phs & Branch EQ */
1835
1836 #define CPN_OP (BITW(14)+BITW(12)) /* Cmp SCSI phs & Branch NOT EQ */
1837
1838
1839 #define ADATA_OUT 0x00
1840 #define ADATA_IN BITW(8)
1841 #define ACOMMAND BITW(10)
1842 #define ASTATUS (BITW(10)+BITW(8))
1843 #define AMSG_OUT (BITW(10)+BITW(9))
1844 #define AMSG_IN (BITW(10)+BITW(9)+BITW(8))
1845 #define AILLEGAL (BITW(9)+BITW(8))
1846
1847
1848 #define BRH_OP BITW(13) /* Branch */
1849
1850
1851 #define ALWAYS 0x00
1852 #define EQUAL BITW(8)
1853 #define NOT_EQ BITW(9)
1854
1855 #define TCB_OP (BITW(13)+BITW(11)) /* Test condition & branch */
1856
1857
1858 #define ATN_SET BITW(8)
1859 #define ATN_RESET BITW(9)
1860 #define XFER_CNT (BITW(9)+BITW(8))
1861 #define FIFO_0 BITW(10)
1862 #define FIFO_NOT0 (BITW(10)+BITW(8))
1863 #define T_USE_SYNC0 (BITW(10)+BITW(9))
1864
1865
1866 #define MPM_OP BITW(15) /* Match phase and move data */
1867
1868 #define MDR_OP (BITW(12)+BITW(11)) /* Move data to Reg. */
1869
1870 #define MRR_OP BITW(14) /* Move DReg. to Reg. */
1871
1872
1873 #define S_IDREG (BIT(2)+BIT(1)+BIT(0))
1874
1875
1876 #define D_AR0 0x00
1877 #define D_AR1 BIT(0)
1878 #define D_AR2 BIT(1)
1879 #define D_AR3 (BIT(1) + BIT(0))
1880 #define D_SDATA BIT(2)
1881 #define D_BUCKET (BIT(2) + BIT(1) + BIT(0))
1882
1883
1884 #define ADR_OP (BITW(13)+BITW(12)) /* Logical AND Reg. w. Data */
1885
1886 #define ADS_OP (BITW(14)+BITW(13)+BITW(12))
1887
1888 #define ODR_OP (BITW(13)+BITW(12)+BITW(11))
1889
1890 #define ODS_OP (BITW(14)+BITW(13)+BITW(12)+BITW(11))
1891
1892 #define STR_OP (BITW(15)+BITW(14)) /* Store to A_Reg. */
1893
1894 #define AINT_ENA1 0x00
1895 #define AINT_STAT1 BITW(8)
1896 #define ASCSI_SIG BITW(9)
1897 #define ASCSI_CNTL (BITW(9)+BITW(8))
1898 #define APORT_CNTL BITW(10)
1899 #define ARST_CNTL (BITW(10)+BITW(8))
1900 #define AXFERCNT0 (BITW(10)+BITW(9))
1901 #define AXFERCNT1 (BITW(10)+BITW(9)+BITW(8))
1902 #define AXFERCNT2 BITW(11)
1903 #define AFIFO_DATA (BITW(11)+BITW(8))
1904 #define ASCSISELID (BITW(11)+BITW(9))
1905 #define ASCSISYNC0 (BITW(11)+BITW(9)+BITW(8))
1906
1907
1908 #define RAT_OP (BITW(14)+BITW(13)+BITW(11))
1909
1910 #define SSI_OP (BITW(15)+BITW(11))
1911
1912
1913 #define SSI_ITAR_DISC (ITAR_DISC >> 8)
1914 #define SSI_IDO_STRT (IDO_STRT >> 8)
1915 #define SSI_IDI_STRT (IDO_STRT >> 8)
1916
1917 #define SSI_ICMD_COMP (ICMD_COMP >> 8)
1918 #define SSI_ITICKLE (ITICKLE >> 8)
1919
1920 #define SSI_IUNKWN (IUNKWN >> 8)
1921 #define SSI_INO_CC (IUNKWN >> 8)
1922 #define SSI_IRFAIL (IUNKWN >> 8)
1923
1924
1925 #define NP 0x10 /*Next Phase */
1926 #define NTCMD 0x02 /*Non- Tagged Command start */
1927 #define CMDPZ 0x04 /*Command phase */
1928 #define DINT 0x12 /*Data Out/In interrupt */
1929 #define DI 0x13 /*Data Out */
1930 #define MI 0x14 /*Message In */
1931 #define DC 0x19 /*Disconnect Message */
1932 #define ST 0x1D /*Status Phase */
1933 #define UNKNWN 0x24 /*Unknown bus action */
1934 #define CC 0x25 /*Command Completion failure */
1935 #define TICK 0x26 /*New target reselected us. */
1936 #define RFAIL 0x27 /*Reselection failed */
1937 #define SELCHK 0x28 /*Select & Check SCSI ID latch reg */
1938
1939
1940 #define ID_MSG_STRT hp_aramBase + 0x00
1941 #define NON_TAG_ID_MSG hp_aramBase + 0x06
1942 #define CMD_STRT hp_aramBase + 0x08
1943 #define SYNC_MSGS hp_aramBase + 0x08
1944
1945
1946
1947
1948
1949 #define TAG_STRT 0x00
1950 #define SELECTION_START 0x00
1951 #define DISCONNECT_START 0x10/2
1952 #define END_DATA_START 0x14/2
1953 #define NONTAG_STRT 0x02/2
1954 #define CMD_ONLY_STRT CMDPZ/2
1955 #define TICKLE_STRT TICK/2
1956 #define SELCHK_STRT SELCHK/2
1957
1958
1959
1960
1961 #define mEEPROM_CLK_DELAY(port) (RD_HARPOON(port+hp_intstat_1))
1962
1963 #define mWAIT_10MS(port) (RD_HARPOON(port+hp_intstat_1))
1964
1965
1966 #define CLR_XFER_CNT(port) (WR_HARPOON(port+hp_xfercnt_0, 0x00))
1967
1968 #define SET_XFER_CNT(port, data) (WR_HARP32(port,hp_xfercnt_0,data))
1969
1970 #define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;}
1971 /* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2), \
1972 xfercnt <<= 16,\
1973 xfercnt |= RDW_HARPOON((USHORT)(port+hp_xfercnt_0)))
1974 */
1975 #if defined(DOS)
1976 #define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((USHORT)(port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),\
1977 addr >>= 16,\
1978 WRW_HARPOON((USHORT)(port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),\
1979 WR_HARP32(port,hp_xfercnt_0,count),\
1980 WRW_HARPOON((USHORT)(port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),\
1981 count >>= 16,\
1982 WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
1983 #else
1984 #define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),\
1985 addr >>= 16,\
1986 WRW_HARPOON((port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),\
1987 WR_HARP32(port,hp_xfercnt_0,count),\
1988 WRW_HARPOON((port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),\
1989 count >>= 16,\
1990 WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
1991 #endif
1992
1993 #define ACCEPT_MSG(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
1994 WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
1995
1996
1997 #define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
1998 WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
1999
2000 #define ACCEPT_STAT(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
2001 WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
2002
2003 #define ACCEPT_STAT_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
2004 WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
2005
2006 #define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),\
2007 WR_HARPOON(port+hp_scsireset, 0x00))
2008
2009 #define ARAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
2010 (RD_HARPOON(p_port+hp_page_ctrl) | SGRAM_ARAM)))
2011
2012 #define SGRAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
2013 (RD_HARPOON(p_port+hp_page_ctrl) & ~SGRAM_ARAM)))
2014
2015 #define MDISABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
2016 (RD_HARPOON(p_port+hp_page_ctrl) | G_INT_DISABLE)))
2017
2018 #define MENABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
2019 (RD_HARPOON(p_port+hp_page_ctrl) & ~G_INT_DISABLE)))
2020
2021
2022
2023 #endif
2024
2025
2026 #if (FW_TYPE==_UCB_MGR_)
2027 void ReadNVRam(PSCCBcard pCurrCard,PUCB p_ucb);
2028 void WriteNVRam(PSCCBcard pCurrCard,PUCB p_ucb);
2029 void UpdateCheckSum(u32bits baseport);
2030 #endif // (FW_TYPE==_UCB_MGR_)
2031
2032 #if defined(DOS)
2033 UCHAR sfm(USHORT port, PSCCB pcurrSCCB);
2034 void scsiStartAuto(USHORT port);
2035 UCHAR sisyncn(USHORT port, UCHAR p_card, UCHAR syncFlag);
2036 void ssel(USHORT port, UCHAR p_card);
2037 void sres(USHORT port, UCHAR p_card, PSCCBcard pCurrCard);
2038 void sdecm(UCHAR message, USHORT port, UCHAR p_card);
2039 void shandem(USHORT port, UCHAR p_card,PSCCB pCurrSCCB);
2040 void stsyncn(USHORT port, UCHAR p_card);
2041 void sisyncr(USHORT port,UCHAR sync_pulse, UCHAR offset);
2042 void sssyncv(USHORT p_port, UCHAR p_id, UCHAR p_sync_value, PSCCBMgr_tar_info currTar_Info);
2043 void sresb(USHORT port, UCHAR p_card);
2044 void sxfrp(USHORT p_port, UCHAR p_card);
2045 void schkdd(USHORT port, UCHAR p_card);
2046 UCHAR RdStack(USHORT port, UCHAR index);
2047 void WrStack(USHORT portBase, UCHAR index, UCHAR data);
2048 UCHAR ChkIfChipInitialized(USHORT ioPort);
2049
2050 #if defined(V302)
2051 UCHAR GetTarLun(USHORT port, UCHAR p_card, UCHAR our_target, PSCCBcard pCurrCard, PUCHAR tag, PUCHAR lun);
2052 #endif
2053
2054 void SendMsg(USHORT port, UCHAR message);
2055 void queueFlushTargSccb(UCHAR p_card, UCHAR thisTarg, UCHAR error_code);
2056 UCHAR scsellDOS(USHORT p_port, UCHAR targ_id);
2057 #else
2058 UCHAR sfm(ULONG port, PSCCB pcurrSCCB);
2059 void scsiStartAuto(ULONG port);
2060 UCHAR sisyncn(ULONG port, UCHAR p_card, UCHAR syncFlag);
2061 void ssel(ULONG port, UCHAR p_card);
2062 void sres(ULONG port, UCHAR p_card, PSCCBcard pCurrCard);
2063 void sdecm(UCHAR message, ULONG port, UCHAR p_card);
2064 void shandem(ULONG port, UCHAR p_card,PSCCB pCurrSCCB);
2065 void stsyncn(ULONG port, UCHAR p_card);
2066 void sisyncr(ULONG port,UCHAR sync_pulse, UCHAR offset);
2067 void sssyncv(ULONG p_port, UCHAR p_id, UCHAR p_sync_value, PSCCBMgr_tar_info currTar_Info);
2068 void sresb(ULONG port, UCHAR p_card);
2069 void sxfrp(ULONG p_port, UCHAR p_card);
2070 void schkdd(ULONG port, UCHAR p_card);
2071 UCHAR RdStack(ULONG port, UCHAR index);
2072 void WrStack(ULONG portBase, UCHAR index, UCHAR data);
2073 UCHAR ChkIfChipInitialized(ULONG ioPort);
2074
2075 #if defined(V302)
2076 UCHAR GetTarLun(ULONG port, UCHAR p_card, UCHAR our_target, PSCCBcard pCurrCard, PUCHAR tar, PUCHAR lun);
2077 #endif
2078
2079 void SendMsg(ULONG port, UCHAR message);
2080 void queueFlushTargSccb(UCHAR p_card, UCHAR thisTarg, UCHAR error_code);
2081 #endif
2082
2083 void ssenss(PSCCBcard pCurrCard);
2084 void sinits(PSCCB p_sccb, UCHAR p_card);
2085 void RNVRamData(PNVRamInfo pNvRamInfo);
2086
2087 #if defined(WIDE_SCSI)
2088 #if defined(DOS)
2089 UCHAR siwidn(USHORT port, UCHAR p_card);
2090 void stwidn(USHORT port, UCHAR p_card);
2091 void siwidr(USHORT port, UCHAR width);
2092 #else
2093 UCHAR siwidn(ULONG port, UCHAR p_card);
2094 void stwidn(ULONG port, UCHAR p_card);
2095 void siwidr(ULONG port, UCHAR width);
2096 #endif
2097 #endif
2098
2099
2100 void queueSelectFail(PSCCBcard pCurrCard, UCHAR p_card);
2101 void queueDisconnect(PSCCB p_SCCB, UCHAR p_card);
2102 void queueCmdComplete(PSCCBcard pCurrCard, PSCCB p_SCCB, UCHAR p_card);
2103 void queueSearchSelect(PSCCBcard pCurrCard, UCHAR p_card);
2104 void queueFlushSccb(UCHAR p_card, UCHAR error_code);
2105 void queueAddSccb(PSCCB p_SCCB, UCHAR card);
2106 UCHAR queueFindSccb(PSCCB p_SCCB, UCHAR p_card);
2107 void utilUpdateResidual(PSCCB p_SCCB);
2108 USHORT CalcCrc16(UCHAR buffer[]);
2109 UCHAR CalcLrc(UCHAR buffer[]);
2110
2111
2112 #if defined(DOS)
2113 void Wait1Second(USHORT p_port);
2114 void Wait(USHORT p_port, UCHAR p_delay);
2115 void utilEEWriteOnOff(USHORT p_port,UCHAR p_mode);
2116 void utilEEWrite(USHORT p_port, USHORT ee_data, USHORT ee_addr);
2117 USHORT utilEERead(USHORT p_port, USHORT ee_addr);
2118 USHORT utilEEReadOrg(USHORT p_port, USHORT ee_addr);
2119 void utilEESendCmdAddr(USHORT p_port, UCHAR ee_cmd, USHORT ee_addr);
2120 #else
2121 void Wait1Second(ULONG p_port);
2122 void Wait(ULONG p_port, UCHAR p_delay);
2123 void utilEEWriteOnOff(ULONG p_port,UCHAR p_mode);
2124 void utilEEWrite(ULONG p_port, USHORT ee_data, USHORT ee_addr);
2125 USHORT utilEERead(ULONG p_port, USHORT ee_addr);
2126 USHORT utilEEReadOrg(ULONG p_port, USHORT ee_addr);
2127 void utilEESendCmdAddr(ULONG p_port, UCHAR ee_cmd, USHORT ee_addr);
2128 #endif
2129
2130
2131
2132 #if defined(OS2)
2133 void far phaseDataOut(ULONG port, UCHAR p_card);
2134 void far phaseDataIn(ULONG port, UCHAR p_card);
2135 void far phaseCommand(ULONG port, UCHAR p_card);
2136 void far phaseStatus(ULONG port, UCHAR p_card);
2137 void far phaseMsgOut(ULONG port, UCHAR p_card);
2138 void far phaseMsgIn(ULONG port, UCHAR p_card);
2139 void far phaseIllegal(ULONG port, UCHAR p_card);
2140 #else
2141 #if defined(DOS)
2142 void phaseDataOut(USHORT port, UCHAR p_card);
2143 void phaseDataIn(USHORT port, UCHAR p_card);
2144 void phaseCommand(USHORT port, UCHAR p_card);
2145 void phaseStatus(USHORT port, UCHAR p_card);
2146 void phaseMsgOut(USHORT port, UCHAR p_card);
2147 void phaseMsgIn(USHORT port, UCHAR p_card);
2148 void phaseIllegal(USHORT port, UCHAR p_card);
2149 #else
2150 void phaseDataOut(ULONG port, UCHAR p_card);
2151 void phaseDataIn(ULONG port, UCHAR p_card);
2152 void phaseCommand(ULONG port, UCHAR p_card);
2153 void phaseStatus(ULONG port, UCHAR p_card);
2154 void phaseMsgOut(ULONG port, UCHAR p_card);
2155 void phaseMsgIn(ULONG port, UCHAR p_card);
2156 void phaseIllegal(ULONG port, UCHAR p_card);
2157 #endif
2158 #endif
2159
2160 #if defined(DOS)
2161 void phaseDecode(USHORT port, UCHAR p_card);
2162 void phaseChkFifo(USHORT port, UCHAR p_card);
2163 void phaseBusFree(USHORT p_port, UCHAR p_card);
2164 #else
2165 void phaseDecode(ULONG port, UCHAR p_card);
2166 void phaseChkFifo(ULONG port, UCHAR p_card);
2167 void phaseBusFree(ULONG p_port, UCHAR p_card);
2168 #endif
2169
2170
2171
2172
2173 #if defined(DOS)
2174 void XbowInit(USHORT port, UCHAR scamFlg);
2175 void BusMasterInit(USHORT p_port);
2176 int DiagXbow(USHORT port);
2177 int DiagBusMaster(USHORT port);
2178 void DiagEEPROM(USHORT p_port);
2179 #else
2180 void XbowInit(ULONG port, UCHAR scamFlg);
2181 void BusMasterInit(ULONG p_port);
2182 int DiagXbow(ULONG port);
2183 int DiagBusMaster(ULONG port);
2184 void DiagEEPROM(ULONG p_port);
2185 #endif
2186
2187
2188
2189
2190 #if defined(DOS)
2191 void busMstrAbort(USHORT port);
2192 UCHAR busMstrTimeOut(USHORT port);
2193 void dataXferProcessor(USHORT port, PSCCBcard pCurrCard);
2194 void busMstrSGDataXferStart(USHORT port, PSCCB pCurrSCCB);
2195 void busMstrDataXferStart(USHORT port, PSCCB pCurrSCCB);
2196 void hostDataXferAbort(USHORT port, UCHAR p_card, PSCCB pCurrSCCB);
2197 #else
2198 void busMstrAbort(ULONG port);
2199 UCHAR busMstrTimeOut(ULONG port);
2200 void dataXferProcessor(ULONG port, PSCCBcard pCurrCard);
2201 void busMstrSGDataXferStart(ULONG port, PSCCB pCurrSCCB);
2202 void busMstrDataXferStart(ULONG port, PSCCB pCurrSCCB);
2203 void hostDataXferAbort(ULONG port, UCHAR p_card, PSCCB pCurrSCCB);
2204 #endif
2205 void hostDataXferRestart(PSCCB currSCCB);
2206
2207
2208 #if defined (DOS)
2209 UCHAR SccbMgr_bad_isr(USHORT p_port, UCHAR p_card, PSCCBcard pCurrCard, USHORT p_int);
2210 #else
2211 UCHAR SccbMgr_bad_isr(ULONG p_port, UCHAR p_card, PSCCBcard pCurrCard, USHORT p_int);
2212
2213 #endif
2214
2215 void SccbMgrTableInitAll(void);
2216 void SccbMgrTableInitCard(PSCCBcard pCurrCard, UCHAR p_card);
2217 void SccbMgrTableInitTarget(UCHAR p_card, UCHAR target);
2218
2219
2220
2221 void scini(UCHAR p_card, UCHAR p_our_id, UCHAR p_power_up);
2222
2223 #if defined(DOS)
2224 int scarb(USHORT p_port, UCHAR p_sel_type);
2225 void scbusf(USHORT p_port);
2226 void scsel(USHORT p_port);
2227 void scasid(UCHAR p_card, USHORT p_port);
2228 UCHAR scxferc(USHORT p_port, UCHAR p_data);
2229 UCHAR scsendi(USHORT p_port, UCHAR p_id_string[]);
2230 UCHAR sciso(USHORT p_port, UCHAR p_id_string[]);
2231 void scwirod(USHORT p_port, UCHAR p_data_bit);
2232 void scwiros(USHORT p_port, UCHAR p_data_bit);
2233 UCHAR scvalq(UCHAR p_quintet);
2234 UCHAR scsell(USHORT p_port, UCHAR targ_id);
2235 void scwtsel(USHORT p_port);
2236 void inisci(UCHAR p_card, USHORT p_port, UCHAR p_our_id);
2237 void scsavdi(UCHAR p_card, USHORT p_port);
2238 #else
2239 int scarb(ULONG p_port, UCHAR p_sel_type);
2240 void scbusf(ULONG p_port);
2241 void scsel(ULONG p_port);
2242 void scasid(UCHAR p_card, ULONG p_port);
2243 UCHAR scxferc(ULONG p_port, UCHAR p_data);
2244 UCHAR scsendi(ULONG p_port, UCHAR p_id_string[]);
2245 UCHAR sciso(ULONG p_port, UCHAR p_id_string[]);
2246 void scwirod(ULONG p_port, UCHAR p_data_bit);
2247 void scwiros(ULONG p_port, UCHAR p_data_bit);
2248 UCHAR scvalq(UCHAR p_quintet);
2249 UCHAR scsell(ULONG p_port, UCHAR targ_id);
2250 void scwtsel(ULONG p_port);
2251 void inisci(UCHAR p_card, ULONG p_port, UCHAR p_our_id);
2252 void scsavdi(UCHAR p_card, ULONG p_port);
2253 #endif
2254 UCHAR scmachid(UCHAR p_card, UCHAR p_id_string[]);
2255
2256
2257 #if defined(DOS)
2258 void autoCmdCmplt(USHORT p_port, UCHAR p_card);
2259 void autoLoadDefaultMap(USHORT p_port);
2260 #else
2261 void autoCmdCmplt(ULONG p_port, UCHAR p_card);
2262 void autoLoadDefaultMap(ULONG p_port);
2263 #endif
2264
2265
2266
2267 #if (FW_TYPE==_SCCB_MGR_)
2268 void OS_start_timer(unsigned long ioport, unsigned long timeout);
2269 void OS_stop_timer(unsigned long ioport, unsigned long timeout);
2270 void OS_disable_int(unsigned char intvec);
2271 void OS_enable_int(unsigned char intvec);
2272 void OS_delay(unsigned long count);
2273 int OS_VirtToPhys(u32bits CardHandle, u32bits *physaddr, u32bits *virtaddr);
2274 #if !(defined(UNIX) || defined(OS2) || defined(SOLARIS_REAL_MODE))
2275 void OS_Lock(PSCCBMGR_INFO pCardInfo);
2276 void OS_UnLock(PSCCBMGR_INFO pCardInfo);
2277 #endif // if FW_TYPE == ...
2278
2279 #endif
2280
2281 extern SCCBCARD BL_Card[MAX_CARDS];
2282 extern SCCBMGR_TAR_INFO sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR];
2283
2284
2285 #if defined(OS2)
2286 extern void (far *s_PhaseTbl[8]) (ULONG, UCHAR);
2287 #else
2288 #if defined(DOS)
2289 extern void (*s_PhaseTbl[8]) (USHORT, UCHAR);
2290 #else
2291 extern void (*s_PhaseTbl[8]) (ULONG, UCHAR);
2292 #endif
2293 #endif
2294
2295 extern SCCBSCAM_INFO scamInfo[MAX_SCSI_TAR];
2296 extern NVRAMINFO nvRamInfo[MAX_MB_CARDS];
2297 #if defined(DOS) || defined(OS2)
2298 extern UCHAR temp_id_string[ID_STRING_LENGTH];
2299 #endif
2300 extern UCHAR scamHAString[];
2301
2302
2303 extern UCHAR mbCards;
2304 #if defined(BUGBUG)
2305 extern UCHAR debug_int[MAX_CARDS][debug_size];
2306 extern UCHAR debug_index[MAX_CARDS];
2307 void Debug_Load(UCHAR p_card, UCHAR p_bug_data);
2308 #endif
2309
2310 #if (FW_TYPE==_SCCB_MGR_)
2311 #if defined(DOS)
2312 extern UCHAR first_time;
2313 #endif
2314 #endif /* (FW_TYPE==_SCCB_MGR_) */
2315
2316 #if (FW_TYPE==_UCB_MGR_)
2317 #if defined(DOS)
2318 extern u08bits first_time;
2319 #endif
2320 #endif /* (FW_TYPE==_UCB_MGR_) */
2321
2322 #if defined(BUGBUG)
2323 void Debug_Load(UCHAR p_card, UCHAR p_bug_data);
2324 #endif
2325
2326 extern unsigned int SccbGlobalFlags;
2327
2328
2329 #ident "$Id: sccb.c 1.18 1997/06/10 16:47:04 mohan Exp $"
2330 /*----------------------------------------------------------------------
2331 *
2332 *
2333 * Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
2334 *
2335 * This file is available under both the GNU General Public License
2336 * and a BSD-style copyright; see LICENSE.FlashPoint for details.
2337 *
2338 * $Workfile: sccb.c $
2339 *
2340 * Description: Functions relating to handling of the SCCB interface
2341 * between the device driver and the HARPOON.
2342 *
2343 * $Date: 1997/06/10 16:47:04 $
2344 *
2345 * $Revision: 1.18 $
2346 *
2347 *----------------------------------------------------------------------*/
2348
2349 /*#include <globals.h>*/
2350
2351 #if (FW_TYPE==_UCB_MGR_)
2352 /*#include <budi.h>*/
2353 /*#include <budioctl.h>*/
2354 #endif
2355
2356 /*#include <sccbmgr.h>*/
2357 /*#include <blx30.h>*/
2358 /*#include <target.h>*/
2359 /*#include <eeprom.h>*/
2360 /*#include <scsi2.h>*/
2361 /*#include <harpoon.h>*/
2362
2363
2364
2365 #if (FW_TYPE==_SCCB_MGR_)
2366 #define mOS_Lock(card) OS_Lock((PSCCBMGR_INFO)(((PSCCBcard)card)->cardInfo))
2367 #define mOS_UnLock(card) OS_UnLock((PSCCBMGR_INFO)(((PSCCBcard)card)->cardInfo))
2368 #else /* FW_TYPE==_UCB_MGR_ */
2369 #define mOS_Lock(card) OS_Lock((u32bits)(((PSCCBcard)card)->ioPort))
2370 #define mOS_UnLock(card) OS_UnLock((u32bits)(((PSCCBcard)card)->ioPort))
2371 #endif
2372
2373
2374 /*
2375 extern SCCBMGR_TAR_INFO sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR];
2376 extern SCCBCARD BL_Card[MAX_CARDS];
2377
2378 extern NVRAMINFO nvRamInfo[MAX_MB_CARDS];
2379 extern UCHAR mbCards;
2380
2381 #if defined (OS2)
2382 extern void (far *s_PhaseTbl[8]) (ULONG, UCHAR);
2383 #else
2384 #if defined(DOS)
2385 extern void (*s_PhaseTbl[8]) (USHORT, UCHAR);
2386 #else
2387 extern void (*s_PhaseTbl[8]) (ULONG, UCHAR);
2388 #endif
2389 #endif
2390
2391
2392 #if defined(BUGBUG)
2393 extern UCHAR debug_int[MAX_CARDS][debug_size];
2394 extern UCHAR debug_index[MAX_CARDS];
2395 void Debug_Load(UCHAR p_card, UCHAR p_bug_data);
2396 #endif
2397 */
2398
2399 #if (FW_TYPE==_SCCB_MGR_)
2400
2401 /*---------------------------------------------------------------------
2402 *
2403 * Function: SccbMgr_sense_adapter
2404 *
2405 * Description: Setup and/or Search for cards and return info to caller.
2406 *
2407 *---------------------------------------------------------------------*/
2408
2409 int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo)
2410 {
2411 #if defined(DOS)
2412 #else
2413 static UCHAR first_time = 1;
2414 #endif
2415
2416 UCHAR i,j,id,ScamFlg;
2417 USHORT temp,temp2,temp3,temp4,temp5,temp6;
2418 #if defined(DOS)
2419 USHORT ioport;
2420 #else
2421 ULONG ioport;
2422 #endif
2423 PNVRamInfo pCurrNvRam;
2424
2425 #if defined(DOS)
2426 ioport = (USHORT)pCardInfo->si_baseaddr;
2427 #else
2428 ioport = pCardInfo->si_baseaddr;
2429 #endif
2430
2431
2432 if (RD_HARPOON(ioport+hp_vendor_id_0) != ORION_VEND_0)
2433 return((int)FAILURE);
2434
2435 if ((RD_HARPOON(ioport+hp_vendor_id_1) != ORION_VEND_1))
2436 return((int)FAILURE);
2437
2438 if ((RD_HARPOON(ioport+hp_device_id_0) != ORION_DEV_0))
2439 return((int)FAILURE);
2440
2441 if ((RD_HARPOON(ioport+hp_device_id_1) != ORION_DEV_1))
2442 return((int)FAILURE);
2443
2444
2445 if (RD_HARPOON(ioport+hp_rev_num) != 0x0f){
2446
2447 /* For new Harpoon then check for sub_device ID LSB
2448 the bits(0-3) must be all ZERO for compatible with
2449 current version of SCCBMgr, else skip this Harpoon
2450 device. */
2451
2452 if (RD_HARPOON(ioport+hp_sub_device_id_0) & 0x0f)
2453 return((int)FAILURE);
2454 }
2455
2456 if (first_time)
2457 {
2458 SccbMgrTableInitAll();
2459 first_time = 0;
2460 mbCards = 0;
2461 }
2462
2463 if(RdStack(ioport, 0) != 0x00) {
2464 if(ChkIfChipInitialized(ioport) == FALSE)
2465 {
2466 pCurrNvRam = NULL;
2467 WR_HARPOON(ioport+hp_semaphore, 0x00);
2468 XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
2469 DiagEEPROM(ioport);
2470 }
2471 else
2472 {
2473 if(mbCards < MAX_MB_CARDS) {
2474 pCurrNvRam = &nvRamInfo[mbCards];
2475 mbCards++;
2476 pCurrNvRam->niBaseAddr = ioport;
2477 RNVRamData(pCurrNvRam);
2478 }else
2479 return((int) FAILURE);
2480 }
2481 }else
2482 pCurrNvRam = NULL;
2483 #if defined (NO_BIOS_OPTION)
2484 pCurrNvRam = NULL;
2485 XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
2486 DiagEEPROM(ioport);
2487 #endif /* No BIOS Option */
2488
2489 WR_HARPOON(ioport+hp_clkctrl_0, CLKCTRL_DEFAULT);
2490 WR_HARPOON(ioport+hp_sys_ctrl, 0x00);
2491
2492 if(pCurrNvRam)
2493 pCardInfo->si_id = pCurrNvRam->niAdapId;
2494 else
2495 pCardInfo->si_id = (UCHAR)(utilEERead(ioport, (ADAPTER_SCSI_ID/2)) &
2496 (UCHAR)0x0FF);
2497
2498 pCardInfo->si_lun = 0x00;
2499 pCardInfo->si_fw_revision = ORION_FW_REV;
2500 temp2 = 0x0000;
2501 temp3 = 0x0000;
2502 temp4 = 0x0000;
2503 temp5 = 0x0000;
2504 temp6 = 0x0000;
2505
2506 for (id = 0; id < (16/2); id++) {
2507
2508 if(pCurrNvRam){
2509 temp = (USHORT) pCurrNvRam->niSyncTbl[id];
2510 temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
2511 (((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
2512 }else
2513 temp = utilEERead(ioport, (USHORT)((SYNC_RATE_TBL/2)+id));
2514
2515 for (i = 0; i < 2; temp >>=8,i++) {
2516
2517 temp2 >>= 1;
2518 temp3 >>= 1;
2519 temp4 >>= 1;
2520 temp5 >>= 1;
2521 temp6 >>= 1;
2522 switch (temp & 0x3)
2523 {
2524 case AUTO_RATE_20: /* Synchronous, 20 mega-transfers/second */
2525 temp6 |= 0x8000; /* Fall through */
2526 case AUTO_RATE_10: /* Synchronous, 10 mega-transfers/second */
2527 temp5 |= 0x8000; /* Fall through */
2528 case AUTO_RATE_05: /* Synchronous, 5 mega-transfers/second */
2529 temp2 |= 0x8000; /* Fall through */
2530 case AUTO_RATE_00: /* Asynchronous */
2531 break;
2532 }
2533
2534 if (temp & DISC_ENABLE_BIT)
2535 temp3 |= 0x8000;
2536
2537 if (temp & WIDE_NEGO_BIT)
2538 temp4 |= 0x8000;
2539
2540 }
2541 }
2542
2543 pCardInfo->si_per_targ_init_sync = temp2;
2544 pCardInfo->si_per_targ_no_disc = temp3;
2545 pCardInfo->si_per_targ_wide_nego = temp4;
2546 pCardInfo->si_per_targ_fast_nego = temp5;
2547 pCardInfo->si_per_targ_ultra_nego = temp6;
2548
2549 if(pCurrNvRam)
2550 i = pCurrNvRam->niSysConf;
2551 else
2552 i = (UCHAR)(utilEERead(ioport, (SYSTEM_CONFIG/2)));
2553
2554 if(pCurrNvRam)
2555 ScamFlg = pCurrNvRam->niScamConf;
2556 else
2557 ScamFlg = (UCHAR) utilEERead(ioport, SCAM_CONFIG/2);
2558
2559 pCardInfo->si_flags = 0x0000;
2560
2561 if (i & 0x01)
2562 pCardInfo->si_flags |= SCSI_PARITY_ENA;
2563
2564 if (!(i & 0x02))
2565 pCardInfo->si_flags |= SOFT_RESET;
2566
2567 if (i & 0x10)
2568 pCardInfo->si_flags |= EXTENDED_TRANSLATION;
2569
2570 if (ScamFlg & SCAM_ENABLED)
2571 pCardInfo->si_flags |= FLAG_SCAM_ENABLED;
2572
2573 if (ScamFlg & SCAM_LEVEL2)
2574 pCardInfo->si_flags |= FLAG_SCAM_LEVEL2;
2575
2576 j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
2577 if (i & 0x04) {
2578 j |= SCSI_TERM_ENA_L;
2579 }
2580 WR_HARPOON(ioport+hp_bm_ctrl, j );
2581
2582 j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
2583 if (i & 0x08) {
2584 j |= SCSI_TERM_ENA_H;
2585 }
2586 WR_HARPOON(ioport+hp_ee_ctrl, j );
2587
2588 if (!(RD_HARPOON(ioport+hp_page_ctrl) & NARROW_SCSI_CARD))
2589
2590 pCardInfo->si_flags |= SUPPORT_16TAR_32LUN;
2591
2592 pCardInfo->si_card_family = HARPOON_FAMILY;
2593 pCardInfo->si_bustype = BUSTYPE_PCI;
2594
2595 if(pCurrNvRam){
2596 pCardInfo->si_card_model[0] = '9';
2597 switch(pCurrNvRam->niModel & 0x0f){
2598 case MODEL_LT:
2599 pCardInfo->si_card_model[1] = '3';
2600 pCardInfo->si_card_model[2] = '0';
2601 break;
2602 case MODEL_LW:
2603 pCardInfo->si_card_model[1] = '5';
2604 pCardInfo->si_card_model[2] = '0';
2605 break;
2606 case MODEL_DL:
2607 pCardInfo->si_card_model[1] = '3';
2608 pCardInfo->si_card_model[2] = '2';
2609 break;
2610 case MODEL_DW:
2611 pCardInfo->si_card_model[1] = '5';
2612 pCardInfo->si_card_model[2] = '2';
2613 break;
2614 }
2615 }else{
2616 temp = utilEERead(ioport, (MODEL_NUMB_0/2));
2617 pCardInfo->si_card_model[0] = (UCHAR)(temp >> 8);
2618 temp = utilEERead(ioport, (MODEL_NUMB_2/2));
2619
2620 pCardInfo->si_card_model[1] = (UCHAR)(temp & 0x00FF);
2621 pCardInfo->si_card_model[2] = (UCHAR)(temp >> 8);
2622 }
2623
2624 if (pCardInfo->si_card_model[1] == '3')
2625 {
2626 if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
2627 pCardInfo->si_flags |= LOW_BYTE_TERM;
2628 }
2629 else if (pCardInfo->si_card_model[2] == '0')
2630 {
2631 temp = RD_HARPOON(ioport+hp_xfer_pad);
2632 WR_HARPOON(ioport+hp_xfer_pad, (temp & ~BIT(4)));
2633 if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
2634 pCardInfo->si_flags |= LOW_BYTE_TERM;
2635 WR_HARPOON(ioport+hp_xfer_pad, (temp | BIT(4)));
2636 if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
2637 pCardInfo->si_flags |= HIGH_BYTE_TERM;
2638 WR_HARPOON(ioport+hp_xfer_pad, temp);
2639 }
2640 else
2641 {
2642 temp = RD_HARPOON(ioport+hp_ee_ctrl);
2643 temp2 = RD_HARPOON(ioport+hp_xfer_pad);
2644 WR_HARPOON(ioport+hp_ee_ctrl, (temp | SEE_CS));
2645 WR_HARPOON(ioport+hp_xfer_pad, (temp2 | BIT(4)));
2646 temp3 = 0;
2647 for (i = 0; i < 8; i++)
2648 {
2649 temp3 <<= 1;
2650 if (!(RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7)))
2651 temp3 |= 1;
2652 WR_HARPOON(ioport+hp_xfer_pad, (temp2 & ~BIT(4)));
2653 WR_HARPOON(ioport+hp_xfer_pad, (temp2 | BIT(4)));
2654 }
2655 WR_HARPOON(ioport+hp_ee_ctrl, temp);
2656 WR_HARPOON(ioport+hp_xfer_pad, temp2);
2657 if (!(temp3 & BIT(7)))
2658 pCardInfo->si_flags |= LOW_BYTE_TERM;
2659 if (!(temp3 & BIT(6)))
2660 pCardInfo->si_flags |= HIGH_BYTE_TERM;
2661 }
2662
2663
2664 ARAM_ACCESS(ioport);
2665
2666 for ( i = 0; i < 4; i++ ) {
2667
2668 pCardInfo->si_XlatInfo[i] =
2669 RD_HARPOON(ioport+hp_aramBase+BIOS_DATA_OFFSET+i);
2670 }
2671
2672 /* return with -1 if no sort, else return with
2673 logical card number sorted by BIOS (zero-based) */
2674
2675 pCardInfo->si_relative_cardnum =
2676 (UCHAR)(RD_HARPOON(ioport+hp_aramBase+BIOS_RELATIVE_CARD)-1);
2677
2678 SGRAM_ACCESS(ioport);
2679
2680 s_PhaseTbl[0] = phaseDataOut;
2681 s_PhaseTbl[1] = phaseDataIn;
2682 s_PhaseTbl[2] = phaseIllegal;
2683 s_PhaseTbl[3] = phaseIllegal;
2684 s_PhaseTbl[4] = phaseCommand;
2685 s_PhaseTbl[5] = phaseStatus;
2686 s_PhaseTbl[6] = phaseMsgOut;
2687 s_PhaseTbl[7] = phaseMsgIn;
2688
2689 pCardInfo->si_present = 0x01;
2690
2691 #if defined(BUGBUG)
2692
2693
2694 for (i = 0; i < MAX_CARDS; i++) {
2695
2696 for (id=0; id<debug_size; id++)
2697 debug_int[i][id] = (UCHAR)0x00;
2698 debug_index[i] = 0;
2699 }
2700
2701 #endif
2702
2703 return(0);
2704 }
2705
2706
2707 /*---------------------------------------------------------------------
2708 *
2709 * Function: SccbMgr_config_adapter
2710 *
2711 * Description: Setup adapter for normal operation (hard reset).
2712 *
2713 *---------------------------------------------------------------------*/
2714
2715 #if defined(DOS)
2716 USHORT SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo)
2717 #else
2718 ULONG SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo)
2719 #endif
2720 {
2721 PSCCBcard CurrCard = NULL;
2722 PNVRamInfo pCurrNvRam;
2723 UCHAR i,j,thisCard, ScamFlg;
2724 USHORT temp,sync_bit_map,id;
2725 #if defined(DOS)
2726 USHORT ioport;
2727 #else
2728 ULONG ioport;
2729 #endif
2730
2731 #if defined(DOS)
2732 ioport = (USHORT)pCardInfo->si_baseaddr;
2733 #else
2734 ioport = pCardInfo->si_baseaddr;
2735 #endif
2736
2737 for(thisCard =0; thisCard <= MAX_CARDS; thisCard++) {
2738
2739 if (thisCard == MAX_CARDS) {
2740
2741 return(FAILURE);
2742 }
2743
2744 if (BL_Card[thisCard].ioPort == ioport) {
2745
2746 CurrCard = &BL_Card[thisCard];
2747 SccbMgrTableInitCard(CurrCard,thisCard);
2748 break;
2749 }
2750
2751 else if (BL_Card[thisCard].ioPort == 0x00) {
2752
2753 BL_Card[thisCard].ioPort = ioport;
2754 CurrCard = &BL_Card[thisCard];
2755
2756 if(mbCards)
2757 for(i = 0; i < mbCards; i++){
2758 if(CurrCard->ioPort == nvRamInfo[i].niBaseAddr)
2759 CurrCard->pNvRamInfo = &nvRamInfo[i];
2760 }
2761 SccbMgrTableInitCard(CurrCard,thisCard);
2762 CurrCard->cardIndex = thisCard;
2763 CurrCard->cardInfo = pCardInfo;
2764
2765 break;
2766 }
2767 }
2768
2769 pCurrNvRam = CurrCard->pNvRamInfo;
2770
2771 if(pCurrNvRam){
2772 ScamFlg = pCurrNvRam->niScamConf;
2773 }
2774 else{
2775 ScamFlg = (UCHAR) utilEERead(ioport, SCAM_CONFIG/2);
2776 }
2777
2778
2779 BusMasterInit(ioport);
2780 XbowInit(ioport, ScamFlg);
2781
2782 #if defined (NO_BIOS_OPTION)
2783
2784
2785 if (DiagXbow(ioport)) return(FAILURE);
2786 if (DiagBusMaster(ioport)) return(FAILURE);
2787
2788 #endif /* No BIOS Option */
2789
2790 autoLoadDefaultMap(ioport);
2791
2792
2793 for (i = 0,id = 0x01; i != pCardInfo->si_id; i++,id <<= 1){}
2794
2795 WR_HARPOON(ioport+hp_selfid_0, id);
2796 WR_HARPOON(ioport+hp_selfid_1, 0x00);
2797 WR_HARPOON(ioport+hp_arb_id, pCardInfo->si_id);
2798 CurrCard->ourId = pCardInfo->si_id;
2799
2800 i = (UCHAR) pCardInfo->si_flags;
2801 if (i & SCSI_PARITY_ENA)
2802 WR_HARPOON(ioport+hp_portctrl_1,(HOST_MODE8 | CHK_SCSI_P));
2803
2804 j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
2805 if (i & LOW_BYTE_TERM)
2806 j |= SCSI_TERM_ENA_L;
2807 WR_HARPOON(ioport+hp_bm_ctrl, j);
2808
2809 j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
2810 if (i & HIGH_BYTE_TERM)
2811 j |= SCSI_TERM_ENA_H;
2812 WR_HARPOON(ioport+hp_ee_ctrl, j );
2813
2814
2815 if (!(pCardInfo->si_flags & SOFT_RESET)) {
2816
2817 sresb(ioport,thisCard);
2818
2819 scini(thisCard, pCardInfo->si_id, 0);
2820 }
2821
2822
2823
2824 if (pCardInfo->si_flags & POST_ALL_UNDERRRUNS)
2825 CurrCard->globalFlags |= F_NO_FILTER;
2826
2827 if(pCurrNvRam){
2828 if(pCurrNvRam->niSysConf & 0x10)
2829 CurrCard->globalFlags |= F_GREEN_PC;
2830 }
2831 else{
2832 if (utilEERead(ioport, (SYSTEM_CONFIG/2)) & GREEN_PC_ENA)
2833 CurrCard->globalFlags |= F_GREEN_PC;
2834 }
2835
2836 /* Set global flag to indicate Re-Negotiation to be done on all
2837 ckeck condition */
2838 if(pCurrNvRam){
2839 if(pCurrNvRam->niScsiConf & 0x04)
2840 CurrCard->globalFlags |= F_DO_RENEGO;
2841 }
2842 else{
2843 if (utilEERead(ioport, (SCSI_CONFIG/2)) & RENEGO_ENA)
2844 CurrCard->globalFlags |= F_DO_RENEGO;
2845 }
2846
2847 if(pCurrNvRam){
2848 if(pCurrNvRam->niScsiConf & 0x08)
2849 CurrCard->globalFlags |= F_CONLUN_IO;
2850 }
2851 else{
2852 if (utilEERead(ioport, (SCSI_CONFIG/2)) & CONNIO_ENA)
2853 CurrCard->globalFlags |= F_CONLUN_IO;
2854 }
2855
2856
2857 temp = pCardInfo->si_per_targ_no_disc;
2858
2859 for (i = 0,id = 1; i < MAX_SCSI_TAR; i++, id <<= 1) {
2860
2861 if (temp & id)
2862 sccbMgrTbl[thisCard][i].TarStatus |= TAR_ALLOW_DISC;
2863 }
2864
2865 sync_bit_map = 0x0001;
2866
2867 for (id = 0; id < (MAX_SCSI_TAR/2); id++) {
2868
2869 if(pCurrNvRam){
2870 temp = (USHORT) pCurrNvRam->niSyncTbl[id];
2871 temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
2872 (((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
2873 }else
2874 temp = utilEERead(ioport, (USHORT)((SYNC_RATE_TBL/2)+id));
2875
2876 for (i = 0; i < 2; temp >>=8,i++) {
2877
2878 if (pCardInfo->si_per_targ_init_sync & sync_bit_map) {
2879
2880 sccbMgrTbl[thisCard][id*2+i].TarEEValue = (UCHAR)temp;
2881 }
2882
2883 else {
2884 sccbMgrTbl[thisCard][id*2+i].TarStatus |= SYNC_SUPPORTED;
2885 sccbMgrTbl[thisCard][id*2+i].TarEEValue =
2886 (UCHAR)(temp & ~EE_SYNC_MASK);
2887 }
2888
2889 #if defined(WIDE_SCSI)
2890 /* if ((pCardInfo->si_per_targ_wide_nego & sync_bit_map) ||
2891 (id*2+i >= 8)){
2892 */
2893 if (pCardInfo->si_per_targ_wide_nego & sync_bit_map){
2894
2895 sccbMgrTbl[thisCard][id*2+i].TarEEValue |= EE_WIDE_SCSI;
2896
2897 }
2898
2899 else { /* NARROW SCSI */
2900 sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
2901 }
2902
2903 #else
2904 sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
2905 #endif
2906
2907
2908 sync_bit_map <<= 1;
2909
2910
2911
2912 }
2913 }
2914
2915 WR_HARPOON((ioport+hp_semaphore),
2916 (UCHAR)(RD_HARPOON((ioport+hp_semaphore)) | SCCB_MGR_PRESENT));
2917
2918 #if defined(DOS)
2919 return((USHORT)CurrCard);
2920 #else
2921 return((ULONG)CurrCard);
2922 #endif
2923 }
2924
2925 #else /* end (FW_TYPE==_SCCB_MGR_) */
2926
2927
2928
2929 STATIC s16bits FP_PresenceCheck(PMGR_INFO pMgrInfo)
2930 {
2931 PMGR_ENTRYPNTS pMgr_EntryPnts = &pMgrInfo->mi_Functions;
2932
2933 pMgr_EntryPnts->UCBMgr_probe_adapter = probe_adapter;
2934 pMgr_EntryPnts->UCBMgr_init_adapter = init_adapter;
2935 pMgr_EntryPnts->UCBMgr_start_UCB = SccbMgr_start_sccb;
2936 pMgr_EntryPnts->UCBMgr_build_UCB = build_UCB;
2937 pMgr_EntryPnts->UCBMgr_abort_UCB = SccbMgr_abort_sccb;
2938 pMgr_EntryPnts->UCBMgr_my_int = SccbMgr_my_int;
2939 pMgr_EntryPnts->UCBMgr_isr = SccbMgr_isr;
2940 pMgr_EntryPnts->UCBMgr_scsi_reset = SccbMgr_scsi_reset;
2941 pMgr_EntryPnts->UCBMgr_timer_expired = SccbMgr_timer_expired;
2942 #ifndef NO_IOCTLS
2943 pMgr_EntryPnts->UCBMgr_unload_card = SccbMgr_unload_card;
2944 pMgr_EntryPnts->UCBMgr_save_foreign_state =
2945 SccbMgr_save_foreign_state;
2946 pMgr_EntryPnts->UCBMgr_restore_foreign_state =
2947 SccbMgr_restore_foreign_state;
2948 pMgr_EntryPnts->UCBMgr_restore_native_state =
2949 SccbMgr_restore_native_state;
2950 #endif /*NO_IOCTLS*/
2951
2952 pMgrInfo->mi_SGListFormat=0x01;
2953 pMgrInfo->mi_DataPtrFormat=0x01;
2954 pMgrInfo->mi_MaxSGElements= (u16bits) 0xffffffff;
2955 pMgrInfo->mi_MgrPrivateLen=sizeof(SCCB);
2956 pMgrInfo->mi_PCIVendorID=BL_VENDOR_ID;
2957 pMgrInfo->mi_PCIDeviceID=FP_DEVICE_ID;
2958 pMgrInfo->mi_MgrAttributes= ATTR_IO_MAPPED +
2959 ATTR_PHYSICAL_ADDRESS +
2960 ATTR_VIRTUAL_ADDRESS +
2961 ATTR_OVERLAPPED_IO_IOCTLS_OK;
2962 pMgrInfo->mi_IoRangeLen = 256;
2963 return(0);
2964 }
2965
2966
2967
2968 /*---------------------------------------------------------------------
2969 *
2970 * Function: probe_adapter
2971 *
2972 * Description: Setup and/or Search for cards and return info to caller.
2973 *
2974 *---------------------------------------------------------------------*/
2975 STATIC s32bits probe_adapter(PADAPTER_INFO pAdapterInfo)
2976 {
2977 u16bits temp,temp2,temp3,temp4;
2978 u08bits i,j,id;
2979
2980 #if defined(DOS)
2981 #else
2982 static u08bits first_time = 1;
2983 #endif
2984 BASE_PORT ioport;
2985 PNVRamInfo pCurrNvRam;
2986
2987 ioport = (BASE_PORT)pAdapterInfo->ai_baseaddr;
2988
2989
2990
2991 if (RD_HARPOON(ioport+hp_vendor_id_0) != ORION_VEND_0)
2992 return(1);
2993
2994 if ((RD_HARPOON(ioport+hp_vendor_id_1) != ORION_VEND_1))
2995 return(2);
2996
2997 if ((RD_HARPOON(ioport+hp_device_id_0) != ORION_DEV_0))
2998 return(3);
2999
3000 if ((RD_HARPOON(ioport+hp_device_id_1) != ORION_DEV_1))
3001 return(4);
3002
3003
3004 if (RD_HARPOON(ioport+hp_rev_num) != 0x0f){
3005
3006
3007 /* For new Harpoon then check for sub_device ID LSB
3008 the bits(0-3) must be all ZERO for compatible with
3009 current version of SCCBMgr, else skip this Harpoon
3010 device. */
3011
3012 if (RD_HARPOON(ioport+hp_sub_device_id_0) & 0x0f)
3013 return(5);
3014 }
3015
3016 if (first_time) {
3017
3018 SccbMgrTableInitAll();
3019 first_time = 0;
3020 mbCards = 0;
3021 }
3022
3023 if(RdStack(ioport, 0) != 0x00) {
3024 if(ChkIfChipInitialized(ioport) == FALSE)
3025 {
3026 pCurrNvRam = NULL;
3027 WR_HARPOON(ioport+hp_semaphore, 0x00);
3028 XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
3029 DiagEEPROM(ioport);
3030 }
3031 else
3032 {
3033 if(mbCards < MAX_MB_CARDS) {
3034 pCurrNvRam = &nvRamInfo[mbCards];
3035 mbCards++;
3036 pCurrNvRam->niBaseAddr = ioport;
3037 RNVRamData(pCurrNvRam);
3038 }else
3039 return((int) FAILURE);
3040 }
3041 }else
3042 pCurrNvRam = NULL;
3043
3044 #if defined (NO_BIOS_OPTION)
3045 pCurrNvRam = NULL;
3046 XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
3047 DiagEEPROM(ioport);
3048 #endif /* No BIOS Option */
3049
3050 WR_HARPOON(ioport+hp_clkctrl_0, CLKCTRL_DEFAULT);
3051 WR_HARPOON(ioport+hp_sys_ctrl, 0x00);
3052
3053 if(pCurrNvRam)
3054 pAdapterInfo->ai_id = pCurrNvRam->niAdapId;
3055 else
3056 pAdapterInfo->ai_id = (u08bits)(utilEERead(ioport, (ADAPTER_SCSI_ID/2)) &
3057 (u08bits)0x0FF);
3058
3059 pAdapterInfo->ai_lun = 0x00;
3060 pAdapterInfo->ai_fw_revision[0] = '3';
3061 pAdapterInfo->ai_fw_revision[1] = '1';
3062 pAdapterInfo->ai_fw_revision[2] = '1';
3063 pAdapterInfo->ai_fw_revision[3] = ' ';
3064 pAdapterInfo->ai_NumChannels = 1;
3065