File: /usr/src/linux/drivers/scsi/NCR53C9x.h
1 /* NCR53C9x.c: Defines and structures for the NCR53C9x generic driver.
2 *
3 * Originaly esp.h: Defines and structures for the Sparc ESP
4 * (Enhanced SCSI Processor) driver under Linux.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 *
8 * Generalization by Jesper Skov (jskov@cygnus.co.uk)
9 *
10 * More generalization (for i386 stuff) by Tymm Twillman (tymm@computer.org)
11 */
12
13 #ifndef NCR53C9X_H
14 #define NCR53C9X_H
15
16 #include <linux/config.h>
17
18 /* djweis for mac driver */
19 #if defined(CONFIG_MAC)
20 #define PAD_SIZE 15
21 #else
22 #define PAD_SIZE 3
23 #endif
24
25 /* Handle multiple hostadapters on Amiga
26 * generally PAD_SIZE = 3
27 * but there is one exception: Oktagon (PAD_SIZE = 1) */
28 #if defined(CONFIG_OKTAGON_SCSI) || defined(CONFIG_OKTAGON_SCSI_MODULE)
29 #undef PAD_SIZE
30 #if defined(CONFIG_BLZ1230_SCSI) || defined(CONFIG_BLZ1230_SCSI_MODULE) || \
31 defined(CONFIG_BLZ2060_SCSI) || defined(CONFIG_BLZ2060_SCSI_MODULE) || \
32 defined(CONFIG_CYBERSTORM_SCSI) || defined(CONFIG_CYBERSTORM_SCSI_MODULE) || \
33 defined(CONFIG_CYBERSTORMII_SCSI) || defined(CONFIG_CYBERSTORMII_SCSI_MODULE) || \
34 defined(CONFIG_FASTLANE_SCSI) || defined(CONFIG_FASTLANE_SCSI_MODULE)
35 #define MULTIPLE_PAD_SIZES
36 #else
37 #define PAD_SIZE 1
38 #endif
39 #endif
40
41 /* Macros for debugging messages */
42
43 #define DEBUG_ESP
44 /* #define DEBUG_ESP_DATA */
45 /* #define DEBUG_ESP_QUEUE */
46 /* #define DEBUG_ESP_DISCONNECT */
47 /* #define DEBUG_ESP_STATUS */
48 /* #define DEBUG_ESP_PHASES */
49 /* #define DEBUG_ESP_WORKBUS */
50 /* #define DEBUG_STATE_MACHINE */
51 /* #define DEBUG_ESP_CMDS */
52 /* #define DEBUG_ESP_IRQS */
53 /* #define DEBUG_SDTR */
54 /* #define DEBUG_ESP_SG */
55
56 /* Use the following to sprinkle debugging messages in a way which
57 * suits you if combinations of the above become too verbose when
58 * trying to track down a specific problem.
59 */
60 /* #define DEBUG_ESP_MISC */
61
62 #if defined(DEBUG_ESP)
63 #define ESPLOG(foo) printk foo
64 #else
65 #define ESPLOG(foo)
66 #endif /* (DEBUG_ESP) */
67
68 #if defined(DEBUG_ESP_DATA)
69 #define ESPDATA(foo) printk foo
70 #else
71 #define ESPDATA(foo)
72 #endif
73
74 #if defined(DEBUG_ESP_QUEUE)
75 #define ESPQUEUE(foo) printk foo
76 #else
77 #define ESPQUEUE(foo)
78 #endif
79
80 #if defined(DEBUG_ESP_DISCONNECT)
81 #define ESPDISC(foo) printk foo
82 #else
83 #define ESPDISC(foo)
84 #endif
85
86 #if defined(DEBUG_ESP_STATUS)
87 #define ESPSTAT(foo) printk foo
88 #else
89 #define ESPSTAT(foo)
90 #endif
91
92 #if defined(DEBUG_ESP_PHASES)
93 #define ESPPHASE(foo) printk foo
94 #else
95 #define ESPPHASE(foo)
96 #endif
97
98 #if defined(DEBUG_ESP_WORKBUS)
99 #define ESPBUS(foo) printk foo
100 #else
101 #define ESPBUS(foo)
102 #endif
103
104 #if defined(DEBUG_ESP_IRQS)
105 #define ESPIRQ(foo) printk foo
106 #else
107 #define ESPIRQ(foo)
108 #endif
109
110 #if defined(DEBUG_SDTR)
111 #define ESPSDTR(foo) printk foo
112 #else
113 #define ESPSDTR(foo)
114 #endif
115
116 #if defined(DEBUG_ESP_MISC)
117 #define ESPMISC(foo) printk foo
118 #else
119 #define ESPMISC(foo)
120 #endif
121
122 /*
123 * padding for register structure
124 */
125 #ifdef CONFIG_JAZZ_ESP
126 #define EREGS_PAD(n)
127 #else
128 #ifndef MULTIPLE_PAD_SIZES
129 #define EREGS_PAD(n) unchar n[PAD_SIZE];
130 #endif
131 #endif
132
133 /* The ESP SCSI controllers have their register sets in three
134 * "classes":
135 *
136 * 1) Registers which are both read and write.
137 * 2) Registers which are read only.
138 * 3) Registers which are write only.
139 *
140 * Yet, they all live within the same IO space.
141 */
142
143 #if !defined(__i386__) && !defined(__x86_64__)
144
145 #ifndef MULTIPLE_PAD_SIZES
146
147 #ifdef CONFIG_CPU_HAS_WB
148 #include <asm/wbflush.h>
149 #define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
150 #else
151 #define esp_write(__reg, __val) ((__reg) = (__val))
152 #endif
153 #define esp_read(__reg) (__reg)
154
155 struct ESP_regs {
156 /* Access Description Offset */
157 volatile unchar esp_tclow; /* rw Low bits of the transfer count 0x00 */
158 EREGS_PAD(tlpad1);
159 volatile unchar esp_tcmed; /* rw Mid bits of the transfer count 0x04 */
160 EREGS_PAD(fdpad);
161 volatile unchar esp_fdata; /* rw FIFO data bits 0x08 */
162 EREGS_PAD(cbpad);
163 volatile unchar esp_cmnd; /* rw SCSI command bits 0x0c */
164 EREGS_PAD(stpad);
165 volatile unchar esp_status; /* ro ESP status register 0x10 */
166 #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
167 EREGS_PAD(irqpd);
168 volatile unchar esp_intrpt; /* ro Kind of interrupt 0x14 */
169 #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
170 EREGS_PAD(sspad);
171 volatile unchar esp_sstep; /* ro Sequence step register 0x18 */
172 #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
173 EREGS_PAD(ffpad);
174 volatile unchar esp_fflags; /* ro Bits of current FIFO info 0x1c */
175 #define esp_soff esp_fflags /* wo Sync offset 0x1c */
176 EREGS_PAD(cf1pd);
177 volatile unchar esp_cfg1; /* rw First configuration register 0x20 */
178 EREGS_PAD(cfpad);
179 volatile unchar esp_cfact; /* wo Clock conversion factor 0x24 */
180 EREGS_PAD(ctpad);
181 volatile unchar esp_ctest; /* wo Chip test register 0x28 */
182 EREGS_PAD(cf2pd);
183 volatile unchar esp_cfg2; /* rw Second configuration register 0x2c */
184 EREGS_PAD(cf3pd);
185
186 /* The following is only found on the 53C9X series SCSI chips */
187 volatile unchar esp_cfg3; /* rw Third configuration register 0x30 */
188 EREGS_PAD(cf4pd);
189 volatile unchar esp_cfg4; /* rw Fourth configuration register 0x34 */
190 EREGS_PAD(thpd);
191 /* The following is found on all chips except the NCR53C90 (ESP100) */
192 volatile unchar esp_tchi; /* rw High bits of transfer count 0x38 */
193 #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
194 EREGS_PAD(fgpad);
195 volatile unchar esp_fgrnd; /* rw Data base for fifo 0x3c */
196 };
197
198 #else /* MULTIPLE_PAD_SIZES */
199
200 #define esp_write(__reg, __val) (*(__reg) = (__val))
201 #define esp_read(__reg) (*(__reg))
202
203 struct ESP_regs {
204 unsigned char io_addr[64]; /* dummy */
205 /* Access Description Offset */
206 #define esp_tclow io_addr /* rw Low bits of the transfer count 0x00 */
207 #define esp_tcmed io_addr + (1<<(esp->shift)) /* rw Mid bits of the transfer count 0x04 */
208 #define esp_fdata io_addr + (2<<(esp->shift)) /* rw FIFO data bits 0x08 */
209 #define esp_cmnd io_addr + (3<<(esp->shift)) /* rw SCSI command bits 0x0c */
210 #define esp_status io_addr + (4<<(esp->shift)) /* ro ESP status register 0x10 */
211 #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
212 #define esp_intrpt io_addr + (5<<(esp->shift)) /* ro Kind of interrupt 0x14 */
213 #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
214 #define esp_sstep io_addr + (6<<(esp->shift)) /* ro Sequence step register 0x18 */
215 #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
216 #define esp_fflags io_addr + (7<<(esp->shift)) /* ro Bits of current FIFO info 0x1c */
217 #define esp_soff esp_fflags /* wo Sync offset 0x1c */
218 #define esp_cfg1 io_addr + (8<<(esp->shift)) /* rw First configuration register 0x20 */
219 #define esp_cfact io_addr + (9<<(esp->shift)) /* wo Clock conversion factor 0x24 */
220 #define esp_ctest io_addr + (10<<(esp->shift)) /* wo Chip test register 0x28 */
221 #define esp_cfg2 io_addr + (11<<(esp->shift)) /* rw Second configuration register 0x2c */
222
223 /* The following is only found on the 53C9X series SCSI chips */
224 #define esp_cfg3 io_addr + (12<<(esp->shift)) /* rw Third configuration register 0x30 */
225 #define esp_cfg4 io_addr + (13<<(esp->shift)) /* rw Fourth configuration register 0x34 */
226
227 /* The following is found on all chips except the NCR53C90 (ESP100) */
228 #define esp_tchi io_addr + (14<<(esp->shift)) /* rw High bits of transfer count 0x38 */
229 #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
230 #define esp_fgrnd io_addr + (15<<(esp->shift)) /* rw Data base for fifo 0x3c */
231 };
232
233 #endif
234
235 #else /* !defined(__i386__) && !defined(__x86_64__) */
236
237 #define esp_write(__reg, __val) outb((__val), (__reg))
238 #define esp_read(__reg) inb((__reg))
239
240 struct ESP_regs {
241 unsigned int io_addr;
242 /* Access Description Offset */
243 #define esp_tclow io_addr /* rw Low bits of the transfer count 0x00 */
244 #define esp_tcmed io_addr + 1 /* rw Mid bits of the transfer count 0x04 */
245 #define esp_fdata io_addr + 2 /* rw FIFO data bits 0x08 */
246 #define esp_cmnd io_addr + 3 /* rw SCSI command bits 0x0c */
247 #define esp_status io_addr + 4 /* ro ESP status register 0x10 */
248 #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
249 #define esp_intrpt io_addr + 5 /* ro Kind of interrupt 0x14 */
250 #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
251 #define esp_sstep io_addr + 6 /* ro Sequence step register 0x18 */
252 #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
253 #define esp_fflags io_addr + 7 /* ro Bits of current FIFO info 0x1c */
254 #define esp_soff esp_fflags /* wo Sync offset 0x1c */
255 #define esp_cfg1 io_addr + 8 /* rw First configuration register 0x20 */
256 #define esp_cfact io_addr + 9 /* wo Clock conversion factor 0x24 */
257 #define esp_ctest io_addr + 10 /* wo Chip test register 0x28 */
258 #define esp_cfg2 io_addr + 11 /* rw Second configuration register 0x2c */
259
260 /* The following is only found on the 53C9X series SCSI chips */
261 #define esp_cfg3 io_addr + 12 /* rw Third configuration register 0x30 */
262 #define esp_cfg4 io_addr + 13 /* rw Fourth configuration register 0x34 */
263
264 /* The following is found on all chips except the NCR53C90 (ESP100) */
265 #define esp_tchi io_addr + 14 /* rw High bits of transfer count 0x38 */
266 #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
267 #define esp_fgrnd io_addr + 15 /* rw Data base for fifo 0x3c */
268 };
269
270 #endif /* !defined(__i386__) && !defined(__x86_64__) */
271
272 /* Various revisions of the ESP board. */
273 enum esp_rev {
274 esp100 = 0x00, /* NCR53C90 - very broken */
275 esp100a = 0x01, /* NCR53C90A */
276 esp236 = 0x02,
277 fas236 = 0x03,
278 fas100a = 0x04,
279 fast = 0x05,
280 fas366 = 0x06,
281 fas216 = 0x07,
282 fsc = 0x08, /* SYM53C94-2 */
283 espunknown = 0x09
284 };
285
286 /* We get one of these for each ESP probed. */
287 struct NCR_ESP {
288 struct NCR_ESP *next; /* Next ESP on probed or NULL */
289 struct ESP_regs *eregs; /* All esp registers */
290 int dma; /* Who I do transfers with. */
291 void *dregs; /* And his registers. */
292 struct Scsi_Host *ehost; /* Backpointer to SCSI Host */
293
294 void *edev; /* Pointer to controller base/SBus */
295 int esp_id; /* Unique per-ESP ID number */
296
297 /* ESP Configuration Registers */
298 unsigned char config1; /* Copy of the 1st config register */
299 unsigned char config2; /* Copy of the 2nd config register */
300 unsigned char config3[16]; /* Copy of the 3rd config register */
301
302 /* The current command we are sending to the ESP chip. This esp_command
303 * ptr needs to be mapped in DVMA area so we can send commands and read
304 * from the ESP fifo without burning precious CPU cycles. Programmed I/O
305 * sucks when we have the DVMA to do it for us. The ESP is stupid and will
306 * only send out 6, 10, and 12 byte SCSI commands, others we need to send
307 * one byte at a time. esp_slowcmd being set says that we are doing one
308 * of the command types ESP doesn't understand, esp_scmdp keeps track of
309 * which byte we are sending, esp_scmdleft says how many bytes to go.
310 */
311 volatile unchar *esp_command; /* Location of command (CPU view) */
312 __u32 esp_command_dvma; /* Location of command (DVMA view) */
313 unsigned char esp_clen; /* Length of this command */
314 unsigned char esp_slowcmd;
315 unsigned char *esp_scmdp;
316 unsigned char esp_scmdleft;
317
318 /* The following are used to determine the cause of an IRQ. Upon every
319 * IRQ entry we synchronize these with the hardware registers.
320 */
321 unchar ireg; /* Copy of ESP interrupt register */
322 unchar sreg; /* Same for ESP status register */
323 unchar seqreg; /* The ESP sequence register */
324
325 /* The following is set when a premature interrupt condition is detected
326 * in some FAS revisions.
327 */
328 unchar fas_premature_intr_workaround;
329
330 /* To save register writes to the ESP, which can be expensive, we
331 * keep track of the previous value that various registers had for
332 * the last target we connected to. If they are the same for the
333 * current target, we skip the register writes as they are not needed.
334 */
335 unchar prev_soff, prev_stp, prev_cfg3;
336
337 /* For each target we keep track of save/restore data
338 * pointer information. This needs to be updated majorly
339 * when we add support for tagged queueing. -DaveM
340 */
341 struct esp_pointers {
342 char *saved_ptr;
343 struct scatterlist *saved_buffer;
344 int saved_this_residual;
345 int saved_buffers_residual;
346 } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;
347
348 /* Clock periods, frequencies, synchronization, etc. */
349 unsigned int cfreq; /* Clock frequency in HZ */
350 unsigned int cfact; /* Clock conversion factor */
351 unsigned int ccycle; /* One ESP clock cycle */
352 unsigned int ctick; /* One ESP clock time */
353 unsigned int radelay; /* FAST chip req/ack delay */
354 unsigned int neg_defp; /* Default negotiation period */
355 unsigned int sync_defp; /* Default sync transfer period */
356 unsigned int max_period; /* longest our period can be */
357 unsigned int min_period; /* shortest period we can withstand */
358 /* For slow to medium speed input clock rates we shoot for 5mb/s,
359 * but for high input clock rates we try to do 10mb/s although I
360 * don't think a transfer can even run that fast with an ESP even
361 * with DMA2 scatter gather pipelining.
362 */
363 #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
364 #define SYNC_DEFP_FAST 0x19 /* 10mb/s */
365
366 unsigned int snip; /* Sync. negotiation in progress */
367 unsigned int wnip; /* WIDE negotiation in progress */
368 unsigned int targets_present; /* targets spoken to before */
369
370 int current_transfer_size; /* Set at beginning of data dma */
371
372 unchar espcmdlog[32]; /* Log of current esp cmds sent. */
373 unchar espcmdent; /* Current entry in esp cmd log. */
374
375 /* Misc. info about this ESP */
376 enum esp_rev erev; /* ESP revision */
377 int irq; /* IRQ for this ESP */
378 int scsi_id; /* Who am I as initiator? */
379 int scsi_id_mask; /* Bitmask of 'me'. */
380 int diff; /* Differential SCSI bus? */
381 int slot; /* Slot the adapter occupies */
382
383 /* Our command queues, only one cmd lives in the current_SC queue. */
384 Scsi_Cmnd *issue_SC; /* Commands to be issued */
385 Scsi_Cmnd *current_SC; /* Who is currently working the bus */
386 Scsi_Cmnd *disconnected_SC; /* Commands disconnected from the bus */
387
388 /* Message goo */
389 unchar cur_msgout[16];
390 unchar cur_msgin[16];
391 unchar prevmsgout, prevmsgin;
392 unchar msgout_len, msgin_len;
393 unchar msgout_ctr, msgin_ctr;
394
395 /* States that we cannot keep in the per cmd structure because they
396 * cannot be assosciated with any specific command.
397 */
398 unchar resetting_bus;
399
400 unchar do_pio_cmds; /* Do command transfer with pio */
401
402 /* How much bits do we have to shift the registers */
403 unsigned char shift;
404
405 /* Functions handling DMA
406 */
407 /* Required functions */
408 int (*dma_bytes_sent)(struct NCR_ESP *, int);
409 int (*dma_can_transfer)(struct NCR_ESP *, Scsi_Cmnd *);
410 void (*dma_dump_state)(struct NCR_ESP *);
411 void (*dma_init_read)(struct NCR_ESP *, __u32, int);
412 void (*dma_init_write)(struct NCR_ESP *, __u32, int);
413 void (*dma_ints_off)(struct NCR_ESP *);
414 void (*dma_ints_on)(struct NCR_ESP *);
415 int (*dma_irq_p)(struct NCR_ESP *);
416 int (*dma_ports_p)(struct NCR_ESP *);
417 void (*dma_setup)(struct NCR_ESP *, __u32, int, int);
418
419 /* Optional functions (i.e. may be initialized to 0) */
420 void (*dma_barrier)(struct NCR_ESP *);
421 void (*dma_drain)(struct NCR_ESP *);
422 void (*dma_invalidate)(struct NCR_ESP *);
423 void (*dma_irq_entry)(struct NCR_ESP *);
424 void (*dma_irq_exit)(struct NCR_ESP *);
425 void (*dma_led_off)(struct NCR_ESP *);
426 void (*dma_led_on)(struct NCR_ESP *);
427 void (*dma_poll)(struct NCR_ESP *, unsigned char *);
428 void (*dma_reset)(struct NCR_ESP *);
429
430 /* Optional virtual DMA functions */
431 void (*dma_mmu_get_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
432 void (*dma_mmu_get_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
433 void (*dma_mmu_release_scsi_one)(struct NCR_ESP *, Scsi_Cmnd *);
434 void (*dma_mmu_release_scsi_sgl)(struct NCR_ESP *, Scsi_Cmnd *);
435 void (*dma_advance_sg)(Scsi_Cmnd *);
436 };
437
438 /* Bitfield meanings for the above registers. */
439
440 /* ESP config reg 1, read-write, found on all ESP chips */
441 #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
442 #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
443 #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
444 #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
445 #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
446 #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
447
448 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236+fsc chips */
449 #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236,fsc) */
450 #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236,fsc) */
451 #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
452 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tmode only) */
453 #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
454 #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
455 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236,fsc) */
456 #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216,fsc) */
457 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */
458 #define ESP_CONFIG2_RFB 0x80 /* Reserve FIFO byte (fsc) */
459 #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
460
461 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+fsc chips */
462 #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/fas366) */
463 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236/fsc) */
464 #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a) */
465 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236/fsc) */
466 #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a) */
467 #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236/fsc) */
468 #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a) */
469 #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236/fsc) */
470 #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a) */
471 #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236/fsc) */
472 #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236/fsc) */
473 #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236/fsc) */
474 #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236/fsc) */
475
476 /* ESP config register 4 read-write, found only on fsc chips */
477 #define ESP_CONFIG4_BBTE 0x01 /* Back-to-Back transfer enable */
478 #define ESP_CONFIG4_TEST 0x02 /* Transfer counter test mode */
479 #define ESP_CONFIG4_EAN 0x04 /* Enable Active Negotiation */
480
481 /* ESP command register read-write */
482 /* Group 1 commands: These may be sent at any point in time to the ESP
483 * chip. None of them can generate interrupts 'cept
484 * the "SCSI bus reset" command if you have not disabled
485 * SCSI reset interrupts in the config1 ESP register.
486 */
487 #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
488 #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
489 #define ESP_CMD_RC 0x02 /* Chip reset */
490 #define ESP_CMD_RS 0x03 /* SCSI bus reset */
491
492 /* Group 2 commands: ESP must be an initiator and connected to a target
493 * for these commands to work.
494 */
495 #define ESP_CMD_TI 0x10 /* Transfer Information */
496 #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
497 #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
498 #define ESP_CMD_TPAD 0x18 /* Transfer Pad */
499 #define ESP_CMD_SATN 0x1a /* Set ATN */
500 #define ESP_CMD_RATN 0x1b /* De-assert ATN */
501
502 /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
503 * to a target as the initiator for these commands to work.
504 */
505 #define ESP_CMD_SMSG 0x20 /* Send message */
506 #define ESP_CMD_SSTAT 0x21 /* Send status */
507 #define ESP_CMD_SDATA 0x22 /* Send data */
508 #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
509 #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
510 #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
511 #define ESP_CMD_DCNCT 0x27 /* Disconnect */
512 #define ESP_CMD_RMSG 0x28 /* Receive Message */
513 #define ESP_CMD_RCMD 0x29 /* Receive Command */
514 #define ESP_CMD_RDATA 0x2a /* Receive Data */
515 #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
516
517 /* Group 4 commands: The ESP must be in the disconnected state and must
518 * not be connected to any targets as initiator for
519 * these commands to work.
520 */
521 #define ESP_CMD_RSEL 0x40 /* Reselect */
522 #define ESP_CMD_SEL 0x41 /* Select w/o ATN */
523 #define ESP_CMD_SELA 0x42 /* Select w/ATN */
524 #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
525 #define ESP_CMD_ESEL 0x44 /* Enable selection */
526 #define ESP_CMD_DSEL 0x45 /* Disable selections */
527 #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
528 #define ESP_CMD_RSEL3 0x47 /* Reselect3 */
529
530 /* This bit enables the ESP's DMA */
531 #define ESP_CMD_DMA 0x80 /* Do DMA? */
532
533 /* ESP status register read-only */
534 #define ESP_STAT_PIO 0x01 /* IO phase bit */
535 #define ESP_STAT_PCD 0x02 /* CD phase bit */
536 #define ESP_STAT_PMSG 0x04 /* MSG phase bit */
537 #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
538 #define ESP_STAT_TDONE 0x08 /* Transfer Completed */
539 #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
540 #define ESP_STAT_PERR 0x20 /* Parity error */
541 #define ESP_STAT_SPAM 0x40 /* Real bad error */
542 /* This indicates the 'interrupt pending' condition, it is a reserved
543 * bit on old revs of the ESP (ESP100, ESP100A, FAS100A).
544 */
545 #define ESP_STAT_INTR 0x80 /* Interrupt */
546
547 /* The status register can be masked with ESP_STAT_PMASK and compared
548 * with the following values to determine the current phase the ESP
549 * (at least thinks it) is in. For our purposes we also add our own
550 * software 'done' bit for our phase management engine.
551 */
552 #define ESP_DOP (0) /* Data Out */
553 #define ESP_DIP (ESP_STAT_PIO) /* Data In */
554 #define ESP_CMDP (ESP_STAT_PCD) /* Command */
555 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
556 #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
557 #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
558
559 /* ESP interrupt register read-only */
560 #define ESP_INTR_S 0x01 /* Select w/o ATN */
561 #define ESP_INTR_SATN 0x02 /* Select w/ATN */
562 #define ESP_INTR_RSEL 0x04 /* Reselected */
563 #define ESP_INTR_FDONE 0x08 /* Function done */
564 #define ESP_INTR_BSERV 0x10 /* Bus service */
565 #define ESP_INTR_DC 0x20 /* Disconnect */
566 #define ESP_INTR_IC 0x40 /* Illegal command given */
567 #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
568
569 /* Interrupt status macros */
570 #define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR))
571 #define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC))
572 #define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN))
573 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S))
574 #define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \
575 (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
576 #define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL))
577
578 /* ESP sequence step register read-only */
579 #define ESP_STEP_VBITS 0x07 /* Valid bits */
580 #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
581 #define ESP_STEP_SID 0x01 /* One msg byte sent */
582 #define ESP_STEP_NCMD 0x02 /* Was not in command phase */
583 #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
584 * bytes to be lost
585 */
586 #define ESP_STEP_FINI4 0x04 /* Command was sent ok */
587
588 /* Ho hum, some ESP's set the step register to this as well... */
589 #define ESP_STEP_FINI5 0x05
590 #define ESP_STEP_FINI6 0x06
591 #define ESP_STEP_FINI7 0x07
592 #define ESP_STEP_SOM 0x08 /* Synchronous Offset Max */
593
594 /* ESP chip-test register read-write */
595 #define ESP_TEST_TARG 0x01 /* Target test mode */
596 #define ESP_TEST_INI 0x02 /* Initiator test mode */
597 #define ESP_TEST_TS 0x04 /* Tristate test mode */
598
599 /* ESP unique ID register read-only, found on fas236+fas100a+fsc only */
600 #define ESP_UID_F100A 0x00 /* FAS100A */
601 #define ESP_UID_F236 0x02 /* FAS236 */
602 #define ESP_UID_FSC 0xa2 /* NCR53CF9x-2 */
603 #define ESP_UID_REV 0x07 /* ESP revision */
604 #define ESP_UID_FAM 0xf8 /* ESP family */
605
606 /* ESP fifo flags register read-only */
607 /* Note that the following implies a 16 byte FIFO on the ESP. */
608 #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
609 #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100,fsc) */
610 #define ESP_FF_SSTEP 0xe0 /* Sequence step */
611
612 /* ESP clock conversion factor register write-only */
613 #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
614 #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
615 #define ESP_CCF_F2 0x02 /* 10MHz */
616 #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
617 #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
618 #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
619 #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
620 #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
621
622 #define ESP_BUS_TIMEOUT 275 /* In milli-seconds */
623 #define ESP_TIMEO_CONST 8192
624 #define FSC_TIMEO_CONST 7668
625 #define ESP_NEG_DEFP(mhz, cfact) \
626 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
627 #define FSC_NEG_DEFP(mhz, cfact) \
628 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (7668 * (cfact)))
629 #define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
630 #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
631
632
633 /* UGLY, UGLY, UGLY! */
634 extern int nesps, esps_in_use, esps_running;
635
636 /* For our interrupt engine. */
637 #define for_each_esp(esp) \
638 for((esp) = espchain; (esp); (esp) = (esp)->next)
639
640
641 /* External functions */
642 extern inline void esp_cmd(struct NCR_ESP *esp, struct ESP_regs *eregs,
643 unchar cmd);
644 extern struct NCR_ESP *esp_allocate(Scsi_Host_Template *, void *);
645 extern void esp_deallocate(struct NCR_ESP *);
646 extern void esp_release(void);
647 extern void esp_initialize(struct NCR_ESP *);
648 extern void esp_intr(int, void *, struct pt_regs *);
649 #endif /* !(NCR53C9X_H) */
650