File: /usr/src/linux/drivers/scsi/aic7xxx/aic7xxx.c
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $Id: //depot/src/aic7xxx/aic7xxx.c#44 $
32 *
33 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.61 2000/11/13 03:35:43 gibbs Exp $
34 */
35
36 #include "aic7xxx_osm.h"
37 #include "aic7xxx_inline.h"
38 #include "aicasm/aicasm_insformat.h"
39
40 /****************************** Softc Data ************************************/
41 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
42
43 /***************************** Lookup Tables **********************************/
44 char *ahc_chip_names[] =
45 {
46 "NONE",
47 "aic7770",
48 "aic7850",
49 "aic7855",
50 "aic7859",
51 "aic7860",
52 "aic7870",
53 "aic7880",
54 "aic7895",
55 "aic7895C",
56 "aic7890/91",
57 "aic7896/97",
58 "aic7892",
59 "aic7899"
60 };
61 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
62
63 /*
64 * Hardware error codes.
65 */
66 struct ahc_hard_error_entry {
67 uint8_t errno;
68 char *errmesg;
69 };
70
71 static struct ahc_hard_error_entry ahc_hard_errors[] = {
72 { ILLHADDR, "Illegal Host Access" },
73 { ILLSADDR, "Illegal Sequencer Address referrenced" },
74 { ILLOPCODE, "Illegal Opcode in sequencer program" },
75 { SQPARERR, "Sequencer Parity Error" },
76 { DPARERR, "Data-path Parity Error" },
77 { MPARERR, "Scratch or SCB Memory Parity Error" },
78 { PCIERRSTAT, "PCI Error detected" },
79 { CIOPARERR, "CIOBUS Parity Error" },
80 };
81 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
82
83 static struct ahc_phase_table_entry ahc_phase_table[] =
84 {
85 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
86 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
87 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
88 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
89 { P_COMMAND, MSG_NOOP, "in Command phase" },
90 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
91 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
92 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
93 { P_BUSFREE, MSG_NOOP, "while idle" },
94 { 0, MSG_NOOP, "in unknown phase" }
95 };
96
97 /*
98 * In most cases we only wish to itterate over real phases, so
99 * exclude the last element from the count.
100 */
101 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
102
103 /*
104 * Valid SCSIRATE values. (p. 3-17)
105 * Provides a mapping of tranfer periods in ns to the proper value to
106 * stick in the scsixfer reg.
107 */
108 static struct ahc_syncrate ahc_syncrates[] =
109 {
110 /* ultra2 fast/ultra period rate */
111 { 0x42, 0x000, 9, "80.0" },
112 { 0x03, 0x000, 10, "40.0" },
113 { 0x04, 0x000, 11, "33.0" },
114 { 0x05, 0x100, 12, "20.0" },
115 { 0x06, 0x110, 15, "16.0" },
116 { 0x07, 0x120, 18, "13.4" },
117 { 0x08, 0x000, 25, "10.0" },
118 { 0x19, 0x010, 31, "8.0" },
119 { 0x1a, 0x020, 37, "6.67" },
120 { 0x1b, 0x030, 43, "5.7" },
121 { 0x1c, 0x040, 50, "5.0" },
122 { 0x00, 0x050, 56, "4.4" },
123 { 0x00, 0x060, 62, "4.0" },
124 { 0x00, 0x070, 68, "3.6" },
125 { 0x00, 0x000, 0, NULL }
126 };
127
128 /* Our Sequencer Program */
129 #include "aic7xxx_seq.h"
130
131 /**************************** Function Declarations ***************************/
132 static struct ahc_tmode_tstate*
133 ahc_alloc_tstate(struct ahc_softc *ahc,
134 u_int scsi_id, char channel);
135 #ifdef AHC_TARGET_MODE
136 static void ahc_free_tstate(struct ahc_softc *ahc,
137 u_int scsi_id, char channel, int force);
138 #endif
139 static struct ahc_syncrate*
140 ahc_devlimited_syncrate(struct ahc_softc *ahc,
141 struct ahc_initiator_tinfo *,
142 u_int *period,
143 u_int *ppr_options,
144 role_t role);
145 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
146 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
147 struct ahc_devinfo *devinfo);
148 static void ahc_scb_devinfo(struct ahc_softc *ahc,
149 struct ahc_devinfo *devinfo,
150 struct scb *scb);
151 static void ahc_assert_atn(struct ahc_softc *ahc);
152 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
153 struct ahc_devinfo *devinfo,
154 struct scb *scb);
155 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
156 struct ahc_devinfo *devinfo);
157 static void ahc_construct_sdtr(struct ahc_softc *ahc,
158 struct ahc_devinfo *devinfo,
159 u_int period, u_int offset);
160 static void ahc_construct_wdtr(struct ahc_softc *ahc,
161 struct ahc_devinfo *devinfo,
162 u_int bus_width);
163 static void ahc_construct_ppr(struct ahc_softc *ahc,
164 struct ahc_devinfo *devinfo,
165 u_int period, u_int offset,
166 u_int bus_width, u_int ppr_options);
167 static void ahc_clear_msg_state(struct ahc_softc *ahc);
168 static void ahc_handle_message_phase(struct ahc_softc *ahc);
169 typedef enum {
170 AHCMSG_1B,
171 AHCMSG_2B,
172 AHCMSG_EXT
173 } ahc_msgtype;
174 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
175 u_int msgval, int full);
176 static int ahc_parse_msg(struct ahc_softc *ahc,
177 struct ahc_devinfo *devinfo);
178 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
179 struct ahc_devinfo *devinfo);
180 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo);
182 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
183 static void ahc_handle_devreset(struct ahc_softc *ahc,
184 struct ahc_devinfo *devinfo,
185 cam_status status, char *message,
186 int verbose_level);
187 #if AHC_TARGET_MODE
188 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
189 struct ahc_devinfo *devinfo,
190 struct scb *scb);
191 #endif
192
193 static bus_dmamap_callback_t ahc_dmamap_cb;
194 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
195 static int ahc_init_scbdata(struct ahc_softc *ahc);
196 static void ahc_fini_scbdata(struct ahc_softc *ahc);
197 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
198 struct scb *prev_scb,
199 struct scb *scb);
200 static int ahc_qinfifo_count(struct ahc_softc *ahc);
201 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
202 u_int prev, u_int scbptr);
203 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
204 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
205 u_int scbpos, u_int prev);
206 static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
207 char channel, int lun, u_int tag,
208 role_t role, uint32_t status);
209 static void ahc_reset_current_bus(struct ahc_softc *ahc);
210 #ifdef AHC_DUMP_SEQ
211 static void ahc_dumpseq(struct ahc_softc *ahc);
212 #endif
213 static void ahc_loadseq(struct ahc_softc *ahc);
214 static int ahc_check_patch(struct ahc_softc *ahc,
215 struct patch **start_patch,
216 u_int start_instr, u_int *skip_addr);
217 static void ahc_download_instr(struct ahc_softc *ahc,
218 u_int instrptr, uint8_t *dconsts);
219 #ifdef AHC_TARGET_MODE
220 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
221 struct ahc_tmode_lstate *lstate,
222 u_int initiator_id,
223 u_int event_type,
224 u_int event_arg);
225 static void ahc_update_scsiid(struct ahc_softc *ahc,
226 u_int targid_mask);
227 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
228 struct target_cmd *cmd);
229 #endif
230 /************************* Sequencer Execution Control ************************/
231 /*
232 * Restart the sequencer program from address zero
233 */
234 void
235 ahc_restart(struct ahc_softc *ahc)
236 {
237
238 ahc_pause(ahc);
239
240 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
241 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
242 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
243
244 /*
245 * Ensure that the sequencer's idea of TQINPOS
246 * matches our own. The sequencer increments TQINPOS
247 * only after it sees a DMA complete and a reset could
248 * occur before the increment leaving the kernel to believe
249 * the command arrived but the sequencer to not.
250 */
251 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
252
253 /* Always allow reselection */
254 ahc_outb(ahc, SCSISEQ,
255 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
256 if ((ahc->features & AHC_CMD_CHAN) != 0) {
257 /* Ensure that no DMA operations are in progress */
258 ahc_outb(ahc, CCSCBCNT, 0);
259 ahc_outb(ahc, CCSGCTL, 0);
260 ahc_outb(ahc, CCSCBCTL, 0);
261 }
262 /*
263 * If we were in the process of DMA'ing SCB data into
264 * an SCB, replace that SCB on the free list. This prevents
265 * an SCB leak.
266 */
267 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
268 ahc_add_curscb_to_free_list(ahc);
269 ahc_outb(ahc, SEQ_FLAGS2,
270 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
271 }
272 ahc_outb(ahc, MWI_RESIDUAL, 0);
273 ahc_outb(ahc, SEQCTL, FASTMODE);
274 ahc_outb(ahc, SEQADDR0, 0);
275 ahc_outb(ahc, SEQADDR1, 0);
276 ahc_unpause(ahc);
277 }
278
279 /************************* Input/Output Queues ********************************/
280 void
281 ahc_run_qoutfifo(struct ahc_softc *ahc)
282 {
283 struct scb *scb;
284 u_int scb_index;
285
286 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
287 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
288
289 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
290 if ((ahc->qoutfifonext & 0x03) == 0x03) {
291 u_int modnext;
292
293 /*
294 * Clear 32bits of QOUTFIFO at a time
295 * so that we don't clobber an incoming
296 * byte DMA to the array on architectures
297 * that only support 32bit load and store
298 * operations.
299 */
300 modnext = ahc->qoutfifonext & ~0x3;
301 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
302 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
303 ahc->shared_data_dmamap,
304 /*offset*/modnext, /*len*/4,
305 BUS_DMASYNC_PREREAD);
306 }
307 ahc->qoutfifonext++;
308
309 scb = ahc_lookup_scb(ahc, scb_index);
310 if (scb == NULL) {
311 printf("%s: WARNING no command for scb %d "
312 "(cmdcmplt)\nQOUTPOS = %d\n",
313 ahc_name(ahc), scb_index,
314 ahc->qoutfifonext - 1);
315 continue;
316 }
317
318 /*
319 * Save off the residual
320 * if there is one.
321 */
322 ahc_update_residual(scb);
323 ahc_done(ahc, scb);
324 }
325 }
326
327 void
328 ahc_run_untagged_queues(struct ahc_softc *ahc)
329 {
330 int i;
331
332 for (i = 0; i < 16; i++)
333 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
334 }
335
336 void
337 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
338 {
339 struct scb *scb;
340
341 if (ahc->untagged_queue_lock != 0)
342 return;
343
344 if ((scb = TAILQ_FIRST(queue)) != NULL
345 && (scb->flags & SCB_ACTIVE) == 0) {
346 scb->flags |= SCB_ACTIVE;
347 ahc_queue_scb(ahc, scb);
348 }
349 }
350
351 /************************* Interrupt Handling *********************************/
352 void
353 ahc_handle_brkadrint(struct ahc_softc *ahc)
354 {
355 /*
356 * We upset the sequencer :-(
357 * Lookup the error message
358 */
359 int i;
360 int error;
361
362 error = ahc_inb(ahc, ERROR);
363 for (i = 0; error != 1 && i < num_errors; i++)
364 error >>= 1;
365 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
366 ahc_name(ahc), ahc_hard_errors[i].errmesg,
367 ahc_inb(ahc, SEQADDR0) |
368 (ahc_inb(ahc, SEQADDR1) << 8));
369
370 ahc_dump_card_state(ahc);
371
372 /* Tell everyone that this HBA is no longer availible */
373 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
374 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
375 CAM_NO_HBA);
376
377 /* Disable all interrupt sources by resetting the controller */
378 ahc_shutdown(ahc);
379 }
380
381 void
382 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
383 {
384 struct scb *scb;
385 struct ahc_devinfo devinfo;
386
387 ahc_fetch_devinfo(ahc, &devinfo);
388
389 /*
390 * Clear the upper byte that holds SEQINT status
391 * codes and clear the SEQINT bit. We will unpause
392 * the sequencer, if appropriate, after servicing
393 * the request.
394 */
395 ahc_outb(ahc, CLRINT, CLRSEQINT);
396 switch (intstat & SEQINT_MASK) {
397 case BAD_STATUS:
398 {
399 u_int scb_index;
400 struct hardware_scb *hscb;
401
402 /*
403 * Set the default return value to 0 (don't
404 * send sense). The sense code will change
405 * this if needed.
406 */
407 ahc_outb(ahc, RETURN_1, 0);
408
409 /*
410 * The sequencer will notify us when a command
411 * has an error that would be of interest to
412 * the kernel. This allows us to leave the sequencer
413 * running in the common case of command completes
414 * without error. The sequencer will already have
415 * dma'd the SCB back up to us, so we can reference
416 * the in kernel copy directly.
417 */
418 scb_index = ahc_inb(ahc, SCB_TAG);
419 scb = ahc_lookup_scb(ahc, scb_index);
420 if (scb == NULL) {
421 printf("%s:%c:%d: ahc_intr - referenced scb "
422 "not valid during seqint 0x%x scb(%d)\n",
423 ahc_name(ahc), devinfo.channel,
424 devinfo.target, intstat, scb_index);
425 ahc_dump_card_state(ahc);
426 panic("for safety");
427 goto unpause;
428 }
429
430 hscb = scb->hscb;
431
432 /* Don't want to clobber the original sense code */
433 if ((scb->flags & SCB_SENSE) != 0) {
434 /*
435 * Clear the SCB_SENSE Flag and have
436 * the sequencer do a normal command
437 * complete.
438 */
439 scb->flags &= ~SCB_SENSE;
440 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
441 break;
442 }
443 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
444 /* Freeze the queue until the client sees the error. */
445 ahc_freeze_devq(ahc, scb);
446 ahc_freeze_scb(scb);
447 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
448 switch (hscb->shared_data.status.scsi_status) {
449 case SCSI_STATUS_OK:
450 printf("%s: Interrupted for staus of 0???\n",
451 ahc_name(ahc));
452 break;
453 case SCSI_STATUS_CMD_TERMINATED:
454 case SCSI_STATUS_CHECK_COND:
455 {
456 struct ahc_dma_seg *sg;
457 struct scsi_sense *sc;
458 struct ahc_initiator_tinfo *targ_info;
459 struct ahc_tmode_tstate *tstate;
460 struct ahc_transinfo *tinfo;
461 #ifdef AHC_DEBUG
462 if (ahc_debug & AHC_SHOWSENSE) {
463 ahc_print_path(ahc, scb);
464 printf("SCB %d: requests Check Status\n",
465 scb->hscb->tag);
466 }
467 #endif
468
469 if (ahc_perform_autosense(scb) == 0)
470 break;
471
472 targ_info = ahc_fetch_transinfo(ahc,
473 devinfo.channel,
474 devinfo.our_scsiid,
475 devinfo.target,
476 &tstate);
477 tinfo = &targ_info->curr;
478 sg = scb->sg_list;
479 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
480 /*
481 * Save off the residual if there is one.
482 */
483 ahc_update_residual(scb);
484 #ifdef AHC_DEBUG
485 if (ahc_debug & AHC_SHOWSENSE) {
486 ahc_print_path(ahc, scb);
487 printf("Sending Sense\n");
488 }
489 #endif
490 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
491 sg->len = ahc_get_sense_bufsize(ahc, scb);
492 sg->len |= AHC_DMA_LAST_SEG;
493
494 /* Fixup byte order */
495 sg->addr = ahc_htole32(sg->addr);
496 sg->len = ahc_htole32(sg->len);
497
498 sc->opcode = REQUEST_SENSE;
499 sc->byte2 = 0;
500 if (tinfo->protocol_version <= SCSI_REV_2
501 && SCB_GET_LUN(scb) < 8)
502 sc->byte2 = SCB_GET_LUN(scb) << 5;
503 sc->unused[0] = 0;
504 sc->unused[1] = 0;
505 sc->length = sg->len;
506 sc->control = 0;
507
508 /*
509 * We can't allow the target to disconnect.
510 * This will be an untagged transaction and
511 * having the target disconnect will make this
512 * transaction indestinguishable from outstanding
513 * tagged transactions.
514 */
515 hscb->control = 0;
516
517 /*
518 * This request sense could be because the
519 * the device lost power or in some other
520 * way has lost our transfer negotiations.
521 * Renegotiate if appropriate. Unit attention
522 * errors will be reported before any data
523 * phases occur.
524 */
525 if (ahc_get_residual(scb)
526 == ahc_get_transfer_length(scb)) {
527 ahc_update_neg_request(ahc, &devinfo,
528 tstate, targ_info,
529 /*force*/TRUE);
530 }
531 if (tstate->auto_negotiate & devinfo.target_mask) {
532 hscb->control |= MK_MESSAGE;
533 scb->flags &= ~SCB_NEGOTIATE;
534 scb->flags |= SCB_AUTO_NEGOTIATE;
535 }
536 hscb->cdb_len = sizeof(*sc);
537 hscb->dataptr = sg->addr;
538 hscb->datacnt = sg->len;
539 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
540 hscb->sgptr = ahc_htole32(hscb->sgptr);
541 scb->sg_count = 1;
542 scb->flags |= SCB_SENSE;
543 ahc_qinfifo_requeue_tail(ahc, scb);
544 ahc_outb(ahc, RETURN_1, SEND_SENSE);
545 #ifdef __FreeBSD__
546 /*
547 * Ensure we have enough time to actually
548 * retrieve the sense.
549 */
550 untimeout(ahc_timeout, (caddr_t)scb,
551 scb->io_ctx->ccb_h.timeout_ch);
552 scb->io_ctx->ccb_h.timeout_ch =
553 timeout(ahc_timeout, (caddr_t)scb, 5 * hz);
554 #endif
555 break;
556 }
557 default:
558 break;
559 }
560 break;
561 }
562 case NO_MATCH:
563 {
564 /* Ensure we don't leave the selection hardware on */
565 ahc_outb(ahc, SCSISEQ,
566 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
567
568 printf("%s:%c:%d: no active SCB for reconnecting "
569 "target - issuing BUS DEVICE RESET\n",
570 ahc_name(ahc), devinfo.channel, devinfo.target);
571 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
572 "ARG_1 == 0x%x ACCUM = 0x%x\n",
573 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
574 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
575 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
576 "SINDEX == 0x%x\n",
577 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
578 ahc_index_busy_tcl(ahc,
579 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
580 ahc_inb(ahc, SAVED_LUN))),
581 ahc_inb(ahc, SINDEX));
582 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
583 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
584 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
585 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
586 ahc_inb(ahc, SCB_CONTROL));
587 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
588 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
589 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
590 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
591 ahc_dump_card_state(ahc);
592 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
593 ahc->msgout_len = 1;
594 ahc->msgout_index = 0;
595 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
596 ahc_outb(ahc, MSG_OUT, HOST_MSG);
597 ahc_assert_atn(ahc);
598 break;
599 }
600 case SEND_REJECT:
601 {
602 u_int rejbyte = ahc_inb(ahc, ACCUM);
603 printf("%s:%c:%d: Warning - unknown message received from "
604 "target (0x%x). Rejecting\n",
605 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
606 break;
607 }
608 case NO_IDENT:
609 {
610 /*
611 * The reconnecting target either did not send an identify
612 * message, or did, but we didn't find an SCB to match and
613 * before it could respond to our ATN/abort, it hit a dataphase.
614 * The only safe thing to do is to blow it away with a bus
615 * reset.
616 */
617 int found;
618
619 printf("%s:%c:%d: Target did not send an IDENTIFY message. "
620 "LASTPHASE = 0x%x, SAVED_SCSIID == 0x%x\n",
621 ahc_name(ahc), devinfo.channel, devinfo.target,
622 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_SCSIID));
623 found = ahc_reset_channel(ahc, devinfo.channel,
624 /*initiate reset*/TRUE);
625 printf("%s: Issued Channel %c Bus Reset. "
626 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel,
627 found);
628 return;
629 }
630 case IGN_WIDE_RES:
631 ahc_handle_ign_wide_residue(ahc, &devinfo);
632 break;
633 case PDATA_REINIT:
634 ahc_reinitialize_dataptrs(ahc);
635 break;
636 case BAD_PHASE:
637 {
638 u_int lastphase;
639
640 lastphase = ahc_inb(ahc, LASTPHASE);
641 printf("%s:%c:%d: unknown scsi bus phase %x, "
642 "lastphase = 0x%x. Attempting to continue\n",
643 ahc_name(ahc), devinfo.channel, devinfo.target,
644 lastphase, ahc_inb(ahc, SCSISIGI));
645 break;
646 }
647 case MISSED_BUSFREE:
648 {
649 u_int lastphase;
650
651 lastphase = ahc_inb(ahc, LASTPHASE);
652 printf("%s:%c:%d: Missed busfree. "
653 "Lastphase = 0x%x, Curphase = 0x%x\n",
654 ahc_name(ahc), devinfo.channel, devinfo.target,
655 lastphase, ahc_inb(ahc, SCSISIGI));
656 ahc_restart(ahc);
657 return;
658 }
659 case HOST_MSG_LOOP:
660 {
661 /*
662 * The sequencer has encountered a message phase
663 * that requires host assistance for completion.
664 * While handling the message phase(s), we will be
665 * notified by the sequencer after each byte is
666 * transfered so we can track bus phase changes.
667 *
668 * If this is the first time we've seen a HOST_MSG_LOOP
669 * interrupt, initialize the state of the host message
670 * loop.
671 */
672 if (ahc->msg_type == MSG_TYPE_NONE) {
673 struct scb *scb;
674 u_int scb_index;
675 u_int bus_phase;
676
677 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
678 if (bus_phase != P_MESGIN
679 && bus_phase != P_MESGOUT) {
680 printf("ahc_intr: HOST_MSG_LOOP bad "
681 "phase 0x%x\n",
682 bus_phase);
683 /*
684 * Probably transitioned to bus free before
685 * we got here. Just punt the message.
686 */
687 ahc_clear_intstat(ahc);
688 ahc_restart(ahc);
689 return;
690 }
691
692 scb_index = ahc_inb(ahc, SCB_TAG);
693 scb = ahc_lookup_scb(ahc, scb_index);
694 if (devinfo.role == ROLE_INITIATOR) {
695 if (scb == NULL)
696 panic("HOST_MSG_LOOP with "
697 "invalid SCB %x\n", scb_index);
698
699 if (bus_phase == P_MESGOUT)
700 ahc_setup_initiator_msgout(ahc,
701 &devinfo,
702 scb);
703 else {
704 ahc->msg_type =
705 MSG_TYPE_INITIATOR_MSGIN;
706 ahc->msgin_index = 0;
707 }
708 } else {
709 if (bus_phase == P_MESGOUT) {
710 ahc->msg_type =
711 MSG_TYPE_TARGET_MSGOUT;
712 ahc->msgin_index = 0;
713 }
714 #if AHC_TARGET_MODE
715 else
716 ahc_setup_target_msgin(ahc,
717 &devinfo,
718 scb);
719 #endif
720 }
721 }
722
723 ahc_handle_message_phase(ahc);
724 break;
725 }
726 case PERR_DETECTED:
727 {
728 /*
729 * If we've cleared the parity error interrupt
730 * but the sequencer still believes that SCSIPERR
731 * is true, it must be that the parity error is
732 * for the currently presented byte on the bus,
733 * and we are not in a phase (data-in) where we will
734 * eventually ack this byte. Ack the byte and
735 * throw it away in the hope that the target will
736 * take us to message out to deliver the appropriate
737 * error message.
738 */
739 if ((intstat & SCSIINT) == 0
740 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
741
742 if ((ahc->features & AHC_DT) == 0) {
743 u_int curphase;
744
745 /*
746 * The hardware will only let you ack bytes
747 * if the expected phase in SCSISIGO matches
748 * the current phase. Make sure this is
749 * currently the case.
750 */
751 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
752 ahc_outb(ahc, LASTPHASE, curphase);
753 ahc_outb(ahc, SCSISIGO, curphase);
754 }
755 ahc_inb(ahc, SCSIDATL);
756 }
757 break;
758 }
759 case DATA_OVERRUN:
760 {
761 /*
762 * When the sequencer detects an overrun, it
763 * places the controller in "BITBUCKET" mode
764 * and allows the target to complete its transfer.
765 * Unfortunately, none of the counters get updated
766 * when the controller is in this mode, so we have
767 * no way of knowing how large the overrun was.
768 */
769 u_int scbindex = ahc_inb(ahc, SCB_TAG);
770 u_int lastphase = ahc_inb(ahc, LASTPHASE);
771 u_int i;
772
773 scb = ahc_lookup_scb(ahc, scbindex);
774 for (i = 0; i < num_phases; i++) {
775 if (lastphase == ahc_phase_table[i].phase)
776 break;
777 }
778 ahc_print_path(ahc, scb);
779 printf("data overrun detected %s."
780 " Tag == 0x%x.\n",
781 ahc_phase_table[i].phasemsg,
782 scb->hscb->tag);
783 ahc_print_path(ahc, scb);
784 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
785 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
786 ahc_get_transfer_length(scb), scb->sg_count);
787 if (scb->sg_count > 0) {
788 for (i = 0; i < scb->sg_count; i++) {
789
790 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
791 i,
792 (ahc_le32toh(scb->sg_list[i].len) >> 24
793 & SG_HIGH_ADDR_BITS),
794 ahc_le32toh(scb->sg_list[i].addr),
795 ahc_le32toh(scb->sg_list[i].len)
796 & AHC_SG_LEN_MASK);
797 }
798 }
799 /*
800 * Set this and it will take effect when the
801 * target does a command complete.
802 */
803 ahc_freeze_devq(ahc, scb);
804 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
805 ahc_freeze_scb(scb);
806
807 if ((ahc->features & AHC_ULTRA2) != 0) {
808 /*
809 * Clear the channel in case we return
810 * to data phase later.
811 */
812 ahc_outb(ahc, SXFRCTL0,
813 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
814 ahc_outb(ahc, SXFRCTL0,
815 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
816 }
817 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
818 u_int dscommand1;
819
820 /* Ensure HHADDR is 0 for future DMA operations. */
821 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
822 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
823 ahc_outb(ahc, HADDR, 0);
824 ahc_outb(ahc, DSCOMMAND1, dscommand1);
825 }
826 break;
827 }
828 case MKMSG_FAILED:
829 {
830 u_int scbindex;
831
832 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
833 ahc_name(ahc), devinfo.channel, devinfo.target,
834 devinfo.lun);
835 scbindex = ahc_inb(ahc, SCB_TAG);
836 scb = ahc_lookup_scb(ahc, scbindex);
837 if (scb != NULL
838 && (scb->flags & SCB_RECOVERY_SCB) != 0)
839 /*
840 * Ensure that we didn't put a second instance of this
841 * SCB into the QINFIFO.
842 */
843 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
844 SCB_GET_CHANNEL(ahc, scb),
845 SCB_GET_LUN(scb), scb->hscb->tag,
846 ROLE_INITIATOR, /*status*/0,
847 SEARCH_REMOVE);
848 break;
849 }
850 case NO_FREE_SCB:
851 {
852 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
853 ahc_dump_card_state(ahc);
854 panic("for safety");
855 break;
856 }
857 case SCB_MISMATCH:
858 {
859 u_int scbptr;
860
861 scbptr = ahc_inb(ahc, SCBPTR);
862 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
863 scbptr, ahc_inb(ahc, ARG_1),
864 ahc->scb_data->hscbs[scbptr].tag);
865 ahc_dump_card_state(ahc);
866 panic("for saftey");
867 break;
868 }
869 case OUT_OF_RANGE:
870 {
871 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
872 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
873 "ARG_1 == 0x%x ACCUM = 0x%x\n",
874 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
875 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
876 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
877 "SINDEX == 0x%x\n, A == 0x%x\n",
878 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
879 ahc_index_busy_tcl(ahc,
880 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
881 ahc_inb(ahc, SAVED_LUN))),
882 ahc_inb(ahc, SINDEX),
883 ahc_inb(ahc, ACCUM));
884 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
885 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
886 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
887 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
888 ahc_inb(ahc, SCB_CONTROL));
889 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
890 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
891 ahc_dump_card_state(ahc);
892 panic("for safety");
893 break;
894 }
895 default:
896 printf("ahc_intr: seqint, "
897 "intstat == 0x%x, scsisigi = 0x%x\n",
898 intstat, ahc_inb(ahc, SCSISIGI));
899 break;
900 }
901 unpause:
902 /*
903 * The sequencer is paused immediately on
904 * a SEQINT, so we should restart it when
905 * we're done.
906 */
907 ahc_unpause(ahc);
908 }
909
910 void
911 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
912 {
913 u_int scb_index;
914 u_int status0;
915 u_int status;
916 struct scb *scb;
917 char cur_channel;
918 char intr_channel;
919
920 /* Make sure the sequencer is in a safe location. */
921 ahc_clear_critical_section(ahc);
922
923 if ((ahc->features & AHC_TWIN) != 0
924 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
925 cur_channel = 'B';
926 else
927 cur_channel = 'A';
928 intr_channel = cur_channel;
929
930 if ((ahc->features & AHC_ULTRA2) != 0)
931 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
932 else
933 status0 = 0;
934 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
935 if (status == 0 && status0 == 0) {
936 if ((ahc->features & AHC_TWIN) != 0) {
937 /* Try the other channel */
938 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
939 status = ahc_inb(ahc, SSTAT1)
940 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
941 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
942 }
943 if (status == 0) {
944 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
945 ahc_outb(ahc, CLRINT, CLRSCSIINT);
946 ahc_unpause(ahc);
947 return;
948 }
949 }
950
951 scb_index = ahc_inb(ahc, SCB_TAG);
952 scb = ahc_lookup_scb(ahc, scb_index);
953 if (scb != NULL
954 && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0)
955 scb = NULL;
956
957 if ((ahc->features & AHC_ULTRA2) != 0
958 && (status0 & IOERR) != 0) {
959 int now_lvd;
960
961 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
962 printf("%s: Transceiver State Has Changed to %s mode\n",
963 ahc_name(ahc), now_lvd ? "LVD" : "SE");
964 ahc_outb(ahc, CLRSINT0, CLRIOERR);
965 /*
966 * When transitioning to SE mode, the reset line
967 * glitches, triggering an arbitration bug in some
968 * Ultra2 controllers. This bug is cleared when we
969 * assert the reset line. Since a reset glitch has
970 * already occurred with this transition and a
971 * transceiver state change is handled just like
972 * a bus reset anyway, asserting the reset line
973 * ourselves is safe.
974 */
975 ahc_reset_channel(ahc, intr_channel,
976 /*Initiate Reset*/now_lvd == 0);
977 } else if ((status & SCSIRSTI) != 0) {
978 printf("%s: Someone reset channel %c\n",
979 ahc_name(ahc), intr_channel);
980 if (intr_channel != cur_channel)
981 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
982 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
983 } else if ((status & SCSIPERR) != 0) {
984 /*
985 * Determine the bus phase and queue an appropriate message.
986 * SCSIPERR is latched true as soon as a parity error
987 * occurs. If the sequencer acked the transfer that
988 * caused the parity error and the currently presented
989 * transfer on the bus has correct parity, SCSIPERR will
990 * be cleared by CLRSCSIPERR. Use this to determine if
991 * we should look at the last phase the sequencer recorded,
992 * or the current phase presented on the bus.
993 */
994 u_int mesg_out;
995 u_int curphase;
996 u_int errorphase;
997 u_int lastphase;
998 u_int scsirate;
999 u_int i;
1000 u_int sstat2;
1001
1002 lastphase = ahc_inb(ahc, LASTPHASE);
1003 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1004 sstat2 = ahc_inb(ahc, SSTAT2);
1005 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1006 /*
1007 * For all phases save DATA, the sequencer won't
1008 * automatically ack a byte that has a parity error
1009 * in it. So the only way that the current phase
1010 * could be 'data-in' is if the parity error is for
1011 * an already acked byte in the data phase. During
1012 * synchronous data-in transfers, we may actually
1013 * ack bytes before latching the current phase in
1014 * LASTPHASE, leading to the discrepancy between
1015 * curphase and lastphase.
1016 */
1017 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1018 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1019 errorphase = curphase;
1020 else
1021 errorphase = lastphase;
1022
1023 for (i = 0; i < num_phases; i++) {
1024 if (errorphase == ahc_phase_table[i].phase)
1025 break;
1026 }
1027 mesg_out = ahc_phase_table[i].mesg_out;
1028 if (scb != NULL)
1029 ahc_print_path(ahc, scb);
1030 else
1031 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1032 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1033 scsirate = ahc_inb(ahc, SCSIRATE);
1034 printf("parity error detected %s. "
1035 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1036 ahc_phase_table[i].phasemsg,
1037 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8),
1038 scsirate);
1039
1040 if ((ahc->features & AHC_DT) != 0) {
1041
1042 if ((sstat2 & CRCVALERR) != 0)
1043 printf("\tCRC Value Mismatch\n");
1044 if ((sstat2 & CRCENDERR) != 0)
1045 printf("\tNo terminal CRC packet recevied\n");
1046 if ((sstat2 & CRCREQERR) != 0)
1047 printf("\tIllegal CRC packet request\n");
1048 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1049 printf("\tUnexpected %sDT Data Phase\n",
1050 (scsirate & SINGLE_EDGE) ? "" : "non-");
1051 }
1052
1053 /*
1054 * We've set the hardware to assert ATN if we
1055 * get a parity error on "in" phases, so all we
1056 * need to do is stuff the message buffer with
1057 * the appropriate message. "In" phases have set
1058 * mesg_out to something other than MSG_NOP.
1059 */
1060 if (mesg_out != MSG_NOOP) {
1061 if (ahc->msg_type != MSG_TYPE_NONE)
1062 ahc->send_msg_perror = TRUE;
1063 else
1064 ahc_outb(ahc, MSG_OUT, mesg_out);
1065 }
1066 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1067 ahc_unpause(ahc);
1068 } else if ((status & SELTO) != 0) {
1069 u_int scbptr;
1070
1071 /* Stop the selection */
1072 ahc_outb(ahc, SCSISEQ, 0);
1073
1074 /* No more pending messages */
1075 ahc_clear_msg_state(ahc);
1076
1077 /* Clear interrupt state */
1078 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1079 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1080
1081 /*
1082 * Although the driver does not care about the
1083 * 'Selection in Progress' status bit, the busy
1084 * LED does. SELINGO is only cleared by a sucessfull
1085 * selection, so we must manually clear it to insure
1086 * the LED turns off just incase no future successful
1087 * selections occur (e.g. no devices on the bus).
1088 */
1089 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1090
1091 scbptr = ahc_inb(ahc, WAITING_SCBH);
1092 ahc_outb(ahc, SCBPTR, scbptr);
1093 scb_index = ahc_inb(ahc, SCB_TAG);
1094
1095 scb = ahc_lookup_scb(ahc, scb_index);
1096 if (scb == NULL) {
1097 printf("%s: ahc_intr - referenced scb not "
1098 "valid during SELTO scb(%d, %d)\n",
1099 ahc_name(ahc), scbptr, scb_index);
1100 } else {
1101 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1102 ahc_freeze_devq(ahc, scb);
1103 }
1104 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1105 ahc_restart(ahc);
1106 } else if ((status & BUSFREE) != 0
1107 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1108 u_int lastphase;
1109 u_int saved_scsiid;
1110 u_int saved_lun;
1111 u_int target;
1112 u_int initiator_role_id;
1113 char channel;
1114 int printerror;
1115
1116 /*
1117 * Clear our selection hardware as soon as possible.
1118 * We may have an entry in the waiting Q for this target,
1119 * that is affected by this busfree and we don't want to
1120 * go about selecting the target while we handle the event.
1121 */
1122 ahc_outb(ahc, SCSISEQ,
1123 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1124
1125 /*
1126 * Disable busfree interrupts and clear the busfree
1127 * interrupt status. We do this here so that several
1128 * bus transactions occur prior to clearing the SCSIINT
1129 * latch. It can take a bit for the clearing to take effect.
1130 */
1131 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1132 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1133
1134 /*
1135 * Look at what phase we were last in.
1136 * If its message out, chances are pretty good
1137 * that the busfree was in response to one of
1138 * our abort requests.
1139 */
1140 lastphase = ahc_inb(ahc, LASTPHASE);
1141 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1142 saved_lun = ahc_inb(ahc, SAVED_LUN);
1143 target = SCSIID_TARGET(ahc, saved_scsiid);
1144 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1145 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1146 printerror = 1;
1147
1148 if (lastphase == P_MESGOUT) {
1149 struct ahc_devinfo devinfo;
1150 u_int tag;
1151
1152 ahc_fetch_devinfo(ahc, &devinfo);
1153 tag = SCB_LIST_NULL;
1154 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1155 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1156 if (ahc->msgout_buf[ahc->msgout_index - 1]
1157 == MSG_ABORT_TAG)
1158 tag = scb->hscb->tag;
1159 ahc_print_path(ahc, scb);
1160 printf("SCB %d - Abort%s Completed.\n",
1161 scb->hscb->tag, tag == SCB_LIST_NULL ?
1162 "" : " Tag");
1163 ahc_abort_scbs(ahc, target, channel,
1164 saved_lun, tag,
1165 ROLE_INITIATOR,
1166 CAM_REQ_ABORTED);
1167 printerror = 0;
1168 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1169 MSG_BUS_DEV_RESET, TRUE)) {
1170 struct ahc_devinfo devinfo;
1171 #ifdef __FreeBSD__
1172 /*
1173 * Don't mark the user's request for this BDR
1174 * as completing with CAM_BDR_SENT. CAM3
1175 * specifies CAM_REQ_CMP.
1176 */
1177 if (scb != NULL
1178 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1179 && ahc_match_scb(ahc, scb, target, channel,
1180 CAM_LUN_WILDCARD,
1181 SCB_LIST_NULL,
1182 ROLE_INITIATOR)) {
1183 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1184 }
1185 #endif
1186 ahc_compile_devinfo(&devinfo,
1187 initiator_role_id,
1188 target,
1189 CAM_LUN_WILDCARD,
1190 channel,
1191 ROLE_INITIATOR);
1192 ahc_handle_devreset(ahc, &devinfo,
1193 CAM_BDR_SENT,
1194 "Bus Device Reset",
1195 /*verbose_level*/0);
1196 printerror = 0;
1197 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1198 MSG_EXT_PPR, FALSE)) {
1199 struct ahc_initiator_tinfo *tinfo;
1200 struct ahc_tmode_tstate *tstate;
1201
1202 /*
1203 * PPR Rejected. Try non-ppr negotiation
1204 * and retry command.
1205 */
1206 tinfo = ahc_fetch_transinfo(ahc,
1207 devinfo.channel,
1208 devinfo.our_scsiid,
1209 devinfo.target,
1210 &tstate);
1211 tinfo->curr.transport_version = 2;
1212 tinfo->goal.transport_version = 2;
1213 tinfo->goal.ppr_options = 0;
1214 ahc_qinfifo_requeue_tail(ahc, scb);
1215 printerror = 0;
1216 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1217 MSG_EXT_WDTR, FALSE)
1218 || ahc_sent_msg(ahc, AHCMSG_EXT,
1219 MSG_EXT_SDTR, FALSE)) {
1220 /*
1221 * Negotiation Rejected. Go-async and
1222 * retry command.
1223 */
1224 ahc_set_width(ahc, &devinfo,
1225 MSG_EXT_WDTR_BUS_8_BIT,
1226 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1227 /*paused*/TRUE);
1228 ahc_set_syncrate(ahc, &devinfo,
1229 /*syncrate*/NULL,
1230 /*period*/0, /*offset*/0,
1231 /*ppr_options*/0,
1232 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1233 /*paused*/TRUE);
1234 ahc_qinfifo_requeue_tail(ahc, scb);
1235 printerror = 0;
1236 }
1237 }
1238 if (printerror != 0) {
1239 u_int i;
1240
1241 if (scb != NULL) {
1242 u_int tag;
1243
1244 if ((scb->hscb->control & TAG_ENB) != 0)
1245 tag = scb->hscb->tag;
1246 else
1247 tag = SCB_LIST_NULL;
1248 ahc_print_path(ahc, scb);
1249 ahc_abort_scbs(ahc, target, channel,
1250 SCB_GET_LUN(scb), tag,
1251 ROLE_INITIATOR,
1252 CAM_UNEXP_BUSFREE);
1253 } else {
1254 /*
1255 * We had not fully identified this connection,
1256 * so we cannot abort anything.
1257 */
1258 printf("%s: ", ahc_name(ahc));
1259 }
1260 for (i = 0; i < num_phases; i++) {
1261 if (lastphase == ahc_phase_table[i].phase)
1262 break;
1263 }
1264 printf("Unexpected busfree %s\n"
1265 "SEQADDR == 0x%x\n",
1266 ahc_phase_table[i].phasemsg,
1267 ahc_inb(ahc, SEQADDR0)
1268 | (ahc_inb(ahc, SEQADDR1) << 8));
1269 }
1270 ahc_clear_msg_state(ahc);
1271 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1272 ahc_restart(ahc);
1273 } else {
1274 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1275 ahc_name(ahc), status);
1276 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1277 }
1278 }
1279
1280 #define AHC_MAX_STEPS 2000
1281 void
1282 ahc_clear_critical_section(struct ahc_softc *ahc)
1283 {
1284 int stepping;
1285 int steps;
1286 u_int simode0;
1287 u_int simode1;
1288
1289 if (ahc->num_critical_sections == 0)
1290 return;
1291
1292 stepping = FALSE;
1293 steps = 0;
1294 simode0 = 0;
1295 simode1 = 0;
1296 for (;;) {
1297 struct cs *cs;
1298 u_int seqaddr;
1299 u_int i;
1300
1301 seqaddr = ahc_inb(ahc, SEQADDR0)
1302 | (ahc_inb(ahc, SEQADDR1) << 8);
1303
1304 /*
1305 * Seqaddr represents the next instruction to execute,
1306 * so we are really executing the instruction just
1307 * before it.
1308 */
1309 if (seqaddr != 0)
1310 seqaddr -= 1;
1311 cs = ahc->critical_sections;
1312 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1313
1314 if (cs->begin < seqaddr && cs->end >= seqaddr)
1315 break;
1316 }
1317
1318 if (i == ahc->num_critical_sections)
1319 break;
1320
1321 if (steps > AHC_MAX_STEPS) {
1322 printf("%s: Infinite loop in critical section\n",
1323 ahc_name(ahc));
1324 ahc_dump_card_state(ahc);
1325 panic("critical section loop");
1326 }
1327
1328 steps++;
1329 if (stepping == FALSE) {
1330
1331 /*
1332 * Disable all interrupt sources so that the
1333 * sequencer will not be stuck by a pausing
1334 * interrupt condition while we attempt to
1335 * leave a critical section.
1336 */
1337 simode0 = ahc_inb(ahc, SIMODE0);
1338 ahc_outb(ahc, SIMODE0, 0);
1339 simode1 = ahc_inb(ahc, SIMODE1);
1340 ahc_outb(ahc, SIMODE1, 0);
1341 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1342 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP);
1343 stepping = TRUE;
1344 }
1345 ahc_outb(ahc, HCNTRL, ahc->unpause);
1346 do {
1347 ahc_delay(200);
1348 } while (!ahc_is_paused(ahc));
1349 }
1350 if (stepping) {
1351 ahc_outb(ahc, SIMODE0, simode0);
1352 ahc_outb(ahc, SIMODE1, simode1);
1353 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP);
1354 }
1355 }
1356
1357 /*
1358 * Clear any pending interrupt status.
1359 */
1360 void
1361 ahc_clear_intstat(struct ahc_softc *ahc)
1362 {
1363 /* Clear any interrupt conditions this may have caused */
1364 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1365 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1366 CLRREQINIT);
1367 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1368 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1369 }
1370
1371 /**************************** Debugging Routines ******************************/
1372 void
1373 ahc_print_scb(struct scb *scb)
1374 {
1375 int i;
1376
1377 struct hardware_scb *hscb = scb->hscb;
1378
1379 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1380 (void *)scb,
1381 hscb->control,
1382 hscb->scsiid,
1383 hscb->lun,
1384 hscb->cdb_len);
1385 printf("Shared Data: %#02x %#02x %#02x %#02x\n",
1386 hscb->shared_data.cdb[0],
1387 hscb->shared_data.cdb[1],
1388 hscb->shared_data.cdb[2],
1389 hscb->shared_data.cdb[3]);
1390 printf(" %#02x %#02x %#02x %#02x\n",
1391 hscb->shared_data.cdb[4],
1392 hscb->shared_data.cdb[5],
1393 hscb->shared_data.cdb[6],
1394 hscb->shared_data.cdb[7]);
1395 printf(" %#02x %#02x %#02x %#02x\n",
1396 hscb->shared_data.cdb[8],
1397 hscb->shared_data.cdb[9],
1398 hscb->shared_data.cdb[10],
1399 hscb->shared_data.cdb[11]);
1400 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1401 ahc_le32toh(hscb->dataptr),
1402 ahc_le32toh(hscb->datacnt),
1403 ahc_le32toh(hscb->sgptr),
1404 hscb->tag);
1405 if (scb->sg_count > 0) {
1406 for (i = 0; i < scb->sg_count; i++) {
1407 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1408 i,
1409 (ahc_le32toh(scb->sg_list[i].len) >> 24
1410 & SG_HIGH_ADDR_BITS),
1411 ahc_le32toh(scb->sg_list[i].addr),
1412 ahc_le32toh(scb->sg_list[i].len));
1413 }
1414 }
1415 }
1416
1417 /************************* Transfer Negotiation *******************************/
1418 /*
1419 * Allocate per target mode instance (ID we respond to as a target)
1420 * transfer negotiation data structures.
1421 */
1422 static struct ahc_tmode_tstate *
1423 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1424 {
1425 struct ahc_tmode_tstate *master_tstate;
1426 struct ahc_tmode_tstate *tstate;
1427 int i;
1428
1429 master_tstate = ahc->enabled_targets[ahc->our_id];
1430 if (channel == 'B') {
1431 scsi_id += 8;
1432 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1433 }
1434 if (ahc->enabled_targets[scsi_id] != NULL
1435 && ahc->enabled_targets[scsi_id] != master_tstate)
1436 panic("%s: ahc_alloc_tstate - Target already allocated",
1437 ahc_name(ahc));
1438 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
1439 if (tstate == NULL)
1440 return (NULL);
1441
1442 /*
1443 * If we have allocated a master tstate, copy user settings from
1444 * the master tstate (taken from SRAM or the EEPROM) for this
1445 * channel, but reset our current and goal settings to async/narrow
1446 * until an initiator talks to us.
1447 */
1448 if (master_tstate != NULL) {
1449 memcpy(tstate, master_tstate, sizeof(*tstate));
1450 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1451 tstate->ultraenb = 0;
1452 for (i = 0; i < 16; i++) {
1453 memset(&tstate->transinfo[i].curr, 0,
1454 sizeof(tstate->transinfo[i].curr));
1455 memset(&tstate->transinfo[i].goal, 0,
1456 sizeof(tstate->transinfo[i].goal));
1457 }
1458 } else
1459 memset(tstate, 0, sizeof(*tstate));
1460 ahc->enabled_targets[scsi_id] = tstate;
1461 return (tstate);
1462 }
1463
1464 #ifdef AHC_TARGET_MODE
1465 /*
1466 * Free per target mode instance (ID we respond to as a target)
1467 * transfer negotiation data structures.
1468 */
1469 static void
1470 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1471 {
1472 struct ahc_tmode_tstate *tstate;
1473
1474 /*
1475 * Don't clean up our "master" tstate.
1476 * It has our default user settings.
1477 */
1478 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1479 || (channel == 'A' && scsi_id == ahc->our_id))
1480 && force == FALSE)
1481 return;
1482
1483 if (channel == 'B')
1484 scsi_id += 8;
1485 tstate = ahc->enabled_targets[scsi_id];
1486 if (tstate != NULL)
1487 free(tstate, M_DEVBUF);
1488 ahc->enabled_targets[scsi_id] = NULL;
1489 }
1490 #endif
1491
1492 /*
1493 * Called when we have an active connection to a target on the bus,
1494 * this function finds the nearest syncrate to the input period limited
1495 * by the capabilities of the bus connectivity of and sync settings for
1496 * the target.
1497 */
1498 struct ahc_syncrate *
1499 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1500 struct ahc_initiator_tinfo *tinfo,
1501 u_int *period, u_int *ppr_options, role_t role) {
1502 struct ahc_transinfo *transinfo;
1503 u_int maxsync;
1504
1505 if ((ahc->features & AHC_ULTRA2) != 0) {
1506 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1507 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1508 maxsync = AHC_SYNCRATE_DT;
1509 } else {
1510 maxsync = AHC_SYNCRATE_ULTRA;
1511 /* Can't do DT on an SE bus */
1512 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1513 }
1514 } else if ((ahc->features & AHC_ULTRA) != 0) {
1515 maxsync = AHC_SYNCRATE_ULTRA;
1516 } else {
1517 maxsync = AHC_SYNCRATE_FAST;
1518 }
1519 /*
1520 * Never allow a value higher than our current goal
1521 * period otherwise we may allow a target initiated
1522 * negotiation to go above the limit as set by the
1523 * user. In the case of an initiator initiated
1524 * sync negotiation, we limit based on the user
1525 * setting. This allows the system to still accept
1526 * incoming negotiations even if target initiated
1527 * negotiation is not performed.
1528 */
1529 if (role == ROLE_TARGET)
1530 transinfo = &tinfo->user;
1531 else
1532 transinfo = &tinfo->goal;
1533 *ppr_options &= transinfo->ppr_options;
1534 if (transinfo->period == 0) {
1535 *period = 0;
1536 *ppr_options = 0;
1537 return (NULL);
1538 }
1539 *period = MAX(*period, transinfo->period);
1540 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1541 }
1542
1543 /*
1544 * Look up the valid period to SCSIRATE conversion in our table.
1545 * Return the period and offset that should be sent to the target
1546 * if this was the beginning of an SDTR.
1547 */
1548 struct ahc_syncrate *
1549 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1550 u_int *ppr_options, u_int maxsync)
1551 {
1552 struct ahc_syncrate *syncrate;
1553
1554 if ((ahc->features & AHC_DT) == 0)
1555 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1556
1557 /* Skip all DT only entries if DT is not available */
1558 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1559 && maxsync < AHC_SYNCRATE_ULTRA2)
1560 maxsync = AHC_SYNCRATE_ULTRA2;
1561
1562 for (syncrate = &ahc_syncrates[maxsync];
1563 syncrate->rate != NULL;
1564 syncrate++) {
1565
1566 /*
1567 * The Ultra2 table doesn't go as low
1568 * as for the Fast/Ultra cards.
1569 */
1570 if ((ahc->features & AHC_ULTRA2) != 0
1571 && (syncrate->sxfr_u2 == 0))
1572 break;
1573
1574 if (*period <= syncrate->period) {
1575 /*
1576 * When responding to a target that requests
1577 * sync, the requested rate may fall between
1578 * two rates that we can output, but still be
1579 * a rate that we can receive. Because of this,
1580 * we want to respond to the target with
1581 * the same rate that it sent to us even
1582 * if the period we use to send data to it
1583 * is lower. Only lower the response period
1584 * if we must.
1585 */
1586 if (syncrate == &ahc_syncrates[maxsync])
1587 *period = syncrate->period;
1588
1589 /*
1590 * At some speeds, we only support
1591 * ST transfers.
1592 */
1593 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1594 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1595 break;
1596 }
1597 }
1598
1599 if ((*period == 0)
1600 || (syncrate->rate == NULL)
1601 || ((ahc->features & AHC_ULTRA2) != 0
1602 && (syncrate->sxfr_u2 == 0))) {
1603 /* Use asynchronous transfers. */
1604 *period = 0;
1605 syncrate = NULL;
1606 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1607 }
1608 return (syncrate);
1609 }
1610
1611 /*
1612 * Convert from an entry in our syncrate table to the SCSI equivalent
1613 * sync "period" factor.
1614 */
1615 u_int
1616 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1617 {
1618 struct ahc_syncrate *syncrate;
1619
1620 if ((ahc->features & AHC_ULTRA2) != 0)
1621 scsirate &= SXFR_ULTRA2;
1622 else
1623 scsirate &= SXFR;
1624
1625 syncrate = &ahc_syncrates[maxsync];
1626 while (syncrate->rate != NULL) {
1627
1628 if ((ahc->features & AHC_ULTRA2) != 0) {
1629 if (syncrate->sxfr_u2 == 0)
1630 break;
1631 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1632 return (syncrate->period);
1633 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1634 return (syncrate->period);
1635 }
1636 syncrate++;
1637 }
1638 return (0); /* async */
1639 }
1640
1641 /*
1642 * Truncate the given synchronous offset to a value the
1643 * current adapter type and syncrate are capable of.
1644 */
1645 void
1646 ahc_validate_offset(struct ahc_softc *ahc,
1647 struct ahc_initiator_tinfo *tinfo,
1648 struct ahc_syncrate *syncrate,
1649 u_int *offset, int wide, role_t role)
1650 {
1651 u_int maxoffset;
1652
1653 /* Limit offset to what we can do */
1654 if (syncrate == NULL) {
1655 maxoffset = 0;
1656 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1657 maxoffset = MAX_OFFSET_ULTRA2;
1658 } else {
1659 if (wide)
1660 maxoffset = MAX_OFFSET_16BIT;
1661 else
1662 maxoffset = MAX_OFFSET_8BIT;
1663 }
1664 *offset = MIN(*offset, maxoffset);
1665 if (tinfo != NULL) {
1666 if (role == ROLE_TARGET)
1667 *offset = MIN(*offset, tinfo->user.offset);
1668 else
1669 *offset = MIN(*offset, tinfo->goal.offset);
1670 }
1671 }
1672
1673 /*
1674 * Truncate the given transfer width parameter to a value the
1675 * current adapter type is capable of.
1676 */
1677 void
1678 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1679 u_int *bus_width, role_t role)
1680 {
1681 switch (*bus_width) {
1682 default:
1683 if (ahc->features & AHC_WIDE) {
1684 /* Respond Wide */
1685 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1686 break;
1687 }
1688 /* FALLTHROUGH */
1689 case MSG_EXT_WDTR_BUS_8_BIT:
1690 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1691 break;
1692 }
1693 if (tinfo != NULL) {
1694 if (role == ROLE_TARGET)
1695 *bus_width = MIN(tinfo->user.width, *bus_width);
1696 else
1697 *bus_width = MIN(tinfo->goal.width, *bus_width);
1698 }
1699 }
1700
1701 /*
1702 * Update the bitmask of targets for which the controller should
1703 * negotiate with at the next convenient oportunity. This currently
1704 * means the next time we send the initial identify messages for
1705 * a new transaction.
1706 */
1707 int
1708 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1709 struct ahc_tmode_tstate *tstate,
1710 struct ahc_initiator_tinfo *tinfo, int force)
1711 {
1712 u_int auto_negotiate_orig;
1713
1714 auto_negotiate_orig = tstate->auto_negotiate;
1715 if (tinfo->curr.period != tinfo->goal.period
1716 || tinfo->curr.width != tinfo->goal.width
1717 || tinfo->curr.offset != tinfo->goal.offset
1718 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1719 || (force
1720 && (tinfo->goal.period != 0
1721 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1722 || tinfo->goal.ppr_options != 0)))
1723 tstate->auto_negotiate |= devinfo->target_mask;
1724 else
1725 tstate->auto_negotiate &= ~devinfo->target_mask;
1726
1727 return (auto_negotiate_orig != tstate->auto_negotiate);
1728 }
1729
1730 /*
1731 * Update the user/goal/curr tables of synchronous negotiation
1732 * parameters as well as, in the case of a current or active update,
1733 * any data structures on the host controller. In the case of an
1734 * active update, the specified target is currently talking to us on
1735 * the bus, so the transfer parameter update must take effect
1736 * immediately.
1737 */
1738 void
1739 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1740 struct ahc_syncrate *syncrate, u_int period,
1741 u_int offset, u_int ppr_options, u_int type, int paused)
1742 {
1743 struct ahc_initiator_tinfo *tinfo;
1744 struct ahc_tmode_tstate *tstate;
1745 u_int old_period;
1746 u_int old_offset;
1747 u_int old_ppr;
1748 int active;
1749 int update_needed;
1750
1751 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1752 update_needed = 0;
1753
1754 if (syncrate == NULL) {
1755 period = 0;
1756 offset = 0;
1757 }
1758
1759 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1760 devinfo->target, &tstate);
1761
1762 if ((type & AHC_TRANS_USER) != 0) {
1763 tinfo->user.period = period;
1764 tinfo->user.offset = offset;
1765 tinfo->user.ppr_options = ppr_options;
1766 }
1767
1768 if ((type & AHC_TRANS_GOAL) != 0) {
1769 tinfo->goal.period = period;
1770 tinfo->goal.offset = offset;
1771 tinfo->goal.ppr_options = ppr_options;
1772 }
1773
1774 old_period = tinfo->curr.period;
1775 old_offset = tinfo->curr.offset;
1776 old_ppr = tinfo->curr.ppr_options;
1777
1778 if ((type & AHC_TRANS_CUR) != 0
1779 && (old_period != period
1780 || old_offset != offset
1781 || old_ppr != ppr_options)) {
1782 u_int scsirate;
1783
1784 update_needed++;
1785 scsirate = tinfo->scsirate;
1786 if ((ahc->features & AHC_ULTRA2) != 0) {
1787
1788 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1789 if (syncrate != NULL) {
1790 scsirate |= syncrate->sxfr_u2;
1791 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1792 scsirate |= ENABLE_CRC;
1793 else
1794 scsirate |= SINGLE_EDGE;
1795 }
1796 } else {
1797
1798 scsirate &= ~(SXFR|SOFS);
1799 /*
1800 * Ensure Ultra mode is set properly for
1801 * this target.
1802 */
1803 tstate->ultraenb &= ~devinfo->target_mask;
1804 if (syncrate != NULL) {
1805 if (syncrate->sxfr & ULTRA_SXFR) {
1806 tstate->ultraenb |=
1807 devinfo->target_mask;
1808 }
1809 scsirate |= syncrate->sxfr & SXFR;
1810 scsirate |= offset & SOFS;
1811 }
1812 if (active) {
1813 u_int sxfrctl0;
1814
1815 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1816 sxfrctl0 &= ~FAST20;
1817 if (tstate->ultraenb & devinfo->target_mask)
1818 sxfrctl0 |= FAST20;
1819 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1820 }
1821 }
1822 if (active) {
1823 ahc_outb(ahc, SCSIRATE, scsirate);
1824 if ((ahc->features & AHC_ULTRA2) != 0)
1825 ahc_outb(ahc, SCSIOFFSET, offset);
1826 }
1827
1828 tinfo->scsirate = scsirate;
1829 tinfo->curr.period = period;
1830 tinfo->curr.offset = offset;
1831 tinfo->curr.ppr_options = ppr_options;
1832
1833 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1834 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1835 if (bootverbose) {
1836 if (offset != 0) {
1837 printf("%s: target %d synchronous at %sMHz%s, "
1838 "offset = 0x%x\n", ahc_name(ahc),
1839 devinfo->target, syncrate->rate,
1840 (ppr_options & MSG_EXT_PPR_DT_REQ)
1841 ? " DT" : "", offset);
1842 } else {
1843 printf("%s: target %d using "
1844 "asynchronous transfers\n",
1845 ahc_name(ahc), devinfo->target);
1846 }
1847 }
1848 }
1849
1850 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
1851 tinfo, /*force*/FALSE);
1852
1853 if (update_needed)
1854 ahc_update_pending_scbs(ahc);
1855 }
1856
1857 /*
1858 * Update the user/goal/curr tables of wide negotiation
1859 * parameters as well as, in the case of a current or active update,
1860 * any data structures on the host controller. In the case of an
1861 * active update, the specified target is currently talking to us on
1862 * the bus, so the transfer parameter update must take effect
1863 * immediately.
1864 */
1865 void
1866 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1867 u_int width, u_int type, int paused)
1868 {
1869 struct ahc_initiator_tinfo *tinfo;
1870 struct ahc_tmode_tstate *tstate;
1871 u_int oldwidth;
1872 int active;
1873 int update_needed;
1874
1875 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1876 update_needed = 0;
1877 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1878 devinfo->target, &tstate);
1879
1880 if ((type & AHC_TRANS_USER) != 0)
1881 tinfo->user.width = width;
1882
1883 if ((type & AHC_TRANS_GOAL) != 0)
1884 tinfo->goal.width = width;
1885
1886 oldwidth = tinfo->curr.width;
1887 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
1888 u_int scsirate;
1889
1890 update_needed++;
1891 scsirate = tinfo->scsirate;
1892 scsirate &= ~WIDEXFER;
1893 if (width == MSG_EXT_WDTR_BUS_16_BIT)
1894 scsirate |= WIDEXFER;
1895
1896 tinfo->scsirate = scsirate;
1897
1898 if (active)
1899 ahc_outb(ahc, SCSIRATE, scsirate);
1900
1901 tinfo->curr.width = width;
1902
1903 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1904 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1905 if (bootverbose) {
1906 printf("%s: target %d using %dbit transfers\n",
1907 ahc_name(ahc), devinfo->target,
1908 8 * (0x01 << width));
1909 }
1910 }
1911
1912 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
1913 tinfo, /*force*/FALSE);
1914 if (update_needed)
1915 ahc_update_pending_scbs(ahc);
1916 }
1917
1918 /*
1919 * Update the current state of tagged queuing for a given target.
1920 */
1921 void
1922 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1923 ahc_queue_alg alg)
1924 {
1925 ahc_platform_set_tags(ahc, devinfo, alg);
1926 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1927 devinfo->lun, AC_TRANSFER_NEG, &alg);
1928 }
1929
1930 /*
1931 * When the transfer settings for a connection change, update any
1932 * in-transit SCBs to contain the new data so the hardware will
1933 * be set correctly during future (re)selections.
1934 */
1935 static void
1936 ahc_update_pending_scbs(struct ahc_softc *ahc)
1937 {
1938 struct scb *pending_scb;
1939 int pending_scb_count;
1940 int i;
1941 int paused;
1942 u_int saved_scbptr;
1943
1944 /*
1945 * Traverse the pending SCB list and ensure that all of the
1946 * SCBs there have the proper settings.
1947 */
1948 pending_scb_count = 0;
1949 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
1950 struct ahc_devinfo devinfo;
1951 struct hardware_scb *pending_hscb;
1952 struct ahc_initiator_tinfo *tinfo;
1953 struct ahc_tmode_tstate *tstate;
1954
1955 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
1956 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
1957 devinfo.our_scsiid,
1958 devinfo.target, &tstate);
1959 pending_hscb = pending_scb->hscb;
1960 pending_hscb->control &= ~ULTRAENB;
1961 if ((tstate->ultraenb & devinfo.target_mask) != 0)
1962 pending_hscb->control |= ULTRAENB;
1963 pending_hscb->scsirate = tinfo->scsirate;
1964 pending_hscb->scsioffset = tinfo->curr.offset;
1965 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
1966 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
1967 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
1968 pending_hscb->control &= ~MK_MESSAGE;
1969 }
1970 ahc_sync_scb(ahc, pending_scb,
1971 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1972 pending_scb_count++;
1973 }
1974
1975 if (pending_scb_count == 0)
1976 return;
1977
1978 if (ahc_is_paused(ahc)) {
1979 paused = 1;
1980 } else {
1981 paused = 0;
1982 ahc_pause(ahc);
1983 }
1984
1985 saved_scbptr = ahc_inb(ahc, SCBPTR);
1986 /* Ensure that the hscbs down on the card match the new information */
1987 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
1988 struct hardware_scb *pending_hscb;
1989 u_int control;
1990 u_int scb_tag;
1991
1992 ahc_outb(ahc, SCBPTR, i);
1993 scb_tag = ahc_inb(ahc, SCB_TAG);
1994 pending_scb = ahc_lookup_scb(ahc, scb_tag);
1995 if (pending_scb == NULL)
1996 continue;
1997
1998 pending_hscb = pending_scb->hscb;
1999 control = ahc_inb(ahc, SCB_CONTROL);
2000 control &= ~(ULTRAENB|MK_MESSAGE);
2001 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2002 ahc_outb(ahc, SCB_CONTROL, control);
2003 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2004 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2005 }
2006 ahc_outb(ahc, SCBPTR, saved_scbptr);
2007
2008 if (paused == 0)
2009 ahc_unpause(ahc);
2010 }
2011
2012 /**************************** Pathing Information *****************************/
2013 static void
2014 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2015 {
2016 u_int saved_scsiid;
2017 role_t role;
2018 int our_id;
2019
2020 if (ahc_inb(ahc, SSTAT0) & TARGET)
2021 role = ROLE_TARGET;
2022 else
2023 role = ROLE_INITIATOR;
2024
2025 if (role == ROLE_TARGET
2026 && (ahc->features & AHC_MULTI_TID) != 0
2027 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
2028 /* We were selected, so pull our id from TARGIDIN */
2029 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2030 } else if ((ahc->features & AHC_ULTRA2) != 0)
2031 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2032 else
2033 our_id = ahc_inb(ahc, SCSIID) & OID;
2034
2035 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2036 ahc_compile_devinfo(devinfo,
2037 our_id,
2038 SCSIID_TARGET(ahc, saved_scsiid),
2039 ahc_inb(ahc, SAVED_LUN),
2040 SCSIID_CHANNEL(ahc, saved_scsiid),
2041 role);
2042 }
2043
2044 struct ahc_phase_table_entry*
2045 ahc_lookup_phase_entry(int phase)
2046 {
2047 struct ahc_phase_table_entry *entry;
2048 struct ahc_phase_table_entry *last_entry;
2049
2050 /*
2051 * num_phases doesn't include the default entry which
2052 * will be returned if the phase doesn't match.
2053 */
2054 last_entry = &ahc_phase_table[num_phases];
2055 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2056 if (phase == entry->phase)
2057 break;
2058 }
2059 return (entry);
2060 }
2061
2062 void
2063 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2064 u_int lun, char channel, role_t role)
2065 {
2066 devinfo->our_scsiid = our_id;
2067 devinfo->target = target;
2068 devinfo->lun = lun;
2069 devinfo->target_offset = target;
2070 devinfo->channel = channel;
2071 devinfo->role = role;
2072 if (channel == 'B')
2073 devinfo->target_offset += 8;
2074 devinfo->target_mask = (0x01 << devinfo->target_offset);
2075 }
2076
2077 static void
2078 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2079 struct scb *scb)
2080 {
2081 role_t role;
2082 int our_id;
2083
2084 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2085 role = ROLE_INITIATOR;
2086 if ((scb->hscb->control & TARGET_SCB) != 0)
2087 role = ROLE_TARGET;
2088 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2089 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2090 }
2091
2092
2093 /************************ Message Phase Processing ****************************/
2094 static void
2095 ahc_assert_atn(struct ahc_softc *ahc)
2096 {
2097 u_int scsisigo;
2098
2099 scsisigo = ATNO;
2100 if ((ahc->features & AHC_DT) == 0)
2101 scsisigo |= ahc_inb(ahc, SCSISIGI);
2102 ahc_outb(ahc, SCSISIGO, scsisigo);
2103 }
2104
2105 /*
2106 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2107 * or enters the initial message out phase, we are interrupted. Fill our
2108 * outgoing message buffer with the appropriate message and beging handing
2109 * the message phase(s) manually.
2110 */
2111 static void
2112 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2113 struct scb *scb)
2114 {
2115 /*
2116 * To facilitate adding multiple messages together,
2117 * each routine should increment the index and len
2118 * variables instead of setting them explicitly.
2119 */
2120 ahc->msgout_index = 0;
2121 ahc->msgout_len = 0;
2122
2123 if ((scb->flags & SCB_DEVICE_RESET) == 0
2124 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2125 u_int identify_msg;
2126
2127 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2128 if ((scb->hscb->control & DISCENB) != 0)
2129 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2130 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2131 ahc->msgout_len++;
2132
2133 if ((scb->hscb->control & TAG_ENB) != 0) {
2134 ahc->msgout_buf[ahc->msgout_index++] =
2135 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2136 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2137 ahc->msgout_len += 2;
2138 }
2139 }
2140
2141 if (scb->flags & SCB_DEVICE_RESET) {
2142 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2143 ahc->msgout_len++;
2144 ahc_print_path(ahc, scb);
2145 printf("Bus Device Reset Message Sent\n");
2146 /*
2147 * Clear our selection hardware in advance of
2148 * the busfree. We may have an entry in the waiting
2149 * Q for this target, and we don't want to go about
2150 * selecting while we handle the busfree and blow it
2151 * away.
2152 */
2153 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2154 } else if ((scb->flags & SCB_ABORT) != 0) {
2155 if ((scb->hscb->control & TAG_ENB) != 0)
2156 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2157 else
2158 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2159 ahc->msgout_len++;
2160 ahc_print_path(ahc, scb);
2161 printf("Abort%s Message Sent\n",
2162 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2163 /*
2164 * Clear our selection hardware in advance of
2165 * the busfree. We may have an entry in the waiting
2166 * Q for this target, and we don't want to go about
2167 * selecting while we handle the busfree and blow it
2168 * away.
2169 */
2170 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2171 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2172 ahc_build_transfer_msg(ahc, devinfo);
2173 } else {
2174 printf("ahc_intr: AWAITING_MSG for an SCB that "
2175 "does not have a waiting message\n");
2176 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2177 devinfo->target_mask);
2178 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2179 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2180 ahc_inb(ahc, MSG_OUT), scb->flags);
2181 }
2182
2183 /*
2184 * Clear the MK_MESSAGE flag from the SCB so we aren't
2185 * asked to send this message again.
2186 */
2187 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2188 scb->hscb->control &= ~MK_MESSAGE;
2189 ahc->msgout_index = 0;
2190 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2191 }
2192
2193 /*
2194 * Build an appropriate transfer negotiation message for the
2195 * currently active target.
2196 */
2197 static void
2198 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2199 {
2200 /*
2201 * We need to initiate transfer negotiations.
2202 * If our current and goal settings are identical,
2203 * we want to renegotiate due to a check condition.
2204 */
2205 struct ahc_initiator_tinfo *tinfo;
2206 struct ahc_tmode_tstate *tstate;
2207 struct ahc_syncrate *rate;
2208 int dowide;
2209 int dosync;
2210 int doppr;
2211 int use_ppr;
2212 u_int period;
2213 u_int ppr_options;
2214 u_int offset;
2215
2216 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2217 devinfo->target, &tstate);
2218 /*
2219 * Filter our period based on the current connection.
2220 * If we can't perform DT transfers on this segment (not in LVD
2221 * mode for instance), then our decision to issue a PPR message
2222 * may change.
2223 */
2224 period = tinfo->goal.period;
2225 ppr_options = tinfo->goal.ppr_options;
2226 /* Target initiated PPR is not allowed in the SCSI spec */
2227 if (devinfo->role == ROLE_TARGET)
2228 ppr_options = 0;
2229 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2230 &ppr_options, devinfo->role);
2231 dowide = tinfo->curr.width != tinfo->goal.width;
2232 dosync = tinfo->curr.period != period;
2233 doppr = tinfo->curr.ppr_options != ppr_options;
2234
2235 if (!dowide && !dosync && !doppr) {
2236 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2237 dosync = tinfo->goal.period != 0;
2238 doppr = tinfo->goal.ppr_options != 0;
2239 }
2240
2241 if (!dowide && !dosync && !doppr) {
2242 panic("ahc_intr: AWAITING_MSG for negotiation, "
2243 "but no negotiation needed\n");
2244 }
2245
2246 use_ppr = (tinfo->curr.transport_version >= 3) || doppr;
2247 /* Target initiated PPR is not allowed in the SCSI spec */
2248 if (devinfo->role == ROLE_TARGET)
2249 use_ppr = 0;
2250
2251 /*
2252 * Both the PPR message and SDTR message require the
2253 * goal syncrate to be limited to what the target device
2254 * is capable of handling (based on whether an LVD->SE
2255 * expander is on the bus), so combine these two cases.
2256 * Regardless, guarantee that if we are using WDTR and SDTR
2257 * messages that WDTR comes first.
2258 */
2259 if (use_ppr || (dosync && !dowide)) {
2260
2261 offset = tinfo->goal.offset;
2262 ahc_validate_offset(ahc, tinfo, rate, &offset,
2263 use_ppr ? tinfo->goal.width
2264 : tinfo->curr.width,
2265 devinfo->role);
2266 if (use_ppr) {
2267 ahc_construct_ppr(ahc, devinfo, period, offset,
2268 tinfo->goal.width, ppr_options);
2269 } else {
2270 ahc_construct_sdtr(ahc, devinfo, period, offset);
2271 }
2272 } else {
2273 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2274 }
2275 }
2276
2277 /*
2278 * Build a synchronous negotiation message in our message
2279 * buffer based on the input parameters.
2280 */
2281 static void
2282 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2283 u_int period, u_int offset)
2284 {
2285 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2286 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2287 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2288 ahc->msgout_buf[ahc->msgout_index++] = period;
2289 ahc->msgout_buf[ahc->msgout_index++] = offset;
2290 ahc->msgout_len += 5;
2291 if (bootverbose) {
2292 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2293 ahc_name(ahc), devinfo->channel, devinfo->target,
2294 devinfo->lun, period, offset);
2295 }
2296 }
2297
2298 /*
2299 * Build a wide negotiateion message in our message
2300 * buffer based on the input parameters.
2301 */
2302 static void
2303 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2304 u_int bus_width)
2305 {
2306 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2307 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2308 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2309 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2310 ahc->msgout_len += 4;
2311 if (bootverbose) {
2312 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2313 ahc_name(ahc), devinfo->channel, devinfo->target,
2314 devinfo->lun, bus_width);
2315 }
2316 }
2317
2318 /*
2319 * Build a parallel protocol request message in our message
2320 * buffer based on the input parameters.
2321 */
2322 static void
2323 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2324 u_int period, u_int offset, u_int bus_width,
2325 u_int ppr_options)
2326 {
2327 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2328 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2329 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2330 ahc->msgout_buf[ahc->msgout_index++] = period;
2331 ahc->msgout_buf[ahc->msgout_index++] = 0;
2332 ahc->msgout_buf[ahc->msgout_index++] = offset;
2333 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2334 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2335 ahc->msgout_len += 8;
2336 if (bootverbose) {
2337 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2338 "offset %x, ppr_options %x\n", ahc_name(ahc),
2339 devinfo->channel, devinfo->target, devinfo->lun,
2340 bus_width, period, offset, ppr_options);
2341 }
2342 }
2343
2344 /*
2345 * Clear any active message state.
2346 */
2347 static void
2348 ahc_clear_msg_state(struct ahc_softc *ahc)
2349 {
2350 ahc->msgout_len = 0;
2351 ahc->msgin_index = 0;
2352 ahc->msg_type = MSG_TYPE_NONE;
2353 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2354 /*
2355 * The target didn't care to respond to our
2356 * message request, so clear ATN.
2357 */
2358 ahc_outb(ahc, CLRSINT1, CLRATNO);
2359 }
2360 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2361 }
2362
2363 /*
2364 * Manual message loop handler.
2365 */
2366 static void
2367 ahc_handle_message_phase(struct ahc_softc *ahc)
2368 {
2369 struct ahc_devinfo devinfo;
2370 u_int bus_phase;
2371 int end_session;
2372
2373 ahc_fetch_devinfo(ahc, &devinfo);
2374 end_session = FALSE;
2375 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2376
2377 reswitch:
2378 switch (ahc->msg_type) {
2379 case MSG_TYPE_INITIATOR_MSGOUT:
2380 {
2381 int lastbyte;
2382 int phasemis;
2383 int msgdone;
2384
2385 if (ahc->msgout_len == 0)
2386 panic("HOST_MSG_LOOP interrupt with no active message");
2387
2388 phasemis = bus_phase != P_MESGOUT;
2389 if (phasemis) {
2390 if (bus_phase == P_MESGIN) {
2391 /*
2392 * Change gears and see if
2393 * this messages is of interest to
2394 * us or should be passed back to
2395 * the sequencer.
2396 */
2397 ahc_outb(ahc, CLRSINT1, CLRATNO);
2398 ahc->send_msg_perror = FALSE;
2399 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2400 ahc->msgin_index = 0;
2401 goto reswitch;
2402 }
2403 end_session = TRUE;
2404 break;
2405 }
2406
2407 if (ahc->send_msg_perror) {
2408 ahc_outb(ahc, CLRSINT1, CLRATNO);
2409 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2410 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2411 break;
2412 }
2413
2414 msgdone = ahc->msgout_index == ahc->msgout_len;
2415 if (msgdone) {
2416 /*
2417 * The target has requested a retry.
2418 * Re-assert ATN, reset our message index to
2419 * 0, and try again.
2420 */
2421 ahc->msgout_index = 0;
2422 ahc_assert_atn(ahc);
2423 }
2424
2425 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2426 if (lastbyte) {
2427 /* Last byte is signified by dropping ATN */
2428 ahc_outb(ahc, CLRSINT1, CLRATNO);
2429 }
2430
2431 /*
2432 * Clear our interrupt status and present
2433 * the next byte on the bus.
2434 */
2435 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2436 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2437 break;
2438 }
2439 case MSG_TYPE_INITIATOR_MSGIN:
2440 {
2441 int phasemis;
2442 int message_done;
2443
2444 phasemis = bus_phase != P_MESGIN;
2445
2446 if (phasemis) {
2447 ahc->msgin_index = 0;
2448 if (bus_phase == P_MESGOUT
2449 && (ahc->send_msg_perror == TRUE
2450 || (ahc->msgout_len != 0
2451 && ahc->msgout_index == 0))) {
2452 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2453 goto reswitch;
2454 }
2455 end_session = TRUE;
2456 break;
2457 }
2458
2459 /* Pull the byte in without acking it */
2460 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2461
2462 message_done = ahc_parse_msg(ahc, &devinfo);
2463
2464 if (message_done) {
2465 /*
2466 * Clear our incoming message buffer in case there
2467 * is another message following this one.
2468 */
2469 ahc->msgin_index = 0;
2470
2471 /*
2472 * If this message illicited a response,
2473 * assert ATN so the target takes us to the
2474 * message out phase.
2475 */
2476 if (ahc->msgout_len != 0)
2477 ahc_assert_atn(ahc);
2478 } else
2479 ahc->msgin_index++;
2480
2481 /* Ack the byte */
2482 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2483 ahc_inb(ahc, SCSIDATL);
2484 break;
2485 }
2486 case MSG_TYPE_TARGET_MSGIN:
2487 {
2488 int msgdone;
2489 int msgout_request;
2490
2491 if (ahc->msgout_len == 0)
2492 panic("Target MSGIN with no active message");
2493
2494 /*
2495 * If we interrupted a mesgout session, the initiator
2496 * will not know this until our first REQ. So, we
2497 * only honor mesgout requests after we've sent our
2498 * first byte.
2499 */
2500 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2501 && ahc->msgout_index > 0)
2502 msgout_request = TRUE;
2503 else
2504 msgout_request = FALSE;
2505
2506 if (msgout_request) {
2507
2508 /*
2509 * Change gears and see if
2510 * this messages is of interest to
2511 * us or should be passed back to
2512 * the sequencer.
2513 */
2514 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2515 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2516 ahc->msgin_index = 0;
2517 /* Dummy read to REQ for first byte */
2518 ahc_inb(ahc, SCSIDATL);
2519 ahc_outb(ahc, SXFRCTL0,
2520 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2521 break;
2522 }
2523
2524 msgdone = ahc->msgout_index == ahc->msgout_len;
2525 if (msgdone) {
2526 ahc_outb(ahc, SXFRCTL0,
2527 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2528 end_session = TRUE;
2529 break;
2530 }
2531
2532 /*
2533 * Present the next byte on the bus.
2534 */
2535 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2536 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2537 break;
2538 }
2539 case MSG_TYPE_TARGET_MSGOUT:
2540 {
2541 int lastbyte;
2542 int msgdone;
2543
2544 /*
2545 * The initiator signals that this is
2546 * the last byte by dropping ATN.
2547 */
2548 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2549
2550 /*
2551 * Read the latched byte, but turn off SPIOEN first
2552 * so that we don't inadvertantly cause a REQ for the
2553 * next byte.
2554 */
2555 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2556 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2557 msgdone = ahc_parse_msg(ahc, &devinfo);
2558 if (msgdone == MSGLOOP_TERMINATED) {
2559 /*
2560 * The message is *really* done in that it caused
2561 * us to go to bus free. The sequencer has already
2562 * been reset at this point, so pull the ejection
2563 * handle.
2564 */
2565 return;
2566 }
2567
2568 ahc->msgin_index++;
2569
2570 /*
2571 * XXX Read spec about initiator dropping ATN too soon
2572 * and use msgdone to detect it.
2573 */
2574 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2575 ahc->msgin_index = 0;
2576
2577 /*
2578 * If this message illicited a response, transition
2579 * to the Message in phase and send it.
2580 */
2581 if (ahc->msgout_len != 0) {
2582 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2583 ahc_outb(ahc, SXFRCTL0,
2584 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2585 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2586 ahc->msgin_index = 0;
2587 break;
2588 }
2589 }
2590
2591 if (lastbyte)
2592 end_session = TRUE;
2593 else {
2594 /* Ask for the next byte. */
2595 ahc_outb(ahc, SXFRCTL0,
2596 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2597 }
2598
2599 break;
2600 }
2601 default:
2602 panic("Unknown REQINIT message type");
2603 }
2604
2605 if (end_session) {
2606 ahc_clear_msg_state(ahc);
2607 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2608 } else
2609 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2610 }
2611
2612 /*
2613 * See if we sent a particular extended message to the target.
2614 * If "full" is true, return true only if the target saw the full
2615 * message. If "full" is false, return true if the target saw at
2616 * least the first byte of the message.
2617 */
2618 static int
2619 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2620 {
2621 int found;
2622 u_int index;
2623
2624 found = FALSE;
2625 index = 0;
2626
2627 while (index < ahc->msgout_len) {
2628 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2629 u_int end_index;
2630
2631 end_index = index + 1 + ahc->msgout_buf[index + 1];
2632 if (ahc->msgout_buf[index+2] == msgval
2633 && type == AHCMSG_EXT) {
2634
2635 if (full) {
2636 if (ahc->msgout_index > end_index)
2637 found = TRUE;
2638 } else if (ahc->msgout_index > index)
2639 found = TRUE;
2640 }
2641 index = end_index;
2642 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2643 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2644
2645 /* Skip tag type and tag id or residue param*/
2646 index += 2;
2647 } else {
2648 /* Single byte message */
2649 if (type == AHCMSG_1B
2650 && ahc->msgout_buf[index] == msgval
2651 && ahc->msgout_index > index)
2652 found = TRUE;
2653 index++;
2654 }
2655
2656 if (found)
2657 break;
2658 }
2659 return (found);
2660 }
2661
2662 /*
2663 * Wait for a complete incoming message, parse it, and respond accordingly.
2664 */
2665 static int
2666 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2667 {
2668 struct ahc_initiator_tinfo *tinfo;
2669 struct ahc_tmode_tstate *tstate;
2670 int reject;
2671 int done;
2672 int response;
2673 u_int targ_scsirate;
2674
2675 done = MSGLOOP_IN_PROG;
2676 response = FALSE;
2677 reject = FALSE;
2678 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2679 devinfo->target, &tstate);
2680 targ_scsirate = tinfo->scsirate;
2681
2682 /*
2683 * Parse as much of the message as is availible,
2684 * rejecting it if we don't support it. When
2685 * the entire message is availible and has been
2686 * handled, return MSGLOOP_MSGCOMPLETE, indicating
2687 * that we have parsed an entire message.
2688 *
2689 * In the case of extended messages, we accept the length
2690 * byte outright and perform more checking once we know the
2691 * extended message type.
2692 */
2693 switch (ahc->msgin_buf[0]) {
2694 case MSG_MESSAGE_REJECT:
2695 response = ahc_handle_msg_reject(ahc, devinfo);
2696 /* FALLTHROUGH */
2697 case MSG_NOOP:
2698 done = MSGLOOP_MSGCOMPLETE;
2699 break;
2700 case MSG_EXTENDED:
2701 {
2702 /* Wait for enough of the message to begin validation */
2703 if (ahc->msgin_index < 2)
2704 break;
2705 switch (ahc->msgin_buf[2]) {
2706 case MSG_EXT_SDTR:
2707 {
2708 struct ahc_syncrate *syncrate;
2709 u_int period;
2710 u_int ppr_options;
2711 u_int offset;
2712 u_int saved_offset;
2713
2714 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
2715 reject = TRUE;
2716 break;
2717 }
2718
2719 /*
2720 * Wait until we have both args before validating
2721 * and acting on this message.
2722 *
2723 * Add one to MSG_EXT_SDTR_LEN to account for
2724 * the extended message preamble.
2725 */
2726 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
2727 break;
2728
2729 period = ahc->msgin_buf[3];
2730 ppr_options = 0;
2731 saved_offset = offset = ahc->msgin_buf[4];
2732 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2733 &ppr_options,
2734 devinfo->role);
2735 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
2736 targ_scsirate & WIDEXFER,
2737 devinfo->role);
2738 if (bootverbose) {
2739 printf("(%s:%c:%d:%d): Received "
2740 "SDTR period %x, offset %x\n\t"
2741 "Filtered to period %x, offset %x\n",
2742 ahc_name(ahc), devinfo->channel,
2743 devinfo->target, devinfo->lun,
2744 ahc->msgin_buf[3], saved_offset,
2745 period, offset);
2746 }
2747 ahc_set_syncrate(ahc, devinfo,
2748 syncrate, period,
2749 offset, ppr_options,
2750 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
2751 /*paused*/TRUE);
2752
2753 /*
2754 * See if we initiated Sync Negotiation
2755 * and didn't have to fall down to async
2756 * transfers.
2757 */
2758 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
2759 /* We started it */
2760 if (saved_offset != offset) {
2761 /* Went too low - force async */
2762 reject = TRUE;
2763 }
2764 } else {
2765 /*
2766 * Send our own SDTR in reply
2767 */
2768 if (bootverbose
2769 && devinfo->role == ROLE_INITIATOR) {
2770 printf("(%s:%c:%d:%d): Target "
2771 "Initiated SDTR\n",
2772 ahc_name(ahc), devinfo->channel,
2773 devinfo->target, devinfo->lun);
2774 }
2775 ahc->msgout_index = 0;
2776 ahc->msgout_len = 0;
2777 ahc_construct_sdtr(ahc, devinfo,
2778 period, offset);
2779 ahc->msgout_index = 0;
2780 response = TRUE;
2781 }
2782 done = MSGLOOP_MSGCOMPLETE;
2783 break;
2784 }
2785 case MSG_EXT_WDTR:
2786 {
2787 u_int bus_width;
2788 u_int saved_width;
2789 u_int sending_reply;
2790
2791 sending_reply = FALSE;
2792 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
2793 reject = TRUE;
2794 break;
2795 }
2796
2797 /*
2798 * Wait until we have our arg before validating
2799 * and acting on this message.
2800 *
2801 * Add one to MSG_EXT_WDTR_LEN to account for
2802 * the extended message preamble.
2803 */
2804 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
2805 break;
2806
2807 bus_width = ahc->msgin_buf[3];
2808 saved_width = bus_width;
2809 ahc_validate_width(ahc, tinfo, &bus_width,
2810 devinfo->role);
2811 if (bootverbose) {
2812 printf("(%s:%c:%d:%d): Received WDTR "
2813 "%x filtered to %x\n",
2814 ahc_name(ahc), devinfo->channel,
2815 devinfo->target, devinfo->lun,
2816 saved_width, bus_width);
2817 }
2818
2819 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
2820 /*
2821 * Don't send a WDTR back to the
2822 * target, since we asked first.
2823 * If the width went higher than our
2824 * request, reject it.
2825 */
2826 if (saved_width > bus_width) {
2827 reject = TRUE;
2828 printf("(%s:%c:%d:%d): requested %dBit "
2829 "transfers. Rejecting...\n",
2830 ahc_name(ahc), devinfo->channel,
2831 devinfo->target, devinfo->lun,
2832 8 * (0x01 << bus_width));
2833 bus_width = 0;
2834 }
2835 } else {
2836 /*
2837 * Send our own WDTR in reply
2838 */
2839 if (bootverbose
2840 && devinfo->role == ROLE_INITIATOR) {
2841 printf("(%s:%c:%d:%d): Target "
2842 "Initiated WDTR\n",
2843 ahc_name(ahc), devinfo->channel,
2844 devinfo->target, devinfo->lun);
2845 }
2846 ahc->msgout_index = 0;
2847 ahc->msgout_len = 0;
2848 ahc_construct_wdtr(ahc, devinfo, bus_width);
2849 ahc->msgout_index = 0;
2850 response = TRUE;
2851 sending_reply = TRUE;
2852 }
2853 ahc_set_width(ahc, devinfo, bus_width,
2854 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
2855 /*paused*/TRUE);
2856 /* After a wide message, we are async */
2857 ahc_set_syncrate(ahc, devinfo,
2858 /*syncrate*/NULL, /*period*/0,
2859 /*offset*/0, /*ppr_options*/0,
2860 AHC_TRANS_ACTIVE, /*paused*/TRUE);
2861 if (sending_reply == FALSE && reject == FALSE) {
2862
2863 if (tinfo->goal.period) {
2864 ahc->msgout_index = 0;
2865 ahc->msgout_len = 0;
2866 ahc_build_transfer_msg(ahc, devinfo);
2867 ahc->msgout_index = 0;
2868 response = TRUE;
2869 }
2870 }
2871 done = MSGLOOP_MSGCOMPLETE;
2872 break;
2873 }
2874 case MSG_EXT_PPR:
2875 {
2876 struct ahc_syncrate *syncrate;
2877 u_int period;
2878 u_int offset;
2879 u_int bus_width;
2880 u_int ppr_options;
2881 u_int saved_width;
2882 u_int saved_offset;
2883 u_int saved_ppr_options;
2884
2885 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
2886 reject = TRUE;
2887 break;
2888 }
2889
2890 /*
2891 * Wait until we have all args before validating
2892 * and acting on this message.
2893 *
2894 * Add one to MSG_EXT_PPR_LEN to account for
2895 * the extended message preamble.
2896 */
2897 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
2898 break;
2899
2900 period = ahc->msgin_buf[3];
2901 offset = ahc->msgin_buf[5];
2902 bus_width = ahc->msgin_buf[6];
2903 saved_width = bus_width;
2904 ppr_options = ahc->msgin_buf[7];
2905 /*
2906 * According to the spec, a DT only
2907 * period factor with no DT option
2908 * set implies async.
2909 */
2910 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2911 && period == 9)
2912 offset = 0;
2913 saved_ppr_options = ppr_options;
2914 saved_offset = offset;
2915
2916 /*
2917 * Mask out any options we don't support
2918 * on any controller. Transfer options are
2919 * only available if we are negotiating wide.
2920 */
2921 ppr_options &= MSG_EXT_PPR_DT_REQ;
2922 if (bus_width == 0)
2923 ppr_options = 0;
2924
2925 ahc_validate_width(ahc, tinfo, &bus_width,
2926 devinfo->role);
2927 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2928 &ppr_options,
2929 devinfo->role);
2930 ahc_validate_offset(ahc, tinfo, syncrate,
2931 &offset, bus_width,
2932 devinfo->role);
2933
2934 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
2935 /*
2936 * If we are unable to do any of the
2937 * requested options (we went too low),
2938 * then we'll have to reject the message.
2939 */
2940 if (saved_width > bus_width
2941 || saved_offset != offset
2942 || saved_ppr_options != ppr_options) {
2943 reject = TRUE;
2944 period = 0;
2945 offset = 0;
2946 bus_width = 0;
2947 ppr_options = 0;
2948 syncrate = NULL;
2949 }
2950 } else {
2951 if (devinfo->role != ROLE_TARGET)
2952 printf("(%s:%c:%d:%d): Target "
2953 "Initiated PPR\n",
2954 ahc_name(ahc), devinfo->channel,
2955 devinfo->target, devinfo->lun);
2956 else
2957 printf("(%s:%c:%d:%d): Initiator "
2958 "Initiated PPR\n",
2959 ahc_name(ahc), devinfo->channel,
2960 devinfo->target, devinfo->lun);
2961 ahc->msgout_index = 0;
2962 ahc->msgout_len = 0;
2963 ahc_construct_ppr(ahc, devinfo, period, offset,
2964 bus_width, ppr_options);
2965 ahc->msgout_index = 0;
2966 response = TRUE;
2967 }
2968 if (bootverbose) {
2969 printf("(%s:%c:%d:%d): Received PPR width %x, "
2970 "period %x, offset %x,options %x\n"
2971 "\tFiltered to width %x, period %x, "
2972 "offset %x, options %x\n",
2973 ahc_name(ahc), devinfo->channel,
2974 devinfo->target, devinfo->lun,
2975 saved_width, ahc->msgin_buf[3],
2976 saved_offset, saved_ppr_options,
2977 bus_width, period, offset, ppr_options);
2978 }
2979 ahc_set_width(ahc, devinfo, bus_width,
2980 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
2981 /*paused*/TRUE);
2982 ahc_set_syncrate(ahc, devinfo,
2983 syncrate, period,
2984 offset, ppr_options,
2985 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
2986 /*paused*/TRUE);
2987 done = MSGLOOP_MSGCOMPLETE;
2988 break;
2989 }
2990 default:
2991 /* Unknown extended message. Reject it. */
2992 reject = TRUE;
2993 break;
2994 }
2995 break;
2996 }
2997 case MSG_BUS_DEV_RESET:
2998 ahc_handle_devreset(ahc, devinfo,
2999 CAM_BDR_SENT,
3000 "Bus Device Reset Received",
3001 /*verbose_level*/0);
3002 ahc_restart(ahc);
3003 done = MSGLOOP_TERMINATED;
3004 break;
3005 case MSG_ABORT_TAG:
3006 case MSG_ABORT:
3007 case MSG_CLEAR_QUEUE:
3008 #ifdef AHC_TARGET_MODE
3009 /* Target mode messages */
3010 if (devinfo->role != ROLE_TARGET) {
3011 reject = TRUE;
3012 break;
3013 }
3014 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3015 devinfo->lun,
3016 ahc->msgin_buf[0] == MSG_ABORT_TAG
3017 ? SCB_LIST_NULL
3018 : ahc_inb(ahc, INITIATOR_TAG),
3019 ROLE_TARGET, CAM_REQ_ABORTED);
3020
3021 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3022 if (tstate != NULL) {
3023 struct ahc_tmode_lstate* lstate;
3024
3025 lstate = tstate->enabled_luns[devinfo->lun];
3026 if (lstate != NULL) {
3027 ahc_queue_lstate_event(ahc, lstate,
3028 devinfo->our_scsiid,
3029 ahc->msgin_buf[0],
3030 /*arg*/0);
3031 ahc_send_lstate_events(ahc, lstate);
3032 }
3033 }
3034 done = MSGLOOP_MSGCOMPLETE;
3035 break;
3036 #endif
3037 case MSG_TERM_IO_PROC:
3038 default:
3039 reject = TRUE;
3040 break;
3041 }
3042
3043 if (reject) {
3044 /*
3045 * Setup to reject the message.
3046 */
3047 ahc->msgout_index = 0;
3048 ahc->msgout_len = 1;
3049 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3050 done = MSGLOOP_MSGCOMPLETE;
3051 response = TRUE;
3052 }
3053
3054 if (done != MSGLOOP_IN_PROG && !response)
3055 /* Clear the outgoing message buffer */
3056 ahc->msgout_len = 0;
3057
3058 return (done);
3059 }
3060
3061 /*
3062 * Process a message reject message.
3063 */
3064 static int
3065 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3066 {
3067 /*
3068 * What we care about here is if we had an
3069 * outstanding SDTR or WDTR message for this
3070 * target. If we did, this is a signal that
3071 * the target is refusing negotiation.
3072 */
3073 struct scb *scb;
3074 struct ahc_initiator_tinfo *tinfo;
3075 struct ahc_tmode_tstate *tstate;
3076 u_int scb_index;
3077 u_int last_msg;
3078 int response = 0;
3079
3080 scb_index = ahc_inb(ahc, SCB_TAG);
3081 scb = ahc_lookup_scb(ahc, scb_index);
3082 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3083 devinfo->our_scsiid,
3084 devinfo->target, &tstate);
3085 /* Might be necessary */
3086 last_msg = ahc_inb(ahc, LAST_MSG);
3087
3088 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3089 /*
3090 * Target does not support the PPR message.
3091 * Attempt to negotiate SPI-2 style.
3092 */
3093 if (bootverbose) {
3094 printf("(%s:%c:%d:%d): PPR Rejected. "
3095 "Trying WDTR/SDTR\n",
3096 ahc_name(ahc), devinfo->channel,
3097 devinfo->target, devinfo->lun);
3098 }
3099 tinfo->goal.ppr_options = 0;
3100 tinfo->curr.transport_version = 2;
3101 tinfo->goal.transport_version = 2;
3102 ahc->msgout_index = 0;
3103 ahc->msgout_len = 0;
3104 ahc_build_transfer_msg(ahc, devinfo);
3105 ahc->msgout_index = 0;
3106 response = 1;
3107 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3108
3109 /* note 8bit xfers */
3110 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3111 "8bit transfers\n", ahc_name(ahc),
3112 devinfo->channel, devinfo->target, devinfo->lun);
3113 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3114 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3115 /*paused*/TRUE);
3116 /*
3117 * No need to clear the sync rate. If the target
3118 * did not accept the command, our syncrate is
3119 * unaffected. If the target started the negotiation,
3120 * but rejected our response, we already cleared the
3121 * sync rate before sending our WDTR.
3122 */
3123 if (tinfo->goal.period) {
3124
3125 /* Start the sync negotiation */
3126 ahc->msgout_index = 0;
3127 ahc->msgout_len = 0;
3128 ahc_build_transfer_msg(ahc, devinfo);
3129 ahc->msgout_index = 0;
3130 response = 1;
3131 }
3132 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3133 /* note asynch xfers and clear flag */
3134 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3135 /*offset*/0, /*ppr_options*/0,
3136 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3137 /*paused*/TRUE);
3138 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3139 "Using asynchronous transfers\n",
3140 ahc_name(ahc), devinfo->channel,
3141 devinfo->target, devinfo->lun);
3142 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3143 int tag_type;
3144 int mask;
3145
3146 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3147
3148 if (tag_type == MSG_SIMPLE_TASK) {
3149 printf("(%s:%c:%d:%d): refuses tagged commands. "
3150 "Performing non-tagged I/O\n", ahc_name(ahc),
3151 devinfo->channel, devinfo->target, devinfo->lun);
3152 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3153 mask = ~0x23;
3154 } else {
3155 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3156 "Performing simple queue tagged I/O only\n",
3157 ahc_name(ahc), devinfo->channel, devinfo->target,
3158 devinfo->lun, tag_type == MSG_ORDERED_TASK
3159 ? "ordered" : "head of queue");
3160 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3161 mask = ~0x03;
3162 }
3163
3164 /*
3165 * Resend the identify for this CCB as the target
3166 * may believe that the selection is invalid otherwise.
3167 */
3168 ahc_outb(ahc, SCB_CONTROL,
3169 ahc_inb(ahc, SCB_CONTROL) & mask);
3170 scb->hscb->control &= mask;
3171 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3172 /*type*/MSG_SIMPLE_TASK);
3173 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3174 ahc_assert_atn(ahc);
3175
3176 /*
3177 * This transaction is now at the head of
3178 * the untagged queue for this target.
3179 */
3180 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3181 struct scb_tailq *untagged_q;
3182
3183 untagged_q =
3184 &(ahc->untagged_queues[devinfo->target_offset]);
3185 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3186 scb->flags |= SCB_UNTAGGEDQ;
3187 }
3188 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3189 scb->hscb->tag);
3190
3191 /*
3192 * Requeue all tagged commands for this target
3193 * currently in our posession so they can be
3194 * converted to untagged commands.
3195 */
3196 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3197 SCB_GET_CHANNEL(ahc, scb),
3198 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3199 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3200 SEARCH_COMPLETE);
3201 } else {
3202 /*
3203 * Otherwise, we ignore it.
3204 */
3205 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3206 ahc_name(ahc), devinfo->channel, devinfo->target,
3207 last_msg);
3208 }
3209 return (response);
3210 }
3211
3212 /*
3213 * Process an ingnore wide residue message.
3214 */
3215 static void
3216 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3217 {
3218 u_int scb_index;
3219 struct scb *scb;
3220
3221 scb_index = ahc_inb(ahc, SCB_TAG);
3222 scb = ahc_lookup_scb(ahc, scb_index);
3223 /*
3224 * XXX Actually check data direction in the sequencer?
3225 * Perhaps add datadir to some spare bits in the hscb?
3226 */
3227 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3228 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3229 /*
3230 * Ignore the message if we haven't
3231 * seen an appropriate data phase yet.
3232 */
3233 } else {
3234 /*
3235 * If the residual occurred on the last
3236 * transfer and the transfer request was
3237 * expected to end on an odd count, do
3238 * nothing. Otherwise, subtract a byte
3239 * and update the residual count accordingly.
3240 */
3241 uint32_t sgptr;
3242
3243 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3244 if ((sgptr & SG_LIST_NULL) != 0
3245 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) {
3246 /*
3247 * If the residual occurred on the last
3248 * transfer and the transfer request was
3249 * expected to end on an odd count, do
3250 * nothing.
3251 */
3252 } else {
3253 struct ahc_dma_seg *sg;
3254 uint32_t data_cnt;
3255 uint32_t data_addr;
3256 uint32_t sglen;
3257
3258 /* Pull in the rest of the sgptr */
3259 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3260 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3261 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8);
3262 sgptr &= SG_PTR_MASK;
3263 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24)
3264 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16)
3265 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8)
3266 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT));
3267
3268 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24)
3269 | (ahc_inb(ahc, SHADDR + 2) << 16)
3270 | (ahc_inb(ahc, SHADDR + 1) << 8)
3271 | (ahc_inb(ahc, SHADDR));
3272
3273 data_cnt += 1;
3274 data_addr -= 1;
3275
3276 sg = ahc_sg_bus_to_virt(scb, sgptr);
3277 /*
3278 * The residual sg ptr points to the next S/G
3279 * to load so we must go back one.
3280 */
3281 sg--;
3282 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3283 if (sg != scb->sg_list
3284 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3285
3286 sg--;
3287 sglen = ahc_le32toh(sg->len);
3288 /*
3289 * Preserve High Address and SG_LIST bits
3290 * while setting the count to 1.
3291 */
3292 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3293 data_addr = ahc_le32toh(sg->addr)
3294 + (sglen & AHC_SG_LEN_MASK) - 1;
3295
3296 /*
3297 * Increment sg so it points to the
3298 * "next" sg.
3299 */
3300 sg++;
3301 sgptr = ahc_sg_virt_to_bus(scb, sg);
3302 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3,
3303 sgptr >> 24);
3304 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2,
3305 sgptr >> 16);
3306 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1,
3307 sgptr >> 8);
3308 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3309 }
3310
3311 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24);
3312 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16);
3313 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8);
3314 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3315 }
3316 }
3317 }
3318
3319
3320 /*
3321 * Reinitialize the data pointers for the active transfer
3322 * based on its current residual.
3323 */
3324 static void
3325 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3326 {
3327 struct scb *scb;
3328 struct ahc_dma_seg *sg;
3329 u_int scb_index;
3330 uint32_t sgptr;
3331 uint32_t resid;
3332 uint32_t dataptr;
3333
3334 scb_index = ahc_inb(ahc, SCB_TAG);
3335 scb = ahc_lookup_scb(ahc, scb_index);
3336 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3337 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3338 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3339 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3340
3341 sgptr &= SG_PTR_MASK;
3342 sg = ahc_sg_bus_to_virt(scb, sgptr);
3343
3344 /* The residual sg_ptr always points to the next sg */
3345 sg--;
3346
3347 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3348 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3349 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3350
3351 dataptr = ahc_le32toh(sg->addr)
3352 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3353 - resid;
3354 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3355 u_int dscommand1;
3356
3357 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3358 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3359 ahc_outb(ahc, HADDR,
3360 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3361 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3362 }
3363 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3364 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3365 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3366 ahc_outb(ahc, HADDR, dataptr);
3367 ahc_outb(ahc, HCNT + 2, resid >> 16);
3368 ahc_outb(ahc, HCNT + 1, resid >> 8);
3369 ahc_outb(ahc, HCNT, resid);
3370 if ((ahc->features & AHC_ULTRA2) == 0) {
3371 ahc_outb(ahc, STCNT + 2, resid >> 16);
3372 ahc_outb(ahc, STCNT + 1, resid >> 8);
3373 ahc_outb(ahc, STCNT, resid);
3374 }
3375 }
3376
3377 /*
3378 * Handle the effects of issuing a bus device reset message.
3379 */
3380 static void
3381 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3382 cam_status status, char *message, int verbose_level)
3383 {
3384 #ifdef AHC_TARGET_MODE
3385 struct ahc_tmode_tstate* tstate;
3386 u_int lun;
3387 #endif
3388 int found;
3389
3390 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3391 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3392 status);
3393
3394 #ifdef AHC_TARGET_MODE
3395 /*
3396 * Send an immediate notify ccb to all target mord peripheral
3397 * drivers affected by this action.
3398 */
3399 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3400 if (tstate != NULL) {
3401 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3402 struct ahc_tmode_lstate* lstate;
3403
3404 lstate = tstate->enabled_luns[lun];
3405 if (lstate == NULL)
3406 continue;
3407
3408 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3409 MSG_BUS_DEV_RESET, /*arg*/0);
3410 ahc_send_lstate_events(ahc, lstate);
3411 }
3412 }
3413 #endif
3414
3415 /*
3416 * Go back to async/narrow transfers and renegotiate.
3417 */
3418 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3419 AHC_TRANS_CUR, /*paused*/TRUE);
3420 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3421 /*period*/0, /*offset*/0, /*ppr_options*/0,
3422 AHC_TRANS_CUR, /*paused*/TRUE);
3423
3424 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3425 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3426
3427 if (message != NULL
3428 && (verbose_level <= bootverbose))
3429 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3430 message, devinfo->channel, devinfo->target, found);
3431 }
3432
3433 #ifdef AHC_TARGET_MODE
3434 static void
3435 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3436 struct scb *scb)
3437 {
3438
3439 /*
3440 * To facilitate adding multiple messages together,
3441 * each routine should increment the index and len
3442 * variables instead of setting them explicitly.
3443 */
3444 ahc->msgout_index = 0;
3445 ahc->msgout_len = 0;
3446
3447 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3448 ahc_build_transfer_msg(ahc, devinfo);
3449 else
3450 panic("ahc_intr: AWAITING target message with no message");
3451
3452 ahc->msgout_index = 0;
3453 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3454 }
3455 #endif
3456 /**************************** Initialization **********************************/
3457 /*
3458 * Allocate a controller structure for a new device
3459 * and perform initial initializion.
3460 */
3461 struct ahc_softc *
3462 ahc_alloc(void *platform_arg, char *name)
3463 {
3464 struct ahc_softc *ahc;
3465 int i;
3466
3467 #ifndef __FreeBSD__
3468 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3469 if (!ahc) {
3470 printf("aic7xxx: cannot malloc softc!\n");
3471 free(name, M_DEVBUF);
3472 return NULL;
3473 }
3474 #else
3475 ahc = device_get_softc((device_t)platform_arg);
3476 #endif
3477 memset(ahc, 0, sizeof(*ahc));
3478 LIST_INIT(&ahc->pending_scbs);
3479 /* We don't know our unit number until the OSM sets it */
3480 ahc->name = name;
3481 ahc->unit = -1;
3482 ahc->description = NULL;
3483 ahc->channel = 'A';
3484 ahc->channel_b = 'B';
3485 ahc->chip = AHC_NONE;
3486 ahc->features = AHC_FENONE;
3487 ahc->bugs = AHC_BUGNONE;
3488 ahc->flags = AHC_FNONE;
3489
3490 for (i = 0; i < 16; i++)
3491 TAILQ_INIT(&ahc->untagged_queues[i]);
3492 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3493 ahc_free(ahc);
3494 ahc = NULL;
3495 }
3496 return (ahc);
3497 }
3498
3499 int
3500 ahc_softc_init(struct ahc_softc *ahc)
3501 {
3502
3503 /* The IRQMS bit is only valid on VL and EISA chips */
3504 if ((ahc->chip & AHC_PCI) != 0)
3505 ahc->unpause &= ~IRQMS;
3506 ahc->pause = ahc->unpause | PAUSE;
3507 /* XXX The shared scb data stuff should be deprecated */
3508 if (ahc->scb_data == NULL) {
3509 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3510 M_DEVBUF, M_NOWAIT);
3511 if (ahc->scb_data == NULL)
3512 return (ENOMEM);
3513 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3514 }
3515
3516 return (0);
3517 }
3518
3519 void
3520 ahc_softc_insert(struct ahc_softc *ahc)
3521 {
3522 struct ahc_softc *list_ahc;
3523
3524 #if AHC_PCI_CONFIG > 0
3525 /*
3526 * Second Function PCI devices need to inherit some
3527 * settings from function 0.
3528 */
3529 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3530 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3531 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3532 ahc_dev_softc_t list_pci;
3533 ahc_dev_softc_t pci;
3534
3535 list_pci = list_ahc->dev_softc;
3536 pci = ahc->dev_softc;
3537 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3538 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
3539 struct ahc_softc *master;
3540 struct ahc_softc *slave;
3541
3542 if (ahc_get_pci_function(list_pci) == 0) {
3543 master = list_ahc;
3544 slave = ahc;
3545 } else {
3546 master = ahc;
3547 slave = list_ahc;
3548 }
3549 slave->flags &= ~AHC_BIOS_ENABLED;
3550 slave->flags |=
3551 master->flags & AHC_BIOS_ENABLED;
3552 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3553 slave->flags |=
3554 master->flags & AHC_PRIMARY_CHANNEL;
3555 break;
3556 }
3557 }
3558 }
3559 #endif
3560
3561 /*
3562 * Insertion sort into our list of softcs.
3563 */
3564 list_ahc = TAILQ_FIRST(&ahc_tailq);
3565 while (list_ahc != NULL
3566 && ahc_softc_comp(list_ahc, ahc) <= 0)
3567 list_ahc = TAILQ_NEXT(list_ahc, links);
3568 if (list_ahc != NULL)
3569 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
3570 else
3571 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
3572 ahc->init_level++;
3573 }
3574
3575 void
3576 ahc_set_unit(struct ahc_softc *ahc, int unit)
3577 {
3578 ahc->unit = unit;
3579 }
3580
3581 void
3582 ahc_set_name(struct ahc_softc *ahc, char *name)
3583 {
3584 if (ahc->name != NULL)
3585 free(ahc->name, M_DEVBUF);
3586 ahc->name = name;
3587 }
3588
3589 void
3590 ahc_free(struct ahc_softc *ahc)
3591 {
3592 int i;
3593
3594 ahc_fini_scbdata(ahc);
3595 switch (ahc->init_level) {
3596 default:
3597 case 5:
3598 ahc_shutdown(ahc);
3599 TAILQ_REMOVE(&ahc_tailq, ahc, links);
3600 /* FALLTHROUGH */
3601 case 4:
3602 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3603 ahc->shared_data_dmamap);
3604 /* FALLTHROUGH */
3605 case 3:
3606 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3607 ahc->shared_data_dmamap);
3608 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3609 ahc->shared_data_dmamap);
3610 /* FALLTHROUGH */
3611 case 2:
3612 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3613 case 1:
3614 #ifndef __linux__
3615 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3616 #endif
3617 break;
3618 case 0:
3619 break;
3620 }
3621
3622 #ifndef __linux__
3623 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
3624 #endif
3625 ahc_platform_free(ahc);
3626 for (i = 0; i < AHC_NUM_TARGETS; i++) {
3627 struct ahc_tmode_tstate *tstate;
3628
3629 tstate = ahc->enabled_targets[i];
3630 if (tstate != NULL) {
3631 #if AHC_TARGET_MODE
3632 int j;
3633
3634 for (j = 0; j < AHC_NUM_LUNS; j++) {
3635 struct ahc_tmode_lstate *lstate;
3636
3637 lstate = tstate->enabled_luns[j];
3638 if (lstate != NULL) {
3639 xpt_free_path(lstate->path);
3640 free(lstate, M_DEVBUF);
3641 }
3642 }
3643 #endif
3644 free(tstate, M_DEVBUF);
3645 }
3646 }
3647 #if AHC_TARGET_MODE
3648 if (ahc->black_hole != NULL) {
3649 xpt_free_path(ahc->black_hole->path);
3650 free(ahc->black_hole, M_DEVBUF);
3651 }
3652 #endif
3653 if (ahc->name != NULL)
3654 free(ahc->name, M_DEVBUF);
3655 #ifndef __FreeBSD__
3656 free(ahc, M_DEVBUF);
3657 #endif
3658 return;
3659 }
3660
3661 void
3662 ahc_shutdown(void *arg)
3663 {
3664 struct ahc_softc *ahc;
3665 int i;
3666
3667 ahc = (struct ahc_softc *)arg;
3668
3669 /* This will reset most registers to 0, but not all */
3670 ahc_reset(ahc);
3671 ahc_outb(ahc, SCSISEQ, 0);
3672 ahc_outb(ahc, SXFRCTL0, 0);
3673 ahc_outb(ahc, DSPCISTATUS, 0);
3674
3675 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++)
3676 ahc_outb(ahc, i, 0);
3677 }
3678
3679 /*
3680 * Reset the controller and record some information about it
3681 * that is only availabel just after a reset.
3682 */
3683 int
3684 ahc_reset(struct ahc_softc *ahc)
3685 {
3686 u_int sblkctl;
3687 u_int sxfrctl1_a, sxfrctl1_b;
3688 int wait;
3689
3690 /*
3691 * Preserve the value of the SXFRCTL1 register for all channels.
3692 * It contains settings that affect termination and we don't want
3693 * to disturb the integrity of the bus.
3694 */
3695 ahc_pause(ahc);
3696 sxfrctl1_b = 0;
3697 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
3698 u_int sblkctl;
3699
3700 /*
3701 * Save channel B's settings in case this chip
3702 * is setup for TWIN channel operation.
3703 */
3704 sblkctl = ahc_inb(ahc, SBLKCTL);
3705 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
3706 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
3707 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
3708 }
3709 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
3710
3711 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
3712
3713 /*
3714 * Ensure that the reset has finished
3715 */
3716 wait = 1000;
3717 do {
3718 ahc_delay(1000);
3719 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
3720
3721 if (wait == 0) {
3722 printf("%s: WARNING - Failed chip reset! "
3723 "Trying to initialize anyway.\n", ahc_name(ahc));
3724 }
3725 ahc_outb(ahc, HCNTRL, ahc->pause);
3726
3727 /* Determine channel configuration */
3728 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
3729 /* No Twin Channel PCI cards */
3730 if ((ahc->chip & AHC_PCI) != 0)
3731 sblkctl &= ~SELBUSB;
3732 switch (sblkctl) {
3733 case 0:
3734 /* Single Narrow Channel */
3735 break;
3736 case 2:
3737 /* Wide Channel */
3738 ahc->features |= AHC_WIDE;
3739 break;
3740 case 8:
3741 /* Twin Channel */
3742 ahc->features |= AHC_TWIN;
3743 break;
3744 default:
3745 printf(" Unsupported adapter type. Ignoring\n");
3746 return(-1);
3747 }
3748
3749 /*
3750 * Reload sxfrctl1.
3751 *
3752 * We must always initialize STPWEN to 1 before we
3753 * restore the saved values. STPWEN is initialized
3754 * to a tri-state condition which can only be cleared
3755 * by turning it on.
3756 */
3757 if ((ahc->features & AHC_TWIN) != 0) {
3758 u_int sblkctl;
3759
3760 sblkctl = ahc_inb(ahc, SBLKCTL);
3761 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
3762 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
3763 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
3764 }
3765 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
3766
3767 #ifdef AHC_DUMP_SEQ
3768 if (ahc->init_level == 0)
3769 ahc_dumpseq(ahc);
3770 #endif
3771
3772 return (0);
3773 }
3774
3775 /*
3776 * Determine the number of SCBs available on the controller
3777 */
3778 int
3779 ahc_probe_scbs(struct ahc_softc *ahc) {
3780 int i;
3781
3782 for (i = 0; i < AHC_SCB_MAX; i++) {
3783
3784 ahc_outb(ahc, SCBPTR, i);
3785 ahc_outb(ahc, SCB_BASE, i);
3786 if (ahc_inb(ahc, SCB_BASE) != i)
3787 break;
3788 ahc_outb(ahc, SCBPTR, 0);
3789 if (ahc_inb(ahc, SCB_BASE) != 0)
3790 break;
3791 }
3792 return (i);
3793 }
3794
3795 static void
3796 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3797 {
3798 bus_addr_t *baddr;
3799
3800 baddr = (bus_addr_t *)arg;
3801 *baddr = segs->ds_addr;
3802 }
3803
3804 static void
3805 ahc_build_free_scb_list(struct ahc_softc *ahc)
3806 {
3807 int i;
3808
3809 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
3810 ahc_outb(ahc, SCBPTR, i);
3811
3812 /* Clear the control byte. */
3813 ahc_outb(ahc, SCB_CONTROL, 0);
3814
3815 /* Set the next pointer */
3816 if ((ahc->flags & AHC_PAGESCBS) != 0)
3817 ahc_outb(ahc, SCB_NEXT, i+1);
3818 else
3819 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
3820
3821 /* Make the tag number invalid */
3822 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
3823 }
3824
3825 /* Make sure that the last SCB terminates the free list */
3826 ahc_outb(ahc, SCBPTR, i-1);
3827 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
3828
3829 /* Ensure we clear the 0 SCB's control byte. */
3830 ahc_outb(ahc, SCBPTR, 0);
3831 ahc_outb(ahc, SCB_CONTROL, 0);
3832 }
3833
3834 static int
3835 ahc_init_scbdata(struct ahc_softc *ahc)
3836 {
3837 struct scb_data *scb_data;
3838
3839 scb_data = ahc->scb_data;
3840 SLIST_INIT(&scb_data->free_scbs);
3841 SLIST_INIT(&scb_data->sg_maps);
3842
3843 /* Allocate SCB resources */
3844 scb_data->scbarray =
3845 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX,
3846 M_DEVBUF, M_NOWAIT);
3847 if (scb_data->scbarray == NULL)
3848 return (ENOMEM);
3849 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX);
3850
3851 /* Determine the number of hardware SCBs and initialize them */
3852
3853 scb_data->maxhscbs = ahc_probe_scbs(ahc);
3854 if ((ahc->flags & AHC_PAGESCBS) != 0) {
3855 /* SCB 0 heads the free list */
3856 ahc_outb(ahc, FREE_SCBH, 0);
3857 } else {
3858 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
3859 }
3860
3861 if (ahc->scb_data->maxhscbs == 0) {
3862 printf("%s: No SCB space found\n", ahc_name(ahc));
3863 return (ENXIO);
3864 }
3865
3866 ahc_build_free_scb_list(ahc);
3867
3868 /*
3869 * Create our DMA tags. These tags define the kinds of device
3870 * accessible memory allocations and memory mappings we will
3871 * need to perform during normal operation.
3872 *
3873 * Unless we need to further restrict the allocation, we rely
3874 * on the restrictions of the parent dmat, hence the common
3875 * use of MAXADDR and MAXSIZE.
3876 */
3877
3878 /* DMA tag for our hardware scb structures */
3879 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3880 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
3881 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3882 /*highaddr*/BUS_SPACE_MAXADDR,
3883 /*filter*/NULL, /*filterarg*/NULL,
3884 AHC_SCB_MAX * sizeof(struct hardware_scb),
3885 /*nsegments*/1,
3886 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3887 /*flags*/0, &scb_data->hscb_dmat) != 0) {
3888 goto error_exit;
3889 }
3890
3891 scb_data->init_level++;
3892
3893 /* Allocation for our hscbs */
3894 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
3895 (void **)&scb_data->hscbs,
3896 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
3897 goto error_exit;
3898 }
3899
3900 scb_data->init_level++;
3901
3902 /* And permanently map them */
3903 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
3904 scb_data->hscbs,
3905 AHC_SCB_MAX * sizeof(struct hardware_scb),
3906 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
3907
3908 scb_data->init_level++;
3909
3910 /* DMA tag for our sense buffers */
3911 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3912 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
3913 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3914 /*highaddr*/BUS_SPACE_MAXADDR,
3915 /*filter*/NULL, /*filterarg*/NULL,
3916 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
3917 /*nsegments*/1,
3918 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3919 /*flags*/0, &scb_data->sense_dmat) != 0) {
3920 goto error_exit;
3921 }
3922
3923 scb_data->init_level++;
3924
3925 /* Allocate them */
3926 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
3927 (void **)&scb_data->sense,
3928 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
3929 goto error_exit;
3930 }
3931
3932 scb_data->init_level++;
3933
3934 /* And permanently map them */
3935 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
3936 scb_data->sense,
3937 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
3938 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
3939
3940 scb_data->init_level++;
3941
3942 /* DMA tag for our S/G structures. We allocate in page sized chunks */
3943 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
3944 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
3945 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3946 /*highaddr*/BUS_SPACE_MAXADDR,
3947 /*filter*/NULL, /*filterarg*/NULL,
3948 PAGE_SIZE, /*nsegments*/1,
3949 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
3950 /*flags*/0, &scb_data->sg_dmat) != 0) {
3951 goto error_exit;
3952 }
3953
3954 scb_data->init_level++;
3955
3956 /* Perform initial CCB allocation */
3957 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb));
3958 ahc_alloc_scbs(ahc);
3959
3960 if (scb_data->numscbs == 0) {
3961 printf("%s: ahc_init_scbdata - "
3962 "Unable to allocate initial scbs\n",
3963 ahc_name(ahc));
3964 goto error_exit;
3965 }
3966
3967 /*
3968 * Tell the sequencer which SCB will be the next one it receives.
3969 */
3970 ahc->next_queued_scb = ahc_get_scb(ahc);
3971 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
3972
3973 /*
3974 * Note that we were successfull
3975 */
3976 return (0);
3977
3978 error_exit:
3979
3980 return (ENOMEM);
3981 }
3982
3983 static void
3984 ahc_fini_scbdata(struct ahc_softc *ahc)
3985 {
3986 struct scb_data *scb_data;
3987
3988 scb_data = ahc->scb_data;
3989 if (scb_data == NULL)
3990 return;
3991
3992 switch (scb_data->init_level) {
3993 default:
3994 case 7:
3995 {
3996 struct sg_map_node *sg_map;
3997
3998 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
3999 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4000 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4001 sg_map->sg_dmamap);
4002 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4003 sg_map->sg_vaddr,
4004 sg_map->sg_dmamap);
4005 free(sg_map, M_DEVBUF);
4006 }
4007 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4008 }
4009 case 6:
4010 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4011 scb_data->sense_dmamap);
4012 case 5:
4013 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4014 scb_data->sense_dmamap);
4015 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4016 scb_data->sense_dmamap);
4017 case 4:
4018 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4019 case 3:
4020 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4021 scb_data->hscb_dmamap);
4022 case 2:
4023 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4024 scb_data->hscb_dmamap);
4025 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4026 scb_data->hscb_dmamap);
4027 case 1:
4028 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4029 break;
4030 case 0:
4031 break;
4032 }
4033 if (scb_data->scbarray != NULL)
4034 free(scb_data->scbarray, M_DEVBUF);
4035 }
4036
4037 void
4038 ahc_alloc_scbs(struct ahc_softc *ahc)
4039 {
4040 struct scb_data *scb_data;
4041 struct scb *next_scb;
4042 struct sg_map_node *sg_map;
4043 bus_addr_t physaddr;
4044 struct ahc_dma_seg *segs;
4045 int newcount;
4046 int i;
4047
4048 scb_data = ahc->scb_data;
4049 if (scb_data->numscbs >= AHC_SCB_MAX)
4050 /* Can't allocate any more */
4051 return;
4052
4053 next_scb = &scb_data->scbarray[scb_data->numscbs];
4054
4055 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4056
4057 if (sg_map == NULL)
4058 return;
4059
4060 /* Allocate S/G space for the next batch of SCBS */
4061 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4062 (void **)&sg_map->sg_vaddr,
4063 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4064 free(sg_map, M_DEVBUF);
4065 return;
4066 }
4067
4068 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4069
4070 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4071 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4072 &sg_map->sg_physaddr, /*flags*/0);
4073
4074 segs = sg_map->sg_vaddr;
4075 physaddr = sg_map->sg_physaddr;
4076
4077 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4078 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) {
4079 struct scb_platform_data *pdata;
4080 #ifndef __linux__
4081 int error;
4082 #endif
4083 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4084 M_DEVBUF, M_NOWAIT);
4085 if (pdata == NULL)
4086 break;
4087 next_scb->platform_data = pdata;
4088 next_scb->sg_map = sg_map;
4089 next_scb->sg_list = segs;
4090 /*
4091 * The sequencer always starts with the second entry.
4092 * The first entry is embedded in the scb.
4093 */
4094 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4095 next_scb->ahc_softc = ahc;
4096 next_scb->flags = SCB_FREE;
4097 #ifndef __linux__
4098 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4099 &next_scb->dmamap);
4100 if (error != 0)
4101 break;
4102 #endif
4103 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4104 next_scb->hscb->tag = ahc->scb_data->numscbs;
4105 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4106 next_scb, links.sle);
4107 segs += AHC_NSEG;
4108 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4109 next_scb++;
4110 ahc->scb_data->numscbs++;
4111 }
4112 }
4113
4114 void
4115 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4116 {
4117 int len;
4118
4119 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4120 buf += len;
4121 if ((ahc->features & AHC_TWIN) != 0)
4122 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4123 "B SCSI Id=%d, primary %c, ",
4124 ahc->our_id, ahc->our_id_b,
4125 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4126 else {
4127 const char *speed;
4128 const char *type;
4129
4130 speed = "";
4131 if ((ahc->features & AHC_ULTRA) != 0) {
4132 speed = "Ultra ";
4133 } else if ((ahc->features & AHC_DT) != 0) {
4134 speed = "Ultra160 ";
4135 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4136 speed = "Ultra2 ";
4137 }
4138 if ((ahc->features & AHC_WIDE) != 0) {
4139 type = "Wide";
4140 } else {
4141 type = "Single";
4142 }
4143 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4144 speed, type, ahc->channel, ahc->our_id);
4145 }
4146 buf += len;
4147
4148 if ((ahc->flags & AHC_PAGESCBS) != 0)
4149 sprintf(buf, "%d/%d SCBs",
4150 ahc->scb_data->maxhscbs, AHC_SCB_MAX);
4151 else
4152 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4153 }
4154
4155 /*
4156 * Start the board, ready for normal operation
4157 */
4158 int
4159 ahc_init(struct ahc_softc *ahc)
4160 {
4161 int max_targ;
4162 int i;
4163 int term;
4164 u_int scsi_conf;
4165 u_int scsiseq_template;
4166 u_int ultraenb;
4167 u_int discenable;
4168 u_int tagenable;
4169 size_t driver_data_size;
4170 uint32_t physaddr;
4171
4172 #ifdef AHC_DEBUG_SEQUENCER
4173 ahc->flags |= AHC_SEQUENCER_DEBUG;
4174 #endif
4175
4176 #ifdef AHC_PRINT_SRAM
4177 printf("Scratch Ram:");
4178 for (i = 0x20; i < 0x5f; i++) {
4179 if (((i % 8) == 0) && (i != 0)) {
4180 printf ("\n ");
4181 }
4182 printf (" 0x%x", ahc_inb(ahc, i));
4183 }
4184 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4185 for (i = 0x70; i < 0x7f; i++) {
4186 if (((i % 8) == 0) && (i != 0)) {
4187 printf ("\n ");
4188 }
4189 printf (" 0x%x", ahc_inb(ahc, i));
4190 }
4191 }
4192 printf ("\n");
4193 #endif
4194 max_targ = 15;
4195
4196 /*
4197 * Assume we have a board at this stage and it has been reset.
4198 */
4199 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4200 ahc->our_id = ahc->our_id_b = 7;
4201
4202 /*
4203 * Default to allowing initiator operations.
4204 */
4205 ahc->flags |= AHC_INITIATORROLE;
4206
4207 /*
4208 * Only allow target mode features if this unit has them enabled.
4209 */
4210 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4211 ahc->features &= ~AHC_TARGETMODE;
4212
4213 #ifndef __linux__
4214 /* DMA tag for mapping buffers into device visible space. */
4215 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4216 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4217 /*lowaddr*/BUS_SPACE_MAXADDR,
4218 /*highaddr*/BUS_SPACE_MAXADDR,
4219 /*filter*/NULL, /*filterarg*/NULL,
4220 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG,
4221 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4222 /*flags*/BUS_DMA_ALLOCNOW,
4223 &ahc->buffer_dmat) != 0) {
4224 return (ENOMEM);
4225 }
4226 #endif
4227
4228 ahc->init_level++;
4229
4230 /*
4231 * DMA tag for our command fifos and other data in system memory
4232 * the card's sequencer must be able to access. For initiator
4233 * roles, we need to allocate space for the the qinfifo and qoutfifo.
4234 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4235 * When providing for the target mode role, we must additionally
4236 * provide space for the incoming target command fifo and an extra
4237 * byte to deal with a dma bug in some chip versions.
4238 */
4239 driver_data_size = 2 * 256 * sizeof(uint8_t);
4240 if ((ahc->features & AHC_TARGETMODE) != 0)
4241 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4242 + /*DMA WideOdd Bug Buffer*/1;
4243 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4244 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4245 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4246 /*highaddr*/BUS_SPACE_MAXADDR,
4247 /*filter*/NULL, /*filterarg*/NULL,
4248 driver_data_size,
4249 /*nsegments*/1,
4250 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4251 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4252 return (ENOMEM);
4253 }
4254
4255 ahc->init_level++;
4256
4257 /* Allocation of driver data */
4258 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4259 (void **)&ahc->qoutfifo,
4260 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4261 return (ENOMEM);
4262 }
4263
4264 ahc->init_level++;
4265
4266 /* And permanently map it in */
4267 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4268 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4269 &ahc->shared_data_busaddr, /*flags*/0);
4270
4271 if ((ahc->features & AHC_TARGETMODE) != 0) {
4272 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4273 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4274 ahc->dma_bug_buf = ahc->shared_data_busaddr
4275 + driver_data_size - 1;
4276 /* All target command blocks start out invalid. */
4277 for (i = 0; i < AHC_TMODE_CMDS; i++)
4278 ahc->targetcmds[i].cmd_valid = 0;
4279 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4280 ahc->tqinfifonext = 1;
4281 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4282 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4283 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4284 }
4285 ahc->qinfifo = &ahc->qoutfifo[256];
4286
4287 ahc->init_level++;
4288
4289 /* Allocate SCB data now that buffer_dmat is initialized */
4290 if (ahc->scb_data->maxhscbs == 0)
4291 if (ahc_init_scbdata(ahc) != 0)
4292 return (ENOMEM);
4293
4294 /*
4295 * Allocate a tstate to house information for our
4296 * initiator presence on the bus as well as the user
4297 * data for any target mode initiator.
4298 */
4299 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4300 printf("%s: unable to allocate ahc_tmode_tstate. "
4301 "Failing attach\n", ahc_name(ahc));
4302 return (ENOMEM);
4303 }
4304
4305 if ((ahc->features & AHC_TWIN) != 0) {
4306 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4307 printf("%s: unable to allocate ahc_tmode_tstate. "
4308 "Failing attach\n", ahc_name(ahc));
4309 return (ENOMEM);
4310 }
4311 }
4312
4313 ahc_outb(ahc, SEQ_FLAGS, 0);
4314 ahc_outb(ahc, SEQ_FLAGS2, 0);
4315
4316 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) {
4317 ahc->flags |= AHC_PAGESCBS;
4318 } else {
4319 ahc->flags &= ~AHC_PAGESCBS;
4320 }
4321
4322 #ifdef AHC_DEBUG
4323 if (ahc_debug & AHC_SHOWMISC) {
4324 printf("%s: hardware scb %d bytes; kernel scb %d bytes; "
4325 "ahc_dma %d bytes\n",
4326 ahc_name(ahc),
4327 sizeof(struct hardware_scb),
4328 sizeof(struct scb),
4329 sizeof(struct ahc_dma_seg));
4330 }
4331 #endif /* AHC_DEBUG */
4332
4333 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4334 if (ahc->features & AHC_TWIN) {
4335
4336 /*
4337 * The device is gated to channel B after a chip reset,
4338 * so set those values first
4339 */
4340 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4341 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4342 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4343 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4344 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4345 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4346 if ((ahc->features & AHC_ULTRA2) != 0)
4347 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4348 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4349 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4350
4351 if ((scsi_conf & RESET_SCSI) != 0
4352 && (ahc->flags & AHC_INITIATORROLE) != 0)
4353 ahc->flags |= AHC_RESET_BUS_B;
4354
4355 /* Select Channel A */
4356 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4357 }
4358 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4359 if ((ahc->features & AHC_ULTRA2) != 0)
4360 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4361 else
4362 ahc_outb(ahc, SCSIID, ahc->our_id);
4363 scsi_conf = ahc_inb(ahc, SCSICONF);
4364 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4365 |term|ahc->seltime
4366 |ENSTIMER|ACTNEGEN);
4367 if ((ahc->features & AHC_ULTRA2) != 0)
4368 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4369 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4370 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4371
4372 if ((scsi_conf & RESET_SCSI) != 0
4373 && (ahc->flags & AHC_INITIATORROLE) != 0)
4374 ahc->flags |= AHC_RESET_BUS_A;
4375
4376 /*
4377 * Look at the information that board initialization or
4378 * the board bios has left us.
4379 */
4380 ultraenb = 0;
4381 tagenable = ALL_TARGETS_MASK;
4382
4383 /* Grab the disconnection disable table and invert it for our needs */
4384 if (ahc->flags & AHC_USEDEFAULTS) {
4385 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4386 "device parameters\n", ahc_name(ahc));
4387 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4388 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4389 discenable = ALL_TARGETS_MASK;
4390 if ((ahc->features & AHC_ULTRA) != 0)
4391 ultraenb = ALL_TARGETS_MASK;
4392 } else {
4393 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4394 | ahc_inb(ahc, DISC_DSB));
4395 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4396 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4397 | ahc_inb(ahc, ULTRA_ENB);
4398 }
4399
4400 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4401 max_targ = 7;
4402
4403 for (i = 0; i <= max_targ; i++) {
4404 struct ahc_initiator_tinfo *tinfo;
4405 struct ahc_tmode_tstate *tstate;
4406 u_int our_id;
4407 u_int target_id;
4408 char channel;
4409
4410 channel = 'A';
4411 our_id = ahc->our_id;
4412 target_id = i;
4413 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4414 channel = 'B';
4415 our_id = ahc->our_id_b;
4416 target_id = i % 8;
4417 }
4418 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4419 target_id, &tstate);
4420 /* Default to async narrow across the board */
4421 memset(tinfo, 0, sizeof(*tinfo));
4422 if (ahc->flags & AHC_USEDEFAULTS) {
4423 if ((ahc->features & AHC_WIDE) != 0)
4424 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4425
4426 /*
4427 * These will be truncated when we determine the
4428 * connection type we have with the target.
4429 */
4430 tinfo->user.period = ahc_syncrates->period;
4431 tinfo->user.offset = ~0;
4432 } else {
4433 u_int scsirate;
4434 uint16_t mask;
4435
4436 /* Take the settings leftover in scratch RAM. */
4437 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4438 mask = (0x01 << i);
4439 if ((ahc->features & AHC_ULTRA2) != 0) {
4440 u_int offset;
4441 u_int maxsync;
4442
4443 if ((scsirate & SOFS) == 0x0F) {
4444 /*
4445 * Haven't negotiated yet,
4446 * so the format is different.
4447 */
4448 scsirate = (scsirate & SXFR) >> 4
4449 | (ultraenb & mask)
4450 ? 0x08 : 0x0
4451 | (scsirate & WIDEXFER);
4452 offset = MAX_OFFSET_ULTRA2;
4453 } else
4454 offset = ahc_inb(ahc, TARG_OFFSET + i);
4455 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4456 /* Set to the lowest sync rate, 5MHz */
4457 scsirate |= 0x1c;
4458 maxsync = AHC_SYNCRATE_ULTRA2;
4459 if ((ahc->features & AHC_DT) != 0)
4460 maxsync = AHC_SYNCRATE_DT;
4461 tinfo->user.period =
4462 ahc_find_period(ahc, scsirate, maxsync);
4463 if (offset == 0)
4464 tinfo->user.period = 0;
4465 else
4466 tinfo->user.offset = ~0;
4467 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4468 && (ahc->features & AHC_DT) != 0)
4469 tinfo->user.ppr_options =
4470 MSG_EXT_PPR_DT_REQ;
4471 } else if ((scsirate & SOFS) != 0) {
4472 if ((scsirate & SXFR) == 0x40
4473 && (ultraenb & mask) != 0) {
4474 /* Treat 10MHz as a non-ultra speed */
4475 scsirate &= ~SXFR;
4476 ultraenb &= ~mask;
4477 }
4478 tinfo->user.period =
4479 ahc_find_period(ahc, scsirate,
4480 (ultraenb & mask)
4481 ? AHC_SYNCRATE_ULTRA
4482 : AHC_SYNCRATE_FAST);
4483 if (tinfo->user.period != 0)
4484 tinfo->user.offset = ~0;
4485 }
4486 if (tinfo->user.period == 0)
4487 tinfo->user.offset = 0;
4488 if ((scsirate & WIDEXFER) != 0
4489 && (ahc->features & AHC_WIDE) != 0)
4490 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4491 tinfo->user.protocol_version = 4;
4492 if ((ahc->features & AHC_DT) != 0)
4493 tinfo->user.transport_version = 3;
4494 else
4495 tinfo->user.transport_version = 2;
4496 tinfo->goal.protocol_version = 2;
4497 tinfo->goal.transport_version = 2;
4498 tinfo->curr.protocol_version = 2;
4499 tinfo->curr.transport_version = 2;
4500 }
4501 tstate->ultraenb = ultraenb;
4502 }
4503 ahc->user_discenable = discenable;
4504 ahc->user_tagenable = tagenable;
4505
4506 /* There are no untagged SCBs active yet. */
4507 for (i = 0; i < 16; i++) {
4508 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4509 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4510 int lun;
4511
4512 /*
4513 * The SCB based BTT allows an entry per
4514 * target and lun pair.
4515 */
4516 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4517 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4518 }
4519 }
4520
4521 /* All of our queues are empty */
4522 for (i = 0; i < 256; i++)
4523 ahc->qoutfifo[i] = SCB_LIST_NULL;
4524 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4525
4526 for (i = 0; i < 256; i++)
4527 ahc->qinfifo[i] = SCB_LIST_NULL;
4528
4529 if ((ahc->features & AHC_MULTI_TID) != 0) {
4530 ahc_outb(ahc, TARGID, 0);
4531 ahc_outb(ahc, TARGID + 1, 0);
4532 }
4533
4534 /*
4535 * Tell the sequencer where it can find our arrays in memory.
4536 */
4537 physaddr = ahc->scb_data->hscb_busaddr;
4538 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4539 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4540 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4541 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4542
4543 physaddr = ahc->shared_data_busaddr;
4544 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4545 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4546 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4547 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4548
4549 /*
4550 * Initialize the group code to command length table.
4551 * This overrides the values in TARG_SCSIRATE, so only
4552 * setup the table after we have processed that information.
4553 */
4554 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4555 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4556 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4557 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4558 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4559 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4560 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4561 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4562
4563 /* Tell the sequencer of our initial queue positions */
4564 ahc_outb(ahc, KERNEL_QINPOS, 0);
4565 ahc_outb(ahc, QINPOS, 0);
4566 ahc_outb(ahc, QOUTPOS, 0);
4567
4568 /*
4569 * Use the built in queue management registers
4570 * if they are available.
4571 */
4572 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4573 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4574 ahc_outb(ahc, SDSCB_QOFF, 0);
4575 ahc_outb(ahc, SNSCB_QOFF, 0);
4576 ahc_outb(ahc, HNSCB_QOFF, 0);
4577 }
4578
4579
4580 /* We don't have any waiting selections */
4581 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4582
4583 /* Our disconnection list is empty too */
4584 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4585
4586 /* Message out buffer starts empty */
4587 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4588
4589 /*
4590 * Setup the allowed SCSI Sequences based on operational mode.
4591 * If we are a target, we'll enalbe select in operations once
4592 * we've had a lun enabled.
4593 */
4594 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4595 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4596 scsiseq_template |= ENRSELI;
4597 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4598
4599 /*
4600 * Load the Sequencer program and Enable the adapter
4601 * in "fast" mode.
4602 */
4603 if (bootverbose)
4604 printf("%s: Downloading Sequencer Program...",
4605 ahc_name(ahc));
4606
4607 ahc_loadseq(ahc);
4608
4609 if ((ahc->features & AHC_ULTRA2) != 0) {
4610 int wait;
4611
4612 /*
4613 * Wait for up to 500ms for our transceivers
4614 * to settle. If the adapter does not have
4615 * a cable attached, the tranceivers may
4616 * never settle, so don't complain if we
4617 * fail here.
4618 */
4619 ahc_pause(ahc);
4620 for (wait = 5000;
4621 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4622 wait--)
4623 ahc_delay(100);
4624 ahc_unpause(ahc);
4625 }
4626 return (0);
4627 }
4628
4629 void
4630 ahc_intr_enable(struct ahc_softc *ahc, int enable)
4631 {
4632 u_int hcntrl;
4633
4634 hcntrl = ahc_inb(ahc, HCNTRL);
4635 hcntrl &= ~INTEN;
4636 ahc->pause &= ~INTEN;
4637 ahc->unpause &= ~INTEN;
4638 if (enable) {
4639 hcntrl |= INTEN;
4640 ahc->pause |= INTEN;
4641 ahc->unpause |= INTEN;
4642 }
4643 ahc_outb(ahc, HCNTRL, hcntrl);
4644 }
4645
4646 /*
4647 * Ensure that the card is paused in a location
4648 * outside of all critical sections and that all
4649 * pending work is completed prior to returning.
4650 * This routine should only be called from outside
4651 * an interrupt context.
4652 */
4653 void
4654 ahc_pause_and_flushwork(struct ahc_softc *ahc)
4655 {
4656 int intstat;
4657 int maxloops;
4658
4659 maxloops = 1000;
4660 ahc->flags |= AHC_ALL_INTERRUPTS;
4661 intstat = 0;
4662 do {
4663 ahc_intr(ahc);
4664 ahc_pause(ahc);
4665 ahc_clear_critical_section(ahc);
4666 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
4667 break;
4668 maxloops--;
4669 } while (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) && --maxloops);
4670 if (maxloops == 0) {
4671 printf("Infinite interrupt loop, INTSTAT = %x",
4672 ahc_inb(ahc, INTSTAT));
4673 }
4674 ahc_platform_flushwork(ahc);
4675 ahc->flags &= ~AHC_ALL_INTERRUPTS;
4676 }
4677
4678 int
4679 ahc_suspend(struct ahc_softc *ahc)
4680 {
4681 uint8_t *ptr;
4682 int i;
4683
4684 ahc_pause_and_flushwork(ahc);
4685
4686 if (LIST_FIRST(&ahc->pending_scbs) != NULL)
4687 return (EBUSY);
4688
4689 #if AHC_TARGET_MODE
4690 /*
4691 * XXX What about ATIOs that have not yet been serviced?
4692 * Perhaps we should just refuse to be suspended if we
4693 * are acting in a target role.
4694 */
4695 if (ahc->pending_device != NULL)
4696 return (EBUSY);
4697 #endif
4698
4699 /* Save volatile registers */
4700 if ((ahc->features & AHC_TWIN) != 0) {
4701 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4702 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ);
4703 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
4704 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1);
4705 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0);
4706 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1);
4707 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER);
4708 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL);
4709 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4710 }
4711 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ);
4712 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
4713 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1);
4714 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0);
4715 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1);
4716 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER);
4717 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL);
4718
4719 if ((ahc->chip & AHC_PCI) != 0) {
4720 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
4721 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
4722 }
4723
4724 if ((ahc->features & AHC_DT) != 0) {
4725 u_int sfunct;
4726
4727 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
4728 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
4729 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE);
4730 ahc_outb(ahc, SFUNCT, sfunct);
4731 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1);
4732 }
4733
4734 if ((ahc->features & AHC_MULTI_FUNC) != 0)
4735 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR);
4736
4737 if ((ahc->features & AHC_ULTRA2) != 0)
4738 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
4739
4740 ptr = ahc->suspend_state.scratch_ram;
4741 for (i = 0; i < 64; i++)
4742 *ptr++ = ahc_inb(ahc, SRAM_BASE + i);
4743
4744 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4745 for (i = 0; i < 16; i++)
4746 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i);
4747 }
4748
4749 ptr = ahc->suspend_state.btt;
4750 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4751 for (i = 0;i < AHC_NUM_TARGETS; i++) {
4752 int j;
4753
4754 for (j = 0;j < AHC_NUM_LUNS; j++) {
4755 u_int tcl;
4756
4757 tcl = BUILD_TCL(i << 4, j);
4758 *ptr = ahc_index_busy_tcl(ahc, tcl);
4759 }
4760 }
4761 }
4762 ahc_shutdown(ahc);
4763 return (0);
4764 }
4765
4766 int
4767 ahc_resume(struct ahc_softc *ahc)
4768 {
4769 uint8_t *ptr;
4770 int i;
4771
4772 ahc_reset(ahc);
4773
4774 ahc_build_free_scb_list(ahc);
4775
4776 /* Restore volatile registers */
4777 if ((ahc->features & AHC_TWIN) != 0) {
4778 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4779 ahc_outb(ahc, SCSIID, ahc->our_id);
4780 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq);
4781 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0);
4782 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1);
4783 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0);
4784 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1);
4785 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer);
4786 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl);
4787 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4788 }
4789 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq);
4790 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0);
4791 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1);
4792 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0);
4793 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1);
4794 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer);
4795 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl);
4796 if ((ahc->features & AHC_ULTRA2) != 0)
4797 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4798 else
4799 ahc_outb(ahc, SCSIID, ahc->our_id);
4800
4801 if ((ahc->chip & AHC_PCI) != 0) {
4802 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0);
4803 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus);
4804 }
4805
4806 if ((ahc->features & AHC_DT) != 0) {
4807 u_int sfunct;
4808
4809 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
4810 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
4811 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode);
4812 ahc_outb(ahc, SFUNCT, sfunct);
4813 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1);
4814 }
4815
4816 if ((ahc->features & AHC_MULTI_FUNC) != 0)
4817 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr);
4818
4819 if ((ahc->features & AHC_ULTRA2) != 0)
4820 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh);
4821
4822 ptr = ahc->suspend_state.scratch_ram;
4823 for (i = 0; i < 64; i++)
4824 ahc_outb(ahc, SRAM_BASE + i, *ptr++);
4825
4826 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4827 for (i = 0; i < 16; i++)
4828 ahc_outb(ahc, TARG_OFFSET + i, *ptr++);
4829 }
4830
4831 ptr = ahc->suspend_state.btt;
4832 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4833 for (i = 0;i < AHC_NUM_TARGETS; i++) {
4834 int j;
4835
4836 for (j = 0;j < AHC_NUM_LUNS; j++) {
4837 u_int tcl;
4838
4839 tcl = BUILD_TCL(i << 4, j);
4840 ahc_busy_tcl(ahc, tcl, *ptr);
4841 }
4842 }
4843 }
4844 return (0);
4845 }
4846
4847 /************************** Busy Target Table *********************************/
4848 /*
4849 * Return the untagged transaction id for a given target/channel lun.
4850 * Optionally, clear the entry.
4851 */
4852 u_int
4853 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
4854 {
4855 u_int scbid;
4856 u_int target_offset;
4857
4858 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4859 u_int saved_scbptr;
4860
4861 saved_scbptr = ahc_inb(ahc, SCBPTR);
4862 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
4863 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
4864 ahc_outb(ahc, SCBPTR, saved_scbptr);
4865 } else {
4866 target_offset = TCL_TARGET_OFFSET(tcl);
4867 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
4868 }
4869
4870 return (scbid);
4871 }
4872
4873 void
4874 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
4875 {
4876 u_int target_offset;
4877
4878 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4879 u_int saved_scbptr;
4880
4881 saved_scbptr = ahc_inb(ahc, SCBPTR);
4882 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
4883 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
4884 ahc_outb(ahc, SCBPTR, saved_scbptr);
4885 } else {
4886 target_offset = TCL_TARGET_OFFSET(tcl);
4887 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
4888 }
4889 }
4890
4891 void
4892 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
4893 {
4894 u_int target_offset;
4895
4896 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4897 u_int saved_scbptr;
4898
4899 saved_scbptr = ahc_inb(ahc, SCBPTR);
4900 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
4901 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
4902 ahc_outb(ahc, SCBPTR, saved_scbptr);
4903 } else {
4904 target_offset = TCL_TARGET_OFFSET(tcl);
4905 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
4906 }
4907 }
4908
4909 /************************** SCB and SCB queue management **********************/
4910 int
4911 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
4912 char channel, int lun, u_int tag, role_t role)
4913 {
4914 int targ = SCB_GET_TARGET(ahc, scb);
4915 char chan = SCB_GET_CHANNEL(ahc, scb);
4916 int slun = SCB_GET_LUN(scb);
4917 int match;
4918
4919 match = ((chan == channel) || (channel == ALL_CHANNELS));
4920 if (match != 0)
4921 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
4922 if (match != 0)
4923 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
4924 if (match != 0) {
4925 #if AHC_TARGET_MODE
4926 int group;
4927
4928 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
4929 if (role == ROLE_INITIATOR) {
4930 match = (group != XPT_FC_GROUP_TMODE)
4931 && ((tag == scb->hscb->tag)
4932 || (tag == SCB_LIST_NULL));
4933 } else if (role == ROLE_TARGET) {
4934 match = (group == XPT_FC_GROUP_TMODE)
4935 && ((tag == scb->io_ctx->csio.tag_id)
4936 || (tag == SCB_LIST_NULL));
4937 }
4938 #else /* !AHC_TARGET_MODE */
4939 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
4940 #endif /* AHC_TARGET_MODE */
4941 }
4942
4943 return match;
4944 }
4945
4946 void
4947 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
4948 {
4949 int target;
4950 char channel;
4951 int lun;
4952
4953 target = SCB_GET_TARGET(ahc, scb);
4954 lun = SCB_GET_LUN(scb);
4955 channel = SCB_GET_CHANNEL(ahc, scb);
4956
4957 ahc_search_qinfifo(ahc, target, channel, lun,
4958 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
4959 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
4960
4961 ahc_platform_freeze_devq(ahc, scb);
4962 }
4963
4964 void
4965 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
4966 {
4967 struct scb *prev_scb;
4968
4969 prev_scb = NULL;
4970 if (ahc_qinfifo_count(ahc) != 0) {
4971 u_int prev_tag;
4972 uint8_t prev_pos;
4973
4974 prev_pos = ahc->qinfifonext - 1;
4975 prev_tag = ahc->qinfifo[prev_pos];
4976 prev_scb = ahc_lookup_scb(ahc, prev_tag);
4977 }
4978 ahc_qinfifo_requeue(ahc, prev_scb, scb);
4979 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4980 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4981 } else {
4982 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4983 }
4984 }
4985
4986 static void
4987 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
4988 struct scb *scb)
4989 {
4990 if (prev_scb == NULL) {
4991 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
4992 } else {
4993 prev_scb->hscb->next = scb->hscb->tag;
4994 ahc_sync_scb(ahc, prev_scb,
4995 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
4996 }
4997 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
4998 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
4999 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5000 }
5001
5002 static int
5003 ahc_qinfifo_count(struct ahc_softc *ahc)
5004 {
5005 u_int8_t qinpos;
5006 u_int8_t diff;
5007
5008 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5009 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5010 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5011 } else
5012 qinpos = ahc_inb(ahc, QINPOS);
5013 diff = ahc->qinfifonext - qinpos;
5014 return (diff);
5015 }
5016
5017 int
5018 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5019 int lun, u_int tag, role_t role, uint32_t status,
5020 ahc_search_action action)
5021 {
5022 struct scb *scb;
5023 struct scb *prev_scb;
5024 uint8_t qinstart;
5025 uint8_t qinpos;
5026 uint8_t qintail;
5027 uint8_t next, prev;
5028 uint8_t curscbptr;
5029 int found;
5030 int maxtarget;
5031 int i;
5032 int have_qregs;
5033
5034 qintail = ahc->qinfifonext;
5035 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5036 if (have_qregs) {
5037 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5038 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5039 } else
5040 qinstart = ahc_inb(ahc, QINPOS);
5041 qinpos = qinstart;
5042 next = ahc_inb(ahc, NEXT_QUEUED_SCB);
5043 found = 0;
5044 prev_scb = NULL;
5045
5046 if (action == SEARCH_COMPLETE) {
5047 /*
5048 * Don't attempt to run any queued untagged transactions
5049 * until we are done with the abort process.
5050 */
5051 ahc_freeze_untagged_queues(ahc);
5052 }
5053
5054 /*
5055 * Start with an empty queue. Entries that are not chosen
5056 * for removal will be re-added to the queue as we go.
5057 */
5058 ahc->qinfifonext = qinpos;
5059 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5060
5061 while (qinpos != qintail) {
5062 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5063 if (scb == NULL) {
5064 printf("qinpos = %d, SCB index = %d\n",
5065 qinpos, ahc->qinfifo[qinpos]);
5066 panic("Loop 1\n");
5067 }
5068
5069 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5070 /*
5071 * We found an scb that needs to be acted on.
5072 */
5073 found++;
5074 switch (action) {
5075 case SEARCH_COMPLETE:
5076 {
5077 cam_status ostat;
5078 cam_status cstat;
5079
5080 ostat = ahc_get_transaction_status(scb);
5081 if (ostat == CAM_REQ_INPROG)
5082 ahc_set_transaction_status(scb,
5083 status);
5084 cstat = ahc_get_transaction_status(scb);
5085 if (cstat != CAM_REQ_CMP)
5086 ahc_freeze_scb(scb);
5087 if ((scb->flags & SCB_ACTIVE) == 0)
5088 printf("Inactive SCB in qinfifo\n");
5089 ahc_done(ahc, scb);
5090
5091 /* FALLTHROUGH */
5092 case SEARCH_REMOVE:
5093 break;
5094 }
5095 case SEARCH_COUNT:
5096 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5097 prev_scb = scb;
5098 break;
5099 }
5100 } else {
5101 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5102 prev_scb = scb;
5103 }
5104 qinpos++;
5105 }
5106
5107 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5108 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5109 } else {
5110 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5111 }
5112
5113 if (action != SEARCH_COUNT
5114 && (found != 0)
5115 && (qinstart != ahc->qinfifonext)) {
5116 /*
5117 * The sequencer may be in the process of dmaing
5118 * down the SCB at the beginning of the queue.
5119 * This could be problematic if either the first,
5120 * or the second SCB is removed from the queue
5121 * (the first SCB includes a pointer to the "next"
5122 * SCB to dma). If we have removed any entries, swap
5123 * the first element in the queue with the next HSCB
5124 * so the sequencer will notice that NEXT_QUEUED_SCB
5125 * has changed during its dma attempt and will retry
5126 * the DMA.
5127 */
5128 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5129
5130 if (scb == NULL) {
5131 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5132 found, qinstart, ahc->qinfifonext);
5133 panic("First/Second Qinfifo fixup\n");
5134 }
5135 /*
5136 * ahc_swap_with_next_hscb forces our next pointer to
5137 * point to the reserved SCB for future commands. Save
5138 * and restore our original next pointer to maintain
5139 * queue integrity.
5140 */
5141 next = scb->hscb->next;
5142 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5143 ahc_swap_with_next_hscb(ahc, scb);
5144 scb->hscb->next = next;
5145 ahc->qinfifo[qinstart] = scb->hscb->tag;
5146
5147 /* Tell the card about the new head of the qinfifo. */
5148 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5149
5150 /* Fixup the tail "next" pointer. */
5151 qintail = ahc->qinfifonext - 1;
5152 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5153 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5154 }
5155
5156 /*
5157 * Search waiting for selection list.
5158 */
5159 curscbptr = ahc_inb(ahc, SCBPTR);
5160 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5161 prev = SCB_LIST_NULL;
5162
5163 while (next != SCB_LIST_NULL) {
5164 uint8_t scb_index;
5165
5166 ahc_outb(ahc, SCBPTR, next);
5167 scb_index = ahc_inb(ahc, SCB_TAG);
5168 if (scb_index >= ahc->scb_data->numscbs) {
5169 printf("Waiting List inconsistency. "
5170 "SCB index == %d, yet numscbs == %d.",
5171 scb_index, ahc->scb_data->numscbs);
5172 ahc_dump_card_state(ahc);
5173 panic("for safety");
5174 }
5175 scb = ahc_lookup_scb(ahc, scb_index);
5176 if (scb == NULL) {
5177 printf("scb_index = %d, next = %d\n",
5178 scb_index, next);
5179 panic("Waiting List traversal\n");
5180 }
5181 if (ahc_match_scb(ahc, scb, target, channel,
5182 lun, SCB_LIST_NULL, role)) {
5183 /*
5184 * We found an scb that needs to be acted on.
5185 */
5186 found++;
5187 switch (action) {
5188 case SEARCH_COMPLETE:
5189 {
5190 cam_status ostat;
5191 cam_status cstat;
5192
5193 ostat = ahc_get_transaction_status(scb);
5194 if (ostat == CAM_REQ_INPROG)
5195 ahc_set_transaction_status(scb,
5196 status);
5197 cstat = ahc_get_transaction_status(scb);
5198 if (cstat != CAM_REQ_CMP)
5199 ahc_freeze_scb(scb);
5200 if ((scb->flags & SCB_ACTIVE) == 0)
5201 printf("Inactive SCB in Waiting List\n");
5202 ahc_done(ahc, scb);
5203 /* FALLTHROUGH */
5204 }
5205 case SEARCH_REMOVE:
5206 next = ahc_rem_wscb(ahc, next, prev);
5207 break;
5208 case SEARCH_COUNT:
5209 prev = next;
5210 next = ahc_inb(ahc, SCB_NEXT);
5211 break;
5212 }
5213 } else {
5214
5215 prev = next;
5216 next = ahc_inb(ahc, SCB_NEXT);
5217 }
5218 }
5219 ahc_outb(ahc, SCBPTR, curscbptr);
5220
5221 /*
5222 * And lastly, the untagged holding queues.
5223 */
5224 i = 0;
5225 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5226
5227 maxtarget = 16;
5228 if (target != CAM_TARGET_WILDCARD) {
5229
5230 i = target;
5231 if (channel == 'B')
5232 i += 8;
5233 maxtarget = i + 1;
5234 }
5235 } else {
5236 maxtarget = 0;
5237 }
5238
5239 for (; i < maxtarget; i++) {
5240 struct scb_tailq *untagged_q;
5241 struct scb *next_scb;
5242
5243 untagged_q = &(ahc->untagged_queues[i]);
5244 next_scb = TAILQ_FIRST(untagged_q);
5245 while (next_scb != NULL) {
5246
5247 scb = next_scb;
5248 next_scb = TAILQ_NEXT(scb, links.tqe);
5249
5250 /*
5251 * The head of the list may be the currently
5252 * active untagged command for a device.
5253 * We're only searching for commands that
5254 * have not been started. A transaction
5255 * marked active but still in the qinfifo
5256 * is removed by the qinfifo scanning code
5257 * above.
5258 */
5259 if ((scb->flags & SCB_ACTIVE) != 0)
5260 continue;
5261
5262 if (ahc_match_scb(ahc, scb, target, channel,
5263 lun, SCB_LIST_NULL, role)) {
5264 /*
5265 * We found an scb that needs to be acted on.
5266 */
5267 found++;
5268 switch (action) {
5269 case SEARCH_COMPLETE:
5270 {
5271 cam_status ostat;
5272 cam_status cstat;
5273
5274 ostat = ahc_get_transaction_status(scb);
5275 if (ostat == CAM_REQ_INPROG)
5276 ahc_set_transaction_status(scb,
5277 status);
5278 cstat = ahc_get_transaction_status(scb);
5279 if (cstat != CAM_REQ_CMP)
5280 ahc_freeze_scb(scb);
5281 if ((scb->flags & SCB_ACTIVE) == 0)
5282 printf("Inactive SCB in untaggedQ\n");
5283 ahc_done(ahc, scb);
5284 break;
5285 }
5286 case SEARCH_REMOVE:
5287 TAILQ_REMOVE(untagged_q, scb,
5288 links.tqe);
5289 break;
5290 case SEARCH_COUNT:
5291 break;
5292 }
5293 }
5294 }
5295 }
5296
5297 if (action == SEARCH_COMPLETE)
5298 ahc_release_untagged_queues(ahc);
5299 return (found);
5300 }
5301
5302 int
5303 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5304 int lun, u_int tag, int stop_on_first, int remove,
5305 int save_state)
5306 {
5307 struct scb *scbp;
5308 u_int next;
5309 u_int prev;
5310 u_int count;
5311 u_int active_scb;
5312
5313 count = 0;
5314 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5315 prev = SCB_LIST_NULL;
5316
5317 if (save_state) {
5318 /* restore this when we're done */
5319 active_scb = ahc_inb(ahc, SCBPTR);
5320 } else
5321 /* Silence compiler */
5322 active_scb = SCB_LIST_NULL;
5323
5324 while (next != SCB_LIST_NULL) {
5325 u_int scb_index;
5326
5327 ahc_outb(ahc, SCBPTR, next);
5328 scb_index = ahc_inb(ahc, SCB_TAG);
5329 if (scb_index >= ahc->scb_data->numscbs) {
5330 printf("Disconnected List inconsistency. "
5331 "SCB index == %d, yet numscbs == %d.",
5332 scb_index, ahc->scb_data->numscbs);
5333 ahc_dump_card_state(ahc);
5334 panic("for safety");
5335 }
5336
5337 if (next == prev) {
5338 panic("Disconnected List Loop. "
5339 "cur SCBPTR == %x, prev SCBPTR == %x.",
5340 next, prev);
5341 }
5342 scbp = ahc_lookup_scb(ahc, scb_index);
5343 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5344 tag, ROLE_INITIATOR)) {
5345 count++;
5346 if (remove) {
5347 next =
5348 ahc_rem_scb_from_disc_list(ahc, prev, next);
5349 } else {
5350 prev = next;
5351 next = ahc_inb(ahc, SCB_NEXT);
5352 }
5353 if (stop_on_first)
5354 break;
5355 } else {
5356 prev = next;
5357 next = ahc_inb(ahc, SCB_NEXT);
5358 }
5359 }
5360 if (save_state)
5361 ahc_outb(ahc, SCBPTR, active_scb);
5362 return (count);
5363 }
5364
5365 /*
5366 * Remove an SCB from the on chip list of disconnected transactions.
5367 * This is empty/unused if we are not performing SCB paging.
5368 */
5369 static u_int
5370 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5371 {
5372 u_int next;
5373
5374 ahc_outb(ahc, SCBPTR, scbptr);
5375 next = ahc_inb(ahc, SCB_NEXT);
5376
5377 ahc_outb(ahc, SCB_CONTROL, 0);
5378
5379 ahc_add_curscb_to_free_list(ahc);
5380
5381 if (prev != SCB_LIST_NULL) {
5382 ahc_outb(ahc, SCBPTR, prev);
5383 ahc_outb(ahc, SCB_NEXT, next);
5384 } else
5385 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5386
5387 return (next);
5388 }
5389
5390 /*
5391 * Add the SCB as selected by SCBPTR onto the on chip list of
5392 * free hardware SCBs. This list is empty/unused if we are not
5393 * performing SCB paging.
5394 */
5395 static void
5396 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5397 {
5398 /*
5399 * Invalidate the tag so that our abort
5400 * routines don't think it's active.
5401 */
5402 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5403
5404 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5405 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5406 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5407 }
5408 }
5409
5410 /*
5411 * Manipulate the waiting for selection list and return the
5412 * scb that follows the one that we remove.
5413 */
5414 static u_int
5415 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5416 {
5417 u_int curscb, next;
5418
5419 /*
5420 * Select the SCB we want to abort and
5421 * pull the next pointer out of it.
5422 */
5423 curscb = ahc_inb(ahc, SCBPTR);
5424 ahc_outb(ahc, SCBPTR, scbpos);
5425 next = ahc_inb(ahc, SCB_NEXT);
5426
5427 /* Clear the necessary fields */
5428 ahc_outb(ahc, SCB_CONTROL, 0);
5429
5430 ahc_add_curscb_to_free_list(ahc);
5431
5432 /* update the waiting list */
5433 if (prev == SCB_LIST_NULL) {
5434 /* First in the list */
5435 ahc_outb(ahc, WAITING_SCBH, next);
5436
5437 /*
5438 * Ensure we aren't attempting to perform
5439 * selection for this entry.
5440 */
5441 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5442 } else {
5443 /*
5444 * Select the scb that pointed to us
5445 * and update its next pointer.
5446 */
5447 ahc_outb(ahc, SCBPTR, prev);
5448 ahc_outb(ahc, SCB_NEXT, next);
5449 }
5450
5451 /*
5452 * Point us back at the original scb position.
5453 */
5454 ahc_outb(ahc, SCBPTR, curscb);
5455 return next;
5456 }
5457
5458 /******************************** Error Handling ******************************/
5459 /*
5460 * Abort all SCBs that match the given description (target/channel/lun/tag),
5461 * setting their status to the passed in status if the status has not already
5462 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5463 * is paused before it is called.
5464 */
5465 int
5466 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5467 int lun, u_int tag, role_t role, uint32_t status)
5468 {
5469 struct scb *scbp;
5470 struct scb *scbp_next;
5471 u_int active_scb;
5472 int i, j;
5473 int maxtarget;
5474 int minlun;
5475 int maxlun;
5476
5477 int found;
5478
5479 /*
5480 * Don't attempt to run any queued untagged transactions
5481 * until we are done with the abort process.
5482 */
5483 ahc_freeze_untagged_queues(ahc);
5484
5485 /* restore this when we're done */
5486 active_scb = ahc_inb(ahc, SCBPTR);
5487
5488 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5489 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5490
5491 /*
5492 * Clean out the busy target table for any untagged commands.
5493 */
5494 i = 0;
5495 maxtarget = 16;
5496 if (target != CAM_TARGET_WILDCARD) {
5497 i = target;
5498 if (channel == 'B')
5499 i += 8;
5500 maxtarget = i + 1;
5501 }
5502
5503 if (lun == CAM_LUN_WILDCARD) {
5504
5505 /*
5506 * Unless we are using an SCB based
5507 * busy targets table, there is only
5508 * one table entry for all luns of
5509 * a target.
5510 */
5511 minlun = 0;
5512 maxlun = 1;
5513 if ((ahc->flags & AHC_SCB_BTT) != 0)
5514 maxlun = AHC_NUM_LUNS;
5515 } else {
5516 minlun = lun;
5517 maxlun = lun + 1;
5518 }
5519
5520 for (;i < maxtarget; i++) {
5521 for (j = minlun;j < maxlun; j++)
5522 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5523 }
5524
5525 /*
5526 * Go through the disconnected list and remove any entries we
5527 * have queued for completion, 0'ing their control byte too.
5528 * We save the active SCB and restore it ourselves, so there
5529 * is no reason for this search to restore it too.
5530 */
5531 ahc_search_disc_list(ahc, target, channel, lun, tag,
5532 /*stop_on_first*/FALSE, /*remove*/TRUE,
5533 /*save_state*/FALSE);
5534
5535 /*
5536 * Go through the hardware SCB array looking for commands that
5537 * were active but not on any list.
5538 */
5539 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5540 u_int scbid;
5541
5542 ahc_outb(ahc, SCBPTR, i);
5543 scbid = ahc_inb(ahc, SCB_TAG);
5544 scbp = ahc_lookup_scb(ahc, scbid);
5545 if (scbp != NULL
5546 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))
5547 ahc_add_curscb_to_free_list(ahc);
5548 }
5549
5550 /*
5551 * Go through the pending CCB list and look for
5552 * commands for this target that are still active.
5553 * These are other tagged commands that were
5554 * disconnected when the reset occurred.
5555 */
5556 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5557 while (scbp_next != NULL) {
5558 scbp = scbp_next;
5559 scbp_next = LIST_NEXT(scbp, pending_links);
5560 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5561 cam_status ostat;
5562
5563 ostat = ahc_get_transaction_status(scbp);
5564 if (ostat == CAM_REQ_INPROG)
5565 ahc_set_transaction_status(scbp, status);
5566 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5567 ahc_freeze_scb(scbp);
5568 if ((scbp->flags & SCB_ACTIVE) == 0)
5569 printf("Inactive SCB on pending list\n");
5570 ahc_done(ahc, scbp);
5571 found++;
5572 }
5573 }
5574 ahc_outb(ahc, SCBPTR, active_scb);
5575 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5576 ahc_release_untagged_queues(ahc);
5577 return found;
5578 }
5579
5580 static void
5581 ahc_reset_current_bus(struct ahc_softc *ahc)
5582 {
5583 uint8_t scsiseq;
5584
5585 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5586 scsiseq = ahc_inb(ahc, SCSISEQ);
5587 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5588 ahc_delay(AHC_BUSRESET_DELAY);
5589 /* Turn off the bus reset */
5590 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5591
5592 ahc_clear_intstat(ahc);
5593
5594 /* Re-enable reset interrupts */
5595 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5596 }
5597
5598 int
5599 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5600 {
5601 struct ahc_devinfo devinfo;
5602 u_int initiator, target, max_scsiid;
5603 u_int sblkctl;
5604 u_int scsiseq;
5605 u_int simode1;
5606 int found;
5607 int restart_needed;
5608 char cur_channel;
5609
5610 ahc->pending_device = NULL;
5611
5612 ahc_compile_devinfo(&devinfo,
5613 CAM_TARGET_WILDCARD,
5614 CAM_TARGET_WILDCARD,
5615 CAM_LUN_WILDCARD,
5616 channel, ROLE_UNKNOWN);
5617 ahc_pause(ahc);
5618
5619 /* Make sure the sequencer is in a safe location. */
5620 ahc_clear_critical_section(ahc);
5621
5622 /*
5623 * Run our command complete fifos to ensure that we perform
5624 * completion processing on any commands that 'completed'
5625 * before the reset occurred.
5626 */
5627 ahc_run_qoutfifo(ahc);
5628 #if AHC_TARGET_MODE
5629 if ((ahc->flags & AHC_TARGETROLE) != 0) {
5630 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5631 }
5632 #endif
5633
5634 /*
5635 * Reset the bus if we are initiating this reset
5636 */
5637 sblkctl = ahc_inb(ahc, SBLKCTL);
5638 cur_channel = 'A';
5639 if ((ahc->features & AHC_TWIN) != 0
5640 && ((sblkctl & SELBUSB) != 0))
5641 cur_channel = 'B';
5642 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5643 if (cur_channel != channel) {
5644 /* Case 1: Command for another bus is active
5645 * Stealthily reset the other bus without
5646 * upsetting the current bus.
5647 */
5648 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5649 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5650 ahc_outb(ahc, SIMODE1, simode1);
5651 if (initiate_reset)
5652 ahc_reset_current_bus(ahc);
5653 ahc_clear_intstat(ahc);
5654 #if AHC_TARGET_MODE
5655 /*
5656 * Bus resets clear ENSELI, so we cannot
5657 * defer re-enabling bus reset interrupts
5658 * if we are in target mode.
5659 */
5660 if ((ahc->flags & AHC_TARGETROLE) != 0)
5661 ahc_outb(ahc, SIMODE1, simode1 | ENSCSIRST);
5662 #endif
5663 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5664 ahc_outb(ahc, SBLKCTL, sblkctl);
5665 restart_needed = FALSE;
5666 } else {
5667 /* Case 2: A command from this bus is active or we're idle */
5668 ahc_clear_msg_state(ahc);
5669 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5670 ahc_outb(ahc, SIMODE1, simode1);
5671 if (initiate_reset)
5672 ahc_reset_current_bus(ahc);
5673 ahc_clear_intstat(ahc);
5674 #if AHC_TARGET_MODE
5675 /*
5676 * Bus resets clear ENSELI, so we cannot
5677 * defer re-enabling bus reset interrupts
5678 * if we are in target mode.
5679 */
5680 if ((ahc->flags & AHC_TARGETROLE) != 0)
5681 ahc_outb(ahc, SIMODE1, simode1 | ENSCSIRST);
5682 #endif
5683 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5684 restart_needed = TRUE;
5685 }
5686
5687 /*
5688 * Clean up all the state information for the
5689 * pending transactions on this bus.
5690 */
5691 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
5692 CAM_LUN_WILDCARD, SCB_LIST_NULL,
5693 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
5694
5695 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
5696
5697 #ifdef AHC_TARGET_MODE
5698 /*
5699 * Send an immediate notify ccb to all target more peripheral
5700 * drivers affected by this action.
5701 */
5702 for (target = 0; target <= max_scsiid; target++) {
5703 struct ahc_tmode_tstate* tstate;
5704 u_int lun;
5705
5706 tstate = ahc->enabled_targets[target];
5707 if (tstate == NULL)
5708 continue;
5709 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
5710 struct ahc_tmode_lstate* lstate;
5711
5712 lstate = tstate->enabled_luns[lun];
5713 if (lstate == NULL)
5714 continue;
5715
5716 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
5717 EVENT_TYPE_BUS_RESET, /*arg*/0);
5718 ahc_send_lstate_events(ahc, lstate);
5719 }
5720 }
5721 #endif
5722 /* Notify the XPT that a bus reset occurred */
5723 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
5724 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
5725
5726 /*
5727 * Revert to async/narrow transfers until we renegotiate.
5728 */
5729 for (target = 0; target <= max_scsiid; target++) {
5730
5731 if (ahc->enabled_targets[target] == NULL)
5732 continue;
5733 for (initiator = 0; initiator <= max_scsiid; initiator++) {
5734 struct ahc_devinfo devinfo;
5735
5736 ahc_compile_devinfo(&devinfo, target, initiator,
5737 CAM_LUN_WILDCARD,
5738 channel, ROLE_UNKNOWN);
5739 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5740 AHC_TRANS_CUR, /*paused*/TRUE);
5741 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
5742 /*period*/0, /*offset*/0,
5743 /*ppr_options*/0, AHC_TRANS_CUR,
5744 /*paused*/TRUE);
5745 }
5746 }
5747
5748 if (restart_needed)
5749 ahc_restart(ahc);
5750 else
5751 ahc_unpause(ahc);
5752 return found;
5753 }
5754
5755
5756 /***************************** Residual Processing ****************************/
5757 /*
5758 * Calculate the residual for a just completed SCB.
5759 */
5760 void
5761 ahc_calc_residual(struct scb *scb)
5762 {
5763 struct hardware_scb *hscb;
5764 struct status_pkt *spkt;
5765 uint32_t sgptr;
5766 uint32_t resid_sgptr;
5767 uint32_t resid;
5768
5769 /*
5770 * 5 cases.
5771 * 1) No residual.
5772 * SG_RESID_VALID clear in sgptr.
5773 * 2) Transferless command
5774 * 3) Never performed any transfers.
5775 * sgptr has SG_FULL_RESID set.
5776 * 4) No residual but target did not
5777 * save data pointers after the
5778 * last transfer, so sgptr was
5779 * never updated.
5780 * 5) We have a partial residual.
5781 * Use residual_sgptr to determine
5782 * where we are.
5783 */
5784
5785 hscb = scb->hscb;
5786 sgptr = ahc_le32toh(hscb->sgptr);
5787 if ((sgptr & SG_RESID_VALID) == 0)
5788 /* Case 1 */
5789 return;
5790 sgptr &= ~SG_RESID_VALID;
5791
5792 if ((sgptr & SG_LIST_NULL) != 0)
5793 /* Case 2 */
5794 return;
5795
5796 spkt = &hscb->shared_data.status;
5797 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
5798 if ((sgptr & SG_FULL_RESID) != 0) {
5799 /* Case 3 */
5800 resid = ahc_get_transfer_length(scb);
5801 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
5802 /* Case 4 */
5803 return;
5804 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
5805 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
5806 } else {
5807 struct ahc_dma_seg *sg;
5808
5809 /*
5810 * Remainder of the SG where the transfer
5811 * stopped.
5812 */
5813 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
5814 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
5815
5816 /* The residual sg_ptr always points to the next sg */
5817 sg--;
5818
5819 /*
5820 * Add up the contents of all residual
5821 * SG segments that are after the SG where
5822 * the transfer stopped.
5823 */
5824 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
5825 sg++;
5826 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
5827 }
5828 }
5829 if ((scb->flags & SCB_SENSE) == 0)
5830 ahc_set_residual(scb, resid);
5831 else
5832 ahc_set_sense_residual(scb, resid);
5833
5834 #ifdef AHC_DEBUG
5835 if ((ahc_debug & AHC_SHOWMISC) != 0) {
5836 ahc_print_path(ahc, scb);
5837 printf("Handled Residual of %d bytes\n", resid);
5838 }
5839 #endif
5840 }
5841
5842 /******************************* Target Mode **********************************/
5843 #ifdef AHC_TARGET_MODE
5844 /*
5845 * Add a target mode event to this lun's queue
5846 */
5847 static void
5848 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
5849 u_int initiator_id, u_int event_type, u_int event_arg)
5850 {
5851 struct ahc_tmode_event *event;
5852 int pending;
5853
5854 xpt_freeze_devq(lstate->path, /*count*/1);
5855 if (lstate->event_w_idx >= lstate->event_r_idx)
5856 pending = lstate->event_w_idx - lstate->event_r_idx;
5857 else
5858 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
5859 - (lstate->event_r_idx - lstate->event_w_idx);
5860
5861 if (event_type == EVENT_TYPE_BUS_RESET
5862 || event_type == MSG_BUS_DEV_RESET) {
5863 /*
5864 * Any earlier events are irrelevant, so reset our buffer.
5865 * This has the effect of allowing us to deal with reset
5866 * floods (an external device holding down the reset line)
5867 * without losing the event that is really interesting.
5868 */
5869 lstate->event_r_idx = 0;
5870 lstate->event_w_idx = 0;
5871 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
5872 }
5873
5874 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
5875 xpt_print_path(lstate->path);
5876 printf("immediate event %x:%x lost\n",
5877 lstate->event_buffer[lstate->event_r_idx].event_type,
5878 lstate->event_buffer[lstate->event_r_idx].event_arg);
5879 lstate->event_r_idx++;
5880 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
5881 lstate->event_r_idx = 0;
5882 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
5883 }
5884
5885 event = &lstate->event_buffer[lstate->event_w_idx];
5886 event->initiator_id = initiator_id;
5887 event->event_type = event_type;
5888 event->event_arg = event_arg;
5889 lstate->event_w_idx++;
5890 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
5891 lstate->event_w_idx = 0;
5892 }
5893
5894 /*
5895 * Send any target mode events queued up waiting
5896 * for immediate notify resources.
5897 */
5898 void
5899 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
5900 {
5901 struct ccb_hdr *ccbh;
5902 struct ccb_immed_notify *inot;
5903
5904 while (lstate->event_r_idx != lstate->event_w_idx
5905 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
5906 struct ahc_tmode_event *event;
5907
5908 event = &lstate->event_buffer[lstate->event_r_idx];
5909 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
5910 inot = (struct ccb_immed_notify *)ccbh;
5911 switch (event->event_type) {
5912 case EVENT_TYPE_BUS_RESET:
5913 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
5914 break;
5915 default:
5916 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
5917 inot->message_args[0] = event->event_type;
5918 inot->message_args[1] = event->event_arg;
5919 break;
5920 }
5921 inot->initiator_id = event->initiator_id;
5922 inot->sense_len = 0;
5923 xpt_done((union ccb *)inot);
5924 lstate->event_r_idx++;
5925 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
5926 lstate->event_r_idx = 0;
5927 }
5928 }
5929 #endif
5930
5931 /******************** Sequencer Program Patching/Download *********************/
5932
5933 #ifdef AHC_DUMP_SEQ
5934 void
5935 ahc_dumpseq(struct ahc_softc* ahc)
5936 {
5937 int i;
5938 int max_prog;
5939
5940 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI)
5941 max_prog = 448;
5942 else if ((ahc->features & AHC_ULTRA2) != 0)
5943 max_prog = 768;
5944 else
5945 max_prog = 512;
5946
5947 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
5948 ahc_outb(ahc, SEQADDR0, 0);
5949 ahc_outb(ahc, SEQADDR1, 0);
5950 for (i = 0; i < max_prog; i++) {
5951 uint8_t ins_bytes[4];
5952
5953 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
5954 printf("0x%08x\n", ins_bytes[0] << 24
5955 | ins_bytes[1] << 16
5956 | ins_bytes[2] << 8
5957 | ins_bytes[3]);
5958 }
5959 }
5960 #endif
5961
5962 static void
5963 ahc_loadseq(struct ahc_softc *ahc)
5964 {
5965 struct cs cs_table[num_critical_sections];
5966 u_int begin_set[num_critical_sections];
5967 u_int end_set[num_critical_sections];
5968 struct patch *cur_patch;
5969 u_int cs_count;
5970 u_int cur_cs;
5971 u_int i;
5972 int downloaded;
5973 u_int skip_addr;
5974 u_int sg_prefetch_cnt;
5975 uint8_t download_consts[7];
5976
5977 /*
5978 * Start out with 0 critical sections
5979 * that apply to this firmware load.
5980 */
5981 cs_count = 0;
5982 cur_cs = 0;
5983 memset(begin_set, 0, sizeof(begin_set));
5984 memset(end_set, 0, sizeof(end_set));
5985
5986 /* Setup downloadable constant table */
5987 download_consts[QOUTFIFO_OFFSET] = 0;
5988 if (ahc->targetcmds != NULL)
5989 download_consts[QOUTFIFO_OFFSET] += 32;
5990 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
5991 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
5992 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
5993 sg_prefetch_cnt = ahc->pci_cachesize;
5994 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
5995 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
5996 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
5997 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
5998 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
5999
6000 cur_patch = patches;
6001 downloaded = 0;
6002 skip_addr = 0;
6003 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6004 ahc_outb(ahc, SEQADDR0, 0);
6005 ahc_outb(ahc, SEQADDR1, 0);
6006
6007 for (i = 0; i < sizeof(seqprog)/4; i++) {
6008 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6009 /*
6010 * Don't download this instruction as it
6011 * is in a patch that was removed.
6012 */
6013 continue;
6014 }
6015 /*
6016 * Move through the CS table until we find a CS
6017 * that might apply to this instruction.
6018 */
6019 for (; cur_cs < num_critical_sections; cur_cs++) {
6020 if (critical_sections[cur_cs].end <= i) {
6021 if (begin_set[cs_count] == TRUE
6022 && end_set[cs_count] == FALSE) {
6023 cs_table[cs_count].end = downloaded;
6024 end_set[cs_count] = TRUE;
6025 cs_count++;
6026 }
6027 continue;
6028 }
6029 if (critical_sections[cur_cs].begin <= i
6030 && begin_set[cs_count] == FALSE) {
6031 cs_table[cs_count].begin = downloaded;
6032 begin_set[cs_count] = TRUE;
6033 }
6034 break;
6035 }
6036 ahc_download_instr(ahc, i, download_consts);
6037 downloaded++;
6038 }
6039
6040 ahc->num_critical_sections = cs_count;
6041 if (cs_count != 0) {
6042
6043 cs_count *= sizeof(struct cs);
6044 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6045 if (ahc->critical_sections == NULL)
6046 panic("ahc_loadseq: Could not malloc");
6047 memcpy(ahc->critical_sections, cs_table, cs_count);
6048 }
6049 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6050 ahc_restart(ahc);
6051
6052 if (bootverbose)
6053 printf(" %d instructions downloaded\n", downloaded);
6054 }
6055
6056 static int
6057 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6058 u_int start_instr, u_int *skip_addr)
6059 {
6060 struct patch *cur_patch;
6061 struct patch *last_patch;
6062 u_int num_patches;
6063
6064 num_patches = sizeof(patches)/sizeof(struct patch);
6065 last_patch = &patches[num_patches];
6066 cur_patch = *start_patch;
6067
6068 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6069
6070 if (cur_patch->patch_func(ahc) == 0) {
6071
6072 /* Start rejecting code */
6073 *skip_addr = start_instr + cur_patch->skip_instr;
6074 cur_patch += cur_patch->skip_patch;
6075 } else {
6076 /* Accepted this patch. Advance to the next
6077 * one and wait for our intruction pointer to
6078 * hit this point.
6079 */
6080 cur_patch++;
6081 }
6082 }
6083
6084 *start_patch = cur_patch;
6085 if (start_instr < *skip_addr)
6086 /* Still skipping */
6087 return (0);
6088
6089 return (1);
6090 }
6091
6092 static void
6093 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6094 {
6095 union ins_formats instr;
6096 struct ins_format1 *fmt1_ins;
6097 struct ins_format3 *fmt3_ins;
6098 u_int opcode;
6099
6100 /*
6101 * The firmware is always compiled into a little endian format.
6102 */
6103 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6104
6105 fmt1_ins = &instr.format1;
6106 fmt3_ins = NULL;
6107
6108 /* Pull the opcode */
6109 opcode = instr.format1.opcode;
6110 switch (opcode) {
6111 case AIC_OP_JMP:
6112 case AIC_OP_JC:
6113 case AIC_OP_JNC:
6114 case AIC_OP_CALL:
6115 case AIC_OP_JNE:
6116 case AIC_OP_JNZ:
6117 case AIC_OP_JE:
6118 case AIC_OP_JZ:
6119 {
6120 struct patch *cur_patch;
6121 int address_offset;
6122 u_int address;
6123 u_int skip_addr;
6124 u_int i;
6125
6126 fmt3_ins = &instr.format3;
6127 address_offset = 0;
6128 address = fmt3_ins->address;
6129 cur_patch = patches;
6130 skip_addr = 0;
6131
6132 for (i = 0; i < address;) {
6133
6134 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6135
6136 if (skip_addr > i) {
6137 int end_addr;
6138
6139 end_addr = MIN(address, skip_addr);
6140 address_offset += end_addr - i;
6141 i = skip_addr;
6142 } else {
6143 i++;
6144 }
6145 }
6146 address -= address_offset;
6147 fmt3_ins->address = address;
6148 /* FALLTHROUGH */
6149 }
6150 case AIC_OP_OR:
6151 case AIC_OP_AND:
6152 case AIC_OP_XOR:
6153 case AIC_OP_ADD:
6154 case AIC_OP_ADC:
6155 case AIC_OP_BMOV:
6156 if (fmt1_ins->parity != 0) {
6157 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6158 }
6159 fmt1_ins->parity = 0;
6160 if ((ahc->features & AHC_CMD_CHAN) == 0
6161 && opcode == AIC_OP_BMOV) {
6162 /*
6163 * Block move was added at the same time
6164 * as the command channel. Verify that
6165 * this is only a move of a single element
6166 * and convert the BMOV to a MOV
6167 * (AND with an immediate of FF).
6168 */
6169 if (fmt1_ins->immediate != 1)
6170 panic("%s: BMOV not supported\n",
6171 ahc_name(ahc));
6172 fmt1_ins->opcode = AIC_OP_AND;
6173 fmt1_ins->immediate = 0xff;
6174 }
6175 /* FALLTHROUGH */
6176 case AIC_OP_ROL:
6177 if ((ahc->features & AHC_ULTRA2) != 0) {
6178 int i, count;
6179
6180 /* Calculate odd parity for the instruction */
6181 for (i = 0, count = 0; i < 31; i++) {
6182 uint32_t mask;
6183
6184 mask = 0x01 << i;
6185 if ((instr.integer & mask) != 0)
6186 count++;
6187 }
6188 if ((count & 0x01) == 0)
6189 instr.format1.parity = 1;
6190 } else {
6191 /* Compress the instruction for older sequencers */
6192 if (fmt3_ins != NULL) {
6193 instr.integer =
6194 fmt3_ins->immediate
6195 | (fmt3_ins->source << 8)
6196 | (fmt3_ins->address << 16)
6197 | (fmt3_ins->opcode << 25);
6198 } else {
6199 instr.integer =
6200 fmt1_ins->immediate
6201 | (fmt1_ins->source << 8)
6202 | (fmt1_ins->destination << 16)
6203 | (fmt1_ins->ret << 24)
6204 | (fmt1_ins->opcode << 25);
6205 }
6206 }
6207 /* The sequencer is a little endian cpu */
6208 instr.integer = ahc_htole32(instr.integer);
6209 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6210 break;
6211 default:
6212 panic("Unknown opcode encountered in seq program");
6213 break;
6214 }
6215 }
6216
6217 void
6218 ahc_dump_card_state(struct ahc_softc *ahc)
6219 {
6220 struct scb *scb;
6221 struct scb_tailq *untagged_q;
6222 int target;
6223 int maxtarget;
6224 int i;
6225 uint8_t last_phase;
6226 uint8_t qinpos;
6227 uint8_t qintail;
6228 uint8_t qoutpos;
6229 uint8_t scb_index;
6230 uint8_t saved_scbptr;
6231
6232 saved_scbptr = ahc_inb(ahc, SCBPTR);
6233
6234 last_phase = ahc_inb(ahc, LASTPHASE);
6235 printf("%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6236 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6237 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6238 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6239 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6240 ahc_inb(ahc, ARG_2));
6241 printf("HCNT = 0x%x\n", ahc_inb(ahc, HCNT));
6242 printf("SCSISEQ = 0x%x, SBLKCTL = 0x%x\n",
6243 ahc_inb(ahc, SCSISEQ), ahc_inb(ahc, SBLKCTL));
6244 printf(" DFCNTRL = 0x%x, DFSTATUS = 0x%x\n",
6245 ahc_inb(ahc, DFCNTRL), ahc_inb(ahc, DFSTATUS));
6246 printf("LASTPHASE = 0x%x, SCSISIGI = 0x%x, SXFRCTL0 = 0x%x\n",
6247 last_phase, ahc_inb(ahc, SCSISIGI), ahc_inb(ahc, SXFRCTL0));
6248 printf("SSTAT0 = 0x%x, SSTAT1 = 0x%x\n",
6249 ahc_inb(ahc, SSTAT0), ahc_inb(ahc, SSTAT1));
6250 if ((ahc->features & AHC_DT) != 0)
6251 printf("SCSIPHASE = 0x%x\n", ahc_inb(ahc, SCSIPHASE));
6252 printf("STACK == 0x%x, 0x%x, 0x%x, 0x%x\n",
6253 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8),
6254 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8),
6255 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8),
6256 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8));
6257 printf("SCB count = %d\n", ahc->scb_data->numscbs);
6258 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6259 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6260 /* QINFIFO */
6261 printf("QINFIFO entries: ");
6262 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6263 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6264 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6265 } else
6266 qinpos = ahc_inb(ahc, QINPOS);
6267 qintail = ahc->qinfifonext;
6268 while (qinpos != qintail) {
6269 printf("%d ", ahc->qinfifo[qinpos]);
6270 qinpos++;
6271 }
6272 printf("\n");
6273
6274 printf("Waiting Queue entries: ");
6275 scb_index = ahc_inb(ahc, WAITING_SCBH);
6276 i = 0;
6277 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6278 ahc_outb(ahc, SCBPTR, scb_index);
6279 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6280 scb_index = ahc_inb(ahc, SCB_NEXT);
6281 }
6282 printf("\n");
6283
6284 printf("Disconnected Queue entries: ");
6285 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6286 i = 0;
6287 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6288 ahc_outb(ahc, SCBPTR, scb_index);
6289 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6290 scb_index = ahc_inb(ahc, SCB_NEXT);
6291 }
6292 printf("\n");
6293
6294 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6295 printf("QOUTFIFO entries: ");
6296 qoutpos = ahc->qoutfifonext;
6297 i = 0;
6298 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6299 printf("%d ", ahc->qoutfifo[qoutpos]);
6300 qoutpos++;
6301 }
6302 printf("\n");
6303
6304 printf("Sequencer Free SCB List: ");
6305 scb_index = ahc_inb(ahc, FREE_SCBH);
6306 i = 0;
6307 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6308 ahc_outb(ahc, SCBPTR, scb_index);
6309 printf("%d ", scb_index);
6310 scb_index = ahc_inb(ahc, SCB_NEXT);
6311 }
6312 printf("\n");
6313
6314 printf("Pending list: ");
6315 i = 0;
6316 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6317 if (i++ > 256)
6318 break;
6319 if (scb != LIST_FIRST(&ahc->pending_scbs))
6320 printf(", ");
6321 printf("%d", scb->hscb->tag);
6322 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6323 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6324 printf("(0x%x, 0x%x)", ahc_inb(ahc, SCB_CONTROL),
6325 ahc_inb(ahc, SCB_TAG));
6326 }
6327 }
6328 printf("\n");
6329
6330 printf("Kernel Free SCB list: ");
6331 i = 0;
6332 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6333 if (i++ > 256)
6334 break;
6335 printf("%d ", scb->hscb->tag);
6336 }
6337 printf("\n");
6338
6339 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6340 for (target = 0; target <= maxtarget; target++) {
6341 untagged_q = &ahc->untagged_queues[target];
6342 if (TAILQ_FIRST(untagged_q) == NULL)
6343 continue;
6344 printf("Untagged Q(%d): ", target);
6345 i = 0;
6346 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6347 if (i++ > 256)
6348 break;
6349 printf("%d ", scb->hscb->tag);
6350 }
6351 printf("\n");
6352 }
6353
6354 ahc_platform_dump_card_state(ahc);
6355 ahc_outb(ahc, SCBPTR, saved_scbptr);
6356 }
6357
6358 /************************* Target Mode ****************************************/
6359 #ifdef AHC_TARGET_MODE
6360 cam_status
6361 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6362 struct ahc_tmode_tstate **tstate,
6363 struct ahc_tmode_lstate **lstate,
6364 int notfound_failure)
6365 {
6366
6367 if ((ahc->features & AHC_TARGETMODE) == 0)
6368 return (CAM_REQ_INVALID);
6369
6370 /*
6371 * Handle the 'black hole' device that sucks up
6372 * requests to unattached luns on enabled targets.
6373 */
6374 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6375 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6376 *tstate = NULL;
6377 *lstate = ahc->black_hole;
6378 } else {
6379 u_int max_id;
6380
6381 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
6382 if (ccb->ccb_h.target_id > max_id)
6383 return (CAM_TID_INVALID);
6384
6385 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6386 return (CAM_LUN_INVALID);
6387
6388 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6389 *lstate = NULL;
6390 if (*tstate != NULL)
6391 *lstate =
6392 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6393 }
6394
6395 if (notfound_failure != 0 && *lstate == NULL)
6396 return (CAM_PATH_INVALID);
6397
6398 return (CAM_REQ_CMP);
6399 }
6400
6401 void
6402 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6403 {
6404 struct ahc_tmode_tstate *tstate;
6405 struct ahc_tmode_lstate *lstate;
6406 struct ccb_en_lun *cel;
6407 cam_status status;
6408 u_int target;
6409 u_int lun;
6410 u_int target_mask;
6411 u_long s;
6412 char channel;
6413
6414 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6415 /*notfound_failure*/FALSE);
6416
6417 if (status != CAM_REQ_CMP) {
6418 ccb->ccb_h.status = status;
6419 return;
6420 }
6421
6422 if ((ahc->features & AHC_MULTIROLE) != 0) {
6423 u_int our_id;
6424
6425 if (cam_sim_bus(sim) == 0)
6426 our_id = ahc->our_id;
6427 else
6428 our_id = ahc->our_id_b;
6429
6430 if (ccb->ccb_h.target_id != our_id) {
6431 if ((ahc->features & AHC_MULTI_TID) != 0
6432 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6433 /*
6434 * Only allow additional targets if
6435 * the initiator role is disabled.
6436 * The hardware cannot handle a re-select-in
6437 * on the initiator id during a re-select-out
6438 * on a different target id.
6439 */
6440 status = CAM_TID_INVALID;
6441 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6442 || ahc->enabled_luns > 0) {
6443 /*
6444 * Only allow our target id to change
6445 * if the initiator role is not configured
6446 * and there are no enabled luns which
6447 * are attached to the currently registered
6448 * scsi id.
6449 */
6450 status = CAM_TID_INVALID;
6451 }
6452 }
6453 }
6454
6455 if (status != CAM_REQ_CMP) {
6456 ccb->ccb_h.status = status;
6457 return;
6458 }
6459
6460 /*
6461 * We now have an id that is valid.
6462 * If we aren't in target mode, switch modes.
6463 */
6464 if ((ahc->flags & AHC_TARGETROLE) == 0
6465 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6466 u_long s;
6467
6468 printf("Configuring Target Mode\n");
6469 ahc_lock(ahc, &s);
6470 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6471 ccb->ccb_h.status = CAM_BUSY;
6472 ahc_unlock(ahc, &s);
6473 return;
6474 }
6475 ahc->flags |= AHC_TARGETROLE;
6476 if ((ahc->features & AHC_MULTIROLE) == 0)
6477 ahc->flags &= ~AHC_INITIATORROLE;
6478 ahc_pause(ahc);
6479 ahc_loadseq(ahc);
6480 ahc_unlock(ahc, &s);
6481 }
6482 cel = &ccb->cel;
6483 target = ccb->ccb_h.target_id;
6484 lun = ccb->ccb_h.target_lun;
6485 channel = SIM_CHANNEL(ahc, sim);
6486 target_mask = 0x01 << target;
6487 if (channel == 'B')
6488 target_mask <<= 8;
6489
6490 if (cel->enable != 0) {
6491 u_int scsiseq;
6492
6493 /* Are we already enabled?? */
6494 if (lstate != NULL) {
6495 xpt_print_path(ccb->ccb_h.path);
6496 printf("Lun already enabled\n");
6497 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6498 return;
6499 }
6500
6501 if (cel->grp6_len != 0
6502 || cel->grp7_len != 0) {
6503 /*
6504 * Don't (yet?) support vendor
6505 * specific commands.
6506 */
6507 ccb->ccb_h.status = CAM_REQ_INVALID;
6508 printf("Non-zero Group Codes\n");
6509 return;
6510 }
6511
6512 /*
6513 * Seems to be okay.
6514 * Setup our data structures.
6515 */
6516 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6517 tstate = ahc_alloc_tstate(ahc, target, channel);
6518 if (tstate == NULL) {
6519 xpt_print_path(ccb->ccb_h.path);
6520 printf("Couldn't allocate tstate\n");
6521 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6522 return;
6523 }
6524 }
6525 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
6526 if (lstate == NULL) {
6527 xpt_print_path(ccb->ccb_h.path);
6528 printf("Couldn't allocate lstate\n");
6529 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6530 return;
6531 }
6532 memset(lstate, 0, sizeof(*lstate));
6533 status = xpt_create_path(&lstate->path, /*periph*/NULL,
6534 xpt_path_path_id(ccb->ccb_h.path),
6535 xpt_path_target_id(ccb->ccb_h.path),
6536 xpt_path_lun_id(ccb->ccb_h.path));
6537 if (status != CAM_REQ_CMP) {
6538 free(lstate, M_DEVBUF);
6539 xpt_print_path(ccb->ccb_h.path);
6540 printf("Couldn't allocate path\n");
6541 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6542 return;
6543 }
6544 SLIST_INIT(&lstate->accept_tios);
6545 SLIST_INIT(&lstate->immed_notifies);
6546 ahc_lock(ahc, &s);
6547 ahc_pause(ahc);
6548 if (target != CAM_TARGET_WILDCARD) {
6549 tstate->enabled_luns[lun] = lstate;
6550 ahc->enabled_luns++;
6551
6552 if ((ahc->features & AHC_MULTI_TID) != 0) {
6553 u_int targid_mask;
6554
6555 targid_mask = ahc_inb(ahc, TARGID)
6556 | (ahc_inb(ahc, TARGID + 1) << 8);
6557
6558 targid_mask |= target_mask;
6559 ahc_outb(ahc, TARGID, targid_mask);
6560 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
6561
6562 ahc_update_scsiid(ahc, targid_mask);
6563 } else {
6564 u_int our_id;
6565 char channel;
6566
6567 channel = SIM_CHANNEL(ahc, sim);
6568 our_id = SIM_SCSI_ID(ahc, sim);
6569
6570 /*
6571 * This can only happen if selections
6572 * are not enabled
6573 */
6574 if (target != our_id) {
6575 u_int sblkctl;
6576 char cur_channel;
6577 int swap;
6578
6579 sblkctl = ahc_inb(ahc, SBLKCTL);
6580 cur_channel = (sblkctl & SELBUSB)
6581 ? 'B' : 'A';
6582 if ((ahc->features & AHC_TWIN) == 0)
6583 cur_channel = 'A';
6584 swap = cur_channel != channel;
6585 if (channel == 'A')
6586 ahc->our_id = target;
6587 else
6588 ahc->our_id_b = target;
6589
6590 if (swap)
6591 ahc_outb(ahc, SBLKCTL,
6592 sblkctl ^ SELBUSB);
6593
6594 ahc_outb(ahc, SCSIID, target);
6595
6596 if (swap)
6597 ahc_outb(ahc, SBLKCTL, sblkctl);
6598 }
6599 }
6600 } else
6601 ahc->black_hole = lstate;
6602 /* Allow select-in operations */
6603 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
6604 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6605 scsiseq |= ENSELI;
6606 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
6607 scsiseq = ahc_inb(ahc, SCSISEQ);
6608 scsiseq |= ENSELI;
6609 ahc_outb(ahc, SCSISEQ, scsiseq);
6610 }
6611 ahc_unpause(ahc);
6612 ahc_unlock(ahc, &s);
6613 ccb->ccb_h.status = CAM_REQ_CMP;
6614 xpt_print_path(ccb->ccb_h.path);
6615 printf("Lun now enabled for target mode\n");
6616 } else {
6617 struct scb *scb;
6618 int i, empty;
6619
6620 if (lstate == NULL) {
6621 ccb->ccb_h.status = CAM_LUN_INVALID;
6622 return;
6623 }
6624
6625 ahc_lock(ahc, &s);
6626
6627 ccb->ccb_h.status = CAM_REQ_CMP;
6628 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6629 struct ccb_hdr *ccbh;
6630
6631 ccbh = &scb->io_ctx->ccb_h;
6632 if (ccbh->func_code == XPT_CONT_TARGET_IO
6633 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
6634 printf("CTIO pending\n");
6635 ccb->ccb_h.status = CAM_REQ_INVALID;
6636 ahc_unlock(ahc, &s);
6637 return;
6638 }
6639 }
6640
6641 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
6642 printf("ATIOs pending\n");
6643 ccb->ccb_h.status = CAM_REQ_INVALID;
6644 }
6645
6646 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
6647 printf("INOTs pending\n");
6648 ccb->ccb_h.status = CAM_REQ_INVALID;
6649 }
6650
6651 if (ccb->ccb_h.status != CAM_REQ_CMP) {
6652 ahc_unlock(ahc, &s);
6653 return;
6654 }
6655
6656 xpt_print_path(ccb->ccb_h.path);
6657 printf("Target mode disabled\n");
6658 xpt_free_path(lstate->path);
6659 free(lstate, M_DEVBUF);
6660
6661 ahc_pause(ahc);
6662 /* Can we clean up the target too? */
6663 if (target != CAM_TARGET_WILDCARD) {
6664 tstate->enabled_luns[lun] = NULL;
6665 ahc->enabled_luns--;
6666 for (empty = 1, i = 0; i < 8; i++)
6667 if (tstate->enabled_luns[i] != NULL) {
6668 empty = 0;
6669 break;
6670 }
6671
6672 if (empty) {
6673 ahc_free_tstate(ahc, target, channel,
6674 /*force*/FALSE);
6675 if (ahc->features & AHC_MULTI_TID) {
6676 u_int targid_mask;
6677
6678 targid_mask = ahc_inb(ahc, TARGID)
6679 | (ahc_inb(ahc, TARGID + 1)
6680 << 8);
6681
6682 targid_mask &= ~target_mask;
6683 ahc_outb(ahc, TARGID, targid_mask);
6684 ahc_outb(ahc, TARGID+1,
6685 (targid_mask >> 8));
6686 ahc_update_scsiid(ahc, targid_mask);
6687 }
6688 }
6689 } else {
6690
6691 ahc->black_hole = NULL;
6692
6693 /*
6694 * We can't allow selections without
6695 * our black hole device.
6696 */
6697 empty = TRUE;
6698 }
6699 if (ahc->enabled_luns == 0) {
6700 /* Disallow select-in */
6701 u_int scsiseq;
6702
6703 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6704 scsiseq &= ~ENSELI;
6705 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
6706 scsiseq = ahc_inb(ahc, SCSISEQ);
6707 scsiseq &= ~ENSELI;
6708 ahc_outb(ahc, SCSISEQ, scsiseq);
6709
6710 if ((ahc->features & AHC_MULTIROLE) == 0) {
6711 printf("Configuring Initiator Mode\n");
6712 ahc->flags &= ~AHC_TARGETROLE;
6713 ahc->flags |= AHC_INITIATORROLE;
6714 ahc_pause(ahc);
6715 ahc_loadseq(ahc);
6716 }
6717 }
6718 ahc_unpause(ahc);
6719 ahc_unlock(ahc, &s);
6720 }
6721 }
6722
6723 static void
6724 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
6725 {
6726 u_int scsiid_mask;
6727 u_int scsiid;
6728
6729 if ((ahc->features & AHC_MULTI_TID) == 0)
6730 panic("ahc_update_scsiid called on non-multitid unit\n");
6731
6732 /*
6733 * Since we will rely on the the TARGID mask
6734 * for selection enables, ensure that OID
6735 * in SCSIID is not set to some other ID
6736 * that we don't want to allow selections on.
6737 */
6738 if ((ahc->features & AHC_ULTRA2) != 0)
6739 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
6740 else
6741 scsiid = ahc_inb(ahc, SCSIID);
6742 scsiid_mask = 0x1 << (scsiid & OID);
6743 if ((targid_mask & scsiid_mask) == 0) {
6744 u_int our_id;
6745
6746 /* ffs counts from 1 */
6747 our_id = ffs(targid_mask);
6748 if (our_id == 0)
6749 our_id = ahc->our_id;
6750 else
6751 our_id--;
6752 scsiid &= TID;
6753 scsiid |= our_id;
6754 }
6755 if ((ahc->features & AHC_ULTRA2) != 0)
6756 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
6757 else
6758 ahc_outb(ahc, SCSIID, scsiid);
6759 }
6760
6761 void
6762 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
6763 {
6764 struct target_cmd *cmd;
6765
6766 /*
6767 * If the card supports auto-access pause,
6768 * we can access the card directly regardless
6769 * of whether it is paused or not.
6770 */
6771 if ((ahc->features & AHC_AUTOPAUSE) != 0)
6772 paused = TRUE;
6773
6774 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
6775 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
6776
6777 /*
6778 * Only advance through the queue if we
6779 * have the resources to process the command.
6780 */
6781 if (ahc_handle_target_cmd(ahc, cmd) != 0)
6782 break;
6783
6784 cmd->cmd_valid = 0;
6785 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
6786 ahc->shared_data_dmamap,
6787 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
6788 sizeof(struct target_cmd),
6789 BUS_DMASYNC_PREREAD);
6790 ahc->tqinfifonext++;
6791
6792 /*
6793 * Lazily update our position in the target mode incoming
6794 * command queue as seen by the sequencer.
6795 */
6796 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
6797 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
6798 u_int hs_mailbox;
6799
6800 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
6801 hs_mailbox &= ~HOST_TQINPOS;
6802 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
6803 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
6804 } else {
6805 if (!paused)
6806 ahc_pause(ahc);
6807 ahc_outb(ahc, KERNEL_TQINPOS,
6808 ahc->tqinfifonext & HOST_TQINPOS);
6809 if (!paused)
6810 ahc_unpause(ahc);
6811 }
6812 }
6813 }
6814 }
6815
6816 static int
6817 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
6818 {
6819 struct ahc_tmode_tstate *tstate;
6820 struct ahc_tmode_lstate *lstate;
6821 struct ccb_accept_tio *atio;
6822 uint8_t *byte;
6823 int initiator;
6824 int target;
6825 int lun;
6826
6827 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
6828 target = SCSIID_OUR_ID(cmd->scsiid);
6829 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
6830
6831 byte = cmd->bytes;
6832 tstate = ahc->enabled_targets[target];
6833 lstate = NULL;
6834 if (tstate != NULL)
6835 lstate = tstate->enabled_luns[lun];
6836
6837 /*
6838 * Commands for disabled luns go to the black hole driver.
6839 */
6840 if (lstate == NULL)
6841 lstate = ahc->black_hole;
6842
6843 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
6844 if (atio == NULL) {
6845 ahc->flags |= AHC_TQINFIFO_BLOCKED;
6846 /*
6847 * Wait for more ATIOs from the peripheral driver for this lun.
6848 */
6849 return (1);
6850 } else
6851 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
6852 #if 0
6853 printf("Incoming command from %d for %d:%d%s\n",
6854 initiator, target, lun,
6855 lstate == ahc->black_hole ? "(Black Holed)" : "");
6856 #endif
6857 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
6858
6859 if (lstate == ahc->black_hole) {
6860 /* Fill in the wildcards */
6861 atio->ccb_h.target_id = target;
6862 atio->ccb_h.target_lun = lun;
6863 }
6864
6865 /*
6866 * Package it up and send it off to
6867 * whomever has this lun enabled.
6868 */
6869 atio->sense_len = 0;
6870 atio->init_id = initiator;
6871 if (byte[0] != 0xFF) {
6872 /* Tag was included */
6873 atio->tag_action = *byte++;
6874 atio->tag_id = *byte++;
6875 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
6876 } else {
6877 atio->ccb_h.flags = 0;
6878 }
6879 byte++;
6880
6881 /* Okay. Now determine the cdb size based on the command code */
6882 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
6883 case 0:
6884 atio->cdb_len = 6;
6885 break;
6886 case 1:
6887 case 2:
6888 atio->cdb_len = 10;
6889 break;
6890 case 4:
6891 atio->cdb_len = 16;
6892 break;
6893 case 5:
6894 atio->cdb_len = 12;
6895 break;
6896 case 3:
6897 default:
6898 /* Only copy the opcode. */
6899 atio->cdb_len = 1;
6900 printf("Reserved or VU command code type encountered\n");
6901 break;
6902 }
6903
6904 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
6905
6906 atio->ccb_h.status |= CAM_CDB_RECVD;
6907
6908 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
6909 /*
6910 * We weren't allowed to disconnect.
6911 * We're hanging on the bus until a
6912 * continue target I/O comes in response
6913 * to this accept tio.
6914 */
6915 #if 0
6916 printf("Received Immediate Command %d:%d:%d - %p\n",
6917 initiator, target, lun, ahc->pending_device);
6918 #endif
6919 ahc->pending_device = lstate;
6920 ahc_freeze_ccb((union ccb *)atio);
6921 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
6922 }
6923 xpt_done((union ccb*)atio);
6924 return (0);
6925 }
6926
6927 #endif
6928