File: /usr/src/linux/drivers/scsi/cyberstorm.c
1 /* cyberstorm.c: Driver for CyberStorm SCSI Controller.
2 *
3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
4 *
5 * The CyberStorm SCSI driver is based on David S. Miller's ESP driver
6 * for the Sparc computers.
7 *
8 * This work was made possible by Phase5 who willingly (and most generously)
9 * supported me with hardware and all the information I needed.
10 */
11
12 /* TODO:
13 *
14 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
15 * to the caches and the Sparc MMU mapping.
16 * 2) Make as few routines required outside the generic driver. A lot of the
17 * routines in this file used to be inline!
18 */
19
20 #include <linux/module.h>
21
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/blk.h>
29 #include <linux/proc_fs.h>
30 #include <linux/stat.h>
31
32 #include "scsi.h"
33 #include "hosts.h"
34 #include "NCR53C9x.h"
35 #include "cyberstorm.h"
36
37 #include <linux/zorro.h>
38 #include <asm/irq.h>
39 #include <asm/amigaints.h>
40 #include <asm/amigahw.h>
41
42 #include <asm/pgtable.h>
43
44 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
45 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
46 static void dma_dump_state(struct NCR_ESP *esp);
47 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
48 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
49 static void dma_ints_off(struct NCR_ESP *esp);
50 static void dma_ints_on(struct NCR_ESP *esp);
51 static int dma_irq_p(struct NCR_ESP *esp);
52 static void dma_led_off(struct NCR_ESP *esp);
53 static void dma_led_on(struct NCR_ESP *esp);
54 static int dma_ports_p(struct NCR_ESP *esp);
55 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
56
57 static unsigned char ctrl_data = 0; /* Keep backup of the stuff written
58 * to ctrl_reg. Always write a copy
59 * to this register when writing to
60 * the hardware register!
61 */
62
63 volatile unsigned char cmd_buffer[16];
64 /* This is where all commands are put
65 * before they are transferred to the ESP chip
66 * via PIO.
67 */
68
69 /***************************************************************** Detection */
70 int __init cyber_esp_detect(Scsi_Host_Template *tpnt)
71 {
72 struct NCR_ESP *esp;
73 struct zorro_dev *z = NULL;
74 unsigned long address;
75
76 while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
77 unsigned long board = z->resource.start;
78 if ((z->id == ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM ||
79 z->id == ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060) &&
80 request_mem_region(board+CYBER_ESP_ADDR,
81 sizeof(struct ESP_regs), "NCR53C9x")) {
82 /* Figure out if this is a CyberStorm or really a
83 * Fastlane/Blizzard Mk II by looking at the board size.
84 * CyberStorm maps 64kB
85 * (ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM does anyway)
86 */
87 if(z->resource.end-board != 0xffff) {
88 release_mem_region(board+CYBER_ESP_ADDR,
89 sizeof(struct ESP_regs));
90 return 0;
91 }
92 esp = esp_allocate(tpnt, (void *)board+CYBER_ESP_ADDR);
93
94 /* Do command transfer with programmed I/O */
95 esp->do_pio_cmds = 1;
96
97 /* Required functions */
98 esp->dma_bytes_sent = &dma_bytes_sent;
99 esp->dma_can_transfer = &dma_can_transfer;
100 esp->dma_dump_state = &dma_dump_state;
101 esp->dma_init_read = &dma_init_read;
102 esp->dma_init_write = &dma_init_write;
103 esp->dma_ints_off = &dma_ints_off;
104 esp->dma_ints_on = &dma_ints_on;
105 esp->dma_irq_p = &dma_irq_p;
106 esp->dma_ports_p = &dma_ports_p;
107 esp->dma_setup = &dma_setup;
108
109 /* Optional functions */
110 esp->dma_barrier = 0;
111 esp->dma_drain = 0;
112 esp->dma_invalidate = 0;
113 esp->dma_irq_entry = 0;
114 esp->dma_irq_exit = 0;
115 esp->dma_led_on = &dma_led_on;
116 esp->dma_led_off = &dma_led_off;
117 esp->dma_poll = 0;
118 esp->dma_reset = 0;
119
120 /* SCSI chip speed */
121 esp->cfreq = 40000000;
122
123 /* The DMA registers on the CyberStorm are mapped
124 * relative to the device (i.e. in the same Zorro
125 * I/O block).
126 */
127 address = (unsigned long)ZTWO_VADDR(board);
128 esp->dregs = (void *)(address + CYBER_DMA_ADDR);
129
130 /* ESP register base */
131 esp->eregs = (struct ESP_regs *)(address + CYBER_ESP_ADDR);
132
133 /* Set the command buffer */
134 esp->esp_command = (volatile unsigned char*) cmd_buffer;
135 esp->esp_command_dvma = virt_to_bus(cmd_buffer);
136
137 esp->irq = IRQ_AMIGA_PORTS;
138 request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
139 "CyberStorm SCSI", esp_intr);
140 /* Figure out our scsi ID on the bus */
141 /* The DMA cond flag contains a hardcoded jumper bit
142 * which can be used to select host number 6 or 7.
143 * However, even though it may change, we use a hardcoded
144 * value of 7.
145 */
146 esp->scsi_id = 7;
147
148 /* We don't have a differential SCSI-bus. */
149 esp->diff = 0;
150
151 esp_initialize(esp);
152
153 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
154 esps_running = esps_in_use;
155 return esps_in_use;
156 }
157 }
158 return 0;
159 }
160
161 /************************************************************* DMA Functions */
162 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
163 {
164 /* Since the CyberStorm DMA is fully dedicated to the ESP chip,
165 * the number of bytes sent (to the ESP chip) equals the number
166 * of bytes in the FIFO - there is no buffering in the DMA controller.
167 * XXXX Do I read this right? It is from host to ESP, right?
168 */
169 return fifo_count;
170 }
171
172 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
173 {
174 /* I don't think there's any limit on the CyberDMA. So we use what
175 * the ESP chip can handle (24 bit).
176 */
177 unsigned long sz = sp->SCp.this_residual;
178 if(sz > 0x1000000)
179 sz = 0x1000000;
180 return sz;
181 }
182
183 static void dma_dump_state(struct NCR_ESP *esp)
184 {
185 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
186 esp->esp_id, ((struct cyber_dma_registers *)
187 (esp->dregs))->cond_reg));
188 ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
189 custom.intreqr, custom.intenar));
190 }
191
192 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
193 {
194 struct cyber_dma_registers *dregs =
195 (struct cyber_dma_registers *) esp->dregs;
196
197 cache_clear(addr, length);
198
199 addr &= ~(1);
200 dregs->dma_addr0 = (addr >> 24) & 0xff;
201 dregs->dma_addr1 = (addr >> 16) & 0xff;
202 dregs->dma_addr2 = (addr >> 8) & 0xff;
203 dregs->dma_addr3 = (addr ) & 0xff;
204 ctrl_data &= ~(CYBER_DMA_WRITE);
205
206 /* Check if physical address is outside Z2 space and of
207 * block length/block aligned in memory. If this is the
208 * case, enable 32 bit transfer. In all other cases, fall back
209 * to 16 bit transfer.
210 * Obviously 32 bit transfer should be enabled if the DMA address
211 * and length are 32 bit aligned. However, this leads to some
212 * strange behavior. Even 64 bit aligned addr/length fails.
213 * Until I've found a reason for this, 32 bit transfer is only
214 * used for full-block transfers (1kB).
215 * -jskov
216 */
217 #if 0
218 if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
219 (addr < 0xff0000)))
220 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
221 else
222 ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
223 #else
224 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
225 #endif
226 dregs->ctrl_reg = ctrl_data;
227 }
228
229 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
230 {
231 struct cyber_dma_registers *dregs =
232 (struct cyber_dma_registers *) esp->dregs;
233
234 cache_push(addr, length);
235
236 addr |= 1;
237 dregs->dma_addr0 = (addr >> 24) & 0xff;
238 dregs->dma_addr1 = (addr >> 16) & 0xff;
239 dregs->dma_addr2 = (addr >> 8) & 0xff;
240 dregs->dma_addr3 = (addr ) & 0xff;
241 ctrl_data |= CYBER_DMA_WRITE;
242
243 /* See comment above */
244 #if 0
245 if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
246 (addr < 0xff0000)))
247 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
248 else
249 ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
250 #else
251 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
252 #endif
253 dregs->ctrl_reg = ctrl_data;
254 }
255
256 static void dma_ints_off(struct NCR_ESP *esp)
257 {
258 disable_irq(esp->irq);
259 }
260
261 static void dma_ints_on(struct NCR_ESP *esp)
262 {
263 enable_irq(esp->irq);
264 }
265
266 static int dma_irq_p(struct NCR_ESP *esp)
267 {
268 /* It's important to check the DMA IRQ bit in the correct way! */
269 return ((esp_read(esp->eregs->esp_status) & ESP_STAT_INTR) &&
270 ((((struct cyber_dma_registers *)(esp->dregs))->cond_reg) &
271 CYBER_DMA_HNDL_INTR));
272 }
273
274 static void dma_led_off(struct NCR_ESP *esp)
275 {
276 ctrl_data &= ~CYBER_DMA_LED;
277 ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
278 }
279
280 static void dma_led_on(struct NCR_ESP *esp)
281 {
282 ctrl_data |= CYBER_DMA_LED;
283 ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
284 }
285
286 static int dma_ports_p(struct NCR_ESP *esp)
287 {
288 return ((custom.intenar) & IF_PORTS);
289 }
290
291 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
292 {
293 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
294 * so when (write) is true, it actually means READ!
295 */
296 if(write){
297 dma_init_read(esp, addr, count);
298 } else {
299 dma_init_write(esp, addr, count);
300 }
301 }
302
303 #define HOSTS_C
304
305 #include "cyberstorm.h"
306
307 static Scsi_Host_Template driver_template = SCSI_CYBERSTORM;
308
309 #include "scsi_module.c"
310
311 int cyber_esp_release(struct Scsi_Host *instance)
312 {
313 #ifdef MODULE
314 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
315
316 esp_deallocate((struct NCR_ESP *)instance->hostdata);
317 esp_release();
318 release_mem_region(address, sizeof(struct ESP_regs));
319 free_irq(IRQ_AMIGA_PORTS, esp_intr);
320 #endif
321 return 1;
322 }
323