File: /usr/src/linux/drivers/scsi/eata_dma.c
1 /************************************************************
2 * *
3 * Linux EATA SCSI driver *
4 * *
5 * based on the CAM document CAM/89-004 rev. 2.0c, *
6 * DPT's driver kit, some internal documents and source, *
7 * and several other Linux scsi drivers and kernel docs. *
8 * *
9 * The driver currently: *
10 * -supports all ISA based EATA-DMA boards *
11 * like PM2011, PM2021, PM2041, PM3021 *
12 * -supports all EISA based EATA-DMA boards *
13 * like PM2012B, PM2022, PM2122, PM2322, PM2042, *
14 * PM3122, PM3222, PM3332 *
15 * -supports all PCI based EATA-DMA boards *
16 * like PM2024, PM2124, PM2044, PM2144, PM3224, *
17 * PM3334 *
18 * -supports the Wide, Ultra Wide and Differential *
19 * versions of the boards *
20 * -supports multiple HBAs with & without IRQ sharing *
21 * -supports all SCSI channels on multi channel boards *
22 * -supports ix86 and MIPS, untested on ALPHA *
23 * -needs identical IDs on all channels of a HBA *
24 * -can be loaded as module *
25 * -displays statistical and hardware information *
26 * in /proc/scsi/eata_dma *
27 * -provides rudimentary latency measurement *
28 * possibilities via /proc/scsi/eata_dma/<hostnum> *
29 * *
30 * (c)1993-96 Michael Neuffer *
31 * mike@i-Connect.Net *
32 * neuffer@mail.uni-mainz.de *
33 * *
34 * This program is free software; you can redistribute it *
35 * and/or modify it under the terms of the GNU General *
36 * Public License as published by the Free Software *
37 * Foundation; either version 2 of the License, or *
38 * (at your option) any later version. *
39 * *
40 * This program is distributed in the hope that it will be *
41 * useful, but WITHOUT ANY WARRANTY; without even the *
42 * implied warranty of MERCHANTABILITY or FITNESS FOR A *
43 * PARTICULAR PURPOSE. See the GNU General Public License *
44 * for more details. *
45 * *
46 * You should have received a copy of the GNU General *
47 * Public License along with this kernel; if not, write to *
48 * the Free Software Foundation, Inc., 675 Mass Ave, *
49 * Cambridge, MA 02139, USA. *
50 * *
51 * I have to thank DPT for their excellent support. I took *
52 * me almost a year and a stopover at their HQ, on my first *
53 * trip to the USA, to get it, but since then they've been *
54 * very helpful and tried to give me all the infos and *
55 * support I need. *
56 * *
57 * Thanks also to Simon Shapiro, Greg Hosler and Mike *
58 * Jagdis who did a lot of testing and found quite a number *
59 * of bugs during the development. *
60 ************************************************************
61 * last change: 96/10/21 OS: Linux 2.0.23 *
62 ************************************************************/
63
64 /* Look in eata_dma.h for configuration and revision information */
65
66 #include <linux/module.h>
67 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/string.h>
70 #include <linux/ioport.h>
71 #include <linux/slab.h>
72 #include <linux/in.h>
73 #include <linux/pci.h>
74 #include <linux/proc_fs.h>
75 #include <linux/delay.h>
76 #include <asm/byteorder.h>
77 #include <asm/types.h>
78 #include <asm/io.h>
79 #include <asm/dma.h>
80 #include <asm/pgtable.h>
81 #ifdef __mips__
82 #include <asm/cachectl.h>
83 #include <linux/spinlock.h>
84 #endif
85 #include <linux/blk.h>
86 #include "scsi.h"
87 #include "sd.h"
88 #include "hosts.h"
89 #include "eata_dma.h"
90 #include "eata_dma_proc.h"
91
92 #include <linux/stat.h>
93 #include <linux/config.h> /* for CONFIG_PCI */
94
95 static u32 ISAbases[] =
96 {0x1F0, 0x170, 0x330, 0x230};
97 static unchar EISAbases[] =
98 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
99 static uint registered_HBAs = 0;
100 static struct Scsi_Host *last_HBA = NULL;
101 static struct Scsi_Host *first_HBA = NULL;
102 static unchar reg_IRQ[] =
103 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
104 static unchar reg_IRQL[] =
105 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
106 static struct eata_sp *status = 0; /* Statuspacket array */
107 static void *dma_scratch = 0;
108
109 static struct eata_register *fake_int_base;
110 static int fake_int_result;
111 static int fake_int_happened;
112
113 static ulong int_counter = 0;
114 static ulong queue_counter = 0;
115
116 void eata_fake_int_handler(s32 irq, void *dev_id, struct pt_regs * regs)
117 {
118 fake_int_result = inb((ulong)fake_int_base + HA_RSTATUS);
119 fake_int_happened = TRUE;
120 DBG(DBG_INTR3, printk("eata_fake_int_handler called irq%d base %p"
121 " res %#x\n", irq, fake_int_base, fake_int_result));
122 return;
123 }
124
125 #include "eata_dma_proc.c"
126
127 #ifdef MODULE
128 int eata_release(struct Scsi_Host *sh)
129 {
130 uint i;
131 if (sh->irq && reg_IRQ[sh->irq] == 1) free_irq(sh->irq, NULL);
132 else reg_IRQ[sh->irq]--;
133
134 kfree((void *)status);
135 kfree((void *)dma_scratch - 4);
136 for (i = 0; i < sh->can_queue; i++){ /* Free all SG arrays */
137 if(SD(sh)->ccb[i].sg_list != NULL)
138 kfree((void *) SD(sh)->ccb[i].sg_list);
139 }
140
141 if (SD(sh)->channel == 0) {
142 if (sh->dma_channel != BUSMASTER) free_dma(sh->dma_channel);
143 if (sh->io_port && sh->n_io_port)
144 release_region(sh->io_port, sh->n_io_port);
145 }
146 return(TRUE);
147 }
148 #endif
149
150
151 inline void eata_latency_in(struct eata_ccb *cp, hostdata *hd)
152 {
153 uint time;
154 time = jiffies - cp->timestamp;
155 if(hd->all_lat[1] > time)
156 hd->all_lat[1] = time;
157 if(hd->all_lat[2] < time)
158 hd->all_lat[2] = time;
159 hd->all_lat[3] += time;
160 hd->all_lat[0]++;
161 if((cp->rw_latency) == WRITE) { /* was WRITE */
162 if(hd->writes_lat[cp->sizeindex][1] > time)
163 hd->writes_lat[cp->sizeindex][1] = time;
164 if(hd->writes_lat[cp->sizeindex][2] < time)
165 hd->writes_lat[cp->sizeindex][2] = time;
166 hd->writes_lat[cp->sizeindex][3] += time;
167 hd->writes_lat[cp->sizeindex][0]++;
168 } else if((cp->rw_latency) == READ) {
169 if(hd->reads_lat[cp->sizeindex][1] > time)
170 hd->reads_lat[cp->sizeindex][1] = time;
171 if(hd->reads_lat[cp->sizeindex][2] < time)
172 hd->reads_lat[cp->sizeindex][2] = time;
173 hd->reads_lat[cp->sizeindex][3] += time;
174 hd->reads_lat[cp->sizeindex][0]++;
175 }
176 }
177
178 inline void eata_latency_out(struct eata_ccb *cp, Scsi_Cmnd *cmd)
179 {
180 int x, z;
181 short *sho;
182 long *lon;
183 x = 0; /* just to keep GCC quiet */
184 cp->timestamp = jiffies; /* For latency measurements */
185 switch(cmd->cmnd[0]) {
186 case WRITE_6:
187 x = cmd->cmnd[4]/2;
188 cp->rw_latency = WRITE;
189 break;
190 case READ_6:
191 x = cmd->cmnd[4]/2;
192 cp->rw_latency = READ;
193 break;
194 case WRITE_10:
195 sho = (short *) &cmd->cmnd[7];
196 x = ntohs(*sho)/2;
197 cp->rw_latency = WRITE;
198 break;
199 case READ_10:
200 sho = (short *) &cmd->cmnd[7];
201 x = ntohs(*sho)/2;
202 cp->rw_latency = READ;
203 break;
204 case WRITE_12:
205 lon = (long *) &cmd->cmnd[6];
206 x = ntohl(*lon)/2;
207 cp->rw_latency = WRITE;
208 break;
209 case READ_12:
210 lon = (long *) &cmd->cmnd[6];
211 x = ntohl(*lon)/2;
212 cp->rw_latency = READ;
213 break;
214 default:
215 cp->rw_latency = OTHER;
216 break;
217 }
218 if (cmd->cmnd[0] == WRITE_6 || cmd->cmnd[0] == WRITE_10 ||
219 cmd->cmnd[0] == WRITE_12 || cmd->cmnd[0] == READ_6 ||
220 cmd->cmnd[0] == READ_10 || cmd->cmnd[0] == READ_12) {
221 for(z = 0; (x > (1 << z)) && (z <= 11); z++)
222 /* nothing */;
223 cp->sizeindex = z;
224 }
225 }
226
227 void eata_int_handler(int, void *, struct pt_regs *);
228
229 void do_eata_int_handler(int irq, void *dev_id, struct pt_regs * regs)
230 {
231 unsigned long flags;
232
233 spin_lock_irqsave(&io_request_lock, flags);
234 eata_int_handler(irq, dev_id, regs);
235 spin_unlock_irqrestore(&io_request_lock, flags);
236 }
237
238 void eata_int_handler(int irq, void *dev_id, struct pt_regs * regs)
239 {
240 uint i, result = 0;
241 uint hba_stat, scsi_stat, eata_stat;
242 Scsi_Cmnd *cmd;
243 struct eata_ccb *ccb;
244 struct eata_sp *sp;
245 uint base;
246 uint x;
247 struct Scsi_Host *sh;
248
249 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
250 if (sh->irq != irq)
251 continue;
252
253 while(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
254
255 int_counter++;
256
257 sp = &SD(sh)->sp;
258 #ifdef __mips__
259 sys_cacheflush(sp, sizeof(struct eata_sp), 2);
260 #endif
261 ccb = sp->ccb;
262
263 if(ccb == NULL) {
264 eata_stat = inb((uint)sh->base + HA_RSTATUS);
265 printk("eata_dma: int_handler, Spurious IRQ %d "
266 "received. CCB pointer not set.\n", irq);
267 break;
268 }
269
270 cmd = ccb->cmd;
271 base = (uint) cmd->host->base;
272 hba_stat = sp->hba_stat;
273
274 scsi_stat = (sp->scsi_stat >> 1) & 0x1f;
275
276 if (sp->EOC == FALSE) {
277 eata_stat = inb(base + HA_RSTATUS);
278 printk(KERN_WARNING "eata_dma: int_handler, board: %x cmd %lx "
279 "returned unfinished.\n"
280 "EATA: %x HBA: %x SCSI: %x spadr %lx spadrirq %lx, "
281 "irq%d\n", base, (long)ccb, eata_stat, hba_stat,
282 scsi_stat,(long)&status, (long)&status[irq], irq);
283 cmd->result = DID_ERROR << 16;
284 ccb->status = FREE;
285 cmd->scsi_done(cmd);
286 break;
287 }
288
289 sp->EOC = FALSE; /* Clean out this flag */
290
291 if (ccb->status == LOCKED || ccb->status == RESET) {
292 printk("eata_dma: int_handler, reseted command pid %ld returned"
293 "\n", cmd->pid);
294 DBG(DBG_INTR && DBG_DELAY, DELAY(1));
295 }
296
297 eata_stat = inb(base + HA_RSTATUS);
298 DBG(DBG_INTR, printk("IRQ %d received, base %#.4x, pid %ld, "
299 "target: %x, lun: %x, ea_s: %#.2x, hba_s: "
300 "%#.2x \n", irq, base, cmd->pid, cmd->target,
301 cmd->lun, eata_stat, hba_stat));
302
303 switch (hba_stat) {
304 case HA_NO_ERROR: /* NO Error */
305 if(HD(cmd)->do_latency == TRUE && ccb->timestamp)
306 eata_latency_in(ccb, HD(cmd));
307 result = DID_OK << 16;
308 break;
309 case HA_ERR_SEL_TO: /* Selection Timeout */
310 case HA_ERR_CMD_TO: /* Command Timeout */
311 result = DID_TIME_OUT << 16;
312 break;
313 case HA_BUS_RESET: /* SCSI Bus Reset Received */
314 result = DID_RESET << 16;
315 DBG(DBG_STATUS, printk(KERN_WARNING "scsi%d: BUS RESET "
316 "received on cmd %ld\n",
317 HD(cmd)->HBA_number, cmd->pid));
318 break;
319 case HA_INIT_POWERUP: /* Initial Controller Power-up */
320 if (cmd->device->type != TYPE_TAPE)
321 result = DID_BUS_BUSY << 16;
322 else
323 result = DID_ERROR << 16;
324
325 for (i = 0; i < MAXTARGET; i++)
326 DBG(DBG_STATUS, printk(KERN_DEBUG "scsi%d: cmd pid %ld "
327 "returned with INIT_POWERUP\n",
328 HD(cmd)->HBA_number, cmd->pid));
329 break;
330 case HA_CP_ABORT_NA:
331 case HA_CP_ABORTED:
332 result = DID_ABORT << 16;
333 DBG(DBG_STATUS, printk(KERN_WARNING "scsi%d: aborted cmd "
334 "returned\n", HD(cmd)->HBA_number));
335 break;
336 case HA_CP_RESET_NA:
337 case HA_CP_RESET:
338 HD(cmd)->resetlevel[cmd->channel] = 0;
339 result = DID_RESET << 16;
340 DBG(DBG_STATUS, printk(KERN_WARNING "scsi%d: reseted cmd "
341 "pid %ldreturned\n",
342 HD(cmd)->HBA_number, cmd->pid));
343 case HA_SCSI_HUNG: /* SCSI Hung */
344 printk(KERN_ERR "scsi%d: SCSI hung\n", HD(cmd)->HBA_number);
345 result = DID_ERROR << 16;
346 break;
347 case HA_RSENSE_FAIL: /* Auto Request-Sense Failed */
348 DBG(DBG_STATUS, printk(KERN_ERR "scsi%d: Auto Request Sense "
349 "Failed\n", HD(cmd)->HBA_number));
350 result = DID_ERROR << 16;
351 break;
352 case HA_UNX_BUSPHASE: /* Unexpected Bus Phase */
353 case HA_UNX_BUS_FREE: /* Unexpected Bus Free */
354 case HA_BUS_PARITY: /* Bus Parity Error */
355 case HA_UNX_MSGRJCT: /* Unexpected Message Reject */
356 case HA_RESET_STUCK: /* SCSI Bus Reset Stuck */
357 case HA_PARITY_ERR: /* Controller Ram Parity */
358 default:
359 result = DID_ERROR << 16;
360 break;
361 }
362 cmd->result = result | (scsi_stat << 1);
363
364 #if DBG_INTR2
365 if (scsi_stat || result || hba_stat || eata_stat != 0x50
366 || cmd->scsi_done == NULL || cmd->device->id == 7)
367 printk("HBA: %d, channel %d, id: %d, lun %d, pid %ld:\n"
368 "eata_stat %#x, hba_stat %#.2x, scsi_stat %#.2x, "
369 "sense_key: %#x, result: %#.8x\n", x,
370 cmd->device->channel, cmd->device->id, cmd->device->lun,
371 cmd->pid, eata_stat, hba_stat, scsi_stat,
372 cmd->sense_buffer[2] & 0xf, cmd->result);
373 DBG(DBG_INTR&&DBG_DELAY,DELAY(1));
374 #endif
375
376 ccb->status = FREE; /* now we can release the slot */
377 cmd->scsi_done(cmd);
378 }
379 }
380
381 return;
382 }
383
384 inline int eata_send_command(u32 addr, u32 base, u8 command)
385 {
386 long loop = R_LIMIT;
387
388 while (inb(base + HA_RAUXSTAT) & HA_ABUSY)
389 if (--loop == 0)
390 return(FALSE);
391
392 if(addr != (u32) NULL)
393 addr = virt_to_bus((void *)addr);
394
395 /*
396 * This is overkill.....but the MIPSen seem to need this
397 * and it will be optimized away for i86 and ALPHA machines.
398 */
399 flush_cache_all();
400
401 /* And now the address in nice little byte chunks */
402 #ifdef __LITTLE_ENDIAN
403 outb(addr, base + HA_WDMAADDR);
404 outb(addr >> 8, base + HA_WDMAADDR + 1);
405 outb(addr >> 16, base + HA_WDMAADDR + 2);
406 outb(addr >> 24, base + HA_WDMAADDR + 3);
407 #else
408 outb(addr >> 24, base + HA_WDMAADDR);
409 outb(addr >> 16, base + HA_WDMAADDR + 1);
410 outb(addr >> 8, base + HA_WDMAADDR + 2);
411 outb(addr, base + HA_WDMAADDR + 3);
412 #endif
413 outb(command, base + HA_WCOMMAND);
414 return(TRUE);
415 }
416
417 inline int eata_send_immediate(u32 base, u32 addr, u8 ifc, u8 code, u8 code2)
418 {
419 if(addr != (u32) NULL)
420 addr = virt_to_bus((void *)addr);
421
422 /*
423 * This is overkill.....but the MIPSen seem to need this
424 * and it will be optimized away for i86 and ALPHA machines.
425 */
426 flush_cache_all();
427
428 outb(0x0, base + HA_WDMAADDR - 1);
429 if(addr){
430 #ifdef __LITTLE_ENDIAN
431 outb(addr, base + HA_WDMAADDR);
432 outb(addr >> 8, base + HA_WDMAADDR + 1);
433 outb(addr >> 16, base + HA_WDMAADDR + 2);
434 outb(addr >> 24, base + HA_WDMAADDR + 3);
435 #else
436 outb(addr >> 24, base + HA_WDMAADDR);
437 outb(addr >> 16, base + HA_WDMAADDR + 1);
438 outb(addr >> 8, base + HA_WDMAADDR + 2);
439 outb(addr, base + HA_WDMAADDR + 3);
440 #endif
441 } else {
442 outb(0x0, base + HA_WDMAADDR);
443 outb(0x0, base + HA_WDMAADDR + 1);
444 outb(code2, base + HA_WCODE2);
445 outb(code, base + HA_WCODE);
446 }
447
448 outb(ifc, base + HA_WIFC);
449 outb(EATA_CMD_IMMEDIATE, base + HA_WCOMMAND);
450 return(TRUE);
451 }
452
453 int eata_queue(Scsi_Cmnd * cmd, void (* done) (Scsi_Cmnd *))
454 {
455 unsigned int i, x, y;
456 ulong flags;
457 hostdata *hd;
458 struct Scsi_Host *sh;
459 struct eata_ccb *ccb;
460 struct scatterlist *sl;
461
462
463 save_flags(flags);
464 cli();
465
466 #if 0
467 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
468 if(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
469 printk("eata_dma: scsi%d interrupt pending in eata_queue.\n"
470 " Calling interrupt handler.\n", sh->host_no);
471 eata_int_handler(sh->irq, 0, 0);
472 }
473 }
474 #endif
475
476 queue_counter++;
477
478 hd = HD(cmd);
479 sh = cmd->host;
480
481 if (cmd->cmnd[0] == REQUEST_SENSE && cmd->sense_buffer[0] != 0) {
482 DBG(DBG_REQSENSE, printk(KERN_DEBUG "Tried to REQUEST SENSE\n"));
483 cmd->result = DID_OK << 16;
484 done(cmd);
485 restore_flags(flags);
486
487 return(0);
488 }
489
490 /* check for free slot */
491 for (y = hd->last_ccb + 1, x = 0; x < sh->can_queue; x++, y++) {
492 if (y >= sh->can_queue)
493 y = 0;
494 if (hd->ccb[y].status == FREE)
495 break;
496 }
497
498 hd->last_ccb = y;
499
500 if (x >= sh->can_queue) {
501 cmd->result = DID_BUS_BUSY << 16;
502 DBG(DBG_QUEUE && DBG_ABNORM,
503 printk(KERN_CRIT "eata_queue pid %ld, HBA QUEUE FULL..., "
504 "returning DID_BUS_BUSY\n", cmd->pid));
505 done(cmd);
506 restore_flags(flags);
507 return(0);
508 }
509 ccb = &hd->ccb[y];
510
511 memset(ccb, 0, sizeof(struct eata_ccb) - sizeof(struct eata_sg_list *));
512
513 ccb->status = USED; /* claim free slot */
514
515 restore_flags(flags);
516
517 DBG(DBG_QUEUE, printk("eata_queue pid %ld, target: %x, lun: %x, y %d\n",
518 cmd->pid, cmd->target, cmd->lun, y));
519 DBG(DBG_QUEUE && DBG_DELAY, DELAY(1));
520
521 if(hd->do_latency == TRUE)
522 eata_latency_out(ccb, cmd);
523
524 cmd->scsi_done = (void *)done;
525
526 switch (cmd->cmnd[0]) {
527 case CHANGE_DEFINITION: case COMPARE: case COPY:
528 case COPY_VERIFY: case LOG_SELECT: case MODE_SELECT:
529 case MODE_SELECT_10: case SEND_DIAGNOSTIC: case WRITE_BUFFER:
530 case FORMAT_UNIT: case REASSIGN_BLOCKS: case RESERVE:
531 case SEARCH_EQUAL: case SEARCH_HIGH: case SEARCH_LOW:
532 case WRITE_6: case WRITE_10: case WRITE_VERIFY:
533 case UPDATE_BLOCK: case WRITE_LONG: case WRITE_SAME:
534 case SEARCH_HIGH_12: case SEARCH_EQUAL_12: case SEARCH_LOW_12:
535 case WRITE_12: case WRITE_VERIFY_12: case SET_WINDOW:
536 case MEDIUM_SCAN: case SEND_VOLUME_TAG:
537 case 0xea: /* alternate number for WRITE LONG */
538 ccb->DataOut = TRUE; /* Output mode */
539 break;
540 case TEST_UNIT_READY:
541 default:
542 ccb->DataIn = TRUE; /* Input mode */
543 }
544
545 /* FIXME: This will will have to be changed once the midlevel driver
546 * allows different HBA IDs on every channel.
547 */
548 if (cmd->target == sh->this_id)
549 ccb->Interpret = TRUE; /* Interpret command */
550
551 if (cmd->use_sg) {
552 ccb->scatter = TRUE; /* SG mode */
553 if (ccb->sg_list == NULL) {
554 ccb->sg_list = kmalloc(sh->sg_tablesize * sizeof(struct eata_sg_list),
555 GFP_ATOMIC | GFP_DMA);
556 }
557 if (ccb->sg_list == NULL)
558 {
559 /*
560 * Claim the bus was busy. Actually we are the problem but this
561 * will do a deferred retry for us ;)
562 */
563 printk(KERN_ERR "eata_dma: Run out of DMA memory for SG lists !\n");
564 cmd->result = DID_BUS_BUSY << 16;
565 ccb->status = FREE;
566 done(cmd);
567 return(0);
568 }
569 ccb->cp_dataDMA = htonl(virt_to_bus(ccb->sg_list));
570
571 ccb->cp_datalen = htonl(cmd->use_sg * sizeof(struct eata_sg_list));
572 sl=(struct scatterlist *)cmd->request_buffer;
573 for(i = 0; i < cmd->use_sg; i++, sl++){
574 ccb->sg_list[i].data = htonl(virt_to_bus(sl->address));
575 ccb->sg_list[i].len = htonl((u32) sl->length);
576 }
577 } else {
578 ccb->scatter = FALSE;
579 ccb->cp_datalen = htonl(cmd->request_bufflen);
580 ccb->cp_dataDMA = htonl(virt_to_bus(cmd->request_buffer));
581 }
582
583 ccb->Auto_Req_Sen = TRUE;
584 ccb->cp_reqDMA = htonl(virt_to_bus(cmd->sense_buffer));
585 ccb->reqlen = sizeof(cmd->sense_buffer);
586
587 ccb->cp_id = cmd->target;
588 ccb->cp_channel = cmd->channel;
589 ccb->cp_lun = cmd->lun;
590 ccb->cp_dispri = TRUE;
591 ccb->cp_identify = TRUE;
592 memcpy(ccb->cp_cdb, cmd->cmnd, cmd->cmd_len);
593
594 ccb->cp_statDMA = htonl(virt_to_bus(&(hd->sp)));
595
596 ccb->cp_viraddr = ccb; /* This will be passed thru, so we don't need to
597 * convert it */
598 ccb->cmd = cmd;
599 cmd->host_scribble = (char *)&hd->ccb[y];
600
601 if(eata_send_command((u32) ccb, (u32) sh->base, EATA_CMD_DMA_SEND_CP) == FALSE) {
602 cmd->result = DID_BUS_BUSY << 16;
603 DBG(DBG_QUEUE && DBG_ABNORM,
604 printk("eata_queue target %d, pid %ld, HBA busy, "
605 "returning DID_BUS_BUSY\n",cmd->target, cmd->pid));
606 ccb->status = FREE;
607 done(cmd);
608 return(0);
609 }
610 DBG(DBG_QUEUE, printk("Queued base %#.4x pid: %ld target: %x lun: %x "
611 "slot %d irq %d\n", (s32)sh->base, cmd->pid,
612 cmd->target, cmd->lun, y, sh->irq));
613 DBG(DBG_QUEUE && DBG_DELAY, DELAY(1));
614
615 return(0);
616 }
617
618
619 int eata_abort(Scsi_Cmnd * cmd)
620 {
621 ulong loop = HZ / 2;
622 ulong flags;
623 int x;
624 struct Scsi_Host *sh;
625
626 save_flags(flags);
627 cli();
628
629 DBG(DBG_ABNORM, printk("eata_abort called pid: %ld target: %x lun: %x"
630 " reason %x\n", cmd->pid, cmd->target, cmd->lun,
631 cmd->abort_reason));
632 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
633
634 /* Some interrupt controllers seem to loose interrupts */
635 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
636 if(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
637 printk("eata_dma: scsi%d interrupt pending in eata_abort.\n"
638 " Calling interrupt handler.\n", sh->host_no);
639 eata_int_handler(sh->irq, 0, 0);
640 }
641 }
642
643 while (inb((u32)(cmd->host->base) + HA_RAUXSTAT) & HA_ABUSY) {
644 if (--loop == 0) {
645 printk("eata_dma: abort, timeout error.\n");
646 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
647 restore_flags(flags);
648 return (SCSI_ABORT_ERROR);
649 }
650 }
651 if (CD(cmd)->status == RESET) {
652 printk("eata_dma: abort, command reset error.\n");
653 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
654 restore_flags(flags);
655 return (SCSI_ABORT_ERROR);
656 }
657 if (CD(cmd)->status == LOCKED) {
658 DBG(DBG_ABNORM, printk("eata_dma: abort, queue slot locked.\n"));
659 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
660 restore_flags(flags);
661 return (SCSI_ABORT_NOT_RUNNING);
662 }
663 if (CD(cmd)->status == USED) {
664 DBG(DBG_ABNORM, printk("Returning: SCSI_ABORT_BUSY\n"));
665 restore_flags(flags);
666 return (SCSI_ABORT_BUSY); /* SNOOZE */
667 }
668 if (CD(cmd)->status == FREE) {
669 DBG(DBG_ABNORM, printk("Returning: SCSI_ABORT_NOT_RUNNING\n"));
670 restore_flags(flags);
671 return (SCSI_ABORT_NOT_RUNNING);
672 }
673 restore_flags(flags);
674 panic("eata_dma: abort: invalid slot status\n");
675 }
676
677 int eata_reset(Scsi_Cmnd * cmd, unsigned int resetflags)
678 {
679 uint x;
680 /* 10 million PCI reads take at least one third of a second */
681 ulong loop = 10 * 1000 * 1000;
682 ulong flags;
683 unchar success = FALSE;
684 Scsi_Cmnd *sp;
685 struct Scsi_Host *sh;
686
687 save_flags(flags);
688 cli();
689
690 DBG(DBG_ABNORM, printk("eata_reset called pid:%ld target: %x lun: %x"
691 " reason %x\n", cmd->pid, cmd->target, cmd->lun,
692 cmd->abort_reason));
693
694 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
695 if(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
696 printk("eata_dma: scsi%d interrupt pending in eata_reset.\n"
697 " Calling interrupt handler.\n", sh->host_no);
698 eata_int_handler(sh->irq, 0, 0);
699 }
700 }
701
702 if (HD(cmd)->state == RESET) {
703 printk("eata_reset: exit, already in reset.\n");
704 restore_flags(flags);
705 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
706 return (SCSI_RESET_ERROR);
707 }
708
709 while (inb((u32)(cmd->host->base) + HA_RAUXSTAT) & HA_ABUSY)
710 if (--loop == 0) {
711 printk("eata_reset: exit, timeout error.\n");
712 restore_flags(flags);
713 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
714 return (SCSI_RESET_ERROR);
715 }
716
717 for (x = 0; x < cmd->host->can_queue; x++) {
718 if (HD(cmd)->ccb[x].status == FREE)
719 continue;
720
721 if (HD(cmd)->ccb[x].status == LOCKED) {
722 HD(cmd)->ccb[x].status = FREE;
723 printk("eata_reset: locked slot %d forced free.\n", x);
724 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
725 continue;
726 }
727
728
729 sp = HD(cmd)->ccb[x].cmd;
730 HD(cmd)->ccb[x].status = RESET;
731
732 if (sp == NULL)
733 panic("eata_reset: slot %d, sp==NULL.\n", x);
734
735 printk("eata_reset: slot %d in reset, pid %ld.\n", x, sp->pid);
736
737 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
738
739 if (sp == cmd)
740 success = TRUE;
741 }
742
743 /* hard reset the HBA */
744 inb((u32) (cmd->host->base) + HA_RSTATUS); /* This might cause trouble */
745 eata_send_command(0, (u32) cmd->host->base, EATA_CMD_RESET);
746
747 HD(cmd)->state = RESET;
748
749 DBG(DBG_ABNORM, printk("eata_reset: board reset done, enabling "
750 "interrupts.\n"));
751
752 DELAY(2); /* In theorie we should get interrupts and set free all
753 * used queueslots */
754
755 DBG(DBG_ABNORM, printk("eata_reset: interrupts disabled again.\n"));
756 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
757
758 for (x = 0; x < cmd->host->can_queue; x++) {
759
760 /* Skip slots already set free by interrupt and those that
761 * are still LOCKED from the last reset */
762 if (HD(cmd)->ccb[x].status != RESET)
763 continue;
764
765 sp = HD(cmd)->ccb[x].cmd;
766 sp->result = DID_RESET << 16;
767
768 /* This mailbox is still waiting for its interrupt */
769 HD(cmd)->ccb[x].status = LOCKED;
770
771 printk("eata_reset: slot %d locked, DID_RESET, pid %ld done.\n",
772 x, sp->pid);
773 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
774
775 sp->scsi_done(sp);
776 }
777
778 HD(cmd)->state = FALSE;
779 restore_flags(flags);
780
781 if (success) {
782 DBG(DBG_ABNORM, printk("eata_reset: exit, pending.\n"));
783 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
784 return (SCSI_RESET_PENDING);
785 } else {
786 DBG(DBG_ABNORM, printk("eata_reset: exit, wakeup.\n"));
787 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
788 return (SCSI_RESET_PUNT);
789 }
790 }
791
792 /* Here we try to determine the optimum queue depth for
793 * each attached device.
794 *
795 * At the moment the algorithm is rather simple
796 */
797 static void eata_select_queue_depths(struct Scsi_Host *host,
798 Scsi_Device *devicelist)
799 {
800 Scsi_Device *device;
801 int devcount = 0;
802 int factor = 0;
803
804 #if CRIPPLE_QUEUE
805 for(device = devicelist; device != NULL; device = device->next) {
806 if(device->host == host)
807 device->queue_depth = 2;
808 }
809 #else
810 /* First we do a sample run go find out what we have */
811 for(device = devicelist; device != NULL; device = device->next) {
812 if (device->host == host) {
813 devcount++;
814 switch(device->type) {
815 case TYPE_DISK:
816 case TYPE_MOD:
817 factor += TYPE_DISK_QUEUE;
818 break;
819 case TYPE_TAPE:
820 factor += TYPE_TAPE_QUEUE;
821 break;
822 case TYPE_WORM:
823 case TYPE_ROM:
824 factor += TYPE_ROM_QUEUE;
825 break;
826 case TYPE_PROCESSOR:
827 case TYPE_SCANNER:
828 default:
829 factor += TYPE_OTHER_QUEUE;
830 break;
831 }
832 }
833 }
834
835 DBG(DBG_REGISTER, printk(KERN_DEBUG "scsi%d: needed queueslots %d\n",
836 host->host_no, factor));
837
838 if(factor == 0) /* We don't want to get a DIV BY ZERO error */
839 factor = 1;
840
841 factor = (SD(host)->queuesize * 10) / factor;
842
843 DBG(DBG_REGISTER, printk(KERN_DEBUG "scsi%d: using factor %dE-1\n",
844 host->host_no, factor));
845
846 /* Now that have the factor we can set the individual queuesizes */
847 for(device = devicelist; device != NULL; device = device->next) {
848 if(device->host == host) {
849 if(SD(device->host)->bustype != IS_ISA){
850 switch(device->type) {
851 case TYPE_DISK:
852 case TYPE_MOD:
853 device->queue_depth = (TYPE_DISK_QUEUE * factor) / 10;
854 break;
855 case TYPE_TAPE:
856 device->queue_depth = (TYPE_TAPE_QUEUE * factor) / 10;
857 break;
858 case TYPE_WORM:
859 case TYPE_ROM:
860 device->queue_depth = (TYPE_ROM_QUEUE * factor) / 10;
861 break;
862 case TYPE_PROCESSOR:
863 case TYPE_SCANNER:
864 default:
865 device->queue_depth = (TYPE_OTHER_QUEUE * factor) / 10;
866 break;
867 }
868 } else /* ISA forces us to limit the queue depth because of the
869 * bounce buffer memory overhead. I know this is cruel */
870 device->queue_depth = 2;
871
872 /*
873 * It showed that we need to set an upper limit of commands
874 * we can allow to queue for a single device on the bus.
875 * If we get above that limit, the broken midlevel SCSI code
876 * will produce bogus timeouts and aborts en masse. :-(
877 */
878 if(device->queue_depth > UPPER_DEVICE_QUEUE_LIMIT)
879 device->queue_depth = UPPER_DEVICE_QUEUE_LIMIT;
880 if(device->queue_depth == 0)
881 device->queue_depth = 1;
882
883 printk(KERN_INFO "scsi%d: queue depth for target %d on channel %d "
884 "set to %d\n", host->host_no, device->id, device->channel,
885 device->queue_depth);
886 }
887 }
888 #endif
889 }
890
891 #if CHECK_BLINK
892 int check_blink_state(long base)
893 {
894 ushort loops = 10;
895 u32 blinkindicator;
896 u32 state = 0x12345678;
897 u32 oldstate = 0;
898
899 blinkindicator = htonl(0x54504442);
900 while ((loops--) && (state != oldstate)) {
901 oldstate = state;
902 state = inl((uint) base + 1);
903 }
904
905 DBG(DBG_BLINK, printk("Did Blink check. Status: %d\n",
906 (state == oldstate) && (state == blinkindicator)));
907
908 if ((state == oldstate) && (state == blinkindicator))
909 return(TRUE);
910 else
911 return (FALSE);
912 }
913 #endif
914
915 char * get_board_data(u32 base, u32 irq, u32 id)
916 {
917 struct eata_ccb *cp;
918 struct eata_sp *sp;
919 static char *buff;
920 ulong i;
921
922 cp = (struct eata_ccb *) kmalloc(sizeof(struct eata_ccb),
923 GFP_ATOMIC | GFP_DMA);
924
925 if(cp==NULL)
926 return NULL;
927
928 sp = (struct eata_sp *) kmalloc(sizeof(struct eata_sp),
929 GFP_ATOMIC | GFP_DMA);
930 if(sp==NULL)
931 {
932 kfree(cp);
933 return NULL;
934 }
935
936 buff = dma_scratch;
937
938 memset(cp, 0, sizeof(struct eata_ccb));
939 memset(sp, 0, sizeof(struct eata_sp));
940 memset(buff, 0, 256);
941
942 cp->DataIn = TRUE;
943 cp->Interpret = TRUE; /* Interpret command */
944 cp->cp_dispri = TRUE;
945 cp->cp_identify = TRUE;
946
947 cp->cp_datalen = htonl(56);
948 cp->cp_dataDMA = htonl(virt_to_bus(buff));
949 cp->cp_statDMA = htonl(virt_to_bus(sp));
950 cp->cp_viraddr = cp;
951
952 cp->cp_id = id;
953 cp->cp_lun = 0;
954
955 cp->cp_cdb[0] = INQUIRY;
956 cp->cp_cdb[1] = 0;
957 cp->cp_cdb[2] = 0;
958 cp->cp_cdb[3] = 0;
959 cp->cp_cdb[4] = 56;
960 cp->cp_cdb[5] = 0;
961
962 fake_int_base = (struct eata_register *) base;
963 fake_int_result = FALSE;
964 fake_int_happened = FALSE;
965
966 eata_send_command((u32) cp, (u32) base, EATA_CMD_DMA_SEND_CP);
967
968 i = jiffies + (3 * HZ);
969 while (fake_int_happened == FALSE && time_before_eq(jiffies, i))
970 barrier();
971
972 DBG(DBG_INTR3, printk(KERN_DEBUG "fake_int_result: %#x hbastat %#x "
973 "scsistat %#x, buff %p sp %p\n",
974 fake_int_result, (u32) (sp->hba_stat /*& 0x7f*/),
975 (u32) sp->scsi_stat, buff, sp));
976
977 kfree((void *)cp);
978 kfree((void *)sp);
979
980 if ((fake_int_result & HA_SERROR) || time_after(jiffies, i)){
981 printk(KERN_WARNING "eata_dma: trying to reset HBA at %x to clear "
982 "possible blink state\n", base);
983 /* hard reset the HBA */
984 inb((u32) (base) + HA_RSTATUS);
985 eata_send_command(0, base, EATA_CMD_RESET);
986 DELAY(1);
987 return (NULL);
988 } else
989 return (buff);
990 }
991
992
993 int get_conf_PIO(u32 base, struct get_conf *buf)
994 {
995 ulong loop = R_LIMIT;
996 u16 *p;
997
998 if(check_region(base, 9))
999 return (FALSE);
1000
1001 memset(buf, 0, sizeof(struct get_conf));
1002
1003 while (inb(base + HA_RSTATUS) & HA_SBUSY)
1004 if (--loop == 0)
1005 return (FALSE);
1006
1007 fake_int_base = (struct eata_register *) base;
1008 fake_int_result = FALSE;
1009 fake_int_happened = FALSE;
1010
1011 DBG(DBG_PIO && DBG_PROBE,
1012 printk("Issuing PIO READ CONFIG to HBA at %#x\n", base));
1013 eata_send_command(0, base, EATA_CMD_PIO_READ_CONFIG);
1014
1015 loop = R_LIMIT;
1016 for (p = (u16 *) buf;
1017 (long)p <= ((long)buf + (sizeof(struct get_conf) / 2)); p++) {
1018 while (!(inb(base + HA_RSTATUS) & HA_SDRQ))
1019 if (--loop == 0)
1020 return (FALSE);
1021
1022 loop = R_LIMIT;
1023 *p = inw(base + HA_RDATA);
1024 }
1025
1026 if (!(inb(base + HA_RSTATUS) & HA_SERROR)) { /* Error ? */
1027 if (htonl(EATA_SIGNATURE) == buf->signature) {
1028 DBG(DBG_PIO&&DBG_PROBE, printk("EATA Controller found at %x "
1029 "EATA Level: %x\n", (uint) base,
1030 (uint) (buf->version)));
1031
1032 while (inb(base + HA_RSTATUS) & HA_SDRQ)
1033 inw(base + HA_RDATA);
1034 return (TRUE);
1035 }
1036 } else {
1037 DBG(DBG_PROBE, printk("eata_dma: get_conf_PIO, error during transfer "
1038 "for HBA at %lx\n", (long)base));
1039 }
1040 return (FALSE);
1041 }
1042
1043
1044 void print_config(struct get_conf *gc)
1045 {
1046 printk("LEN: %d ver:%d OCS:%d TAR:%d TRNXFR:%d MORES:%d DMAS:%d\n",
1047 (u32) ntohl(gc->len), gc->version,
1048 gc->OCS_enabled, gc->TAR_support, gc->TRNXFR, gc->MORE_support,
1049 gc->DMA_support);
1050 printk("DMAV:%d HAAV:%d SCSIID0:%d ID1:%d ID2:%d QUEUE:%d SG:%d SEC:%d\n",
1051 gc->DMA_valid, gc->HAA_valid, gc->scsi_id[3], gc->scsi_id[2],
1052 gc->scsi_id[1], ntohs(gc->queuesiz), ntohs(gc->SGsiz), gc->SECOND);
1053 printk("IRQ:%d IRQT:%d DMAC:%d FORCADR:%d SG_64K:%d SG_UAE:%d MID:%d "
1054 "MCH:%d MLUN:%d\n",
1055 gc->IRQ, gc->IRQ_TR, (8 - gc->DMA_channel) & 7, gc->FORCADR,
1056 gc->SG_64K, gc->SG_UAE, gc->MAX_ID, gc->MAX_CHAN, gc->MAX_LUN);
1057 printk("RIDQ:%d PCI:%d EISA:%d\n",
1058 gc->ID_qest, gc->is_PCI, gc->is_EISA);
1059 DBG(DPT_DEBUG, DELAY(14));
1060 }
1061
1062 short register_HBA(u32 base, struct get_conf *gc, Scsi_Host_Template * tpnt,
1063 u8 bustype)
1064 {
1065 ulong size = 0;
1066 unchar dma_channel = 0;
1067 char *buff = 0;
1068 unchar bugs = 0;
1069 struct Scsi_Host *sh;
1070 hostdata *hd;
1071 int x;
1072
1073
1074 DBG(DBG_REGISTER, print_config(gc));
1075
1076 if (gc->DMA_support == FALSE) {
1077 printk("The EATA HBA at %#.4x does not support DMA.\n"
1078 "Please use the EATA-PIO driver.\n", base);
1079 return (FALSE);
1080 }
1081 if(gc->HAA_valid == FALSE || ntohl(gc->len) < 0x22)
1082 gc->MAX_CHAN = 0;
1083
1084 if (reg_IRQ[gc->IRQ] == FALSE) { /* Interrupt already registered ? */
1085 if (!request_irq(gc->IRQ, (void *) eata_fake_int_handler, SA_INTERRUPT,
1086 "eata_dma", NULL)){
1087 reg_IRQ[gc->IRQ]++;
1088 if (!gc->IRQ_TR)
1089 reg_IRQL[gc->IRQ] = TRUE; /* IRQ is edge triggered */
1090 } else {
1091 printk("Couldn't allocate IRQ %d, Sorry.", gc->IRQ);
1092 return (FALSE);
1093 }
1094 } else { /* More than one HBA on this IRQ */
1095 if (reg_IRQL[gc->IRQ] == TRUE) {
1096 printk("Can't support more than one HBA on this IRQ,\n"
1097 " if the IRQ is edge triggered. Sorry.\n");
1098 return (FALSE);
1099 } else
1100 reg_IRQ[gc->IRQ]++;
1101 }
1102
1103
1104 /* If DMA is supported but DMA_valid isn't set to indicate that
1105 * the channel number is given we must have pre 2.0 firmware (1.7?)
1106 * which leaves us to guess since the "newer ones" also don't set the
1107 * DMA_valid bit.
1108 */
1109 if (gc->DMA_support && !gc->DMA_valid && gc->DMA_channel) {
1110 printk(KERN_WARNING "eata_dma: If you are using a pre 2.0 firmware "
1111 "please update it !\n"
1112 " You can get new firmware releases from ftp.dpt.com\n");
1113 gc->DMA_channel = (base == 0x1f0 ? 3 /* DMA=5 */ : 2 /* DMA=6 */);
1114 gc->DMA_valid = TRUE;
1115 }
1116
1117 /* if gc->DMA_valid it must be an ISA HBA and we have to register it */
1118 dma_channel = BUSMASTER;
1119 if (gc->DMA_valid) {
1120 if (request_dma(dma_channel = (8 - gc->DMA_channel) & 7, "eata_dma")) {
1121 printk(KERN_WARNING "Unable to allocate DMA channel %d for ISA HBA"
1122 " at %#.4x.\n", dma_channel, base);
1123 reg_IRQ[gc->IRQ]--;
1124 if (reg_IRQ[gc->IRQ] == 0)
1125 free_irq(gc->IRQ, NULL);
1126 if (gc->IRQ_TR == FALSE)
1127 reg_IRQL[gc->IRQ] = FALSE;
1128 return (FALSE);
1129 }
1130 }
1131
1132 if (dma_channel != BUSMASTER) {
1133 disable_dma(dma_channel);
1134 clear_dma_ff(dma_channel);
1135 set_dma_mode(dma_channel, DMA_MODE_CASCADE);
1136 enable_dma(dma_channel);
1137 }
1138
1139 if (bustype != IS_EISA && bustype != IS_ISA)
1140 buff = get_board_data(base, gc->IRQ, gc->scsi_id[3]);
1141
1142 if (buff == NULL) {
1143 if (bustype == IS_EISA || bustype == IS_ISA) {
1144 bugs = bugs || BROKEN_INQUIRY;
1145 } else {
1146 if (gc->DMA_support == FALSE)
1147 printk(KERN_WARNING "HBA at %#.4x doesn't support DMA. "
1148 "Sorry\n", base);
1149 else
1150 printk(KERN_WARNING "HBA at %#.4x does not react on INQUIRY. "
1151 "Sorry.\n", base);
1152 if (gc->DMA_valid)
1153 free_dma(dma_channel);
1154 reg_IRQ[gc->IRQ]--;
1155 if (reg_IRQ[gc->IRQ] == 0)
1156 free_irq(gc->IRQ, NULL);
1157 if (gc->IRQ_TR == FALSE)
1158 reg_IRQL[gc->IRQ] = FALSE;
1159 return (FALSE);
1160 }
1161 }
1162
1163 if (gc->DMA_support == FALSE && buff != NULL)
1164 printk(KERN_WARNING "HBA %.12sat %#.4x doesn't set the DMA_support "
1165 "flag correctly.\n", &buff[16], base);
1166
1167 request_region(base, 9, "eata_dma"); /* We already checked the
1168 * availability, so this
1169 * should not fail.
1170 */
1171
1172 if(ntohs(gc->queuesiz) == 0) {
1173 gc->queuesiz = ntohs(64);
1174 printk(KERN_WARNING "Warning: Queue size has to be corrected. Assuming"
1175 " 64 queueslots\n"
1176 " This might be a PM2012B with a defective Firmware\n"
1177 " Contact DPT support@dpt.com for an upgrade\n");
1178 }
1179
1180 size = sizeof(hostdata) + ((sizeof(struct eata_ccb) + sizeof(long))
1181 * ntohs(gc->queuesiz));
1182
1183 DBG(DBG_REGISTER, printk("scsi_register size: %ld\n", size));
1184
1185 sh = scsi_register(tpnt, size);
1186
1187 if(sh != NULL) {
1188
1189 hd = SD(sh);
1190
1191 memset(hd->reads, 0, sizeof(u32) * 26);
1192
1193 sh->select_queue_depths = eata_select_queue_depths;
1194
1195 hd->bustype = bustype;
1196
1197 /*
1198 * If we are using a ISA board, we can't use extended SG,
1199 * because we would need excessive amounts of memory for
1200 * bounce buffers.
1201 */
1202 if (gc->SG_64K==TRUE && ntohs(gc->SGsiz)==64 && hd->bustype!=IS_ISA){
1203 sh->sg_tablesize = SG_SIZE_BIG;
1204 } else {
1205 sh->sg_tablesize = ntohs(gc->SGsiz);
1206 if (sh->sg_tablesize > SG_SIZE || sh->sg_tablesize == 0) {
1207 if (sh->sg_tablesize == 0)
1208 printk(KERN_WARNING "Warning: SG size had to be fixed.\n"
1209 "This might be a PM2012 with a defective Firmware"
1210 "\nContact DPT support@dpt.com for an upgrade\n");
1211 sh->sg_tablesize = SG_SIZE;
1212 }
1213 }
1214 hd->sgsize = sh->sg_tablesize;
1215 }
1216
1217 if(sh != NULL) {
1218 sh->can_queue = hd->queuesize = ntohs(gc->queuesiz);
1219 sh->cmd_per_lun = 0;
1220 }
1221
1222 if(sh == NULL) {
1223 DBG(DBG_REGISTER, printk(KERN_NOTICE "eata_dma: couldn't register HBA"
1224 " at%x \n", base));
1225 scsi_unregister(sh);
1226 if (gc->DMA_valid)
1227 free_dma(dma_channel);
1228
1229 reg_IRQ[gc->IRQ]--;
1230 if (reg_IRQ[gc->IRQ] == 0)
1231 free_irq(gc->IRQ, NULL);
1232 if (gc->IRQ_TR == FALSE)
1233 reg_IRQL[gc->IRQ] = FALSE;
1234 return (FALSE);
1235 }
1236
1237
1238 hd->broken_INQUIRY = (bugs & BROKEN_INQUIRY);
1239
1240 if(hd->broken_INQUIRY == TRUE) {
1241 strcpy(hd->vendor, "DPT");
1242 strcpy(hd->name, "??????????");
1243 strcpy(hd->revision, "???.?");
1244 hd->firmware_revision = 0;
1245 } else {
1246 strncpy(hd->vendor, &buff[8], 8);
1247 hd->vendor[8] = 0;
1248 strncpy(hd->name, &buff[16], 17);
1249 hd->name[17] = 0;
1250 hd->revision[0] = buff[32];
1251 hd->revision[1] = buff[33];
1252 hd->revision[2] = buff[34];
1253 hd->revision[3] = '.';
1254 hd->revision[4] = buff[35];
1255 hd->revision[5] = 0;
1256 hd->firmware_revision = (buff[32] << 24) + (buff[33] << 16)
1257 + (buff[34] << 8) + buff[35];
1258 }
1259
1260 if (hd->firmware_revision >= (('0'<<24) + ('7'<<16) + ('G'<< 8) + '0'))
1261 hd->immediate_support = 1;
1262 else
1263 hd->immediate_support = 0;
1264
1265 switch (ntohl(gc->len)) {
1266 case 0x1c:
1267 hd->EATA_revision = 'a';
1268 break;
1269 case 0x1e:
1270 hd->EATA_revision = 'b';
1271 break;
1272 case 0x22:
1273 hd->EATA_revision = 'c';
1274 break;
1275 case 0x24:
1276 hd->EATA_revision = 'z';
1277 default:
1278 hd->EATA_revision = '?';
1279 }
1280
1281
1282 if(ntohl(gc->len) >= 0x22) {
1283 sh->max_id = gc->MAX_ID + 1;
1284 sh->max_lun = gc->MAX_LUN + 1;
1285 } else {
1286 sh->max_id = 8;
1287 sh->max_lun = 8;
1288 }
1289
1290 hd->HBA_number = sh->host_no;
1291 hd->channel = gc->MAX_CHAN;
1292 sh->max_channel = gc->MAX_CHAN;
1293 sh->unique_id = base;
1294 sh->base = base;
1295 sh->io_port = base;
1296 sh->n_io_port = 9;
1297 sh->irq = gc->IRQ;
1298 sh->dma_channel = dma_channel;
1299
1300 /* FIXME:
1301 * SCSI midlevel code should support different HBA ids on every channel
1302 */
1303 sh->this_id = gc->scsi_id[3];
1304
1305 if (gc->SECOND)
1306 hd->primary = FALSE;
1307 else
1308 hd->primary = TRUE;
1309
1310 if (hd->bustype != IS_ISA) {
1311 sh->unchecked_isa_dma = FALSE;
1312 } else {
1313 sh->unchecked_isa_dma = TRUE; /* We're doing ISA DMA */
1314 }
1315
1316 for(x = 0; x <= 11; x++){ /* Initialize min. latency */
1317 hd->writes_lat[x][1] = 0xffffffff;
1318 hd->reads_lat[x][1] = 0xffffffff;
1319 }
1320 hd->all_lat[1] = 0xffffffff;
1321
1322 hd->next = NULL; /* build a linked list of all HBAs */
1323 hd->prev = last_HBA;
1324 if(hd->prev != NULL)
1325 SD(hd->prev)->next = sh;
1326 last_HBA = sh;
1327 if (first_HBA == NULL)
1328 first_HBA = sh;
1329 registered_HBAs++;
1330
1331 return (TRUE);
1332 }
1333
1334
1335
1336 void find_EISA(struct get_conf *buf, Scsi_Host_Template * tpnt)
1337 {
1338 u32 base;
1339 int i;
1340
1341 #if CHECKPAL
1342 u8 pal1, pal2, pal3;
1343 #endif
1344
1345 for (i = 0; i < MAXEISA; i++) {
1346 if (EISAbases[i] == TRUE) { /* Still a possibility ? */
1347
1348 base = 0x1c88 + (i * 0x1000);
1349 #if CHECKPAL
1350 pal1 = inb((u16)base - 8);
1351 pal2 = inb((u16)base - 7);
1352 pal3 = inb((u16)base - 6);
1353
1354 if (((pal1 == DPT_ID1) && (pal2 == DPT_ID2)) ||
1355 ((pal1 == NEC_ID1) && (pal2 == NEC_ID2) && (pal3 == NEC_ID3))||
1356 ((pal1 == ATT_ID1) && (pal2 == ATT_ID2) && (pal3 == ATT_ID3))){
1357 DBG(DBG_PROBE, printk("EISA EATA id tags found: %x %x %x \n",
1358 (int)pal1, (int)pal2, (int)pal3));
1359 #endif
1360 if (get_conf_PIO(base, buf) == TRUE) {
1361 if (buf->IRQ) {
1362 DBG(DBG_EISA, printk("Registering EISA HBA\n"));
1363 register_HBA(base, buf, tpnt, IS_EISA);
1364 } else
1365 printk("eata_dma: No valid IRQ. HBA removed from list\n");
1366 }
1367 #if CHECK_BLINK
1368 else {
1369 if (check_blink_state(base))
1370 printk("HBA is in BLINK state. Consult your HBAs "
1371 "Manual to correct this.\n");
1372 }
1373 #endif
1374 /* Nothing found here so we take it from the list */
1375 EISAbases[i] = 0;
1376 #if CHECKPAL
1377 }
1378 #endif
1379 }
1380 }
1381 return;
1382 }
1383
1384 void find_ISA(struct get_conf *buf, Scsi_Host_Template * tpnt)
1385 {
1386 int i;
1387
1388 for (i = 0; i < MAXISA; i++) {
1389 if (ISAbases[i]) {
1390 if (get_conf_PIO(ISAbases[i],buf) == TRUE){
1391 DBG(DBG_ISA, printk("Registering ISA HBA\n"));
1392 register_HBA(ISAbases[i], buf, tpnt, IS_ISA);
1393 }
1394 #if CHECK_BLINK
1395 else {
1396 if (check_blink_state(ISAbases[i]))
1397 printk("HBA is in BLINK state. Consult your HBAs "
1398 "Manual to correct this.\n");
1399 }
1400 #endif
1401 ISAbases[i] = 0;
1402 }
1403 }
1404 return;
1405 }
1406
1407 void find_PCI(struct get_conf *buf, Scsi_Host_Template * tpnt)
1408 {
1409 #ifndef CONFIG_PCI
1410 printk("eata_dma: kernel PCI support not enabled. Skipping scan for PCI HBAs.\n");
1411 #else
1412 struct pci_dev *dev = NULL;
1413 u32 base, x;
1414 u8 pal1, pal2, pal3;
1415
1416 while ((dev = pci_find_device(PCI_VENDOR_ID_DPT, PCI_DEVICE_ID_DPT, dev)) != NULL) {
1417 DBG(DBG_PROBE && DBG_PCI,
1418 printk("eata_dma: find_PCI, HBA at %s\n", dev->name));
1419 if (pci_enable_device(dev))
1420 continue;
1421 pci_set_master(dev);
1422 base = pci_resource_flags(dev, 0);
1423 if (base & IORESOURCE_MEM) {
1424 printk("eata_dma: invalid base address of device %s\n", dev->name);
1425 continue;
1426 }
1427 base = pci_resource_start(dev, 0);
1428 /* EISA tag there ? */
1429 pal1 = inb(base);
1430 pal2 = inb(base + 1);
1431 pal3 = inb(base + 2);
1432 if (((pal1 == DPT_ID1) && (pal2 == DPT_ID2)) ||
1433 ((pal1 == NEC_ID1) && (pal2 == NEC_ID2) &&
1434 (pal3 == NEC_ID3)) ||
1435 ((pal1 == ATT_ID1) && (pal2 == ATT_ID2) &&
1436 (pal3 == ATT_ID3)))
1437 base += 0x08;
1438 else
1439 base += 0x10; /* Now, THIS is the real address */
1440 if (base != 0x1f8) {
1441 /* We didn't find it in the primary search */
1442 if (get_conf_PIO(base, buf) == TRUE) {
1443 /* OK. We made it till here, so we can go now
1444 * and register it. We only have to check and
1445 * eventually remove it from the EISA and ISA list
1446 */
1447 DBG(DBG_PCI, printk("Registering PCI HBA\n"));
1448 register_HBA(base, buf, tpnt, IS_PCI);
1449
1450 if (base < 0x1000) {
1451 for (x = 0; x < MAXISA; ++x) {
1452 if (ISAbases[x] == base) {
1453 ISAbases[x] = 0;
1454 break;
1455 }
1456 }
1457 } else if ((base & 0x0fff) == 0x0c88)
1458 EISAbases[(base >> 12) & 0x0f] = 0;
1459 }
1460 #if CHECK_BLINK
1461 else if (check_blink_state(base) == TRUE) {
1462 printk("eata_dma: HBA is in BLINK state.\n"
1463 "Consult your HBAs manual to correct this.\n");
1464 }
1465 #endif
1466 }
1467 }
1468 #endif /* #ifndef CONFIG_PCI */
1469 }
1470
1471 int eata_detect(Scsi_Host_Template * tpnt)
1472 {
1473 struct Scsi_Host *HBA_ptr;
1474 struct get_conf gc;
1475 int i;
1476
1477 DBG((DBG_PROBE && DBG_DELAY) || DPT_DEBUG,
1478 printk("Using lots of delays to let you read the debugging output\n"));
1479
1480 tpnt->proc_name = "eata_dma";
1481
1482 status = kmalloc(512, GFP_ATOMIC | GFP_DMA);
1483 dma_scratch = kmalloc(1024, GFP_ATOMIC | GFP_DMA);
1484
1485 if(status == NULL || dma_scratch == NULL) {
1486 printk("eata_dma: can't allocate enough memory to probe for hosts !\n");
1487 if(status)
1488 kfree(status);
1489 if(dma_scratch)
1490 kfree(dma_scratch);
1491 return(0);
1492 }
1493
1494 dma_scratch += 4;
1495
1496 find_PCI(&gc, tpnt);
1497
1498 find_EISA(&gc, tpnt);
1499
1500 find_ISA(&gc, tpnt);
1501
1502 for (i = 0; i <= MAXIRQ; i++) { /* Now that we know what we have, we */
1503 if (reg_IRQ[i] >= 1){ /* exchange the interrupt handler which */
1504 free_irq(i, NULL); /* we used for probing with the real one */
1505 request_irq(i, (void *)(do_eata_int_handler), SA_INTERRUPT|SA_SHIRQ,
1506 "eata_dma", NULL);
1507 }
1508 }
1509
1510 HBA_ptr = first_HBA;
1511
1512 if (registered_HBAs != 0) {
1513 printk("EATA (Extended Attachment) driver version: %d.%d%s"
1514 "\ndeveloped in co-operation with DPT\n"
1515 "(c) 1993-96 Michael Neuffer, mike@i-Connect.Net\n",
1516 VER_MAJOR, VER_MINOR, VER_SUB);
1517 printk("Registered HBAs:");
1518 printk("\nHBA no. Boardtype Revis EATA Bus BaseIO IRQ"
1519 " DMA Ch ID Pr QS S/G IS\n");
1520 for (i = 1; i <= registered_HBAs; i++) {
1521 printk("scsi%-2d: %.12s v%s 2.0%c %s %#.4x %2d",
1522 HBA_ptr->host_no, SD(HBA_ptr)->name, SD(HBA_ptr)->revision,
1523 SD(HBA_ptr)->EATA_revision, (SD(HBA_ptr)->bustype == 'P')?
1524 "PCI ":(SD(HBA_ptr)->bustype == 'E')?"EISA":"ISA ",
1525 (u32) HBA_ptr->base, HBA_ptr->irq);
1526 if(HBA_ptr->dma_channel != BUSMASTER)
1527 printk(" %2x ", HBA_ptr->dma_channel);
1528 else
1529 printk(" %s", "BMST");
1530 printk(" %d %d %c %3d %3d %c\n",
1531 SD(HBA_ptr)->channel+1, HBA_ptr->this_id,
1532 (SD(HBA_ptr)->primary == TRUE)?'Y':'N',
1533 HBA_ptr->can_queue, HBA_ptr->sg_tablesize,
1534 (SD(HBA_ptr)->immediate_support == TRUE)?'Y':'N');
1535 HBA_ptr = SD(HBA_ptr)->next;
1536 }
1537 } else {
1538 kfree((void *)status);
1539 }
1540
1541 kfree((void *)dma_scratch - 4);
1542
1543 DBG(DPT_DEBUG, DELAY(12));
1544
1545 return(registered_HBAs);
1546 }
1547
1548 /* Eventually this will go into an include file, but this will be later */
1549 static Scsi_Host_Template driver_template = EATA_DMA;
1550 #include "scsi_module.c"
1551
1552 /*
1553 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1554 * Emacs will notice this stuff at the end of the file and automatically
1555 * adjust the settings for this buffer only. This must remain at the end
1556 * of the file.
1557 * ---------------------------------------------------------------------------
1558 * Local variables:
1559 * c-indent-level: 4
1560 * c-brace-imaginary-offset: 0
1561 * c-brace-offset: -4
1562 * c-argdecl-indent: 4
1563 * c-label-offset: -4
1564 * c-continued-statement-offset: 4
1565 * c-continued-brace-offset: 0
1566 * tab-width: 8
1567 * End:
1568 */
1569