File: /usr/src/linux/arch/i386/kernel/i8259.c
1 #include <linux/config.h>
2 #include <linux/ptrace.h>
3 #include <linux/errno.h>
4 #include <linux/signal.h>
5 #include <linux/sched.h>
6 #include <linux/ioport.h>
7 #include <linux/interrupt.h>
8 #include <linux/timex.h>
9 #include <linux/slab.h>
10 #include <linux/random.h>
11 #include <linux/smp_lock.h>
12 #include <linux/init.h>
13 #include <linux/kernel_stat.h>
14
15 #include <asm/atomic.h>
16 #include <asm/system.h>
17 #include <asm/io.h>
18 #include <asm/irq.h>
19 #include <asm/bitops.h>
20 #include <asm/pgtable.h>
21 #include <asm/delay.h>
22 #include <asm/desc.h>
23 #include <asm/apic.h>
24
25 #include <linux/irq.h>
26
27 /*
28 * Common place to define all x86 IRQ vectors
29 *
30 * This builds up the IRQ handler stubs using some ugly macros in irq.h
31 *
32 * These macros create the low-level assembly IRQ routines that save
33 * register context and call do_IRQ(). do_IRQ() then does all the
34 * operations that are needed to keep the AT (or SMP IOAPIC)
35 * interrupt-controller happy.
36 */
37
38 BUILD_COMMON_IRQ()
39
40 #define BI(x,y) \
41 BUILD_IRQ(x##y)
42
43 #define BUILD_16_IRQS(x) \
44 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
45 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
46 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
47 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
48
49 /*
50 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
51 * (these are usually mapped to vectors 0x20-0x2f)
52 */
53 BUILD_16_IRQS(0x0)
54
55 #ifdef CONFIG_X86_IO_APIC
56 /*
57 * The IO-APIC gives us many more interrupt sources. Most of these
58 * are unused but an SMP system is supposed to have enough memory ...
59 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
60 * across the spectrum, so we really want to be prepared to get all
61 * of these. Plus, more powerful systems might have more than 64
62 * IO-APIC registers.
63 *
64 * (these are usually mapped into the 0x30-0xff vector range)
65 */
66 BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
67 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
68 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
69 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
70 #endif
71
72 #undef BUILD_16_IRQS
73 #undef BI
74
75
76 /*
77 * The following vectors are part of the Linux architecture, there
78 * is no hardware IRQ pin equivalent for them, they are triggered
79 * through the ICC by us (IPIs)
80 */
81 #ifdef CONFIG_SMP
82 BUILD_SMP_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
83 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
84 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
85 #endif
86
87 /*
88 * every pentium local APIC has two 'local interrupts', with a
89 * soft-definable vector attached to both interrupts, one of
90 * which is a timer interrupt, the other one is error counter
91 * overflow. Linux uses the local APIC timer interrupt to get
92 * a much simpler SMP time architecture:
93 */
94 #ifdef CONFIG_X86_LOCAL_APIC
95 BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
96 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
97 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
98 #endif
99
100 #define IRQ(x,y) \
101 IRQ##x##y##_interrupt
102
103 #define IRQLIST_16(x) \
104 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
105 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
106 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
107 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
108
109 void (*interrupt[NR_IRQS])(void) = {
110 IRQLIST_16(0x0),
111
112 #ifdef CONFIG_X86_IO_APIC
113 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
114 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
115 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
116 IRQLIST_16(0xc), IRQLIST_16(0xd)
117 #endif
118 };
119
120 #undef IRQ
121 #undef IRQLIST_16
122
123 /*
124 * This is the 'legacy' 8259A Programmable Interrupt Controller,
125 * present in the majority of PC/AT boxes.
126 * plus some generic x86 specific things if generic specifics makes
127 * any sense at all.
128 * this file should become arch/i386/kernel/irq.c when the old irq.c
129 * moves to arch independent land
130 */
131
132 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
133
134 static void end_8259A_irq (unsigned int irq)
135 {
136 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
137 enable_8259A_irq(irq);
138 }
139
140 #define shutdown_8259A_irq disable_8259A_irq
141
142 void mask_and_ack_8259A(unsigned int);
143
144 static unsigned int startup_8259A_irq(unsigned int irq)
145 {
146 enable_8259A_irq(irq);
147 return 0; /* never anything pending */
148 }
149
150 static struct hw_interrupt_type i8259A_irq_type = {
151 "XT-PIC",
152 startup_8259A_irq,
153 shutdown_8259A_irq,
154 enable_8259A_irq,
155 disable_8259A_irq,
156 mask_and_ack_8259A,
157 end_8259A_irq,
158 NULL
159 };
160
161 /*
162 * 8259A PIC functions to handle ISA devices:
163 */
164
165 /*
166 * This contains the irq mask for both 8259A irq controllers,
167 */
168 static unsigned int cached_irq_mask = 0xffff;
169
170 #define __byte(x,y) (((unsigned char *)&(y))[x])
171 #define cached_21 (__byte(0,cached_irq_mask))
172 #define cached_A1 (__byte(1,cached_irq_mask))
173
174 /*
175 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
176 * boards the timer interrupt is not really connected to any IO-APIC pin,
177 * it's fed to the master 8259A's IR0 line only.
178 *
179 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
180 * this 'mixed mode' IRQ handling costs nothing because it's only used
181 * at IRQ setup time.
182 */
183 unsigned long io_apic_irqs;
184
185 void disable_8259A_irq(unsigned int irq)
186 {
187 unsigned int mask = 1 << irq;
188 unsigned long flags;
189
190 spin_lock_irqsave(&i8259A_lock, flags);
191 cached_irq_mask |= mask;
192 if (irq & 8)
193 outb(cached_A1,0xA1);
194 else
195 outb(cached_21,0x21);
196 spin_unlock_irqrestore(&i8259A_lock, flags);
197 }
198
199 void enable_8259A_irq(unsigned int irq)
200 {
201 unsigned int mask = ~(1 << irq);
202 unsigned long flags;
203
204 spin_lock_irqsave(&i8259A_lock, flags);
205 cached_irq_mask &= mask;
206 if (irq & 8)
207 outb(cached_A1,0xA1);
208 else
209 outb(cached_21,0x21);
210 spin_unlock_irqrestore(&i8259A_lock, flags);
211 }
212
213 int i8259A_irq_pending(unsigned int irq)
214 {
215 unsigned int mask = 1<<irq;
216 unsigned long flags;
217 int ret;
218
219 spin_lock_irqsave(&i8259A_lock, flags);
220 if (irq < 8)
221 ret = inb(0x20) & mask;
222 else
223 ret = inb(0xA0) & (mask >> 8);
224 spin_unlock_irqrestore(&i8259A_lock, flags);
225
226 return ret;
227 }
228
229 void make_8259A_irq(unsigned int irq)
230 {
231 disable_irq_nosync(irq);
232 io_apic_irqs &= ~(1<<irq);
233 irq_desc[irq].handler = &i8259A_irq_type;
234 enable_irq(irq);
235 }
236
237 /*
238 * This function assumes to be called rarely. Switching between
239 * 8259A registers is slow.
240 * This has to be protected by the irq controller spinlock
241 * before being called.
242 */
243 static inline int i8259A_irq_real(unsigned int irq)
244 {
245 int value;
246 int irqmask = 1<<irq;
247
248 if (irq < 8) {
249 outb(0x0B,0x20); /* ISR register */
250 value = inb(0x20) & irqmask;
251 outb(0x0A,0x20); /* back to the IRR register */
252 return value;
253 }
254 outb(0x0B,0xA0); /* ISR register */
255 value = inb(0xA0) & (irqmask >> 8);
256 outb(0x0A,0xA0); /* back to the IRR register */
257 return value;
258 }
259
260 /*
261 * Careful! The 8259A is a fragile beast, it pretty
262 * much _has_ to be done exactly like this (mask it
263 * first, _then_ send the EOI, and the order of EOI
264 * to the two 8259s is important!
265 */
266 void mask_and_ack_8259A(unsigned int irq)
267 {
268 unsigned int irqmask = 1 << irq;
269 unsigned long flags;
270
271 spin_lock_irqsave(&i8259A_lock, flags);
272 /*
273 * Lightweight spurious IRQ detection. We do not want
274 * to overdo spurious IRQ handling - it's usually a sign
275 * of hardware problems, so we only do the checks we can
276 * do without slowing down good hardware unnecesserily.
277 *
278 * Note that IRQ7 and IRQ15 (the two spurious IRQs
279 * usually resulting from the 8259A-1|2 PICs) occur
280 * even if the IRQ is masked in the 8259A. Thus we
281 * can check spurious 8259A IRQs without doing the
282 * quite slow i8259A_irq_real() call for every IRQ.
283 * This does not cover 100% of spurious interrupts,
284 * but should be enough to warn the user that there
285 * is something bad going on ...
286 */
287 if (cached_irq_mask & irqmask)
288 goto spurious_8259A_irq;
289 cached_irq_mask |= irqmask;
290
291 handle_real_irq:
292 if (irq & 8) {
293 inb(0xA1); /* DUMMY - (do we need this?) */
294 outb(cached_A1,0xA1);
295 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
296 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
297 } else {
298 inb(0x21); /* DUMMY - (do we need this?) */
299 outb(cached_21,0x21);
300 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
301 }
302 spin_unlock_irqrestore(&i8259A_lock, flags);
303 return;
304
305 spurious_8259A_irq:
306 /*
307 * this is the slow path - should happen rarely.
308 */
309 if (i8259A_irq_real(irq))
310 /*
311 * oops, the IRQ _is_ in service according to the
312 * 8259A - not spurious, go handle it.
313 */
314 goto handle_real_irq;
315
316 {
317 static int spurious_irq_mask;
318 /*
319 * At this point we can be sure the IRQ is spurious,
320 * lets ACK and report it. [once per IRQ]
321 */
322 if (!(spurious_irq_mask & irqmask)) {
323 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
324 spurious_irq_mask |= irqmask;
325 }
326 atomic_inc(&irq_err_count);
327 /*
328 * Theoretically we do not have to handle this IRQ,
329 * but in Linux this does not cause problems and is
330 * simpler for us.
331 */
332 goto handle_real_irq;
333 }
334 }
335
336 void __init init_8259A(int auto_eoi)
337 {
338 unsigned long flags;
339
340 spin_lock_irqsave(&i8259A_lock, flags);
341
342 outb(0xff, 0x21); /* mask all of 8259A-1 */
343 outb(0xff, 0xA1); /* mask all of 8259A-2 */
344
345 /*
346 * outb_p - this has to work on a wide range of PC hardware.
347 */
348 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
349 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
350 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
351 if (auto_eoi)
352 outb_p(0x03, 0x21); /* master does Auto EOI */
353 else
354 outb_p(0x01, 0x21); /* master expects normal EOI */
355
356 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
357 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
358 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
359 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
360 is to be investigated) */
361
362 if (auto_eoi)
363 /*
364 * in AEOI mode we just have to mask the interrupt
365 * when acking.
366 */
367 i8259A_irq_type.ack = disable_8259A_irq;
368 else
369 i8259A_irq_type.ack = mask_and_ack_8259A;
370
371 udelay(100); /* wait for 8259A to initialize */
372
373 outb(cached_21, 0x21); /* restore master IRQ mask */
374 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
375
376 spin_unlock_irqrestore(&i8259A_lock, flags);
377 }
378
379 /*
380 * Note that on a 486, we don't want to do a SIGFPE on an irq13
381 * as the irq is unreliable, and exception 16 works correctly
382 * (ie as explained in the intel literature). On a 386, you
383 * can't use exception 16 due to bad IBM design, so we have to
384 * rely on the less exact irq13.
385 *
386 * Careful.. Not only is IRQ13 unreliable, but it is also
387 * leads to races. IBM designers who came up with it should
388 * be shot.
389 */
390
391 static void math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
392 {
393 extern void math_error(void *);
394 outb(0,0xF0);
395 if (ignore_irq13 || !boot_cpu_data.hard_math)
396 return;
397 math_error((void *)regs->eip);
398 }
399
400 /*
401 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
402 * so allow interrupt sharing.
403 */
404 static struct irqaction irq13 = { math_error_irq, 0, 0, "fpu", NULL, NULL };
405
406 /*
407 * IRQ2 is cascade interrupt to second interrupt controller
408 */
409
410 #ifndef CONFIG_VISWS
411 static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
412 #endif
413
414
415 void __init init_ISA_irqs (void)
416 {
417 int i;
418
419 #ifdef CONFIG_X86_LOCAL_APIC
420 init_bsp_APIC();
421 #endif
422 init_8259A(0);
423
424 for (i = 0; i < NR_IRQS; i++) {
425 irq_desc[i].status = IRQ_DISABLED;
426 irq_desc[i].action = 0;
427 irq_desc[i].depth = 1;
428
429 if (i < 16) {
430 /*
431 * 16 old-style INTA-cycle interrupts:
432 */
433 irq_desc[i].handler = &i8259A_irq_type;
434 } else {
435 /*
436 * 'high' PCI IRQs filled in on demand
437 */
438 irq_desc[i].handler = &no_irq_type;
439 }
440 }
441 }
442
443 void __init init_IRQ(void)
444 {
445 int i;
446
447 #ifndef CONFIG_X86_VISWS_APIC
448 init_ISA_irqs();
449 #else
450 init_VISWS_APIC_irqs();
451 #endif
452 /*
453 * Cover the whole vector space, no vector can escape
454 * us. (some of these will be overridden and become
455 * 'special' SMP interrupts)
456 */
457 for (i = 0; i < NR_IRQS; i++) {
458 int vector = FIRST_EXTERNAL_VECTOR + i;
459 if (vector != SYSCALL_VECTOR)
460 set_intr_gate(vector, interrupt[i]);
461 }
462
463 #ifdef CONFIG_SMP
464 /*
465 * IRQ0 must be given a fixed assignment and initialized,
466 * because it's used before the IO-APIC is set up.
467 */
468 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
469
470 /*
471 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
472 * IPI, driven by wakeup.
473 */
474 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
475
476 /* IPI for invalidation */
477 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
478
479 /* IPI for generic function call */
480 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
481 #endif
482
483 #ifdef CONFIG_X86_LOCAL_APIC
484 /* self generated IPI for local APIC timer */
485 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
486
487 /* IPI vectors for APIC spurious and error interrupts */
488 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
489 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
490 #endif
491
492 /*
493 * Set the clock to HZ Hz, we already have a valid
494 * vector now:
495 */
496 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
497 outb_p(LATCH & 0xff , 0x40); /* LSB */
498 outb(LATCH >> 8 , 0x40); /* MSB */
499
500 #ifndef CONFIG_VISWS
501 setup_irq(2, &irq2);
502 #endif
503
504 /*
505 * External FPU? Set up irq13 if so, for
506 * original braindamaged IBM FERR coupling.
507 */
508 if (boot_cpu_data.hard_math && !cpu_has_fpu)
509 setup_irq(13, &irq13);
510 }
511