File: /usr/src/linux/drivers/scsi/gdth.h
1 #ifndef _GDTH_H
2 #define _GDTH_H
3
4 /*
5 * Header file for the GDT ISA/EISA/PCI Disk Array Controller driver for Linux
6 *
7 * gdth.h Copyright (C) 1995-01 ICP vortex Computersysteme GmbH, Achim Leubner
8 * See gdth.c for further informations and
9 * below for supported controller types
10 *
11 * <achim@vortex.de>
12 *
13 * $Id: gdth.h,v 1.44 2001/08/21 11:19:05 achim Exp $
14 */
15
16 #include <linux/version.h>
17 #include <linux/types.h>
18
19 #ifndef NULL
20 #define NULL 0
21 #endif
22 #ifndef TRUE
23 #define TRUE 1
24 #endif
25 #ifndef FALSE
26 #define FALSE 0
27 #endif
28
29 /* defines, macros */
30
31 /* driver version */
32 #define GDTH_VERSION_STR "2.03"
33 #define GDTH_VERSION 2
34 #define GDTH_SUBVERSION 3
35
36 /* protocol version */
37 #define PROTOCOL_VERSION 1
38
39 /* OEM IDs */
40 #define OEM_ID_ICP 0x941c
41 #define OEM_ID_INTEL 0x8000
42
43 /* controller classes */
44 #define GDT_ISA 0x01 /* ISA controller */
45 #define GDT_EISA 0x02 /* EISA controller */
46 #define GDT_PCI 0x03 /* PCI controller */
47 #define GDT_PCINEW 0x04 /* new PCI controller */
48 #define GDT_PCIMPR 0x05 /* PCI MPR controller */
49 /* GDT_EISA, controller subtypes EISA */
50 #define GDT3_ID 0x0130941c /* GDT3000/3020 */
51 #define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */
52 #define GDT3B_ID 0x0330941c /* GDT3000B/3010A */
53 /* GDT_ISA */
54 #define GDT2_ID 0x0120941c /* GDT2000/2020 */
55
56 /* vendor ID, device IDs (PCI) */
57 /* these defines should already exist in <linux/pci.h> */
58 #ifndef PCI_VENDOR_ID_VORTEX
59 #define PCI_VENDOR_ID_VORTEX 0x1119 /* PCI controller vendor ID */
60 #endif
61 #ifndef PCI_VENDOR_ID_INTEL
62 #define PCI_VENDOR_ID_INTEL 0x8086
63 #endif
64
65 #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
66 /* GDT_PCI */
67 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
68 #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
69 /* GDT_PCINEW */
70 #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
71 #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
72 #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
73 #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
74 /* GDT_PCINEW, wide/ultra SCSI controllers */
75 #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
76 #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
77 #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
78 #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
79 /* GDT_PCINEW, wide SCSI controllers */
80 #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
81 #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
82 #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
83 #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
84 #endif
85
86 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
87 /* GDT_MPR, RP series, wide/ultra SCSI */
88 #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
89 #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
90 #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
91 #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
92 /* GDT_MPR, RP series, narrow/ultra SCSI */
93 #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
94 #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
95 #endif
96 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
97 /* GDT_MPR, RD series, wide/ultra SCSI */
98 #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
99 #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
100 #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
101 #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
102 /* GDT_MPR, RD series, narrow/ultra SCSI */
103 #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
104 #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
105 /* GDT_MPR, RD series, wide/ultra2 SCSI */
106 #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
107 GDT6618RD */
108 #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
109 GDT6628RD */
110 #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
111 #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
112 /* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
113 #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
114 GDT7618RN */
115 #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
116 GDT7628RN */
117 #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
118 #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
119 #endif
120
121 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
122 /* GDT_MPR, RD series, Fibre Channel */
123 #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
124 #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
125 /* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
126 #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
127 #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
128 #endif
129
130 #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
131 /* GDT_MPR, last device ID */
132 #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
133 #endif
134
135 #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
136 /* new GDT Rx Controller */
137 #define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300
138 #endif
139
140 #ifndef PCI_DEVICE_ID_INTEL_SRC
141 /* Intel Storage RAID Controller */
142 #define PCI_DEVICE_ID_INTEL_SRC 0x600
143 #endif
144
145 /* limits */
146 #define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */
147 #define GDTH_SCRATCH_ORD 0 /* order 0 means 1 page */
148 #define GDTH_MAXCMDS 124
149 #define GDTH_MAXC_P_L 16 /* max. cmds per lun */
150 #define GDTH_MAX_RAW 2 /* max. cmds per raw device */
151 #define MAXOFFSETS 128
152 #define MAXHA 16
153 #define MAXID 127
154 #define MAXLUN 8
155 #define MAXBUS 6
156 #define MAX_HDRIVES 100 /* max. host drive count */
157 #define MAX_LDRIVES 255 /* max. log. drive count */
158 #define MAX_EVENTS 100 /* event buffer count */
159 #define MAX_RES_ARGS 40 /* device reservation,
160 must be a multiple of 4 */
161 #define MAXCYLS 1024
162 #define HEADS 64
163 #define SECS 32 /* mapping 64*32 */
164 #define MEDHEADS 127
165 #define MEDSECS 63 /* mapping 127*63 */
166 #define BIGHEADS 255
167 #define BIGSECS 63 /* mapping 255*63 */
168
169 /* special command ptr. */
170 #define UNUSED_CMND ((Scsi_Cmnd *)-1)
171 #define INTERNAL_CMND ((Scsi_Cmnd *)-2)
172 #define SCREEN_CMND ((Scsi_Cmnd *)-3)
173 #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
174
175 /* controller services */
176 #define SCSIRAWSERVICE 3
177 #define CACHESERVICE 9
178 #define SCREENSERVICE 11
179
180 /* screenservice defines */
181 #define MSG_INV_HANDLE -1 /* special message handle */
182 #define MSGLEN 16 /* size of message text */
183 #define MSG_SIZE 34 /* size of message structure */
184 #define MSG_REQUEST 0 /* async. event: message */
185
186 /* cacheservice defines */
187 #define SECTOR_SIZE 0x200 /* always 512 bytes per sec. */
188
189 /* DPMEM constants */
190 #define DPMEM_MAGIC 0xC0FFEE11
191 #define IC_HEADER_BYTES 48
192 #define IC_QUEUE_BYTES 4
193 #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
194
195 /* cluster_type constants */
196 #define CLUSTER_DRIVE 1
197 #define CLUSTER_MOUNTED 2
198 #define CLUSTER_RESERVED 4
199 #define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
200
201 /* commands for all services, cache service */
202 #define GDT_INIT 0 /* service initialization */
203 #define GDT_READ 1 /* read command */
204 #define GDT_WRITE 2 /* write command */
205 #define GDT_INFO 3 /* information about devices */
206 #define GDT_FLUSH 4 /* flush dirty cache buffers */
207 #define GDT_IOCTL 5 /* ioctl command */
208 #define GDT_DEVTYPE 9 /* additional information */
209 #define GDT_MOUNT 10 /* mount cache device */
210 #define GDT_UNMOUNT 11 /* unmount cache device */
211 #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
212 #define GDT_GET_FEAT 13 /* get features */
213 #define GDT_WRITE_THR 16 /* write through */
214 #define GDT_READ_THR 17 /* read through */
215 #define GDT_EXT_INFO 18 /* extended info */
216 #define GDT_RESET 19 /* controller reset */
217 #define GDT_RESERVE_DRV 20 /* reserve host drive */
218 #define GDT_RELEASE_DRV 21 /* release host drive */
219 #define GDT_CLUST_INFO 22 /* cluster info */
220 #define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/
221 #define GDT_CLUST_RESET 24 /* releases the cluster drives*/
222 #define GDT_FREEZE_IO 25 /* freezes all IOs */
223 #define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */
224
225 /* raw service commands */
226 #define GDT_RESERVE 14 /* reserve dev. to raw serv. */
227 #define GDT_RELEASE 15 /* release device */
228 #define GDT_RESERVE_ALL 16 /* reserve all devices */
229 #define GDT_RELEASE_ALL 17 /* release all devices */
230 #define GDT_RESET_BUS 18 /* reset bus */
231 #define GDT_SCAN_START 19 /* start device scan */
232 #define GDT_SCAN_END 20 /* stop device scan */
233
234 /* screen service commands */
235 #define GDT_REALTIME 3 /* realtime clock to screens. */
236
237 /* IOCTL command defines */
238 #define SCSI_DR_INFO 0x00 /* SCSI drive info */
239 #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
240 #define SCSI_DR_LIST 0x06 /* SCSI drive list */
241 #define SCSI_DEF_CNT 0x15 /* grown/primary defects */
242 #define DSK_STATISTICS 0x4b /* SCSI disk statistics */
243 #define IOCHAN_DESC 0x5d /* description of IO channel */
244 #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */
245 #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
246 #define ARRAY_INFO 0x12 /* array drive info */
247 #define ARRAY_DRV_LIST 0x0f /* array drive list */
248 #define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */
249 #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
250 #define CACHE_DRV_CNT 0x01 /* cache drive count */
251 #define CACHE_DRV_LIST 0x02 /* cache drive list */
252 #define CACHE_INFO 0x04 /* cache info */
253 #define CACHE_CONFIG 0x05 /* cache configuration */
254 #define CACHE_DRV_INFO 0x07 /* cache drive info */
255 #define BOARD_FEATURES 0x15 /* controller features */
256 #define BOARD_INFO 0x28 /* controller info */
257 #define HOST_GET 0x10001L /* get host drive list */
258 #define IO_CHANNEL 0x00020000L /* default IO channel */
259 #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
260
261 /* service errors */
262 #define S_OK 1 /* no error */
263 #define S_GENERR 6 /* general error */
264 #define S_BSY 7 /* controller busy */
265 #define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */
266 #define S_RAW_SCSI 12 /* raw serv.: target error */
267 #define S_RAW_ILL 0xff /* raw serv.: illegal */
268
269 /* timeout values */
270 #define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */
271 #define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */
272 #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
273
274 /* priorities */
275 #define DEFAULT_PRI 0x20
276 #define IOCTL_PRI 0x10
277 #define HIGH_PRI 0x08
278
279 /* data directions */
280 #define GDTH_DATA_IN 0x01000000L /* data from target */
281 #define GDTH_DATA_OUT 0x00000000L /* data to target */
282
283 /* BMIC registers (EISA controllers) */
284 #define ID0REG 0x0c80 /* board ID */
285 #define EINTENABREG 0x0c89 /* interrupt enable */
286 #define SEMA0REG 0x0c8a /* command semaphore */
287 #define SEMA1REG 0x0c8b /* status semaphore */
288 #define LDOORREG 0x0c8d /* local doorbell */
289 #define EDENABREG 0x0c8e /* EISA system doorbell enab. */
290 #define EDOORREG 0x0c8f /* EISA system doorbell */
291 #define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */
292 #define EISAREG 0x0cc0 /* EISA configuration */
293
294 /* other defines */
295 #define LINUX_OS 8 /* used for cache optim. */
296 #define SCATTER_GATHER 1 /* s/g feature */
297 #define GDTH_MAXSG 32 /* max. s/g elements */
298 #define SECS32 0x1f /* round capacity */
299 #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
300 #define LOCALBOARD 0 /* board node always 0 */
301 #define ASYNCINDEX 0 /* cmd index async. event */
302 #define SPEZINDEX 1 /* cmd index unknown service */
303 #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
304
305
306 /* typedefs */
307 typedef u32 ulong32;
308 #define PACKED __attribute__((packed))
309
310 /* screenservice message */
311 typedef struct {
312 ulong32 msg_handle; /* message handle */
313 ulong32 msg_len; /* size of message */
314 ulong32 msg_alen; /* answer length */
315 unchar msg_answer; /* answer flag */
316 unchar msg_ext; /* more messages */
317 unchar msg_reserved[2];
318 char msg_text[MSGLEN+2]; /* the message text */
319 } PACKED gdth_msg_str;
320
321 /* IOCTL data structures */
322 /* SCSI drive info */
323 typedef struct {
324 unchar vendor[8]; /* vendor string */
325 unchar product[16]; /* product string */
326 unchar revision[4]; /* revision */
327 ulong32 sy_rate; /* current rate for sync. tr. */
328 ulong32 sy_max_rate; /* max. rate for sync. tr. */
329 ulong32 no_ldrive; /* belongs to this log. drv.*/
330 ulong32 blkcnt; /* number of blocks */
331 ushort blksize; /* size of block in bytes */
332 unchar available; /* flag: access is available */
333 unchar init; /* medium is initialized */
334 unchar devtype; /* SCSI devicetype */
335 unchar rm_medium; /* medium is removable */
336 unchar wp_medium; /* medium is write protected */
337 unchar ansi; /* SCSI I/II or III? */
338 unchar protocol; /* same as ansi */
339 unchar sync; /* flag: sync. transfer enab. */
340 unchar disc; /* flag: disconnect enabled */
341 unchar queueing; /* flag: command queing enab. */
342 unchar cached; /* flag: caching enabled */
343 unchar target_id; /* target ID of device */
344 unchar lun; /* LUN id of device */
345 unchar orphan; /* flag: drive fragment */
346 ulong32 last_error; /* sense key or drive state */
347 ulong32 last_result; /* result of last command */
348 ulong32 check_errors; /* err. in last surface check */
349 unchar percent; /* progress for surface check */
350 unchar last_check; /* IOCTRL operation */
351 unchar res[2];
352 ulong32 flags; /* from 1.19/2.19: raw reserv.*/
353 unchar multi_bus; /* multi bus dev? (fibre ch.) */
354 unchar mb_status; /* status: available? */
355 unchar res2[2];
356 unchar mb_alt_status; /* status on second bus */
357 unchar mb_alt_bid; /* number of second bus */
358 unchar mb_alt_tid; /* target id on second bus */
359 unchar res3;
360 unchar fc_flag; /* from 1.22/2.22: info valid?*/
361 unchar res4;
362 ushort fc_frame_size; /* frame size (bytes) */
363 char wwn[8]; /* world wide name */
364 } PACKED gdth_diskinfo_str;
365
366 /* get SCSI channel count */
367 typedef struct {
368 ulong32 channel_no; /* number of channel */
369 ulong32 drive_cnt; /* drive count */
370 unchar siop_id; /* SCSI processor ID */
371 unchar siop_state; /* SCSI processor state */
372 } PACKED gdth_getch_str;
373
374 /* get SCSI drive numbers */
375 typedef struct {
376 ulong32 sc_no; /* SCSI channel */
377 ulong32 sc_cnt; /* sc_list[] elements */
378 ulong32 sc_list[MAXID]; /* minor device numbers */
379 } PACKED gdth_drlist_str;
380
381 /* get grown/primary defect count */
382 typedef struct {
383 unchar sddc_type; /* 0x08: grown, 0x10: prim. */
384 unchar sddc_format; /* list entry format */
385 unchar sddc_len; /* list entry length */
386 unchar sddc_res;
387 ulong32 sddc_cnt; /* entry count */
388 } PACKED gdth_defcnt_str;
389
390 /* disk statistics */
391 typedef struct {
392 ulong32 bid; /* SCSI channel */
393 ulong32 first; /* first SCSI disk */
394 ulong32 entries; /* number of elements */
395 ulong32 count; /* (R) number of init. el. */
396 ulong32 mon_time; /* time stamp */
397 struct {
398 unchar tid; /* target ID */
399 unchar lun; /* LUN */
400 unchar res[2];
401 ulong32 blk_size; /* block size in bytes */
402 ulong32 rd_count; /* bytes read */
403 ulong32 wr_count; /* bytes written */
404 ulong32 rd_blk_count; /* blocks read */
405 ulong32 wr_blk_count; /* blocks written */
406 ulong32 retries; /* retries */
407 ulong32 reassigns; /* reassigns */
408 } PACKED list[1];
409 } PACKED gdth_dskstat_str;
410
411 /* IO channel header */
412 typedef struct {
413 ulong32 version; /* version (-1UL: newest) */
414 unchar list_entries; /* list entry count */
415 unchar first_chan; /* first channel number */
416 unchar last_chan; /* last channel number */
417 unchar chan_count; /* (R) channel count */
418 ulong32 list_offset; /* offset of list[0] */
419 } PACKED gdth_iochan_header;
420
421 /* get IO channel description */
422 typedef struct {
423 gdth_iochan_header hdr;
424 struct {
425 ulong32 address; /* channel address */
426 unchar type; /* type (SCSI, FCAL) */
427 unchar local_no; /* local number */
428 ushort features; /* channel features */
429 } PACKED list[MAXBUS];
430 } PACKED gdth_iochan_str;
431
432 /* get raw IO channel description */
433 typedef struct {
434 gdth_iochan_header hdr;
435 struct {
436 unchar proc_id; /* processor id */
437 unchar proc_defect; /* defect ? */
438 unchar reserved[2];
439 } PACKED list[MAXBUS];
440 } PACKED gdth_raw_iochan_str;
441
442 /* array drive component */
443 typedef struct {
444 ulong32 al_controller; /* controller ID */
445 unchar al_cache_drive; /* cache drive number */
446 unchar al_status; /* cache drive state */
447 unchar al_res[2];
448 } PACKED gdth_arraycomp_str;
449
450 /* array drive information */
451 typedef struct {
452 unchar ai_type; /* array type (RAID0,4,5) */
453 unchar ai_cache_drive_cnt; /* active cachedrives */
454 unchar ai_state; /* array drive state */
455 unchar ai_master_cd; /* master cachedrive */
456 ulong32 ai_master_controller; /* ID of master controller */
457 ulong32 ai_size; /* user capacity [sectors] */
458 ulong32 ai_striping_size; /* striping size [sectors] */
459 ulong32 ai_secsize; /* sector size [bytes] */
460 ulong32 ai_err_info; /* failed cache drive */
461 unchar ai_name[8]; /* name of the array drive */
462 unchar ai_controller_cnt; /* number of controllers */
463 unchar ai_removable; /* flag: removable */
464 unchar ai_write_protected; /* flag: write protected */
465 unchar ai_devtype; /* type: always direct access */
466 gdth_arraycomp_str ai_drives[35]; /* drive components: */
467 unchar ai_drive_entries; /* number of drive components */
468 unchar ai_protected; /* protection flag */
469 unchar ai_verify_state; /* state of a parity verify */
470 unchar ai_ext_state; /* extended array drive state */
471 unchar ai_expand_state; /* array expand state (>=2.18)*/
472 unchar ai_reserved[3];
473 } PACKED gdth_arrayinf_str;
474
475 /* get array drive list */
476 typedef struct {
477 ulong32 controller_no; /* controller no. */
478 unchar cd_handle; /* master cachedrive */
479 unchar is_arrayd; /* Flag: is array drive? */
480 unchar is_master; /* Flag: is array master? */
481 unchar is_parity; /* Flag: is parity drive? */
482 unchar is_hotfix; /* Flag: is hotfix drive? */
483 unchar res[3];
484 } PACKED gdth_alist_str;
485
486 typedef struct {
487 ulong32 entries_avail; /* allocated entries */
488 ulong32 entries_init; /* returned entries */
489 ulong32 first_entry; /* first entry number */
490 ulong32 list_offset; /* offset of following list */
491 gdth_alist_str list[1]; /* list */
492 } PACKED gdth_arcdl_str;
493
494 /* cache info/config IOCTL */
495 typedef struct {
496 ulong32 version; /* firmware version */
497 ushort state; /* cache state (on/off) */
498 ushort strategy; /* cache strategy */
499 ushort write_back; /* write back state (on/off) */
500 ushort block_size; /* cache block size */
501 } PACKED gdth_cpar_str;
502
503 typedef struct {
504 ulong32 csize; /* cache size */
505 ulong32 read_cnt; /* read/write counter */
506 ulong32 write_cnt;
507 ulong32 tr_hits; /* hits */
508 ulong32 sec_hits;
509 ulong32 sec_miss; /* misses */
510 } PACKED gdth_cstat_str;
511
512 typedef struct {
513 gdth_cpar_str cpar;
514 gdth_cstat_str cstat;
515 } PACKED gdth_cinfo_str;
516
517 /* cache drive info */
518 typedef struct {
519 unchar cd_name[8]; /* cache drive name */
520 ulong32 cd_devtype; /* SCSI devicetype */
521 ulong32 cd_ldcnt; /* number of log. drives */
522 ulong32 cd_last_error; /* last error */
523 unchar cd_initialized; /* drive is initialized */
524 unchar cd_removable; /* media is removable */
525 unchar cd_write_protected; /* write protected */
526 unchar cd_flags; /* Pool Hot Fix? */
527 ulong32 ld_blkcnt; /* number of blocks */
528 ulong32 ld_blksize; /* blocksize */
529 ulong32 ld_dcnt; /* number of disks */
530 ulong32 ld_slave; /* log. drive index */
531 ulong32 ld_dtype; /* type of logical drive */
532 ulong32 ld_last_error; /* last error */
533 unchar ld_name[8]; /* log. drive name */
534 unchar ld_error; /* error */
535 } PACKED gdth_cdrinfo_str;
536
537 /* board features */
538 typedef struct {
539 unchar chaining; /* Chaining supported */
540 unchar striping; /* Striping (RAID-0) supp. */
541 unchar mirroring; /* Mirroring (RAID-1) supp. */
542 unchar raid; /* RAID-4/5/10 supported */
543 } PACKED gdth_bfeat_str;
544
545 /* board info IOCTL */
546 typedef struct {
547 ulong32 ser_no; /* serial no. */
548 unchar oem_id[2]; /* OEM ID */
549 ushort ep_flags; /* eprom flags */
550 ulong32 proc_id; /* processor ID */
551 ulong32 memsize; /* memory size (bytes) */
552 unchar mem_banks; /* memory banks */
553 unchar chan_type; /* channel type */
554 unchar chan_count; /* channel count */
555 unchar rdongle_pres; /* dongle present? */
556 ulong32 epr_fw_ver; /* (eprom) firmware version */
557 ulong32 upd_fw_ver; /* (update) firmware version */
558 ulong32 upd_revision; /* update revision */
559 char type_string[16]; /* controller name */
560 char raid_string[16]; /* RAID firmware name */
561 unchar update_pres; /* update present? */
562 unchar xor_pres; /* XOR engine present? */
563 unchar prom_type; /* ROM type (eprom/flash) */
564 unchar prom_count; /* number of ROM devices */
565 ulong32 dup_pres; /* duplexing module present? */
566 ulong32 chan_pres; /* number of expansion chn. */
567 ulong32 mem_pres; /* memory expansion inst. ? */
568 unchar ft_bus_system; /* fault bus supported? */
569 unchar subtype_valid; /* board_subtype valid? */
570 unchar board_subtype; /* subtype/hardware level */
571 unchar ramparity_pres; /* RAM parity check hardware? */
572 } PACKED gdth_binfo_str;
573
574 /* get host drive info */
575 typedef struct {
576 char name[8]; /* host drive name */
577 ulong32 size; /* size (sectors) */
578 unchar host_drive; /* host drive number */
579 unchar log_drive; /* log. drive (master) */
580 unchar reserved;
581 unchar rw_attribs; /* r/w attribs */
582 ulong32 start_sec; /* start sector */
583 } PACKED gdth_hentry_str;
584
585 typedef struct {
586 ulong32 entries; /* entry count */
587 ulong32 offset; /* offset of entries */
588 unchar secs_p_head; /* sectors/head */
589 unchar heads_p_cyl; /* heads/cylinder */
590 unchar reserved;
591 unchar clust_drvtype; /* cluster drive type */
592 ulong32 location; /* controller number */
593 gdth_hentry_str entry[MAX_HDRIVES]; /* entries */
594 } PACKED gdth_hget_str;
595
596 /* scatter/gather element */
597 typedef struct {
598 ulong32 sg_ptr; /* address */
599 ulong32 sg_len; /* length */
600 } PACKED gdth_sg_str;
601
602 /* command structure */
603 typedef struct {
604 ulong32 BoardNode; /* board node (always 0) */
605 ulong32 CommandIndex; /* command number */
606 ushort OpCode; /* the command (READ,..) */
607 union {
608 struct {
609 ushort DeviceNo; /* number of cache drive */
610 ulong32 BlockNo; /* block number */
611 ulong32 BlockCnt; /* block count */
612 ulong32 DestAddr; /* dest. addr. (if s/g: -1) */
613 ulong32 sg_canz; /* s/g element count */
614 gdth_sg_str sg_lst[GDTH_MAXSG]; /* s/g list */
615 } PACKED cache; /* cache service cmd. str. */
616 struct {
617 ushort param_size; /* size of p_param buffer */
618 ulong32 subfunc; /* IOCTL function */
619 ulong32 channel; /* device */
620 ulong32 p_param; /* buffer */
621 } PACKED ioctl; /* IOCTL command structure */
622 struct {
623 ushort reserved;
624 union {
625 struct {
626 ulong32 msg_handle; /* message handle */
627 ulong32 msg_addr; /* message buffer address */
628 } PACKED msg;
629 unchar data[12]; /* buffer for rtc data, ... */
630 } su;
631 } PACKED screen; /* screen service cmd. str. */
632 struct {
633 ushort reserved;
634 ulong32 direction; /* data direction */
635 ulong32 mdisc_time; /* disc. time (0: no timeout)*/
636 ulong32 mcon_time; /* connect time(0: no to.) */
637 ulong32 sdata; /* dest. addr. (if s/g: -1) */
638 ulong32 sdlen; /* data length (bytes) */
639 ulong32 clen; /* SCSI cmd. length(6,10,12) */
640 unchar cmd[12]; /* SCSI command */
641 unchar target; /* target ID */
642 unchar lun; /* LUN */
643 unchar bus; /* SCSI bus number */
644 unchar priority; /* only 0 used */
645 ulong32 sense_len; /* sense data length */
646 ulong32 sense_data; /* sense data addr. */
647 ulong32 link_p; /* linked cmds (not supp.) */
648 ulong32 sg_ranz; /* s/g element count */
649 gdth_sg_str sg_lst[GDTH_MAXSG]; /* s/g list */
650 } PACKED raw; /* raw service cmd. struct. */
651 } u;
652 /* additional variables */
653 unchar Service; /* controller service */
654 ushort Status; /* command result */
655 ulong32 Info; /* additional information */
656 Scsi_Cmnd *RequestBuffer; /* request buffer */
657 } PACKED gdth_cmd_str;
658
659 /* controller event structure */
660 #define ES_ASYNC 1
661 #define ES_DRIVER 2
662 #define ES_TEST 3
663 #define ES_SYNC 4
664 typedef struct {
665 ushort size; /* size of structure */
666 union {
667 char stream[16];
668 struct {
669 ushort ionode;
670 ushort service;
671 ulong32 index;
672 } PACKED driver;
673 struct {
674 ushort ionode;
675 ushort service;
676 ushort status;
677 ulong32 info;
678 unchar scsi_coord[3];
679 } PACKED async;
680 struct {
681 ushort ionode;
682 ushort service;
683 ushort status;
684 ulong32 info;
685 ushort hostdrive;
686 unchar scsi_coord[3];
687 unchar sense_key;
688 } PACKED sync;
689 struct {
690 ulong32 l1, l2, l3, l4;
691 } PACKED test;
692 } eu;
693 ulong32 severity;
694 unchar event_string[256];
695 } PACKED gdth_evt_data;
696
697 typedef struct {
698 ulong32 first_stamp;
699 ulong32 last_stamp;
700 ushort same_count;
701 ushort event_source;
702 ushort event_idx;
703 unchar application;
704 unchar reserved;
705 gdth_evt_data event_data;
706 } PACKED gdth_evt_str;
707
708
709 /* DPRAM structures */
710
711 /* interface area ISA/PCI */
712 typedef struct {
713 unchar S_Cmd_Indx; /* special command */
714 unchar volatile S_Status; /* status special command */
715 ushort reserved1;
716 ulong32 S_Info[4]; /* add. info special command */
717 unchar volatile Sema0; /* command semaphore */
718 unchar reserved2[3];
719 unchar Cmd_Index; /* command number */
720 unchar reserved3[3];
721 ushort volatile Status; /* command status */
722 ushort Service; /* service(for async.events) */
723 ulong32 Info[2]; /* additional info */
724 struct {
725 ushort offset; /* command offs. in the DPRAM*/
726 ushort serv_id; /* service */
727 } PACKED comm_queue[MAXOFFSETS]; /* command queue */
728 ulong32 bios_reserved[2];
729 unchar gdt_dpr_cmd[1]; /* commands */
730 } PACKED gdt_dpr_if;
731
732 /* SRAM structure PCI controllers */
733 typedef struct {
734 ulong32 magic; /* controller ID from BIOS */
735 ushort need_deinit; /* switch betw. BIOS/driver */
736 unchar switch_support; /* see need_deinit */
737 unchar padding[9];
738 unchar os_used[16]; /* OS code per service */
739 unchar unused[28];
740 unchar fw_magic; /* contr. ID from firmware */
741 } PACKED gdt_pci_sram;
742
743 /* SRAM structure EISA controllers (but NOT GDT3000/3020) */
744 typedef struct {
745 unchar os_used[16]; /* OS code per service */
746 ushort need_deinit; /* switch betw. BIOS/driver */
747 unchar switch_support; /* see need_deinit */
748 unchar padding;
749 } PACKED gdt_eisa_sram;
750
751
752 /* DPRAM ISA controllers */
753 typedef struct {
754 union {
755 struct {
756 unchar bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
757 ulong32 magic; /* controller (EISA) ID */
758 ushort need_deinit; /* switch betw. BIOS/driver */
759 unchar switch_support; /* see need_deinit */
760 unchar padding[9];
761 unchar os_used[16]; /* OS code per service */
762 } PACKED dp_sram;
763 unchar bios_area[0x4000]; /* 16KB reserved for BIOS */
764 } bu;
765 union {
766 gdt_dpr_if ic; /* interface area */
767 unchar if_area[0x3000]; /* 12KB for interface */
768 } u;
769 struct {
770 unchar memlock; /* write protection DPRAM */
771 unchar event; /* release event */
772 unchar irqen; /* board interrupts enable */
773 unchar irqdel; /* acknowledge board int. */
774 unchar volatile Sema1; /* status semaphore */
775 unchar rq; /* IRQ/DRQ configuration */
776 } PACKED io;
777 } PACKED gdt2_dpram_str;
778
779 /* DPRAM PCI controllers */
780 typedef struct {
781 union {
782 gdt_dpr_if ic; /* interface area */
783 unchar if_area[0xff0-sizeof(gdt_pci_sram)];
784 } u;
785 gdt_pci_sram gdt6sr; /* SRAM structure */
786 struct {
787 unchar unused0[1];
788 unchar volatile Sema1; /* command semaphore */
789 unchar unused1[3];
790 unchar irqen; /* board interrupts enable */
791 unchar unused2[2];
792 unchar event; /* release event */
793 unchar unused3[3];
794 unchar irqdel; /* acknowledge board int. */
795 unchar unused4[3];
796 } PACKED io;
797 } PACKED gdt6_dpram_str;
798
799 /* PLX register structure (new PCI controllers) */
800 typedef struct {
801 unchar cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
802 unchar unused1[0x3f];
803 unchar volatile sema0_reg; /* command semaphore */
804 unchar volatile sema1_reg; /* status semaphore */
805 unchar unused2[2];
806 ushort volatile status; /* command status */
807 ushort service; /* service */
808 ulong32 info[2]; /* additional info */
809 unchar unused3[0x10];
810 unchar ldoor_reg; /* PCI to local doorbell */
811 unchar unused4[3];
812 unchar volatile edoor_reg; /* local to PCI doorbell */
813 unchar unused5[3];
814 unchar control0; /* control0 register(unused) */
815 unchar control1; /* board interrupts enable */
816 unchar unused6[0x16];
817 } PACKED gdt6c_plx_regs;
818
819 /* DPRAM new PCI controllers */
820 typedef struct {
821 union {
822 gdt_dpr_if ic; /* interface area */
823 unchar if_area[0x4000-sizeof(gdt_pci_sram)];
824 } u;
825 gdt_pci_sram gdt6sr; /* SRAM structure */
826 } PACKED gdt6c_dpram_str;
827
828 /* i960 register structure (PCI MPR controllers) */
829 typedef struct {
830 unchar unused1[16];
831 unchar volatile sema0_reg; /* command semaphore */
832 unchar unused2;
833 unchar volatile sema1_reg; /* status semaphore */
834 unchar unused3;
835 ushort volatile status; /* command status */
836 ushort service; /* service */
837 ulong32 info[2]; /* additional info */
838 unchar ldoor_reg; /* PCI to local doorbell */
839 unchar unused4[11];
840 unchar volatile edoor_reg; /* local to PCI doorbell */
841 unchar unused5[7];
842 unchar edoor_en_reg; /* board interrupts enable */
843 unchar unused6[27];
844 ulong32 unused7[939];
845 ulong32 severity;
846 char evt_str[256]; /* event string */
847 } PACKED gdt6m_i960_regs;
848
849 /* DPRAM PCI MPR controllers */
850 typedef struct {
851 gdt6m_i960_regs i960r; /* 4KB i960 registers */
852 union {
853 gdt_dpr_if ic; /* interface area */
854 unchar if_area[0x3000-sizeof(gdt_pci_sram)];
855 } u;
856 gdt_pci_sram gdt6sr; /* SRAM structure */
857 } PACKED gdt6m_dpram_str;
858
859
860 /* PCI resources */
861 typedef struct {
862 #if LINUX_VERSION_CODE >= 0x02015C
863 struct pci_dev *pdev;
864 #endif
865 ushort vendor_id; /* vendor (ICP, Intel, ..) */
866 ushort device_id; /* device ID (0,..,9) */
867 ushort subdevice_id; /* sub device ID */
868 unchar bus; /* PCI bus */
869 unchar device_fn; /* PCI device/function no. */
870 ulong dpmem; /* DPRAM address */
871 ulong io; /* IO address */
872 ulong io_mm; /* IO address mem. mapped */
873 unchar irq; /* IRQ */
874 } gdth_pci_str;
875
876
877 /* controller information structure */
878 typedef struct {
879 ushort oem_id; /* OEM */
880 ushort type; /* controller class */
881 ushort raw_feat; /* feat. raw service (s/g,..) */
882 ulong32 stype; /* subtype (PCI: device ID) */
883 ushort subdevice_id; /* sub device ID (PCI) */
884 ushort fw_vers; /* firmware version */
885 ushort cache_feat; /* feat. cache serv. (s/g,..) */
886 ushort bmic; /* BMIC address (EISA) */
887 void *brd; /* DPRAM address */
888 ulong32 brd_phys; /* slot number/BIOS address */
889 gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
890 gdth_cmd_str *pccb; /* address command structure */
891 char *pscratch; /* scratch (DMA) buffer */
892 unchar scratch_busy; /* in use? */
893 unchar scan_mode; /* current scan mode */
894 unchar irq; /* IRQ */
895 unchar drq; /* DRQ (ISA controllers) */
896 ushort status; /* command status */
897 ushort service; /* service/firmware ver./.. */
898 ulong32 info;
899 ulong32 info2; /* additional info */
900 Scsi_Cmnd *req_first; /* top of request queue */
901 struct {
902 unchar present; /* Flag: host drive present? */
903 unchar is_logdrv; /* Flag: log. drive (master)? */
904 unchar is_arraydrv; /* Flag: array drive? */
905 unchar is_master; /* Flag: array drive master? */
906 unchar is_parity; /* Flag: parity drive? */
907 unchar is_hotfix; /* Flag: hotfix drive? */
908 unchar master_no; /* number of master drive */
909 unchar lock; /* drive locked? (hot plug) */
910 unchar heads; /* mapping */
911 unchar secs;
912 ushort devtype; /* further information */
913 ulong32 size; /* capacity */
914 unchar ldr_no; /* log. drive no. */
915 unchar rw_attribs; /* r/w attributes */
916 unchar cluster_type; /* cluster properties */
917 unchar media_changed; /* Flag:MOUNT/UNMOUNT occured */
918 ulong32 start_sec; /* start sector */
919 } hdr[MAX_LDRIVES]; /* host drives */
920 struct {
921 unchar lock; /* channel locked? (hot plug) */
922 unchar pdev_cnt; /* physical device count */
923 unchar local_no; /* local channel number */
924 unchar io_cnt[MAXID]; /* current IO count */
925 ulong32 address; /* channel address */
926 ulong32 id_list[MAXID]; /* IDs of the phys. devices */
927 } raw[MAXBUS]; /* SCSI channels */
928 struct {
929 Scsi_Cmnd *cmnd; /* pending request */
930 ushort service; /* service */
931 } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */
932 unchar bus_cnt; /* SCSI bus count */
933 unchar tid_cnt; /* Target ID count */
934 unchar bus_id[MAXBUS]; /* IOP IDs */
935 unchar virt_bus; /* number of virtual bus */
936 unchar more_proc; /* more /proc info supported */
937 ushort cmd_cnt; /* command count in DPRAM */
938 ushort cmd_len; /* length of actual command */
939 ushort cmd_offs_dpmem; /* actual offset in DPRAM */
940 ushort ic_all_size; /* sizeof DPRAM interf. area */
941 gdth_cpar_str cpar; /* controller cache par. */
942 gdth_bfeat_str bfeat; /* controller features */
943 gdth_binfo_str binfo; /* controller info */
944 gdth_evt_data dvr; /* event structure */
945 #if LINUX_VERSION_CODE >= 0x02015F
946 spinlock_t smp_lock;
947 #endif
948 } gdth_ha_str;
949
950 /* structure for scsi_register(), SCSI bus != 0 */
951 typedef struct {
952 ushort hanum;
953 ushort busnum;
954 } gdth_num_str;
955
956 /* structure for scsi_register() */
957 typedef struct {
958 gdth_num_str numext; /* must be the first element */
959 gdth_ha_str haext;
960 gdth_cmd_str cmdext;
961 } gdth_ext_str;
962
963
964 /* INQUIRY data format */
965 typedef struct {
966 unchar type_qual;
967 unchar modif_rmb;
968 unchar version;
969 unchar resp_aenc;
970 unchar add_length;
971 unchar reserved1;
972 unchar reserved2;
973 unchar misc;
974 unchar vendor[8];
975 unchar product[16];
976 unchar revision[4];
977 } PACKED gdth_inq_data;
978
979 /* READ_CAPACITY data format */
980 typedef struct {
981 ulong32 last_block_no;
982 ulong32 block_length;
983 } PACKED gdth_rdcap_data;
984
985 /* REQUEST_SENSE data format */
986 typedef struct {
987 unchar errorcode;
988 unchar segno;
989 unchar key;
990 ulong32 info;
991 unchar add_length;
992 ulong32 cmd_info;
993 unchar adsc;
994 unchar adsq;
995 unchar fruc;
996 unchar key_spec[3];
997 } PACKED gdth_sense_data;
998
999 /* MODE_SENSE data format */
1000 typedef struct {
1001 struct {
1002 unchar data_length;
1003 unchar med_type;
1004 unchar dev_par;
1005 unchar bd_length;
1006 } PACKED hd;
1007 struct {
1008 unchar dens_code;
1009 unchar block_count[3];
1010 unchar reserved;
1011 unchar block_length[3];
1012 } PACKED bd;
1013 } PACKED gdth_modep_data;
1014
1015 /* stack frame */
1016 typedef struct {
1017 ulong b[10]; /* 32/64 bit compiler ! */
1018 } PACKED gdth_stackframe;
1019
1020
1021 /* function prototyping */
1022
1023 int gdth_detect(Scsi_Host_Template *);
1024 int gdth_release(struct Scsi_Host *);
1025 int gdth_queuecommand(Scsi_Cmnd *,void (*done)(Scsi_Cmnd *));
1026 int gdth_abort(Scsi_Cmnd *);
1027 #if LINUX_VERSION_CODE >= 0x010346
1028 int gdth_reset(Scsi_Cmnd *, unsigned int reset_flags);
1029 #else
1030 int gdth_reset(Scsi_Cmnd *);
1031 #endif
1032 const char *gdth_info(struct Scsi_Host *);
1033
1034 #if LINUX_VERSION_CODE >= 0x020322
1035 int gdth_bios_param(Disk *,kdev_t,int *);
1036 int gdth_proc_info(char *,char **,off_t,int,int,int);
1037 int gdth_eh_abort(Scsi_Cmnd *scp);
1038 int gdth_eh_device_reset(Scsi_Cmnd *scp);
1039 int gdth_eh_bus_reset(Scsi_Cmnd *scp);
1040 int gdth_eh_host_reset(Scsi_Cmnd *scp);
1041 #define GDTH { proc_name: "gdth", \
1042 proc_info: gdth_proc_info, \
1043 name: "GDT SCSI Disk Array Controller",\
1044 detect: gdth_detect, \
1045 release: gdth_release, \
1046 info: gdth_info, \
1047 command: NULL, \
1048 queuecommand: gdth_queuecommand, \
1049 eh_abort_handler: gdth_eh_abort, \
1050 eh_device_reset_handler: gdth_eh_device_reset, \
1051 eh_bus_reset_handler: gdth_eh_bus_reset, \
1052 eh_host_reset_handler: gdth_eh_host_reset, \
1053 abort: gdth_abort, \
1054 reset: gdth_reset, \
1055 bios_param: gdth_bios_param, \
1056 can_queue: GDTH_MAXCMDS, \
1057 this_id: -1, \
1058 sg_tablesize: GDTH_MAXSG, \
1059 cmd_per_lun: GDTH_MAXC_P_L, \
1060 present: 0, \
1061 unchecked_isa_dma: 1, \
1062 use_clustering: ENABLE_CLUSTERING, \
1063 use_new_eh_code: 1 /* use new error code */ }
1064
1065 #elif LINUX_VERSION_CODE >= 0x02015F
1066 int gdth_bios_param(Disk *,kdev_t,int *);
1067 extern struct proc_dir_entry proc_scsi_gdth;
1068 int gdth_proc_info(char *,char **,off_t,int,int,int);
1069 int gdth_eh_abort(Scsi_Cmnd *scp);
1070 int gdth_eh_device_reset(Scsi_Cmnd *scp);
1071 int gdth_eh_bus_reset(Scsi_Cmnd *scp);
1072 int gdth_eh_host_reset(Scsi_Cmnd *scp);
1073 #define GDTH { proc_dir: &proc_scsi_gdth, \
1074 proc_info: gdth_proc_info, \
1075 name: "GDT SCSI Disk Array Controller",\
1076 detect: gdth_detect, \
1077 release: gdth_release, \
1078 info: gdth_info, \
1079 command: NULL, \
1080 queuecommand: gdth_queuecommand, \
1081 eh_abort_handler: gdth_eh_abort, \
1082 eh_device_reset_handler: gdth_eh_device_reset, \
1083 eh_bus_reset_handler: gdth_eh_bus_reset, \
1084 eh_host_reset_handler: gdth_eh_host_reset, \
1085 abort: gdth_abort, \
1086 reset: gdth_reset, \
1087 bios_param: gdth_bios_param, \
1088 can_queue: GDTH_MAXCMDS, \
1089 this_id: -1, \
1090 sg_tablesize: GDTH_MAXSG, \
1091 cmd_per_lun: GDTH_MAXC_P_L, \
1092 present: 0, \
1093 unchecked_isa_dma: 1, \
1094 use_clustering: ENABLE_CLUSTERING, \
1095 use_new_eh_code: 1 /* use new error code */ }
1096
1097 #elif LINUX_VERSION_CODE >= 0x010300
1098 int gdth_bios_param(Disk *,kdev_t,int *);
1099 extern struct proc_dir_entry proc_scsi_gdth;
1100 int gdth_proc_info(char *,char **,off_t,int,int,int);
1101 #define GDTH { NULL, NULL, \
1102 &proc_scsi_gdth, \
1103 gdth_proc_info, \
1104 "GDT SCSI Disk Array Controller", \
1105 gdth_detect, \
1106 gdth_release, \
1107 gdth_info, \
1108 NULL, \
1109 gdth_queuecommand, \
1110 gdth_abort, \
1111 gdth_reset, \
1112 NULL, \
1113 gdth_bios_param, \
1114 GDTH_MAXCMDS, \
1115 -1, \
1116 GDTH_MAXSG, \
1117 GDTH_MAXC_P_L, \
1118 0, \
1119 1, \
1120 ENABLE_CLUSTERING}
1121
1122 #else
1123 int gdth_bios_param(Disk *,int,int *);
1124 #define GDTH { NULL, NULL, \
1125 "GDT SCSI Disk Array Controller", \
1126 gdth_detect, \
1127 gdth_release, \
1128 gdth_info, \
1129 NULL, \
1130 gdth_queuecommand, \
1131 gdth_abort, \
1132 gdth_reset, \
1133 NULL, \
1134 gdth_bios_param, \
1135 GDTH_MAXCMDS, \
1136 -1, \
1137 GDTH_MAXSG, \
1138 GDTH_MAXC_P_L, \
1139 0, \
1140 1, \
1141 ENABLE_CLUSTERING}
1142 #endif
1143
1144 #endif
1145
1146