File: /usr/src/linux/drivers/scsi/i60uscsi.h
1 /**************************************************************************
2 * Initio A100 device driver for Linux.
3 *
4 * Copyright (c) 1994-1998 Initio Corporation
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * --------------------------------------------------------------------------
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions, and the following disclaimer,
28 * without modification, immediately at the beginning of the file.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
34 *
35 * Where this Software is combined with software released under the terms of
36 * the GNU General Public License ("GPL") and the terms of the GPL would require the
37 * combined work to also be released under the terms of the GPL, the terms
38 * and conditions of this License will apply in addition to those of the
39 * GPL with the exception of any terms or conditions of this License that
40 * conflict with, or are expressly prohibited by, the GPL.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
46 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * SUCH DAMAGE.
53 *
54 **************************************************************************
55 *
56 * Module: inia100.h
57 * Description: INI-A100U2W LINUX device driver header
58 * Revision History:
59 * 06/18/98 HL, Initial Version 1.02
60 * 12/19/98 bv, v1.02a Use spinlocks for 2.1.95 and up.
61 **************************************************************************/
62
63 #include <linux/config.h>
64
65 #define ULONG unsigned long
66 #define PVOID void *
67 #define USHORT unsigned short
68 #define UCHAR unsigned char
69 #define BYTE unsigned char
70 #define WORD unsigned short
71 #define DWORD unsigned long
72 #define UBYTE unsigned char
73 #define UWORD unsigned short
74 #define UDWORD unsigned long
75 #ifdef ALPHA
76 #define U32 unsigned int
77 #else
78 #define U32 unsigned long
79 #endif
80
81 #ifndef NULL
82 #define NULL 0 /* zero */
83 #endif
84 #ifndef TRUE
85 #define TRUE (1) /* boolean true */
86 #endif
87 #ifndef FALSE
88 #define FALSE (0) /* boolean false */
89 #endif
90 #ifndef FAILURE
91 #define FAILURE (-1)
92 #endif
93 #if 1
94 #define ORC_MAXQUEUE 245
95 #else
96 #define ORC_MAXQUEUE 25
97 #endif
98
99 #define TOTAL_SG_ENTRY 32
100 #define MAX_TARGETS 16
101 #define IMAX_CDB 15
102 #define SENSE_SIZE 14
103 #define MAX_SUPPORTED_ADAPTERS 4
104 #define SUCCESSFUL 0x00
105
106 #define I920_DEVICE_ID 0x0002 /* Initio's inic-950 product ID */
107
108 /************************************************************************/
109 /* Scatter-Gather Element Structure */
110 /************************************************************************/
111 typedef struct ORC_SG_Struc {
112 U32 SG_Ptr; /* Data Pointer */
113 U32 SG_Len; /* Data Length */
114 } ORC_SG;
115
116 typedef struct inia100_Adpt_Struc {
117 UWORD ADPT_BIOS; /* 0 */
118 UWORD ADPT_BASE; /* 1 */
119 UBYTE ADPT_Bus; /* 2 */
120 UBYTE ADPT_Device; /* 3 */
121 UBYTE ADPT_INTR; /* 4 */
122 } INIA100_ADPT_STRUCT;
123
124
125 /* SCSI related definition */
126 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
127 #define DISC_ALLOW 0xC0 /* Disconnect is allowed */
128
129
130 #define ORC_OFFSET_SCB 16
131 #define ORC_MAX_SCBS 250
132 #define MAX_CHANNELS 2
133 #define MAX_ESCB_ELE 64
134 #define TCF_DRV_255_63 0x0400
135
136 /********************************************************/
137 /* Orchid Configuration Register Set */
138 /********************************************************/
139 #define ORC_PVID 0x00 /* Vendor ID */
140 #define ORC_VENDOR_ID 0x1101 /* Orchid vendor ID */
141 #define ORC_PDID 0x02 /* Device ID */
142 #define ORC_DEVICE_ID 0x1060 /* Orchid device ID */
143 #define ORC_COMMAND 0x04 /* Command */
144 #define BUSMS 0x04 /* BUS MASTER Enable */
145 #define IOSPA 0x01 /* IO Space Enable */
146 #define ORC_STATUS 0x06 /* Status register */
147 #define ORC_REVISION 0x08 /* Revision number */
148 #define ORC_BASE 0x10 /* Base address */
149 #define ORC_BIOS 0x50 /* Expansion ROM base address */
150 #define ORC_INT_NUM 0x3C /* Interrupt line */
151 #define ORC_INT_PIN 0x3D /* Interrupt pin */
152
153
154 /********************************************************/
155 /* Orchid Host Command Set */
156 /********************************************************/
157 #define ORC_CMD_NOP 0x00 /* Host command - NOP */
158 #define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */
159 #define ORC_CMD_ECHO 0x02 /* Host command - ECHO */
160 #define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */
161 #define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */
162 #define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */
163 #define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */
164 #define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */
165
166 /********************************************************/
167 /* Orchid Register Set */
168 /********************************************************/
169 #define ORC_GINTS 0xA0 /* Global Interrupt Status */
170 #define QINT 0x04 /* Reply Queue Interrupt */
171 #define ORC_GIMSK 0xA1 /* Global Interrupt MASK */
172 #define MQINT 0x04 /* Mask Reply Queue Interrupt */
173 #define ORC_GCFG 0xA2 /* Global Configure */
174 #define EEPRG 0x01 /* Enable EEPROM programming */
175 #define ORC_GSTAT 0xA3 /* Global status */
176 #define WIDEBUS 0x10 /* Wide SCSI Devices connected */
177 #define ORC_HDATA 0xA4 /* Host Data */
178 #define ORC_HCTRL 0xA5 /* Host Control */
179 #define SCSIRST 0x80 /* SCSI bus reset */
180 #define HDO 0x40 /* Host data out */
181 #define HOSTSTOP 0x02 /* Host stop RISC engine */
182 #define DEVRST 0x01 /* Device reset */
183 #define ORC_HSTUS 0xA6 /* Host Status */
184 #define HDI 0x02 /* Host data in */
185 #define RREADY 0x01 /* RISC engine is ready to receive */
186 #define ORC_NVRAM 0xA7 /* Nvram port address */
187 #define SE2CS 0x008
188 #define SE2CLK 0x004
189 #define SE2DO 0x002
190 #define SE2DI 0x001
191 #define ORC_PQUEUE 0xA8 /* Posting queue FIFO */
192 #define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */
193 #define ORC_RQUEUE 0xAA /* Reply queue FIFO */
194 #define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */
195 #define ORC_FWBASEADR 0xAC /* Firmware base address */
196
197 #define ORC_EBIOSADR0 0xB0 /* External Bios address */
198 #define ORC_EBIOSADR1 0xB1 /* External Bios address */
199 #define ORC_EBIOSADR2 0xB2 /* External Bios address */
200 #define ORC_EBIOSDATA 0xB3 /* External Bios address */
201
202 #define ORC_SCBSIZE 0xB7 /* SCB size register */
203 #define ORC_SCBBASE0 0xB8 /* SCB base address 0 */
204 #define ORC_SCBBASE1 0xBC /* SCB base address 1 */
205
206 #define ORC_RISCCTL 0xE0 /* RISC Control */
207 #define PRGMRST 0x002
208 #define DOWNLOAD 0x001
209 #define ORC_PRGMCTR0 0xE2 /* RISC program counter */
210 #define ORC_PRGMCTR1 0xE3 /* RISC program counter */
211 #define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */
212
213 typedef struct orc_extended_scb { /* Extended SCB */
214 ORC_SG ESCB_SGList[TOTAL_SG_ENTRY]; /*0 Start of SG list */
215 unsigned char *SCB_Srb; /*50 SRB Pointer */
216 // Scsi_Cmnd *SCB_Srb; /*50 SRB Pointer */
217 } ESCB;
218
219 /***********************************************************************
220 SCSI Control Block
221 ************************************************************************/
222 typedef struct orc_scb { /* Scsi_Ctrl_Blk */
223 UBYTE SCB_Opcode; /*00 SCB command code&residual */
224 UBYTE SCB_Flags; /*01 SCB Flags */
225 UBYTE SCB_Target; /*02 Target Id */
226 UBYTE SCB_Lun; /*03 Lun */
227 U32 SCB_Reserved0; /*04 Reserved for ORCHID must 0 */
228 U32 SCB_XferLen; /*08 Data Transfer Length */
229 U32 SCB_Reserved1; /*0C Reserved for ORCHID must 0 */
230 U32 SCB_SGLen; /*10 SG list # * 8 */
231 U32 SCB_SGPAddr; /*14 SG List Buf physical Addr */
232 U32 SCB_SGPAddrHigh; /*18 SG Buffer high physical Addr */
233 UBYTE SCB_HaStat; /*1C Host Status */
234 UBYTE SCB_TaStat; /*1D Target Status */
235 UBYTE SCB_Status; /*1E SCB status */
236 UBYTE SCB_Link; /*1F Link pointer, default 0xFF */
237 UBYTE SCB_SenseLen; /*20 Sense Allocation Length */
238 UBYTE SCB_CDBLen; /*21 CDB Length */
239 UBYTE SCB_Ident; /*22 Identify */
240 UBYTE SCB_TagMsg; /*23 Tag Message */
241 UBYTE SCB_CDB[IMAX_CDB]; /*24 SCSI CDBs */
242 UBYTE SCB_ScbIdx; /*3C Index for this ORCSCB */
243 U32 SCB_SensePAddr; /*34 Sense Buffer physical Addr */
244
245 ESCB *SCB_EScb; /*38 Extended SCB Pointer */
246 #ifndef ALPHA
247 UBYTE SCB_Reserved2[4]; /*3E Reserved for Driver use */
248 #endif
249 } ORC_SCB;
250
251 /* Opcodes of ORCSCB_Opcode */
252 #define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */
253 #define ORC_BUSDEVRST 0x01 /* SCSI Bus Device Reset */
254
255 /* Status of ORCSCB_Status */
256 #define SCB_COMPLETE 0x00 /* SCB request completed */
257 #define SCB_POST 0x01 /* SCB is posted by the HOST */
258
259 /* Bit Definition for ORCSCB_Flags */
260 #define SCF_DISINT 0x01 /* Disable HOST interrupt */
261 #define SCF_DIR 0x18 /* Direction bits */
262 #define SCF_NO_DCHK 0x00 /* Direction determined by SCSI */
263 #define SCF_DIN 0x08 /* From Target to Initiator */
264 #define SCF_DOUT 0x10 /* From Initiator to Target */
265 #define SCF_NO_XF 0x18 /* No data transfer */
266 #define SCF_POLL 0x40
267
268 /* Error Codes for ORCSCB_HaStat */
269 #define HOST_SEL_TOUT 0x11
270 #define HOST_DO_DU 0x12
271 #define HOST_BUS_FREE 0x13
272 #define HOST_BAD_PHAS 0x14
273 #define HOST_INV_CMD 0x16
274 #define HOST_SCSI_RST 0x1B
275 #define HOST_DEV_RST 0x1C
276
277
278 /* Error Codes for ORCSCB_TaStat */
279 #define TARGET_CHK_COND 0x02
280 #define TARGET_BUSY 0x08
281 #define TARGET_TAG_FULL 0x28
282
283
284 /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
285 #define MSG_STAG 0x20
286 #define MSG_HTAG 0x21
287 #define MSG_OTAG 0x22
288
289 #define MSG_IGNOREWIDE 0x23
290
291 #define MSG_IDENT 0x80
292 #define MSG_DISC 0x40 /* Disconnect allowed */
293
294
295 /* SCSI MESSAGE */
296 #define MSG_EXTEND 0x01
297 #define MSG_SDP 0x02
298 #define MSG_ABORT 0x06
299 #define MSG_REJ 0x07
300 #define MSG_NOP 0x08
301 #define MSG_PARITY 0x09
302 #define MSG_DEVRST 0x0C
303 #define MSG_STAG 0x20
304
305 /***********************************************************************
306 Target Device Control Structure
307 **********************************************************************/
308
309 typedef struct ORC_Tar_Ctrl_Struc {
310 UBYTE TCS_DrvDASD; /* 6 */
311 UBYTE TCS_DrvSCSI; /* 7 */
312 UBYTE TCS_DrvHead; /* 8 */
313 UWORD TCS_DrvFlags; /* 4 */
314 UBYTE TCS_DrvSector; /* 7 */
315 } ORC_TCS, *PORC_TCS;
316
317 /* Bit Definition for TCF_DrvFlags */
318 #define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */
319 #define TCS_DF_NOSCSI_SUPT 0x40 /* Suppress OS/2 SCSI Mgr support */
320
321
322 /***********************************************************************
323 Host Adapter Control Structure
324 ************************************************************************/
325 typedef struct ORC_Ha_Ctrl_Struc {
326 USHORT HCS_Base; /* 00 */
327 UBYTE HCS_Index; /* 02 */
328 UBYTE HCS_Intr; /* 04 */
329 UBYTE HCS_SCSI_ID; /* 06 H/A SCSI ID */
330 UBYTE HCS_BIOS; /* 07 BIOS configuration */
331
332 UBYTE HCS_Flags; /* 0B */
333 UBYTE HCS_HAConfig1; /* 1B SCSI0MAXTags */
334 UBYTE HCS_MaxTar; /* 1B SCSI0MAXTags */
335
336 USHORT HCS_Units; /* Number of units this adapter */
337 USHORT HCS_AFlags; /* Adapter info. defined flags */
338 ULONG HCS_Timeout; /* Adapter timeout value */
339 PVOID HCS_virScbArray; /* 28 Virtual Pointer to SCB array */
340 U32 HCS_physScbArray; /* Scb Physical address */
341 PVOID HCS_virEscbArray; /* Virtual pointer to ESCB Scatter list */
342 U32 HCS_physEscbArray; /* scatter list Physical address */
343 UBYTE TargetFlag[16]; /* 30 target configuration, TCF_EN_TAG */
344 UBYTE MaximumTags[16]; /* 40 ORC_MAX_SCBS */
345 UBYTE ActiveTags[16][16]; /* 50 */
346 ORC_TCS HCS_Tcs[16]; /* 28 */
347 U32 BitAllocFlag[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */
348 #if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,95)
349 spinlock_t BitAllocFlagLock;
350 #endif
351 ULONG pSRB_head;
352 ULONG pSRB_tail;
353 #if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,95)
354 spinlock_t pSRB_lock;
355 #endif
356 } ORC_HCS;
357
358 /* Bit Definition for HCS_Flags */
359
360 #define HCF_SCSI_RESET 0x01 /* SCSI BUS RESET */
361 #define HCF_PARITY 0x02 /* parity card */
362 #define HCF_LVDS 0x10 /* parity card */
363
364 /* Bit Definition for TargetFlag */
365
366 #define TCF_EN_255 0x08
367 #define TCF_EN_TAG 0x10
368 #define TCF_BUSY 0x20
369 #define TCF_DISCONNECT 0x40
370 #define TCF_SPIN_UP 0x80
371
372 /* Bit Definition for HCS_AFlags */
373 #define HCS_AF_IGNORE 0x01 /* Adapter ignore */
374 #define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */
375 #define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */
376
377
378 /*---------------------------------------*/
379 /* TimeOut for RESET to complete (30s) */
380 /* */
381 /* After a RESET the drive is checked */
382 /* every 200ms. */
383 /*---------------------------------------*/
384 #define DELAYED_RESET_MAX (30*1000L)
385 #define DELAYED_RESET_INTERVAL 200L
386
387 /*----------------------------------------------*/
388 /* TimeOut for IRQ from last interrupt (5s) */
389 /*----------------------------------------------*/
390 #define IRQ_TIMEOUT_INTERVAL (5*1000L)
391
392 /*----------------------------------------------*/
393 /* Retry Delay interval (200ms) */
394 /*----------------------------------------------*/
395 #define DELAYED_RETRY_INTERVAL 200L
396
397 #define INQUIRY_SIZE 36
398 #define CAPACITY_SIZE 8
399 #define DEFAULT_SENSE_LEN 14
400
401 #define DEVICE_NOT_FOUND 0x86
402
403 /*----------------------------------------------*/
404 /* Definition for PCI device */
405 /*----------------------------------------------*/
406 #define MAX_PCI_DEVICES 21
407 #define MAX_PCI_BUSES 8
408
409 typedef struct Adpt_Struc {
410 USHORT ADPT_BIOS; /* 0 */
411 UBYTE ADPT_BASE; /* 1 */
412 UBYTE ADPT_Bus; /* 2 */
413 UBYTE ADPT_Device; /* 3 */
414 UBYTE ADPT_Reserved[3];
415 } JACS, *PJACS;
416
417 typedef struct _NVRAM {
418 /*----------header ---------------*/
419 UCHAR SubVendorID0; /* 00 - Sub Vendor ID */
420 UCHAR SubVendorID1; /* 00 - Sub Vendor ID */
421 UCHAR SubSysID0; /* 02 - Sub System ID */
422 UCHAR SubSysID1; /* 02 - Sub System ID */
423 UCHAR SubClass; /* 04 - Sub Class */
424 UCHAR VendorID0; /* 05 - Vendor ID */
425 UCHAR VendorID1; /* 05 - Vendor ID */
426 UCHAR DeviceID0; /* 07 - Device ID */
427 UCHAR DeviceID1; /* 07 - Device ID */
428 UCHAR Reserved0[2]; /* 09 - Reserved */
429 UCHAR Revision; /* 0B - Revision of data structure */
430 /* ----Host Adapter Structure ---- */
431 UCHAR NumOfCh; /* 0C - Number of SCSI channel */
432 UCHAR BIOSConfig1; /* 0D - BIOS configuration 1 */
433 UCHAR BIOSConfig2; /* 0E - BIOS boot channel&target ID */
434 UCHAR BIOSConfig3; /* 0F - BIOS configuration 3 */
435 /* ----SCSI channel Structure ---- */
436 /* from "CTRL-I SCSI Host Adapter SetUp menu " */
437 UCHAR SCSI0Id; /* 10 - Channel 0 SCSI ID */
438 UCHAR SCSI0Config; /* 11 - Channel 0 SCSI configuration */
439 UCHAR SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */
440 UCHAR SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */
441 UCHAR ReservedforChannel0[2]; /* 14 - Reserved */
442
443 /* ----SCSI target Structure ---- */
444 /* from "CTRL-I SCSI device SetUp menu " */
445 UCHAR Target00Config; /* 16 - Channel 0 Target 0 config */
446 UCHAR Target01Config; /* 17 - Channel 0 Target 1 config */
447 UCHAR Target02Config; /* 18 - Channel 0 Target 2 config */
448 UCHAR Target03Config; /* 19 - Channel 0 Target 3 config */
449 UCHAR Target04Config; /* 1A - Channel 0 Target 4 config */
450 UCHAR Target05Config; /* 1B - Channel 0 Target 5 config */
451 UCHAR Target06Config; /* 1C - Channel 0 Target 6 config */
452 UCHAR Target07Config; /* 1D - Channel 0 Target 7 config */
453 UCHAR Target08Config; /* 1E - Channel 0 Target 8 config */
454 UCHAR Target09Config; /* 1F - Channel 0 Target 9 config */
455 UCHAR Target0AConfig; /* 20 - Channel 0 Target A config */
456 UCHAR Target0BConfig; /* 21 - Channel 0 Target B config */
457 UCHAR Target0CConfig; /* 22 - Channel 0 Target C config */
458 UCHAR Target0DConfig; /* 23 - Channel 0 Target D config */
459 UCHAR Target0EConfig; /* 24 - Channel 0 Target E config */
460 UCHAR Target0FConfig; /* 25 - Channel 0 Target F config */
461
462 UCHAR SCSI1Id; /* 26 - Channel 1 SCSI ID */
463 UCHAR SCSI1Config; /* 27 - Channel 1 SCSI configuration */
464 UCHAR SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */
465 UCHAR SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */
466 UCHAR ReservedforChannel1[2]; /* 2A - Reserved */
467
468 /* ----SCSI target Structure ---- */
469 /* from "CTRL-I SCSI device SetUp menu " */
470 UCHAR Target10Config; /* 2C - Channel 1 Target 0 config */
471 UCHAR Target11Config; /* 2D - Channel 1 Target 1 config */
472 UCHAR Target12Config; /* 2E - Channel 1 Target 2 config */
473 UCHAR Target13Config; /* 2F - Channel 1 Target 3 config */
474 UCHAR Target14Config; /* 30 - Channel 1 Target 4 config */
475 UCHAR Target15Config; /* 31 - Channel 1 Target 5 config */
476 UCHAR Target16Config; /* 32 - Channel 1 Target 6 config */
477 UCHAR Target17Config; /* 33 - Channel 1 Target 7 config */
478 UCHAR Target18Config; /* 34 - Channel 1 Target 8 config */
479 UCHAR Target19Config; /* 35 - Channel 1 Target 9 config */
480 UCHAR Target1AConfig; /* 36 - Channel 1 Target A config */
481 UCHAR Target1BConfig; /* 37 - Channel 1 Target B config */
482 UCHAR Target1CConfig; /* 38 - Channel 1 Target C config */
483 UCHAR Target1DConfig; /* 39 - Channel 1 Target D config */
484 UCHAR Target1EConfig; /* 3A - Channel 1 Target E config */
485 UCHAR Target1FConfig; /* 3B - Channel 1 Target F config */
486 UCHAR reserved[3]; /* 3C - Reserved */
487 /* ---------- CheckSum ---------- */
488 UCHAR CheckSum; /* 3F - Checksum of NVRam */
489 } NVRAM, *PNVRAM;
490
491 /* Bios Configuration for nvram->BIOSConfig1 */
492 #define NBC_BIOSENABLE 0x01 /* BIOS enable */
493 #define NBC_CDROM 0x02 /* Support bootable CDROM */
494 #define NBC_REMOVABLE 0x04 /* Support removable drive */
495
496 /* Bios Configuration for nvram->BIOSConfig2 */
497 #define NBB_TARGET_MASK 0x0F /* Boot SCSI target ID number */
498 #define NBB_CHANL_MASK 0xF0 /* Boot SCSI channel number */
499
500 /* Bit definition for nvram->SCSIConfig */
501 #define NCC_BUSRESET 0x01 /* Reset SCSI bus at power up */
502 #define NCC_PARITYCHK 0x02 /* SCSI parity enable */
503 #define NCC_LVDS 0x10 /* Enable LVDS */
504 #define NCC_ACTTERM1 0x20 /* Enable active terminator 1 */
505 #define NCC_ACTTERM2 0x40 /* Enable active terminator 2 */
506 #define NCC_AUTOTERM 0x80 /* Enable auto termination */
507
508 /* Bit definition for nvram->TargetxConfig */
509 #define NTC_PERIOD 0x07 /* Maximum Sync. Speed */
510 #define NTC_1GIGA 0x08 /* 255 head / 63 sectors (64/32) */
511 #define NTC_NO_SYNC 0x10 /* NO SYNC. NEGO */
512 #define NTC_NO_WIDESYNC 0x20 /* NO WIDE SYNC. NEGO */
513 #define NTC_DISC_ENABLE 0x40 /* Enable SCSI disconnect */
514 #define NTC_SPINUP 0x80 /* Start disk drive */
515
516 /* Default NVRam values */
517 #define NBC_DEFAULT (NBC_ENABLE)
518 #define NCC_DEFAULT (NCC_BUSRESET | NCC_AUTOTERM | NCC_PARITYCHK)
519 #define NCC_MAX_TAGS 0x20 /* Maximum tags per target */
520 #define NCC_RESET_TIME 0x0A /* SCSI RESET recovering time */
521 #define NTC_DEFAULT (NTC_1GIGA | NTC_NO_WIDESYNC | NTC_DISC_ENABLE)
522
523 typedef union { /* Union define for mechanism 1 */
524 struct {
525 unsigned char RegNum;
526 unsigned char FcnNum:3;
527 unsigned char DeviceNum:5;
528 unsigned char BusNum;
529 unsigned char Reserved:7;
530 unsigned char Enable:1;
531 } sConfigAdr;
532 unsigned long lConfigAdr;
533 } CONFIG_ADR;
534
535 typedef union { /* Union define for mechanism 2 */
536 struct {
537 unsigned char RegNum;
538 unsigned char DeviceNum;
539 unsigned short Reserved;
540 } sHostAdr;
541 unsigned long lHostAdr;
542 } HOST_ADR;
543
544 #define ORC_RD(x,y) (UCHAR)(inb( (int)((ULONG)((ULONG)x+(UCHAR)y)) ))
545 #define ORC_RDLONG(x,y) (long)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
546
547 #define ORC_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
548 #define ORC_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
549 #define ORC_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
550
551
552 #define SCSI_ABORT_SNOOZE 0
553 #define SCSI_ABORT_SUCCESS 1
554 #define SCSI_ABORT_PENDING 2
555 #define SCSI_ABORT_BUSY 3
556 #define SCSI_ABORT_NOT_RUNNING 4
557 #define SCSI_ABORT_ERROR 5
558
559 #define SCSI_RESET_SNOOZE 0
560 #define SCSI_RESET_PUNT 1
561 #define SCSI_RESET_SUCCESS 2
562 #define SCSI_RESET_PENDING 3
563 #define SCSI_RESET_WAKEUP 4
564 #define SCSI_RESET_NOT_RUNNING 5
565 #define SCSI_RESET_ERROR 6
566
567 #define SCSI_RESET_SYNCHRONOUS 0x01
568 #define SCSI_RESET_ASYNCHRONOUS 0x02
569 #define SCSI_RESET_SUGGEST_BUS_RESET 0x04
570 #define SCSI_RESET_SUGGEST_HOST_RESET 0x08
571
572 #define SCSI_RESET_BUS_RESET 0x100
573 #define SCSI_RESET_HOST_RESET 0x200
574 #define SCSI_RESET_ACTION 0xff
575