File: /usr/src/linux/drivers/scsi/mesh.c
1 /*
2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
3 * bus adaptor found on Power Macintosh computers.
4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
5 * controller.
6 *
7 * Paul Mackerras, August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 */
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/types.h>
14 #include <linux/string.h>
15 #include <linux/slab.h>
16 #include <linux/blk.h>
17 #include <linux/proc_fs.h>
18 #include <linux/stat.h>
19 #include <linux/tqueue.h>
20 #include <linux/interrupt.h>
21 #include <linux/reboot.h>
22 #include <linux/spinlock.h>
23 #include <asm/dbdma.h>
24 #include <asm/io.h>
25 #include <asm/pgtable.h>
26 #include <asm/prom.h>
27 #include <asm/system.h>
28 #include <asm/irq.h>
29 #include <asm/hydra.h>
30 #include <asm/processor.h>
31 #include <asm/feature.h>
32 #ifdef CONFIG_PMAC_PBOOK
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #endif
36
37 #include "scsi.h"
38 #include "hosts.h"
39 #include "mesh.h"
40
41 /*
42 * To do:
43 * - handle aborts correctly
44 * - retry arbitration if lost (unless higher levels do this for us)
45 */
46
47 #define MESH_NEW_STYLE_EH
48
49 #if 1
50 #undef KERN_DEBUG
51 #define KERN_DEBUG KERN_WARNING
52 #endif
53
54 #if CONFIG_SCSI_MESH_SYNC_RATE == 0
55 int mesh_sync_period = 100;
56 int mesh_sync_offset = 0;
57 #else
58 int mesh_sync_period = 1000 / CONFIG_SCSI_MESH_SYNC_RATE; /* ns */
59 int mesh_sync_offset = 15;
60 #endif
61
62 int mesh_sync_targets = 0xff; /* targets to set synchronous (bitmap) */
63 int mesh_resel_targets = 0xff; /* targets that we let disconnect (bitmap) */
64 int mesh_debug_targets = 0; /* print debug for these targets */
65 unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
66
67 #define ALLOW_SYNC(tgt) ((mesh_sync_targets >> (tgt)) & 1)
68 #define ALLOW_RESEL(tgt) ((mesh_resel_targets >> (tgt)) & 1)
69 #define ALLOW_DEBUG(tgt) ((mesh_debug_targets >> (tgt)) & 1)
70 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->target))
71
72 #undef MESH_DBG
73 #define N_DBG_LOG 50
74 #define N_DBG_SLOG 20
75 #define NUM_DBG_EVENTS 13
76 #undef DBG_USE_TB /* bombs on 601 */
77
78 struct dbglog {
79 char *fmt;
80 u32 tb;
81 u8 phase;
82 u8 bs0;
83 u8 bs1;
84 u8 tgt;
85 int d;
86 };
87
88 enum mesh_phase {
89 idle,
90 arbitrating,
91 selecting,
92 commanding,
93 dataing,
94 statusing,
95 busfreeing,
96 disconnecting,
97 reselecting
98 };
99
100 enum msg_phase {
101 msg_none,
102 msg_out,
103 msg_out_xxx,
104 msg_out_last,
105 msg_in,
106 msg_in_bad,
107 };
108
109 enum sdtr_phase {
110 do_sdtr,
111 sdtr_sent,
112 sdtr_done
113 };
114
115 struct mesh_target {
116 enum sdtr_phase sdtr_state;
117 int sync_params;
118 int data_goes_out; /* guess as to data direction */
119 Scsi_Cmnd *current_req;
120 u32 saved_ptr;
121 int want_abort;
122 #ifdef MESH_DBG
123 int log_ix;
124 int n_log;
125 struct dbglog log[N_DBG_LOG];
126 #endif
127 };
128
129 struct mesh_state {
130 volatile struct mesh_regs *mesh;
131 int meshintr;
132 volatile struct dbdma_regs *dma;
133 int dmaintr;
134 struct Scsi_Host *host;
135 struct mesh_state *next;
136 Scsi_Cmnd *request_q;
137 Scsi_Cmnd *request_qtail;
138 enum mesh_phase phase; /* what we're currently trying to do */
139 enum msg_phase msgphase;
140 int conn_tgt; /* target we're connected to */
141 Scsi_Cmnd *current_req; /* req we're currently working on */
142 int data_ptr;
143 int dma_started;
144 int dma_count;
145 int stat;
146 int aborting;
147 int expect_reply;
148 int n_msgin;
149 u8 msgin[16];
150 int n_msgout;
151 int last_n_msgout;
152 u8 msgout[16];
153 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
154 int clk_freq;
155 struct mesh_target tgts[8];
156 void *dma_cmd_space;
157 struct device_node *ofnode;
158 u8* mio_base;
159 #ifndef MESH_NEW_STYLE_EH
160 Scsi_Cmnd *completed_q;
161 Scsi_Cmnd *completed_qtail;
162 struct tq_struct tqueue;
163 #endif
164 #ifdef MESH_DBG
165 int log_ix;
166 int n_log;
167 struct dbglog log[N_DBG_SLOG];
168 #endif
169 };
170
171 #ifdef MESH_DBG
172
173 static void dlog(struct mesh_state *ms, char *fmt, int a);
174 static void dumplog(struct mesh_state *ms, int tgt);
175 static void dumpslog(struct mesh_state *ms);
176
177 #else
178 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
179 {}
180 static inline void dumplog(struct mesh_state *ms, int tgt)
181 {}
182 static inline void dumpslog(struct mesh_state *ms)
183 {}
184
185 #endif /* MESH_DBG */
186 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
187
188 static struct mesh_state *all_meshes;
189
190 static void mesh_init(struct mesh_state *);
191 static int mesh_notify_reboot(struct notifier_block *, unsigned long, void *);
192 static void mesh_dump_regs(struct mesh_state *);
193 static void mesh_start(struct mesh_state *);
194 static void mesh_start_cmd(struct mesh_state *, Scsi_Cmnd *);
195 #ifndef MESH_NEW_STYLE_EH
196 static void finish_cmds(void *);
197 #endif
198 static void add_sdtr_msg(struct mesh_state *);
199 static void set_sdtr(struct mesh_state *, int, int);
200 static void start_phase(struct mesh_state *);
201 static void get_msgin(struct mesh_state *);
202 static int msgin_length(struct mesh_state *);
203 static void cmd_complete(struct mesh_state *);
204 static void phase_mismatch(struct mesh_state *);
205 static void reselected(struct mesh_state *);
206 static void handle_reset(struct mesh_state *);
207 static void handle_error(struct mesh_state *);
208 static void handle_exception(struct mesh_state *);
209 static void mesh_interrupt(int, void *, struct pt_regs *);
210 static void do_mesh_interrupt(int, void *, struct pt_regs *);
211 static void handle_msgin(struct mesh_state *);
212 static void mesh_done(struct mesh_state *, int);
213 static void mesh_completed(struct mesh_state *, Scsi_Cmnd *);
214 static void set_dma_cmds(struct mesh_state *, Scsi_Cmnd *);
215 static void halt_dma(struct mesh_state *);
216 static int data_goes_out(Scsi_Cmnd *);
217 static void do_abort(struct mesh_state *ms);
218 static void set_mesh_power(struct mesh_state *ms, int state);
219
220 #ifdef CONFIG_PMAC_PBOOK
221 static int mesh_notify_sleep(struct pmu_sleep_notifier *self, int when);
222 static struct pmu_sleep_notifier mesh_sleep_notifier = {
223 mesh_notify_sleep,
224 SLEEP_LEVEL_BLOCK,
225 };
226 #endif
227
228 static struct notifier_block mesh_notifier = {
229 mesh_notify_reboot,
230 NULL,
231 0
232 };
233
234 int
235 mesh_detect(Scsi_Host_Template *tp)
236 {
237 struct device_node *mesh;
238 int nmeshes, tgt, *cfp, minper;
239 struct mesh_state *ms, **prev_statep;
240 struct Scsi_Host *mesh_host;
241 void *dma_cmd_space;
242
243 if (_machine == _MACH_Pmac) {
244 use_active_neg = (find_devices("mac-io") ? 0 : SEQ_ACTIVE_NEG);
245 } else {
246 /* CHRP mac-io */
247 use_active_neg = SEQ_ACTIVE_NEG;
248 }
249
250 nmeshes = 0;
251 prev_statep = &all_meshes;
252 /*
253 * On powermacs, the MESH node has device_type "mesh".
254 * On chrp machines, its device_type is "scsi" with
255 * "chrp,mesh0" as its `compatible' property.
256 */
257 mesh = find_devices("mesh");
258 if (mesh == 0)
259 mesh = find_compatible_devices("scsi", "chrp,mesh0");
260 for (; mesh != 0; mesh = mesh->next) {
261 struct device_node *mio;
262
263 if (mesh->n_addrs != 2 || mesh->n_intrs != 2) {
264 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
265 " (got %d,%d)", mesh->n_addrs, mesh->n_intrs);
266 continue;
267 }
268 mesh_host = scsi_register(tp, sizeof(struct mesh_state));
269 if (mesh_host == 0) {
270 printk(KERN_ERR "mesh: couldn't register host");
271 continue;
272 }
273 mesh_host->unique_id = nmeshes;
274 #if !defined(MODULE)
275 note_scsi_host(mesh, mesh_host);
276 #endif
277
278 ms = (struct mesh_state *) mesh_host->hostdata;
279 if (ms == 0)
280 panic("no mesh state");
281 memset(ms, 0, sizeof(*ms));
282 ms->host = mesh_host;
283 ms->ofnode = mesh;
284 ms->mesh = (volatile struct mesh_regs *)
285 ioremap(mesh->addrs[0].address, 0x1000);
286 ms->dma = (volatile struct dbdma_regs *)
287 ioremap(mesh->addrs[1].address, 0x1000);
288 ms->meshintr = mesh->intrs[0].line;
289 ms->dmaintr = mesh->intrs[1].line;
290
291 /* Space for dma command list: +1 for stop command,
292 +1 to allow for aligning. */
293 dma_cmd_space = kmalloc((mesh_host->sg_tablesize + 2) *
294 sizeof(struct dbdma_cmd), GFP_KERNEL);
295 if (dma_cmd_space == 0)
296 panic("mesh: couldn't allocate dma command space");
297 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
298 memset(ms->dma_cmds, 0, (mesh_host->sg_tablesize + 1)
299 * sizeof(struct dbdma_cmd));
300 ms->dma_cmd_space = dma_cmd_space;
301
302 ms->current_req = 0;
303 for (tgt = 0; tgt < 8; ++tgt) {
304 ms->tgts[tgt].sdtr_state = do_sdtr;
305 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
306 ms->tgts[tgt].current_req = 0;
307 }
308 #ifndef MESH_NEW_STYLE_EH
309 ms->tqueue.routine = finish_cmds;
310 ms->tqueue.data = ms;
311 #endif
312 *prev_statep = ms;
313 prev_statep = &ms->next;
314
315 if ((cfp = (int *) get_property(mesh, "clock-frequency",
316 NULL))) {
317 ms->clk_freq = *cfp;
318 } else {
319 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
320 ms->clk_freq = 50000000;
321 }
322 /* The maximum sync rate is clock / 5; increase
323 mesh_sync_period if necessary. */
324 minper = 1000000000 / (ms->clk_freq / 5); /* ns */
325 if (mesh_sync_period < minper)
326 mesh_sync_period = minper;
327
328 ms->mio_base = 0;
329 for (mio = ms->ofnode->parent; mio; mio = mio->parent)
330 if (strcmp(mio->name, "mac-io") == 0 && mio->n_addrs > 0)
331 break;
332 if (mio)
333 ms->mio_base = (u8 *) ioremap(mio->addrs[0].address, 0x40);
334 set_mesh_power(ms, 1);
335
336 mesh_init(ms);
337
338 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
339 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
340 }
341
342 ++nmeshes;
343 }
344
345 if ((_machine == _MACH_Pmac) && (nmeshes > 0)) {
346 #ifdef CONFIG_PMAC_PBOOK
347 pmu_register_sleep_notifier(&mesh_sleep_notifier);
348 #endif /* CONFIG_PMAC_PBOOK */
349 register_reboot_notifier(&mesh_notifier);
350 }
351
352 return nmeshes;
353 }
354
355 int
356 mesh_release(struct Scsi_Host *host)
357 {
358 struct mesh_state *ms = (struct mesh_state *) host->hostdata;
359
360 if (ms == 0)
361 return 0;
362 if (ms->mesh)
363 iounmap((void *) ms->mesh);
364 if (ms->dma)
365 iounmap((void *) ms->dma);
366 if (ms->mio_base)
367 iounmap((void *) ms->mio_base);
368 kfree(ms->dma_cmd_space);
369 free_irq(ms->meshintr, ms);
370 feature_clear(ms->ofnode, FEATURE_MESH_enable);
371 return 0;
372 }
373
374 static void
375 set_mesh_power(struct mesh_state *ms, int state)
376 {
377 if (_machine != _MACH_Pmac)
378 return;
379 if (state) {
380 feature_set(ms->ofnode, FEATURE_MESH_enable);
381 /* This seems to enable the termination power. strangely
382 this doesn't fully agree with OF, but with MacOS */
383 if (ms->mio_base)
384 out_8(ms->mio_base + 0x36, 0x70);
385 mdelay(200);
386 } else {
387 feature_clear(ms->ofnode, FEATURE_MESH_enable);
388 if (ms->mio_base)
389 out_8(ms->mio_base + 0x36, 0x34);
390 mdelay(10);
391 }
392 }
393
394 #ifdef CONFIG_PMAC_PBOOK
395 /*
396 * notify clients before sleep and reset bus afterwards
397 */
398 int
399 mesh_notify_sleep(struct pmu_sleep_notifier *self, int when)
400 {
401 struct mesh_state *ms;
402
403 switch (when) {
404 case PBOOK_SLEEP_REQUEST:
405 /* XXX We should wait for current transactions and queue
406 * new ones that would be posted beyond this point
407 */
408 break;
409 case PBOOK_SLEEP_REJECT:
410 break;
411
412 case PBOOK_SLEEP_NOW:
413 for (ms = all_meshes; ms != 0; ms = ms->next) {
414 disable_irq(ms->meshintr);
415 set_mesh_power(ms, 0);
416 }
417 break;
418 case PBOOK_WAKE:
419 for (ms = all_meshes; ms != 0; ms = ms->next) {
420 set_mesh_power(ms, 1);
421 mesh_init(ms);
422 enable_irq(ms->meshintr);
423 }
424 break;
425 }
426 return PBOOK_SLEEP_OK;
427 }
428 #endif /* CONFIG_PMAC_PBOOK */
429
430 int
431 mesh_queue(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *))
432 {
433 unsigned long flags;
434 struct mesh_state *ms;
435
436 cmd->scsi_done = done;
437 cmd->host_scribble = NULL;
438
439 ms = (struct mesh_state *) cmd->host->hostdata;
440
441 save_flags(flags);
442 cli();
443 if (ms->request_q == NULL)
444 ms->request_q = cmd;
445 else
446 ms->request_qtail->host_scribble = (void *) cmd;
447 ms->request_qtail = cmd;
448
449 if (ms->phase == idle)
450 mesh_start(ms);
451
452 restore_flags(flags);
453 return 0;
454 }
455
456 int
457 mesh_abort(Scsi_Cmnd *cmd)
458 {
459 struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
460
461 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
462 mesh_dump_regs(ms);
463 dumplog(ms, cmd->target);
464 dumpslog(ms);
465 return SCSI_ABORT_SNOOZE;
466 }
467
468 static void
469 mesh_dump_regs(struct mesh_state *ms)
470 {
471 volatile struct mesh_regs *mr = ms->mesh;
472 volatile struct dbdma_regs *md = ms->dma;
473 int t;
474 struct mesh_target *tp;
475
476 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
477 ms, mr, md);
478 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
479 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
480 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
481 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
482 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
483 mr->sync_params);
484 while(in_8(&mr->fifo_count))
485 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
486 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
487 in_le32(&md->status), in_le32(&md->cmdptr));
488 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
489 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
490 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
491 ms->dma_started, ms->dma_count, ms->n_msgout);
492 for (t = 0; t < 8; ++t) {
493 tp = &ms->tgts[t];
494 if (tp->current_req == NULL)
495 continue;
496 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
497 t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
498 }
499 }
500
501 int
502 mesh_reset(Scsi_Cmnd *cmd, unsigned how)
503 {
504 struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
505 volatile struct mesh_regs *mr = ms->mesh;
506 volatile struct dbdma_regs *md = ms->dma;
507 unsigned long flags;
508 int ret;
509
510 printk(KERN_DEBUG "mesh_reset %x\n", how);
511 ret = SCSI_RESET_BUS_RESET;
512 save_flags(flags);
513 cli();
514 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
515 out_8(&mr->exception, 0xff); /* clear all exception bits */
516 out_8(&mr->error, 0xff); /* clear all error bits */
517 if (how & SCSI_RESET_SUGGEST_HOST_RESET) {
518 out_8(&mr->sequence, SEQ_RESETMESH);
519 ret |= SCSI_RESET_HOST_RESET;
520 udelay(1);
521 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
522 out_8(&mr->source_id, ms->host->this_id);
523 out_8(&mr->sel_timeout, 25); /* 250ms */
524 out_8(&mr->sync_params, ASYNC_PARAMS);
525 }
526 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
527 udelay(30); /* leave it on for >= 25us */
528 out_8(&mr->bus_status1, 0); /* negate RST */
529 #ifdef DO_ASYNC_RESET
530 if (how & SCSI_RESET_ASYNCHRONOUS) {
531 restore_flags(flags);
532 ret |= SCSI_RESET_PENDING;
533 } else
534 #endif
535 {
536 handle_reset(ms);
537 restore_flags(flags);
538 #ifndef MESH_NEW_STYLE_EH
539 finish_cmds(ms);
540 #endif
541 ret |= SCSI_RESET_SUCCESS;
542 }
543 return ret;
544 }
545
546 /*
547 * If we leave drives set for synchronous transfers (especially
548 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
549 * So, on reboot we reset the SCSI bus.
550 */
551 static int
552 mesh_notify_reboot(struct notifier_block *this, unsigned long code, void *x)
553 {
554 struct mesh_state *ms;
555 volatile struct mesh_regs *mr;
556
557 if (code == SYS_DOWN) {
558 printk(KERN_INFO "resetting MESH scsi bus(es)\n");
559 for (ms = all_meshes; ms != 0; ms = ms->next) {
560 mr = ms->mesh;
561 out_8(&mr->intr_mask, 0);
562 out_8(&mr->interrupt,
563 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
564 out_8(&mr->bus_status1, BS1_RST);
565 udelay(30);
566 out_8(&mr->bus_status1, 0);
567 }
568 }
569 return NOTIFY_DONE;
570 }
571
572 int
573 mesh_command(Scsi_Cmnd *cmd)
574 {
575 printk(KERN_WARNING "whoops... mesh_command called\n");
576 return -1;
577 }
578
579 static void
580 mesh_init(struct mesh_state *ms)
581 {
582 volatile struct mesh_regs *mr = ms->mesh;
583 volatile struct dbdma_regs *md = ms->dma;
584
585 udelay(100);
586
587 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
588 out_8(&mr->exception, 0xff); /* clear all exception bits */
589 out_8(&mr->error, 0xff); /* clear all error bits */
590 out_8(&mr->sequence, SEQ_RESETMESH);
591 udelay(10);
592 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
593 out_8(&mr->source_id, ms->host->this_id);
594 out_8(&mr->sel_timeout, 25); /* 250ms */
595 out_8(&mr->sync_params, ASYNC_PARAMS);
596
597 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
598 udelay(30); /* leave it on for >= 25us */
599 out_8(&mr->bus_status1, 0); /* negate RST */
600
601 out_8(&mr->sequence, SEQ_FLUSHFIFO);
602 udelay(1);
603 out_8(&mr->sync_params, ASYNC_PARAMS);
604 out_8(&mr->sequence, SEQ_ENBRESEL);
605 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
606 }
607
608 /*
609 * Start the next command for a MESH.
610 * Should be called with interrupts disabled.
611 */
612 static void
613 mesh_start(struct mesh_state *ms)
614 {
615 Scsi_Cmnd *cmd, *prev, *next;
616
617 if (ms->phase != idle || ms->current_req != NULL) {
618 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
619 ms->phase, ms);
620 return;
621 }
622
623 while (ms->phase == idle) {
624 prev = NULL;
625 for (cmd = ms->request_q; ; cmd = (Scsi_Cmnd *) cmd->host_scribble) {
626 if (cmd == NULL)
627 return;
628 if (ms->tgts[cmd->target].current_req == NULL)
629 break;
630 prev = cmd;
631 }
632 next = (Scsi_Cmnd *) cmd->host_scribble;
633 if (prev == NULL)
634 ms->request_q = next;
635 else
636 prev->host_scribble = (void *) next;
637 if (next == NULL)
638 ms->request_qtail = prev;
639
640 mesh_start_cmd(ms, cmd);
641 }
642 }
643
644 static void
645 mesh_start_cmd(struct mesh_state *ms, Scsi_Cmnd *cmd)
646 {
647 volatile struct mesh_regs *mr = ms->mesh;
648 int t;
649
650 ms->current_req = cmd;
651 ms->tgts[cmd->target].data_goes_out = data_goes_out(cmd);
652 ms->tgts[cmd->target].current_req = cmd;
653
654 #if 1
655 if (DEBUG_TARGET(cmd)) {
656 int i;
657 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=",
658 cmd, cmd->serial_number, cmd->target);
659 for (i = 0; i < cmd->cmd_len; ++i)
660 printk(" %x", cmd->cmnd[i]);
661 printk(" use_sg=%d buffer=%p bufflen=%u\n",
662 cmd->use_sg, cmd->request_buffer, cmd->request_bufflen);
663 }
664 #endif
665
666 ms->phase = arbitrating;
667 ms->msgphase = msg_none;
668 ms->data_ptr = 0;
669 ms->dma_started = 0;
670 ms->n_msgout = 0;
671 ms->last_n_msgout = 0;
672 ms->expect_reply = 0;
673 ms->conn_tgt = cmd->target;
674 ms->tgts[cmd->target].saved_ptr = 0;
675 ms->stat = DID_OK;
676 ms->aborting = 0;
677 #ifdef MESH_DBG
678 ms->tgts[cmd->target].n_log = 0;
679 dlog(ms, "start cmd=%x", (int) cmd);
680 #endif
681
682 /* Off we go */
683 dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
684 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
685 out_8(&mr->interrupt, INT_CMDDONE);
686 out_8(&mr->sequence, SEQ_ENBRESEL);
687 udelay(1);
688
689 if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
690 /*
691 * Some other device has the bus or is arbitrating for it -
692 * probably a target which is about to reselect us.
693 */
694 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
695 MKWORD(mr->interrupt, mr->exception,
696 mr->error, mr->fifo_count));
697 for (t = 100; t > 0; --t) {
698 if ((mr->bus_status1 & (BS1_BSY | BS1_SEL)) == 0)
699 break;
700 if (in_8(&mr->interrupt) != 0) {
701 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
702 MKWORD(mr->interrupt, mr->exception,
703 mr->error, mr->fifo_count));
704 mesh_interrupt(0, (void *)ms, 0);
705 if (ms->phase != arbitrating)
706 return;
707 }
708 udelay(1);
709 }
710 if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
711 /* XXX should try again in a little while */
712 ms->stat = DID_BUS_BUSY;
713 ms->phase = idle;
714 mesh_done(ms, 0);
715 return;
716 }
717 }
718
719 /*
720 * Apparently the mesh has a bug where it will assert both its
721 * own bit and the target's bit on the bus during arbitration.
722 */
723 out_8(&mr->dest_id, mr->source_id);
724
725 /*
726 * There appears to be a race with reselection sometimes,
727 * where a target reselects us just as we issue the
728 * arbitrate command. It seems that then the arbitrate
729 * command just hangs waiting for the bus to be free
730 * without giving us a reselection exception.
731 * The only way I have found to get it to respond correctly
732 * is this: disable reselection before issuing the arbitrate
733 * command, then after issuing it, if it looks like a target
734 * is trying to reselect us, reset the mesh and then enable
735 * reselection.
736 */
737 out_8(&mr->sequence, SEQ_DISRESEL);
738 if (in_8(&mr->interrupt) != 0) {
739 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
740 MKWORD(mr->interrupt, mr->exception,
741 mr->error, mr->fifo_count));
742 mesh_interrupt(0, (void *)ms, 0);
743 if (ms->phase != arbitrating)
744 return;
745 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
746 MKWORD(mr->interrupt, mr->exception,
747 mr->error, mr->fifo_count));
748 }
749
750 out_8(&mr->sequence, SEQ_ARBITRATE);
751
752 for (t = 230; t > 0; --t) {
753 if (in_8(&mr->interrupt) != 0)
754 break;
755 udelay(1);
756 }
757 dlog(ms, "after arb, intr/exc/err/fc=%.8x",
758 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
759 if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
760 && (mr->bus_status0 & BS0_IO)) {
761 /* looks like a reselection - try resetting the mesh */
762 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
763 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
764 out_8(&mr->sequence, SEQ_RESETMESH);
765 udelay(10);
766 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
767 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
768 out_8(&mr->sequence, SEQ_ENBRESEL);
769 for (t = 10; t > 0 && mr->interrupt == 0; --t)
770 udelay(1);
771 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
772 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
773 #ifndef MESH_MULTIPLE_HOSTS
774 if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
775 && (mr->bus_status0 & BS0_IO)) {
776 printk(KERN_ERR "mesh: controller not responding"
777 " to reselection!\n");
778 /*
779 * If this is a target reselecting us, and the
780 * mesh isn't responding, the higher levels of
781 * the scsi code will eventually time out and
782 * reset the bus.
783 */
784 }
785 #endif
786 }
787 }
788
789 #ifndef MESH_NEW_STYLE_EH
790 static void
791 finish_cmds(void *data)
792 {
793 struct mesh_state *ms = data;
794 Scsi_Cmnd *cmd;
795 unsigned long flags;
796
797 for (;;) {
798 spin_lock_irqsave(&io_request_lock, flags);
799 cmd = ms->completed_q;
800 if (cmd == NULL) {
801 spin_unlock_irqrestore(&io_request_lock, flags);
802 break;
803 }
804 ms->completed_q = (Scsi_Cmnd *) cmd->host_scribble;
805 (*cmd->scsi_done)(cmd);
806 spin_unlock_irqrestore(&io_request_lock, flags);
807 }
808 }
809 #endif /* MESH_NEW_STYLE_EH */
810
811 static inline void
812 add_sdtr_msg(struct mesh_state *ms)
813 {
814 int i = ms->n_msgout;
815
816 ms->msgout[i] = EXTENDED_MESSAGE;
817 ms->msgout[i+1] = 3;
818 ms->msgout[i+2] = EXTENDED_SDTR;
819 ms->msgout[i+3] = mesh_sync_period/4;
820 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
821 ms->n_msgout = i + 5;
822 }
823
824 static void
825 set_sdtr(struct mesh_state *ms, int period, int offset)
826 {
827 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
828 volatile struct mesh_regs *mr = ms->mesh;
829 int v, tr;
830
831 tp->sdtr_state = sdtr_done;
832 if (offset == 0) {
833 /* asynchronous */
834 if (SYNC_OFF(tp->sync_params))
835 printk(KERN_INFO "mesh: target %d now asynchronous\n",
836 ms->conn_tgt);
837 tp->sync_params = ASYNC_PARAMS;
838 out_8(&mr->sync_params, ASYNC_PARAMS);
839 return;
840 }
841 /*
842 * We need to compute ceil(clk_freq * period / 500e6) - 2
843 * without incurring overflow.
844 */
845 v = (ms->clk_freq / 5000) * period;
846 if (v <= 250000) {
847 /* special case: sync_period == 5 * clk_period */
848 v = 0;
849 /* units of tr are 100kB/s */
850 tr = (ms->clk_freq + 250000) / 500000;
851 } else {
852 /* sync_period == (v + 2) * 2 * clk_period */
853 v = (v + 99999) / 100000 - 2;
854 if (v > 15)
855 v = 15; /* oops */
856 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
857 }
858 if (offset > 15)
859 offset = 15; /* can't happen */
860 tp->sync_params = SYNC_PARAMS(offset, v);
861 out_8(&mr->sync_params, tp->sync_params);
862 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
863 ms->conn_tgt, tr/10, tr%10);
864 }
865
866 static void
867 start_phase(struct mesh_state *ms)
868 {
869 int i, seq, nb;
870 volatile struct mesh_regs *mr = ms->mesh;
871 volatile struct dbdma_regs *md = ms->dma;
872 Scsi_Cmnd *cmd = ms->current_req;
873 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
874
875 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
876 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
877 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
878 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
879 switch (ms->msgphase) {
880 case msg_none:
881 break;
882
883 case msg_in:
884 out_8(&mr->count_hi, 0);
885 out_8(&mr->count_lo, 1);
886 out_8(&mr->sequence, SEQ_MSGIN + seq);
887 ms->n_msgin = 0;
888 return;
889
890 case msg_out:
891 /*
892 * To make sure ATN drops before we assert ACK for
893 * the last byte of the message, we have to do the
894 * last byte specially.
895 */
896 if (ms->n_msgout <= 0) {
897 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
898 ms->n_msgout);
899 mesh_dump_regs(ms);
900 ms->msgphase = msg_none;
901 break;
902 }
903 if (ALLOW_DEBUG(ms->conn_tgt)) {
904 printk(KERN_DEBUG "mesh: sending %d msg bytes:",
905 ms->n_msgout);
906 for (i = 0; i < ms->n_msgout; ++i)
907 printk(" %x", ms->msgout[i]);
908 printk("\n");
909 }
910 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
911 ms->msgout[1], ms->msgout[2]));
912 out_8(&mr->count_hi, 0);
913 out_8(&mr->sequence, SEQ_FLUSHFIFO);
914 udelay(1);
915 /*
916 * If ATN is not already asserted, we assert it, then
917 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
918 */
919 if ((mr->bus_status0 & BS0_ATN) == 0) {
920 dlog(ms, "bus0 was %.2x explictly asserting ATN", mr->bus_status0);
921 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
922 udelay(1);
923 out_8(&mr->count_lo, 1);
924 out_8(&mr->sequence, SEQ_MSGOUT + seq);
925 out_8(&mr->bus_status0, 0); /* release explicit ATN */
926 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
927 }
928 if (ms->n_msgout == 1) {
929 /*
930 * We can't issue the SEQ_MSGOUT without ATN
931 * until the target has asserted REQ. The logic
932 * in cmd_complete handles both situations:
933 * REQ already asserted or not.
934 */
935 cmd_complete(ms);
936 } else {
937 out_8(&mr->count_lo, ms->n_msgout - 1);
938 out_8(&mr->sequence, SEQ_MSGOUT + seq);
939 for (i = 0; i < ms->n_msgout - 1; ++i)
940 out_8(&mr->fifo, ms->msgout[i]);
941 }
942 return;
943
944 default:
945 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
946 ms->msgphase);
947 }
948
949 switch (ms->phase) {
950 case selecting:
951 out_8(&mr->dest_id, ms->conn_tgt);
952 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
953 break;
954 case commanding:
955 out_8(&mr->sync_params, tp->sync_params);
956 out_8(&mr->count_hi, 0);
957 if (cmd) {
958 out_8(&mr->count_lo, cmd->cmd_len);
959 out_8(&mr->sequence, SEQ_COMMAND + seq);
960 for (i = 0; i < cmd->cmd_len; ++i)
961 out_8(&mr->fifo, cmd->cmnd[i]);
962 } else {
963 out_8(&mr->count_lo, 6);
964 out_8(&mr->sequence, SEQ_COMMAND + seq);
965 for (i = 0; i < 6; ++i)
966 out_8(&mr->fifo, 0);
967 }
968 break;
969 case dataing:
970 /* transfer data, if any */
971 if (!ms->dma_started) {
972 set_dma_cmds(ms, cmd);
973 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
974 out_le32(&md->control, (RUN << 16) | RUN);
975 ms->dma_started = 1;
976 }
977 nb = ms->dma_count;
978 if (nb > 0xfff0)
979 nb = 0xfff0;
980 ms->dma_count -= nb;
981 ms->data_ptr += nb;
982 out_8(&mr->count_lo, nb);
983 out_8(&mr->count_hi, nb >> 8);
984 out_8(&mr->sequence, (tp->data_goes_out?
985 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
986 break;
987 case statusing:
988 out_8(&mr->count_hi, 0);
989 out_8(&mr->count_lo, 1);
990 out_8(&mr->sequence, SEQ_STATUS + seq);
991 break;
992 case busfreeing:
993 case disconnecting:
994 out_8(&mr->sequence, SEQ_ENBRESEL);
995 udelay(1);
996 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
997 MKWORD(mr->interrupt, mr->exception, mr->error,
998 mr->fifo_count));
999 out_8(&mr->sequence, SEQ_BUSFREE);
1000 break;
1001 default:
1002 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
1003 ms->phase);
1004 dumpslog(ms);
1005 }
1006
1007 }
1008
1009 static inline void
1010 get_msgin(struct mesh_state *ms)
1011 {
1012 volatile struct mesh_regs *mr = ms->mesh;
1013 int i, n;
1014
1015 n = mr->fifo_count;
1016 if (n != 0) {
1017 i = ms->n_msgin;
1018 ms->n_msgin = i + n;
1019 for (; n > 0; --n)
1020 ms->msgin[i++] = in_8(&mr->fifo);
1021 }
1022 }
1023
1024 static inline int
1025 msgin_length(struct mesh_state *ms)
1026 {
1027 int b, n;
1028
1029 n = 1;
1030 if (ms->n_msgin > 0) {
1031 b = ms->msgin[0];
1032 if (b == 1) {
1033 /* extended message */
1034 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
1035 } else if (0x20 <= b && b <= 0x2f) {
1036 /* 2-byte message */
1037 n = 2;
1038 }
1039 }
1040 return n;
1041 }
1042
1043 static void
1044 cmd_complete(struct mesh_state *ms)
1045 {
1046 volatile struct mesh_regs *mr = ms->mesh;
1047 Scsi_Cmnd *cmd = ms->current_req;
1048 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1049 int seq, n, t;
1050
1051 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1052 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1053 switch (ms->msgphase) {
1054 case msg_out_xxx:
1055 /* huh? we expected a phase mismatch */
1056 ms->n_msgin = 0;
1057 ms->msgphase = msg_in;
1058 /* fall through */
1059
1060 case msg_in:
1061 /* should have some message bytes in fifo */
1062 get_msgin(ms);
1063 n = msgin_length(ms);
1064 if (ms->n_msgin < n) {
1065 out_8(&mr->count_lo, n - ms->n_msgin);
1066 out_8(&mr->sequence, SEQ_MSGIN + seq);
1067 } else {
1068 ms->msgphase = msg_none;
1069 handle_msgin(ms);
1070 start_phase(ms);
1071 }
1072 break;
1073
1074 case msg_in_bad:
1075 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1076 udelay(1);
1077 out_8(&mr->count_lo, 1);
1078 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1079 break;
1080
1081 case msg_out:
1082 /*
1083 * To get the right timing on ATN wrt ACK, we have
1084 * to get the MESH to drop ACK, wait until REQ gets
1085 * asserted, then drop ATN. To do this we first
1086 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1087 * then change the command to a SEQ_MSGOUT w/o ATN.
1088 * If we don't see REQ in a reasonable time, we
1089 * change the command to SEQ_MSGIN with ATN,
1090 * wait for the phase mismatch interrupt, then
1091 * issue the SEQ_MSGOUT without ATN.
1092 */
1093 out_8(&mr->count_lo, 1);
1094 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1095 t = 30; /* wait up to 30us */
1096 while ((mr->bus_status0 & BS0_REQ) == 0 && --t >= 0)
1097 udelay(1);
1098 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1099 MKWORD(mr->error, mr->exception,
1100 mr->fifo_count, mr->count_lo));
1101 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1102 /* whoops, target didn't do what we expected */
1103 ms->last_n_msgout = ms->n_msgout;
1104 ms->n_msgout = 0;
1105 if (in_8(&mr->interrupt) & INT_ERROR) {
1106 printk(KERN_ERR "mesh: error %x in msg_out\n",
1107 in_8(&mr->error));
1108 handle_error(ms);
1109 return;
1110 }
1111 if (in_8(&mr->exception) != EXC_PHASEMM)
1112 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1113 in_8(&mr->exception));
1114 else
1115 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1116 in_8(&mr->bus_status0));
1117 handle_exception(ms);
1118 return;
1119 }
1120 if (mr->bus_status0 & BS0_REQ) {
1121 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1122 udelay(1);
1123 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1124 ms->msgphase = msg_out_last;
1125 } else {
1126 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1127 ms->msgphase = msg_out_xxx;
1128 }
1129 break;
1130
1131 case msg_out_last:
1132 ms->last_n_msgout = ms->n_msgout;
1133 ms->n_msgout = 0;
1134 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1135 start_phase(ms);
1136 break;
1137
1138 case msg_none:
1139 switch (ms->phase) {
1140 case idle:
1141 printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1142 dumpslog(ms);
1143 return;
1144 case selecting:
1145 dlog(ms, "Selecting phase at command completion",0);
1146 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1147 (cmd? cmd->lun: 0));
1148 ms->n_msgout = 1;
1149 ms->expect_reply = 0;
1150 if (ms->aborting) {
1151 ms->msgout[0] = ABORT;
1152 ms->n_msgout++;
1153 } else if (tp->sdtr_state == do_sdtr) {
1154 /* add SDTR message */
1155 add_sdtr_msg(ms);
1156 ms->expect_reply = 1;
1157 tp->sdtr_state = sdtr_sent;
1158 }
1159 ms->msgphase = msg_out;
1160 /*
1161 * We need to wait for REQ before dropping ATN.
1162 * We wait for at most 30us, then fall back to
1163 * a scheme where we issue a SEQ_COMMAND with ATN,
1164 * which will give us a phase mismatch interrupt
1165 * when REQ does come, and then we send the message.
1166 */
1167 t = 230; /* wait up to 230us */
1168 while ((mr->bus_status0 & BS0_REQ) == 0) {
1169 if (--t < 0) {
1170 dlog(ms, "impatient for req", ms->n_msgout);
1171 ms->msgphase = msg_none;
1172 break;
1173 }
1174 udelay(1);
1175 }
1176 break;
1177 case dataing:
1178 if (ms->dma_count != 0) {
1179 start_phase(ms);
1180 return;
1181 }
1182 /*
1183 * We can get a phase mismatch here if the target
1184 * changes to the status phase, even though we have
1185 * had a command complete interrupt. Then, if we
1186 * issue the SEQ_STATUS command, we'll get a sequence
1187 * error interrupt. Which isn't so bad except that
1188 * occasionally the mesh actually executes the
1189 * SEQ_STATUS *as well as* giving us the sequence
1190 * error and phase mismatch exception.
1191 */
1192 out_8(&mr->sequence, 0);
1193 out_8(&mr->interrupt,
1194 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1195 halt_dma(ms);
1196 break;
1197 case statusing:
1198 if (cmd) {
1199 cmd->SCp.Status = mr->fifo;
1200 if (DEBUG_TARGET(cmd))
1201 printk(KERN_DEBUG "mesh: status is %x\n",
1202 cmd->SCp.Status);
1203 }
1204 ms->msgphase = msg_in;
1205 break;
1206 case busfreeing:
1207 mesh_done(ms, 1);
1208 return;
1209 case disconnecting:
1210 ms->current_req = 0;
1211 ms->phase = idle;
1212 mesh_start(ms);
1213 return;
1214 default:
1215 break;
1216 }
1217 ++ms->phase;
1218 start_phase(ms);
1219 break;
1220 }
1221 }
1222
1223 static void phase_mismatch(struct mesh_state *ms)
1224 {
1225 volatile struct mesh_regs *mr = ms->mesh;
1226 int phase;
1227
1228 dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1229 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1230 phase = mr->bus_status0 & BS0_PHASE;
1231 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1232 /* output the last byte of the message, without ATN */
1233 out_8(&mr->count_lo, 1);
1234 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1235 udelay(1);
1236 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1237 ms->msgphase = msg_out_last;
1238 return;
1239 }
1240
1241 if (ms->msgphase == msg_in) {
1242 get_msgin(ms);
1243 if (ms->n_msgin)
1244 handle_msgin(ms);
1245 }
1246
1247 if (ms->dma_started)
1248 halt_dma(ms);
1249 if (mr->fifo_count) {
1250 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1251 udelay(1);
1252 }
1253
1254 ms->msgphase = msg_none;
1255 switch (phase) {
1256 case BP_DATAIN:
1257 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1258 ms->phase = dataing;
1259 break;
1260 case BP_DATAOUT:
1261 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1262 ms->phase = dataing;
1263 break;
1264 case BP_COMMAND:
1265 ms->phase = commanding;
1266 break;
1267 case BP_STATUS:
1268 ms->phase = statusing;
1269 break;
1270 case BP_MSGIN:
1271 ms->msgphase = msg_in;
1272 ms->n_msgin = 0;
1273 break;
1274 case BP_MSGOUT:
1275 ms->msgphase = msg_out;
1276 if (ms->n_msgout == 0) {
1277 if (ms->aborting) {
1278 do_abort(ms);
1279 } else {
1280 if (ms->last_n_msgout == 0) {
1281 printk(KERN_DEBUG
1282 "mesh: no msg to repeat\n");
1283 ms->msgout[0] = NOP;
1284 ms->last_n_msgout = 1;
1285 }
1286 ms->n_msgout = ms->last_n_msgout;
1287 }
1288 }
1289 break;
1290 default:
1291 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1292 ms->stat = DID_ERROR;
1293 mesh_done(ms, 1);
1294 return;
1295 }
1296
1297 start_phase(ms);
1298 }
1299
1300 static void
1301 reselected(struct mesh_state *ms)
1302 {
1303 volatile struct mesh_regs *mr = ms->mesh;
1304 Scsi_Cmnd *cmd;
1305 struct mesh_target *tp;
1306 int b, t, prev;
1307
1308 switch (ms->phase) {
1309 case idle:
1310 break;
1311 case arbitrating:
1312 if ((cmd = ms->current_req) != NULL) {
1313 /* put the command back on the queue */
1314 cmd->host_scribble = (void *) ms->request_q;
1315 if (ms->request_q == NULL)
1316 ms->request_qtail = cmd;
1317 ms->request_q = cmd;
1318 tp = &ms->tgts[cmd->target];
1319 tp->current_req = NULL;
1320 }
1321 break;
1322 case busfreeing:
1323 ms->phase = reselecting;
1324 mesh_done(ms, 0);
1325 break;
1326 case disconnecting:
1327 break;
1328 default:
1329 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
1330 ms->msgphase, ms->phase, ms->conn_tgt);
1331 dumplog(ms, ms->conn_tgt);
1332 dumpslog(ms);
1333 }
1334
1335 ms->current_req = NULL;
1336 ms->phase = dataing;
1337 ms->msgphase = msg_in;
1338 ms->dma_started = 0;
1339 ms->n_msgout = 0;
1340 ms->last_n_msgout = 0;
1341 prev = ms->conn_tgt;
1342
1343 /*
1344 * We seem to get abortive reselections sometimes.
1345 */
1346 while ((mr->bus_status1 & BS1_BSY) == 0) {
1347 static int mesh_aborted_resels;
1348 mesh_aborted_resels++;
1349 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1350 udelay(1);
1351 out_8(&mr->sequence, SEQ_ENBRESEL);
1352 udelay(5);
1353 dlog(ms, "extra resel err/exc/fc = %.6x",
1354 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
1355 }
1356 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1357 udelay(1);
1358 out_8(&mr->sequence, SEQ_ENBRESEL);
1359 udelay(1);
1360 out_8(&mr->sync_params, ASYNC_PARAMS);
1361
1362 /*
1363 * Find out who reselected us.
1364 */
1365 if (mr->fifo_count == 0) {
1366 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
1367 ms->conn_tgt = ms->host->this_id;
1368 goto bogus;
1369 }
1370 /* get the last byte in the fifo */
1371 do {
1372 b = in_8(&mr->fifo);
1373 dlog(ms, "reseldata %x", b);
1374 } while (in_8(&mr->fifo_count));
1375 for (t = 0; t < 8; ++t)
1376 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
1377 break;
1378 if (b != (1 << t) + (1 << ms->host->this_id)) {
1379 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
1380 ms->conn_tgt = ms->host->this_id;
1381 goto bogus;
1382 }
1383
1384
1385 /*
1386 * Set up to continue with that target's transfer.
1387 */
1388 ms->conn_tgt = t;
1389 tp = &ms->tgts[t];
1390 out_8(&mr->sync_params, tp->sync_params);
1391 if (ALLOW_DEBUG(t)) {
1392 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
1393 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
1394 tp->saved_ptr, tp->data_goes_out, tp->current_req);
1395 }
1396 ms->current_req = tp->current_req;
1397 if (tp->current_req == NULL) {
1398 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
1399 goto bogus;
1400 }
1401 ms->data_ptr = tp->saved_ptr;
1402 dlog(ms, "resel prev tgt=%d", prev);
1403 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
1404 start_phase(ms);
1405 return;
1406
1407 bogus:
1408 dumplog(ms, ms->conn_tgt);
1409 dumpslog(ms);
1410 ms->data_ptr = 0;
1411 ms->aborting = 1;
1412 start_phase(ms);
1413 }
1414
1415 static void do_abort(struct mesh_state *ms)
1416 {
1417 ms->msgout[0] = ABORT;
1418 ms->n_msgout = 1;
1419 ms->aborting = 1;
1420 ms->stat = DID_ABORT;
1421 dlog(ms, "abort", 0);
1422 }
1423
1424 static void
1425 handle_reset(struct mesh_state *ms)
1426 {
1427 int tgt;
1428 struct mesh_target *tp;
1429 Scsi_Cmnd *cmd;
1430 volatile struct mesh_regs *mr = ms->mesh;
1431
1432 for (tgt = 0; tgt < 8; ++tgt) {
1433 tp = &ms->tgts[tgt];
1434 if ((cmd = tp->current_req) != NULL) {
1435 cmd->result = DID_RESET << 16;
1436 tp->current_req = NULL;
1437 mesh_completed(ms, cmd);
1438 }
1439 ms->tgts[tgt].sdtr_state = do_sdtr;
1440 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1441 }
1442 ms->current_req = NULL;
1443 while ((cmd = ms->request_q) != NULL) {
1444 ms->request_q = (Scsi_Cmnd *) cmd->host_scribble;
1445 cmd->result = DID_RESET << 16;
1446 mesh_completed(ms, cmd);
1447 }
1448 ms->phase = idle;
1449 ms->msgphase = msg_none;
1450 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1451 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1452 udelay(1);
1453 out_8(&mr->sync_params, ASYNC_PARAMS);
1454 out_8(&mr->sequence, SEQ_ENBRESEL);
1455 }
1456
1457 static void
1458 do_mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1459 {
1460 unsigned long flags;
1461
1462 spin_lock_irqsave(&io_request_lock, flags);
1463 mesh_interrupt(irq, dev_id, ptregs);
1464 spin_unlock_irqrestore(&io_request_lock, flags);
1465 }
1466
1467 static void handle_error(struct mesh_state *ms)
1468 {
1469 int err, exc, count;
1470 volatile struct mesh_regs *mr = ms->mesh;
1471
1472 err = in_8(&mr->error);
1473 exc = in_8(&mr->exception);
1474 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1475 dlog(ms, "error err/exc/fc/cl=%.8x",
1476 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1477 if (err & ERR_SCSIRESET) {
1478 /* SCSI bus was reset */
1479 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1480 "waiting for end...");
1481 while ((mr->bus_status1 & BS1_RST) != 0)
1482 udelay(1);
1483 printk("done\n");
1484 handle_reset(ms);
1485 /* request_q is empty, no point in mesh_start() */
1486 return;
1487 }
1488 if (err & ERR_UNEXPDISC) {
1489 /* Unexpected disconnect */
1490 if (exc & EXC_RESELECTED) {
1491 reselected(ms);
1492 return;
1493 }
1494 if (!ms->aborting) {
1495 printk(KERN_WARNING "mesh: target %d aborted\n",
1496 ms->conn_tgt);
1497 dumplog(ms, ms->conn_tgt);
1498 dumpslog(ms);
1499 }
1500 out_8(&mr->interrupt, INT_CMDDONE);
1501 ms->stat = DID_ABORT;
1502 mesh_done(ms, 1);
1503 return;
1504 }
1505 if (err & ERR_PARITY) {
1506 if (ms->msgphase == msg_in) {
1507 printk(KERN_ERR "mesh: msg parity error, target %d\n",
1508 ms->conn_tgt);
1509 ms->msgout[0] = MSG_PARITY_ERROR;
1510 ms->n_msgout = 1;
1511 ms->msgphase = msg_in_bad;
1512 cmd_complete(ms);
1513 return;
1514 }
1515 if (ms->stat == DID_OK) {
1516 printk(KERN_ERR "mesh: parity error, target %d\n",
1517 ms->conn_tgt);
1518 ms->stat = DID_PARITY;
1519 }
1520 count = (mr->count_hi << 8) + mr->count_lo;
1521 if (count == 0) {
1522 cmd_complete(ms);
1523 } else {
1524 /* reissue the data transfer command */
1525 out_8(&mr->sequence, mr->sequence);
1526 }
1527 return;
1528 }
1529 if (err & ERR_SEQERR) {
1530 if (exc & EXC_RESELECTED) {
1531 /* This can happen if we issue a command to
1532 get the bus just after the target reselects us. */
1533 static int mesh_resel_seqerr;
1534 mesh_resel_seqerr++;
1535 reselected(ms);
1536 return;
1537 }
1538 if (exc == EXC_PHASEMM) {
1539 static int mesh_phasemm_seqerr;
1540 mesh_phasemm_seqerr++;
1541 phase_mismatch(ms);
1542 return;
1543 }
1544 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1545 err, exc);
1546 } else {
1547 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1548 }
1549 mesh_dump_regs(ms);
1550 dumplog(ms, ms->conn_tgt);
1551 if (ms->phase > selecting && (mr->bus_status1 & BS1_BSY)) {
1552 /* try to do what the target wants */
1553 do_abort(ms);
1554 phase_mismatch(ms);
1555 return;
1556 }
1557 ms->stat = DID_ERROR;
1558 mesh_done(ms, 1);
1559 }
1560
1561 static void handle_exception(struct mesh_state *ms)
1562 {
1563 int exc;
1564 volatile struct mesh_regs *mr = ms->mesh;
1565
1566 exc = in_8(&mr->exception);
1567 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1568 if (exc & EXC_RESELECTED) {
1569 static int mesh_resel_exc;
1570 mesh_resel_exc++;
1571 reselected(ms);
1572 } else if (exc == EXC_ARBLOST) {
1573 printk(KERN_DEBUG "mesh: lost arbitration\n");
1574 ms->stat = DID_BUS_BUSY;
1575 mesh_done(ms, 1);
1576 } else if (exc == EXC_SELTO) {
1577 /* selection timed out */
1578 ms->stat = DID_BAD_TARGET;
1579 mesh_done(ms, 1);
1580 } else if (exc == EXC_PHASEMM) {
1581 /* target wants to do something different:
1582 find out what it wants and do it. */
1583 phase_mismatch(ms);
1584 } else {
1585 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1586 mesh_dump_regs(ms);
1587 dumplog(ms, ms->conn_tgt);
1588 do_abort(ms);
1589 phase_mismatch(ms);
1590 }
1591 }
1592
1593 static void
1594 mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1595 {
1596 struct mesh_state *ms = (struct mesh_state *) dev_id;
1597 volatile struct mesh_regs *mr = ms->mesh;
1598 int intr;
1599
1600 #if 0
1601 if (ALLOW_DEBUG(ms->conn_tgt))
1602 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1603 "phase=%d msgphase=%d\n", mr->bus_status0,
1604 mr->interrupt, mr->exception, mr->error,
1605 ms->phase, ms->msgphase);
1606 #endif
1607 while ((intr = in_8(&mr->interrupt)) != 0) {
1608 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1609 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1610 if (intr & INT_ERROR) {
1611 handle_error(ms);
1612 } else if (intr & INT_EXCEPTION) {
1613 handle_exception(ms);
1614 } else if (intr & INT_CMDDONE) {
1615 out_8(&mr->interrupt, INT_CMDDONE);
1616 cmd_complete(ms);
1617 }
1618 }
1619 }
1620
1621 static void
1622 handle_msgin(struct mesh_state *ms)
1623 {
1624 int i, code;
1625 Scsi_Cmnd *cmd = ms->current_req;
1626 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1627
1628 if (ms->n_msgin == 0)
1629 return;
1630 code = ms->msgin[0];
1631 if (ALLOW_DEBUG(ms->conn_tgt)) {
1632 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1633 for (i = 0; i < ms->n_msgin; ++i)
1634 printk(" %x", ms->msgin[i]);
1635 printk("\n");
1636 }
1637 dlog(ms, "msgin msg=%.8x",
1638 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1639
1640 ms->expect_reply = 0;
1641 ms->n_msgout = 0;
1642 if (ms->n_msgin < msgin_length(ms))
1643 goto reject;
1644 if (cmd)
1645 cmd->SCp.Message = code;
1646 switch (code) {
1647 case COMMAND_COMPLETE:
1648 break;
1649 case EXTENDED_MESSAGE:
1650 switch (ms->msgin[2]) {
1651 case EXTENDED_MODIFY_DATA_POINTER:
1652 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1653 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1654 break;
1655 case EXTENDED_SDTR:
1656 if (tp->sdtr_state != sdtr_sent) {
1657 /* reply with an SDTR */
1658 add_sdtr_msg(ms);
1659 /* limit period to at least his value,
1660 offset to no more than his */
1661 if (ms->msgout[3] < ms->msgin[3])
1662 ms->msgout[3] = ms->msgin[3];
1663 if (ms->msgout[4] > ms->msgin[4])
1664 ms->msgout[4] = ms->msgin[4];
1665 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1666 ms->msgphase = msg_out;
1667 } else {
1668 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1669 }
1670 break;
1671 default:
1672 goto reject;
1673 }
1674 break;
1675 case SAVE_POINTERS:
1676 tp->saved_ptr = ms->data_ptr;
1677 break;
1678 case RESTORE_POINTERS:
1679 ms->data_ptr = tp->saved_ptr;
1680 break;
1681 case DISCONNECT:
1682 ms->phase = disconnecting;
1683 break;
1684 case ABORT:
1685 break;
1686 case MESSAGE_REJECT:
1687 if (tp->sdtr_state == sdtr_sent)
1688 set_sdtr(ms, 0, 0);
1689 break;
1690 case NOP:
1691 break;
1692 default:
1693 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1694 if (cmd == NULL) {
1695 do_abort(ms);
1696 ms->msgphase = msg_out;
1697 } else if (code != cmd->lun + IDENTIFY_BASE) {
1698 printk(KERN_WARNING "mesh: lun mismatch "
1699 "(%d != %d) on reselection from "
1700 "target %d\n", i, cmd->lun,
1701 ms->conn_tgt);
1702 }
1703 break;
1704 }
1705 goto reject;
1706 }
1707 return;
1708
1709 reject:
1710 printk(KERN_WARNING "mesh: rejecting message from target %d:",
1711 ms->conn_tgt);
1712 for (i = 0; i < ms->n_msgin; ++i)
1713 printk(" %x", ms->msgin[i]);
1714 printk("\n");
1715 ms->msgout[0] = MESSAGE_REJECT;
1716 ms->n_msgout = 1;
1717 ms->msgphase = msg_out;
1718 }
1719
1720 static void
1721 mesh_done(struct mesh_state *ms, int start_next)
1722 {
1723 Scsi_Cmnd *cmd;
1724 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1725
1726 cmd = ms->current_req;
1727 ms->current_req = 0;
1728 tp->current_req = 0;
1729 if (cmd) {
1730 cmd->result = (ms->stat << 16) + cmd->SCp.Status;
1731 if (ms->stat == DID_OK)
1732 cmd->result += (cmd->SCp.Message << 8);
1733 if (DEBUG_TARGET(cmd)) {
1734 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
1735 cmd->result, ms->data_ptr, cmd->request_bufflen);
1736 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
1737 && cmd->request_buffer != 0) {
1738 unsigned char *b = cmd->request_buffer;
1739 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
1740 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
1741 }
1742 }
1743 cmd->SCp.this_residual -= ms->data_ptr;
1744 mesh_completed(ms, cmd);
1745 }
1746 if (start_next) {
1747 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
1748 udelay(1);
1749 ms->phase = idle;
1750 mesh_start(ms);
1751 }
1752 }
1753
1754 static void
1755 mesh_completed(struct mesh_state *ms, Scsi_Cmnd *cmd)
1756 {
1757 #ifdef MESH_NEW_STYLE_EH
1758 (*cmd->scsi_done)(cmd);
1759 #else
1760 if (ms->completed_q == NULL)
1761 ms->completed_q = cmd;
1762 else
1763 ms->completed_qtail->host_scribble = (void *) cmd;
1764 ms->completed_qtail = cmd;
1765 cmd->host_scribble = NULL;
1766 queue_task(&ms->tqueue, &tq_immediate);
1767 mark_bh(IMMEDIATE_BH);
1768 #endif /* MESH_NEW_STYLE_EH */
1769 }
1770
1771 /*
1772 * Set up DMA commands for transferring data.
1773 */
1774 static void
1775 set_dma_cmds(struct mesh_state *ms, Scsi_Cmnd *cmd)
1776 {
1777 int i, dma_cmd, total, off, dtot;
1778 struct scatterlist *scl;
1779 struct dbdma_cmd *dcmds;
1780
1781 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1782 OUTPUT_MORE: INPUT_MORE;
1783 dcmds = ms->dma_cmds;
1784 dtot = 0;
1785 if (cmd) {
1786 cmd->SCp.this_residual = cmd->request_bufflen;
1787 if (cmd->use_sg > 0) {
1788 total = 0;
1789 scl = (struct scatterlist *) cmd->buffer;
1790 off = ms->data_ptr;
1791 for (i = 0; i < cmd->use_sg; ++i, ++scl) {
1792 total += scl->length;
1793 if (off >= scl->length) {
1794 off -= scl->length;
1795 continue;
1796 }
1797 if (scl->length > 0xffff)
1798 panic("mesh: scatterlist element >= 64k");
1799 st_le16(&dcmds->req_count, scl->length - off);
1800 st_le16(&dcmds->command, dma_cmd);
1801 st_le32(&dcmds->phy_addr,
1802 virt_to_phys(scl->address) + off);
1803 dcmds->xfer_status = 0;
1804 ++dcmds;
1805 dtot += scl->length - off;
1806 off = 0;
1807 }
1808 } else if (ms->data_ptr < cmd->request_bufflen) {
1809 dtot = cmd->request_bufflen - ms->data_ptr;
1810 if (dtot > 0xffff)
1811 panic("mesh: transfer size >= 64k");
1812 st_le16(&dcmds->req_count, dtot);
1813 st_le32(&dcmds->phy_addr,
1814 virt_to_phys(cmd->request_buffer) + ms->data_ptr);
1815 dcmds->xfer_status = 0;
1816 ++dcmds;
1817 }
1818 }
1819 if (dtot == 0) {
1820 /* Either the target has overrun our buffer,
1821 or the caller didn't provide a buffer. */
1822 static char mesh_extra_buf[64];
1823
1824 dtot = sizeof(mesh_extra_buf);
1825 st_le16(&dcmds->req_count, dtot);
1826 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf));
1827 dcmds->xfer_status = 0;
1828 ++dcmds;
1829 }
1830 dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1831 st_le16(&dcmds[-1].command, dma_cmd);
1832 memset(dcmds, 0, sizeof(*dcmds));
1833 st_le16(&dcmds->command, DBDMA_STOP);
1834 ms->dma_count = dtot;
1835 }
1836
1837 static void
1838 halt_dma(struct mesh_state *ms)
1839 {
1840 volatile struct dbdma_regs *md = ms->dma;
1841 volatile struct mesh_regs *mr = ms->mesh;
1842 Scsi_Cmnd *cmd = ms->current_req;
1843 int t, nb;
1844
1845 if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1846 /* wait a little while until the fifo drains */
1847 t = 50;
1848 while (t > 0 && mr->fifo_count != 0
1849 && (in_le32(&md->status) & ACTIVE) != 0) {
1850 --t;
1851 udelay(1);
1852 }
1853 }
1854 out_le32(&md->control, RUN << 16); /* turn off RUN bit */
1855 nb = (mr->count_hi << 8) + mr->count_lo;
1856 dlog(ms, "halt_dma fc/count=%.6x",
1857 MKWORD(0, mr->fifo_count, 0, nb));
1858 if (ms->tgts[ms->conn_tgt].data_goes_out)
1859 nb += mr->fifo_count;
1860 /* nb is the number of bytes not yet transferred
1861 to/from the target. */
1862 ms->data_ptr -= nb;
1863 dlog(ms, "data_ptr %x", ms->data_ptr);
1864 if (ms->data_ptr < 0) {
1865 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1866 ms->data_ptr, nb, ms);
1867 ms->data_ptr = 0;
1868 #ifdef MESH_DBG
1869 dumplog(ms, ms->conn_tgt);
1870 dumpslog(ms);
1871 #endif /* MESH_DBG */
1872 } else if (cmd && cmd->request_bufflen != 0 &&
1873 ms->data_ptr > cmd->request_bufflen) {
1874 printk(KERN_DEBUG "mesh: target %d overrun, "
1875 "data_ptr=%x total=%x goes_out=%d\n",
1876 ms->conn_tgt, ms->data_ptr, cmd->request_bufflen,
1877 ms->tgts[ms->conn_tgt].data_goes_out);
1878 }
1879 ms->dma_started = 0;
1880 }
1881
1882 /*
1883 * Work out whether we expect data to go out from the host adaptor or into it.
1884 * (If this information is available from somewhere else in the scsi
1885 * code, somebody please let me know :-)
1886 */
1887 static int
1888 data_goes_out(Scsi_Cmnd *cmd)
1889 {
1890 switch (cmd->cmnd[0]) {
1891 case CHANGE_DEFINITION:
1892 case COMPARE:
1893 case COPY:
1894 case COPY_VERIFY:
1895 case FORMAT_UNIT:
1896 case LOG_SELECT:
1897 case MEDIUM_SCAN:
1898 case MODE_SELECT:
1899 case MODE_SELECT_10:
1900 case REASSIGN_BLOCKS:
1901 case RESERVE:
1902 case SEARCH_EQUAL:
1903 case SEARCH_EQUAL_12:
1904 case SEARCH_HIGH:
1905 case SEARCH_HIGH_12:
1906 case SEARCH_LOW:
1907 case SEARCH_LOW_12:
1908 case SEND_DIAGNOSTIC:
1909 case SEND_VOLUME_TAG:
1910 case SET_WINDOW:
1911 case UPDATE_BLOCK:
1912 case WRITE_BUFFER:
1913 case WRITE_6:
1914 case WRITE_10:
1915 case WRITE_12:
1916 case WRITE_LONG:
1917 case WRITE_LONG_2: /* alternate code for WRITE_LONG */
1918 case WRITE_SAME:
1919 case WRITE_VERIFY:
1920 case WRITE_VERIFY_12:
1921 return 1;
1922 default:
1923 return 0;
1924 }
1925 }
1926
1927 #ifdef MESH_DBG
1928 static inline u32 readtb(void)
1929 {
1930 u32 tb;
1931
1932 #ifdef DBG_USE_TB
1933 /* Beware: if you enable this, it will crash on 601s. */
1934 asm ("mftb %0" : "=r" (tb) : );
1935 #else
1936 tb = 0;
1937 #endif
1938 return tb;
1939 }
1940
1941 static void dlog(struct mesh_state *ms, char *fmt, int a)
1942 {
1943 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1944 struct dbglog *tlp, *slp;
1945
1946 tlp = &tp->log[tp->log_ix];
1947 slp = &ms->log[ms->log_ix];
1948 tlp->fmt = fmt;
1949 tlp->tb = readtb();
1950 tlp->phase = (ms->msgphase << 4) + ms->phase;
1951 tlp->bs0 = ms->mesh->bus_status0;
1952 tlp->bs1 = ms->mesh->bus_status1;
1953 tlp->tgt = ms->conn_tgt;
1954 tlp->d = a;
1955 *slp = *tlp;
1956 if (++tp->log_ix >= N_DBG_LOG)
1957 tp->log_ix = 0;
1958 if (tp->n_log < N_DBG_LOG)
1959 ++tp->n_log;
1960 if (++ms->log_ix >= N_DBG_SLOG)
1961 ms->log_ix = 0;
1962 if (ms->n_log < N_DBG_SLOG)
1963 ++ms->n_log;
1964 }
1965
1966 static void dumplog(struct mesh_state *ms, int t)
1967 {
1968 struct mesh_target *tp = &ms->tgts[t];
1969 struct dbglog *lp;
1970 int i;
1971
1972 if (tp->n_log == 0)
1973 return;
1974 i = tp->log_ix - tp->n_log;
1975 if (i < 0)
1976 i += N_DBG_LOG;
1977 tp->n_log = 0;
1978 do {
1979 lp = &tp->log[i];
1980 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
1981 t, lp->bs1, lp->bs0, lp->phase);
1982 #ifdef DBG_USE_TB
1983 printk("tb=%10u ", lp->tb);
1984 #endif
1985 printk(lp->fmt, lp->d);
1986 printk("\n");
1987 if (++i >= N_DBG_LOG)
1988 i = 0;
1989 } while (i != tp->log_ix);
1990 }
1991
1992 static void dumpslog(struct mesh_state *ms)
1993 {
1994 struct dbglog *lp;
1995 int i;
1996
1997 if (ms->n_log == 0)
1998 return;
1999 i = ms->log_ix - ms->n_log;
2000 if (i < 0)
2001 i += N_DBG_SLOG;
2002 ms->n_log = 0;
2003 do {
2004 lp = &ms->log[i];
2005 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
2006 lp->bs1, lp->bs0, lp->phase, lp->tgt);
2007 #ifdef DBG_USE_TB
2008 printk("tb=%10u ", lp->tb);
2009 #endif
2010 printk(lp->fmt, lp->d);
2011 printk("\n");
2012 if (++i >= N_DBG_SLOG)
2013 i = 0;
2014 } while (i != ms->log_ix);
2015 }
2016 #endif /* MESH_DBG */
2017
2018 static Scsi_Host_Template driver_template = SCSI_MESH;
2019
2020 #include "scsi_module.c"
2021